TPS75201-EP TI | Alldatasheet
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TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Controlled Baseline – One Assembly/Test Site, One Fabrication Site /C0068Enhanced Diminishing Manufacturing Sources (DMS) Support /C0068Enhanced Product-Change Notification /C0068Qualification Pedigree† /C00682-A Low-Dropout Voltage Regulator /C0068Available in 1.5-V, 1.8-V, 2.5-V, 3.3-V Fixed Output and Adjustable Versions /C0068Open Drain Power-On Reset With 100-ms Delay (TPS752xx) /C0068Open Drain Power-Good (PG) Status Output (TPS754xx) /C0068Dropout Voltage Typically 210 mV at 2 A (TPS75233) † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over the specified temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. /C0068Ultralow 75-µA Typical Quiescent Current /C0068Fast Transient Response /C00682% Tolerance Over Specified Conditions for Fixed-Output Versions /C006820-Pin TSSOP (PWP) PowerPAD Package /C0068Thermal Shutdown Protection
description
The TPS752xx and TPS754xx are low dropout regulators with integrated power-on reset and power good (PG) functions respectively. These devices are capable of supplying 2 A of output current with a dropout of 210 mV (TPS75233, TPS75433). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. TPS752xx and TPS754xx are designed to have fast transient response for larger load current changes. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 210 mV at an output current of 2 A for the TPS75x33) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 1 µA at TJ = 25°C. The RESET (SVS, POR, or power on reset) output of the TPS752xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (i.e., over load condition) of its regulated voltage. Copyright 2003, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. PowerPAD is a trademark of Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PWP PACKAGE (TOP VIEW) GND/HEATSINK NC IN IN EN RESET or PG‡ FB/SENSE OUTPUT OUTPUT GND/HEATSINK GND/HEATSINK NC NC GND NC NC NC NC NC GND/HEATSINK NC – No internal connection ‡ PG is on the TPS754xx and RESET is on the TPS752xx
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TJ – Junction Temperature – °C –40 10 110 60 – Dropout Voltage – mVVDO TPS75x33 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 300 160 250 200 150 100 IO = 0.5 A IO = 1.5 A IO = 2 A t – Time – ms TPS75x33 LOAD TRANSIENT RESPONSE I – Output Current – AO VO – Change in∆ Output Voltage – mV –150 3214 5 7 68 9 1 00 –50 IL=2 A C L=100 µF (Tantalum) VO =3.3 V –100 description (continued) The TPS754xx has a power good terminal (PG) as an active high, open drain output, which can be used to implement a power-on reset or a low-battery indicator. The TPS752xx or the TPS754xx are offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS752xx and the TPS754xx families are available in 20 pin TSSOP (PWP) packages. AVAILABLE OPTIONS/ORDERING INFORMATION † TJ OUTPUT VOLTAGE TSSOP (PWP) TJ OUTPUT VOLTAGE (TYP) RESET PG
3.3 V TPS75233QPWPEP TPS75433QPWPEP ‡
2.5 V TPS75225QPWPEP TPS75425QPWPEP ‡
–40°C to 125°C 1.8 V TPS75218QPWPEP TPS75418QPWPEP ‡40 C to 125 C
1.5 V TPS75215QPWPEP TPS75415QPWPEP ‡
Adjustable 1.5 V to 5 VTPS75201QPWPEP TPS75401QPWPEP ‡ † The TPS75x01 is programmable using an external resistor divider (see application information). The PWP package is available taped and reeled. Add an R suffix to the device type (e.g., TPS75201QPWPREP) to indicate tape and reel. ‡ Product preview
† See application information section for capacitor selection details. Figure 1. Typical Application Configuration (For Fixed Output Options)
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003
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functional block diagram— fixed-voltage version Vref = 1.1834 V OUT EN GND PG or RESET IN SENSE100 ms Delay (for RESET Option) Terminal Functions (TPS752xx) TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION EN 5 I Enable Input FB/SENSE 7 I Feedback input voltage for adjustable device (sense input for fixed-voltage option) GND 17 Regulator ground GND/HEATSINK 1, 10, 11, 20 Ground/heatsink IN 3, 4 I Input voltage NC 2, 12, 13, 14, 15, 16, 18, 19 No connection OUTPUT 8, 9 O Regulated output voltage RESET 6 O Reset output Terminal Functions (TPS754xx) TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION EN 5 I Enable Input FB/SENSE 7 I Feedback input voltage for adjustable device (sense input for fixed-voltage option) GND 17 Regulator ground GND/HEATSINK 1, 10, 11, 20 Ground/heatsink IN 3, 4 I Input voltage NC 2, 12, 13, 14, 15, 16, 18, 19 No connection OUTPUT 8, 9 O Regulated output voltage PG 6 O Power good output
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS752xx RESET timing diagram ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ VI Vres (see Note A) Vres t t t VO Threshold Voltage RESET Output 100 ms Delay 100 ms Delay Output Undefined Output Undefined VIT+(see Note B) VIT–(see Note B) VIT–(see Note B) VIT+(see Note B) Less than 5% of the output voltage NOTES: A. V res is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO ) VIT– to VIT+ is the hysteresis voltage.
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS754xx PG timing diagram ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ VI VPG (see Note A) VPG t t t VO Threshold Voltage PG Output Output Undefined Output Undefined VIT+(see Note B) VIT–(see Note B) VIT–(see Note B) VIT+(see Note B) NOTES: A. V PG is the minimum input voltage for a valid PG. The symbol VPG is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT –Trip voltage is typically 17% lower than the output voltage (83%VO ) VIT– to VIT+ is the hysteresis voltage.
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating junction temperature range (unless otherwise noted)/C0276 † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltage values are with respect to network terminal ground. DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURES PACKAGE AIR FLOW (CFM) TA < 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING PWP § 0 2.9 W 23.5 mW/°C 1.9 W 1.5 W PWP § 300 4.3 W 34.6 mW/ °C 2.8 W 2.2 W PWP ¶ 0 3 W 23.8 mW/°C 1.9 W 1.5 W PWP ¶ 300 7.2 W 57.9 mW/°C 4.6 W 3.8 W § This parameter is measured with the recommended copper heat sink pattern on a 1-layer PCB, 5-in × 5-in PCB, 1 oz. copper, 2-in × 2-in coverage (4 in2). ¶ This parameter is measured with the recommended copper heat sink pattern on a 8-layer PCB, 1.5-in × 2-in PCB, 1 oz. copper with layers 1, 2, 4, 5, 7, and 8 at 5% coverage (0.9 in2) and layers 3 and 6 at 100% coverage (6 in2). For more information, refer to TI technical brief SLMA002. recommended operating conditions MIN MAX UNIT Input voltage, VI# 2.7 5 V Output voltage range, VO 1.5 5 V Output current, IO 0 2.0 A Operating virtual junction temperature, TJ –40 125 °C # To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003
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electrical characteristics over recommended operating junction temperature range (TJ = –40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 47 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Adjustable 1.5 V ≤ VO ≤ 5 V, T J = 25°C VOAdjustable Voltage 1.5 V ≤ VO ≤ 5 V 0.98VO 1.02VO 1 5 V Output TJ = 25°C, 2.7 V < V IN < 5 V 1.5 1.5 V Output 2.7 V < VIN < 5 V 1.470 1.530 Output voltage 1 8 V Output TJ = 25°C, 2.8 V < V IN < 5 V 1.8 VOut ut voltage (see Notes 1 and 3) 1.8 V Output 2.8 V < VIN < 5 V 1.764 1.836 V 2 5 V Output TJ = 25°C, 3.5 V < V IN < 5 V 2.5 2.5 V Output 3.5 V < VIN < 5 V 2.450 2.550 3 3 V Output TJ = 25°C, 4.3 V < V IN < 5 V 3.3 3.3 V Output 4.3 V < VIN < 5 V 3.234 3.366 Quiescent current (GND current) (see Note 1) TJ = 25°C, See Note 3 75 AQuiescent current (GND current) (see Note 1) See Note 3 125 µA Output voltage line regulation (∆VO /VO ) VO + 1 V < VI ≤ 5 V, T J = 25°C, 0.01 %/VOut ut voltage line regulation (∆VO /VO ) (see Notes 1 and 2) VO + 1 V < VI < 5 V 0.1 %/V Load regulation (see Note 3) 1 mV Output noise voltage BW = 300 Hz to 50 kHz, VO = 1.5 V C O = 100 µF, T J = 25°C 60 µVrms Output current Limit VO = 0 V 3.3 4.5 A Thermal shutdown junction temperature 150 °C Standby current EN = VI, TJ = 25°C, 1 µA Standby current EN = VI 10 µA FB input current TPS75x01 FB = 1.5 V –1 1 µA High level enable input voltage 2 V Low level enable input voltage 0.7 V Power supply ripple rejection (see Note 2) f = 100 Hz, C O = 100 µF, TJ = 25°C, See Note 1, I O = 2 A 60 dB Minimum input voltage for valid RESET IO(RESET) = 300µA, V (RESET) ≤ 0.8 V 1 1.3 V Trip threshold voltage VO decreasing 92 98 %V O Reset (TPS752xx) Hysteresis voltage Measured at VO 0.5 %V O(TP S752xx) Output low voltage VI = 2.7 V, I O(RESET) = 1 mA 0.15 0.4 V Leakage current V(RESET) = 5 V 1 µA RESET time-out delay 100 ms NOTES: 1. Minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum IN voltage 5V. 2. If VO ≤ 1.8 V then Vimin = 2.7 V, Vimax = 5 V: Line Reg. (mV)/C0043/C0466% /C0324V/C0467/C0032 V O /C0466V imax/C00422.7 V/C0467 100 /C00321000 If VO ≥ 2.5 V then Vimin = VO + 1 V, Vimax = 5 V: Line Reg. (mV)/C0043/C0466% /C0324V/C0467/C0032 V O /C0466V imax/C0042/C0466V O /C00411V /C0467/C0467 100 /C00321000 3. IO = 1 mA to 2 A
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating junction temperature range (TJ = –40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 47 µF (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Minimum input voltage for valid PG IO(PG) = 300 µA V(PG) ≤ 0.8 V 1.1 1.3 V PG Trip threshold voltage VO decreasing 80 86 %V O PG (TPS754xx) Hysteresis voltage Measured at VO 0.5 %V O(TPS754xx) Output low voltage IO(PG) = 1 mA 0.15 0.4 V Leakage current V(PG) = 5.5 V 1 µA Input current (EN) EN = VI –1 1 µA Input current (EN) EN = 0 V –1 0 1 µA High level EN input voltage 2 V Low level EN input voltage 0.7 V Dropout voltage (3.3 V Output) (see Note 4) IO = 2 A, TJ = 25°C VI = 3.2 V, 210 mVDro out voltage (3.3 V Out ut) (see Note 4) IO = 2 A, VI = 3.2 V 400 mV NOTE 4: IN voltage equals VO (Typ) – 100 mV; TPS75x15, TPS75x18 and TPS75x25 dropout voltage limited by input voltage range limitations (i.e., TPS75x33 input voltage needs to drop to 3.2 V for purpose of this test). Table of Graphs FIGURE V Output voltage vs Output current 2, 3 VO Output voltage vs Junction temperature 4, 5, Ground current vs Junction temperature 6 Power supply ripple rejection vs Frequency 7 Output spectral noise density vs Frequency 8 Zo Output impedance vs Frequency 9 V Dropout voltage vs Input voltage 10 VDO Dropout voltage vs Junction temperature 11 Input voltage (min) vs Output voltage 12 Line transient response 13, 15 Load transient response 14, 16 VO Output voltage vs Time 17 Equivalent series resistance (ESR) vs Output current 19, 20
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IO – Output Current – mA TPS75x33 OUTPUT VOLTAGE vs OUTPUT CURRENT 3.303 3.297 3.301 3.299 3.295 500 1500 3.305 – Output Voltage – VVO 1000 VO 2000 VI = 4.3 V TJ = 25°C Figure 3 IO – Output Current – mA TPS75x15 OUTPUT VOLTAGE vs OUTPUT CURRENT 1.502 1.499 1.501 1.5 1.498 1.503 – Output Voltage – VVO 1.497 500 1500 1000 2000 VO VI = 2.7 V TJ = 25°C TJ – Junction Temperature – °C TPS75x33 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE – Output Voltage – VVO Figure 4 3.31 –50 0 3.33 150 3.35 3.29 50 100 3.25 3.27 1 mA 3.23 3.37 2 A TJ – Junction Temperature – °C TPS75x15 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE – Output Voltage – VVO Figure 5 1.48 –40 10 1.50 11060 160 1.52 1.51 1.49 1.47 1.53 1 mA 2 A
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VI – Input Voltage – V 150 100 3.52.5 – Dropout Voltage – mV 4.5 5 VDO 250 200 300 350 TJ = 125°C TJ = 25°C TJ = –40°C IO = 2 A Figure 11 TJ – Junction Temperature – °C –40 10 110 60 – Dropout Voltage – mVVDO TPS75x33 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 300 160 250 200 150 100 IO = 0.5 A IO = 1.5 A IO = 2 A Figure 12 2.7 – Input Voltage (Min) – V INPUT VOLTAGE (MIN) vs OUTPUT VOLTAGE 3 3.25 3.5 VI VO – Output Voltage – V IO = 2 A TA = 25°C TA = 125°C TA = –40°C Figure 13 VO – Change in 100 TPS75x15 LINE TRANSIENT RESPONSE VI t – Time – m s – Input Voltage – V ∆ Output Voltage – mV IO =2 A C O =100 µF VO =1.5 V –100 dv dt /C00431V µs
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Figure 18. Test Circuit for Typical Regions of Stability (Figures 19 and 20) (Fixed Output Options) and PWB trace resistance to Co.
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
The TPS752xx or TPS754xx families include four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V and 3.3 V), and an adjustable regulator, the TPS75x01 (adjustable from 1.5 V to 5 V). minimum load requirements The TPS752xx and TPS754xx families are stable even at no load; no minimum load is required for operation. pin functions enable (EN) The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in shutdown mode. When EN goes to logic low, then the device will be enabled. power good (PG) (TPS752xx) The PG terminal is an open drain, active high output that indicates the status of VO (output of the LDO). When VO reaches 83% of the regulated voltage, PG will go to a high impedance state. It will go to a low-impedance state when VO falls below 83% (i.e. over load condition) of the regulated voltage. The open drain output of the PG terminal requires a pullup resistor. sense (SENSE) The SENSE terminal of the fixed-output options must be connected to the regulator output, and the connection should be as short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the SENSE connection in such a way to minimize/avoid noise pickup. Adding RC networks between the SENSE terminal and V O to filter noise is not recommended because it may cause the regulator to oscillate. feedback (FB) FB is an input terminal used for the adjustable-output options and must be connected to an external feedback resistor divider. The FB connection should be as short as possible. It is essential to route it in such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and V O to filter noise is not recommended because it may cause the regulator to oscillate. reset (RESET) (TPS754xx) The RESET terminal is an open drain, active low output that indicates the status of VO . When VO reaches 95% of the regulated voltage, RESET will go to a low-impedance state after a 100-ms delay. RESET will go to a high-impedance state when VO is below 95% of the regulated voltage. The open-drain output of the RESET terminal requires a pullup resistor. GND/HEATSINK All GND/HEATSINK terminals are connected directly to the mount pad for thermal-enhanced operation. These terminals could be connected to GND or left floating. input capacitor For a typical application, an input bypass capacitor (0.22 µF – 1 µF) is recommended for device stability. This capacitor should be as close to the input pins as possible. For fast transient condition where droop at the input of the LDO may occur due to high inrush current, it is recommended to place a larger capacitor at the input as well. The size of this capacitor is dependant on the output current and response time of the main power supply, as well as the distance to the load (LDO).
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003
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As with most LDO regulators, the TPS752xx and TPS754xx require an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 47 µF and the ESR (equivalent series resistance) must be between 100 mΩ and 10 Ω . Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described in this section. Larger capacitors provide a wider range of stability and better load transient response. This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the user’s application. When necessary to achieve low height requirements along with high output current and/or high load capacitance, several higher ESR capacitors can be used in parallel to meet these guidelines. ESR and transient response LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitors are used to support the load current while LDO amplifier is responding. In most applications, one capacitor is used to support both functions. Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any capacitor can therefore be drawn as shown in Figure 21. R ESR LESL C Figure 21. ESR and ESL
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the minimum output voltage requirement. ESR 1 ESR 2 ESR 3 t1 t2 IO VO Figure 23. Correlation of Different ESRs and Their Influence to the Regulation of VO at a
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 programming the TPS75x01 adjustable LDO regulator The output voltage of the TPS75x01 adjustable regulator is programmed using an external resistor divider as shown in Figure 24. The output voltage is calculated using: V O /C0043V ref/C0032/C04661 /C0041R1 R2 /C0467 (1) Where: Vref = 1.1834 V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 40-µA divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at 40 µA and then calculate R1 using: R1 /C0043 /C0466 V O V ref /C00421/C0467/C0032R2 (2) OUTPUT VOLTAGE R1 R2 2.5 V 3.3 V 3.6 V UNIT 33.2 53.6 61.9 30.1 30.1 30.1 kΩ kΩ kΩ OUTPUT VOLTAGE PROGRAMMING GUIDE VO VI RESET / PG OUT FB/SENSE GND EN IN ≤ 0.7 V ≥ 2 V TPS75x01 RESET or PG Output 0.22 µF 250 kΩ NOTE: To reduce noise and prevent oscillation, R1 and R2 need to be as close as possible to the FB/SENSE terminal. C O Figure 24. TPS75x01 Adjustable LDO Regulator Programming
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
The TPS752xx and TPS754xx PMOS-pass transistors has a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS752xx and TPS754xx also feature internal current limiting and thermal protection. During normal operation, the TPS752xx and TPS754xx limit output current to approximately 3.3 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator operation resumes. power dissipation and junction temperature Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, P D(max), and the actual dissipation, PD , which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using the following equation: P D(max) /C0043 TJmax /C0042TA R /C0113JA Where: TJmax is the maximum allowable junction temperature TA is the ambient temperature. R θJA is the thermal resistance junction-to-ambient for the package, i.e., 34.6°C/W for the 20-terminal PWP with no airflow (see Table 1). (3) The regulator dissipation is calculated using: P D /C0043/C0466V I/C0042V O /C0467/C0032IO (4) Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal protection circuit.
TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
thermally enhanced TSSOP-20 (PWP – PowerPad ) (continued) The thermal pad is directly connected to the substrate of the IC, which for the TPS752xxQPWPEP and TPS754xxQPWPEP series is a secondary electrical connection to device ground. The heat-sink surface that is added to the PWP can be a ground plane or left electrically isolated. In TO220-type surface-mount packages, the thermal connection is also the primary electrical connection for a given terminal which is not always ground. The PWP package provides up to 16 independent leads that can be used as inputs and outputs (Note: leads 1, 10, 11, and 20 are internally connected to the thermal pad and the IC substrate). 100 02 35 – Thermal Resistance – 125 THERMAL RESISTANCE vs COPPER HEAT-SINK AREA 150 7814 60.3 Natural Convection 50 ft/min 250 ft/min 300 ft/min C/W° Copper Heat-Sink Area – cm2 100 ft/min 150 ft/min 200 ft/min R JAθ Figure 26
Figure 27. Power Ratings of the PWP Package at Ambient Temperatures of 25°C, 55°C, and 105°C
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
- As discussed earlier, copper has been added on the PWB to conduct heat away from the device. R
of airflow introduced into the system. Board size 3.2 in. × 3.2 in. Figure 28. PWB Layout (Including Copper Heatsink Area) for Thermally Enhanced PWP Package operating limit) and TA is the ambient temperature.
MHTS001D – JANUARY 1995 – REVISED MAY 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PWP (R-PDSO-G) PowerPAD PLASTIC SMALL-OUTLINE 4073225/F 10/98 0,50 0,75 0,25 0,15 NOM Thermal Pad (See Note D) Gage Plane 2824 7,70 7,90 6,40 6,60 9,60 9,80 6,60 6,20 0,19 4,50 4,30 0,15 A 0,30 1,20 MAX 1614 5,10 4,90 PINS 4,90 5,10 DIM A MIN A MAX 0,05 Seating Plane 0,65 0,10 M0,10 0°–/C02578°
20 PINS SHOWN
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusions. D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153 PowerPAD is a trademark of Texas Instruments Incorporated.
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