V62/03629-02YE

TPS3307-18-EP_16 TI1 | Alldatasheet

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/C0084/C0080/C0083/C0051/C0051/C0048/C0055/C0262/C0049/C0056/C0262/C0069/C0080/C0044 /C0084/C0080/C0083/C0051/C0051/C0048/C0055/C0262/C0051/C0051/C0262/C0069/C0080 /C0084/C0082/C0073/C0080/C0076/C0069 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0083 SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005

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description (continued) The various supply voltage supervisors are designed to monitor the nominal supply voltage as shown in the following supply voltage monitoring table. SUPPLY VOLTAGE MONITORING DEVICE NOMINAL SUPERVISED VOLTAGE THRESHOLD VOLTAGE (TYP) DEVICE SENSE1 SENSE2 SENSE3 SENSE1 SENSE2 SENSE3 TPS3307-33 5 V 3.3 V User defined 4.55 V 2.93 V 1.25 V† † The actual sense voltage has to be adjusted by an external resistor divider according to the application requirements. During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supply voltage supervisor monitors the SENSEn inputs and keeps RESET active as long as SENSEn remain below the threshold voltage VIT+. An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system reset. The delay time, tdtyp = 200 ms, starts after all SENSEn inputs have risen above the threshold voltage VIT+. When the voltage at any SENSE input drops below the threshold voltage VIT–, the RESET output becomes active (low) again. The TPS3307-xx family of devices incorporates a manual reset input, MR. A low level at MR causes RESET to become active. In addition to the active-low RESET output, the TPS3307-xx family includes an active-high RESET output. The devices are available in either 8-pin MSOP or a standard 8-pin SO packages and are characterized for operation over a temperature range of −55°C to 125°C.

ORDERING INFORMATION

TA PACKAGE ‡ ORDERABLE PART NUMBER TOP-SIDE MARKING Small Outline (D)Tape and Reel TPS3307-18MDREP 30718E −55°C to 125°C PowerPad µ-Small Outline (DGN) Tape and Reel TPS3307-33MDGNREP BNP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION/TRUTH TABLES MR SENSE1 > V IT1 SENSE2 > V IT2 SENSE3 > V IT3 RESET RESET L X X X L H H 0 0 0 L H H 0 0 1 L H H 0 1 0 L H H 0 1 1 L H H 1 0 0 L H H 1 0 1 L H H 1 1 0 L H H 1 1 1 H L X = Don’t care

/C0084/C0080/C0083/C0051/C0051/C0048/C0055/C0262/C0049/C0056/C0262/C0069/C0080/C0044 /C0084/C0080/C0083/C0051/C0051/C0048/C0055/C0262/C0051/C0051/C0262/C0069/C0080 /C0084/C0082/C0073/C0080/C0076/C0069 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0083 SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram Reference Voltage of 1.25 V RESET Logic + Timer Oscillator 14 kΩ VDD MR SENSE 1 SENSE 2 GND SENSE 3 RESET RESET TPS3307 timing diagram td td td RESET Because of SENSE Below VIT RESET Because of MR RESET Because of SENSE Below VIT− RESET Because of SENSE Below VIT− SENSEn V(nom) VIT− MR RESET t t t

/C0084/C0080/C0083/C0051/C0051/C0048/C0055/C0262/C0049/C0056/C0262/C0069/C0080/C0044 /C0084/C0080/C0083/C0051/C0051/C0048/C0055/C0262/C0051/C0051/C0262/C0069/C0080 /C0084/C0082/C0073/C0080/C0076/C0069 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0083 SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t = 1000 h continuously. NOTE 2: The thermal impedance, θJA, for the D package is determined for JEDEC high-K PCB (JESD51-7). The thermal impedance value for the DGN package is determined for Texas Instruments recommended assembly for PowerPAD packages. See Texas Instruments technical briefs SLMA002 and SLMA004 for more information about utilizing the PowerPAD thermally enhanced package. Thermal impedance, θJA, values for the D and DGN packages using JEDEC low-K PCB (JESD51-3) are 215 °C/W and 296°C/W, respectively. NOTE 3: Long-term, high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/sc/ep for more information. recommended operating conditions at specified temperature range MIN MAX UNIT Supply voltage, VDD 2 6 V Input voltage at MR and SENSE3, VI 0 VDD +0.3 V Input voltage at SENSE1 and SENSE2, VI 0 (VDD +0.3)VIT/1.25 V V High-level input voltage at MR, VIH 0.7xVDD V Low-level input voltage at MR, VIL 0.3×VDD V Input transition rise and fall rate at MR, ∆t/∆V 50 ns/V Operating free-air temperature range, TA −55 125 °C

/C0084/C0080/C0083/C0051/C0051/C0048/C0055/C0262/C0049/C0056/C0262/C0069/C0080/C0044 /C0084/C0080/C0083/C0051/C0051/C0048/C0055/C0262/C0051/C0051/C0262/C0069/C0080 /C0084/C0082/C0073/C0080/C0076/C0069 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0083 SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD = 2 V to 6 V, IOH = −20 µA VDD – 0.2 V VOH High-level output voltage VDD = 3.3 V, I OH = −2 mA VDD – 0.4 V VVOH High-level output voltage VDD = 6 V, I OH = −3 mA VDD – 0.4 V V VDD = 2 V to 6 V, IOL = 20 µA 0.2 VOL Low-level output voltage VDD = 3.3 V, I OL = 2 mA 0.4 VVOL Low-level output voltage VDD = 6 V, I OL = 3 mA 0.4 Power-up reset voltage (see Note 4) VDD ≥ 1.1 V, I OL = 20 µA 0.4 V SENSE3 1.2 1.25 1.29 VIT− Negative-going input threshold SENSE1, VDD = 2 V to 6 V VSENSE = 1.8 V 1.6 1.68 1.73 VVIT− Negative-going input threshold voltage (see Note 5) SENSE1, SENSE2 VDD = 2 V to 6 VVSENSE = 3.3 V 2.8 2.93 3.02 Vvoltage (see Note 5) SENSE2 VSENSE = 5 V 4.4 4.55 4.67 VIT− = 1.25 V 2 10 30 Vhys Hysteresis at VSENSEn input VIT− = 1.68 V 2 15 40 mVVhys Hysteresis at VSENSEn input VIT− = 2.93 V 3 30 60 mV VIT− = 4.55 V 3 40 80 MR MR = 0.7 × VDD, VDD = 6 V −130 −180 IH High-level input current SENSE1 VSENSE1 = V DD = 6 V 5 8 AIH High-level input current SENSE2 VSENSE2 = V DD = 6 V 6 9 µA SENSE3 VSENSE3 = V DD −1 1 IL Low-level input current MR MR = 0 V, V DD = 6 V −430 −600 AIL Low-level input current SENSEn VSENSE1,2,3 = 0 V −1 1 µA IDD Supply current 40 µΑ C i Input capacitance VI = 0 V to VDD 10 pF NOTES: 4. The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V 5. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1 µF) should be placed close to the supply terminals.

/C0084/C0080/C0083/C0051/C0051/C0048/C0055/C0262/C0049/C0056/C0262/C0069/C0080/C0044 /C0084/C0080/C0083/C0051/C0051/C0048/C0055/C0262/C0051/C0051/C0262/C0069/C0080 /C0084/C0082/C0073/C0080/C0076/C0069 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0083 SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005

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timing requirements at VDD = 2 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tw Pulse width SENSEn VSENSEnL = VIT− −0.2 V, V SENSEnH = VIT+ + 0.2 V 6 µs tw Pulse width MR VIH = 0.7 × VDD ,V IL = 0.3 × VDD 100 ns switching characteristics at VDD = 2 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td Delay time VI(SENSEn) ≥ VIT+ + 0.2 V, MR ≥ 0.7 × VDD , See timing diagram 140 200 280 ms tPHL Propagation (delay) time, high-to-low level output MR to RESET VI(SENSEn) ≥ VIT+ + 0.2 V, 200 600 ns tPLH Propagation (delay) time, low-to-high level output MR to RESET VI(SENSEn) ≥ VIT+ + 0.2 V, VIH = 0.7 × VDD ,V IL = 0.3 × VDD 200 600 ns tPHL Propagation (delay) time, high-to-low level output SENSEn to RESET VIH ≥ VIT+ + 0.2 V, VIL ≤ VIT− − 0.2 V, 1 5 s tPLH Propagation (delay) time, low-to-high level output SENSEn to RESET VIH ≥ VIT+ + 0.2 V, VIL ≤ VIT− − 0.2 V, MR ≥ 0.7 × VDD 1 5 µs

/C0084/C0080/C0083/C0051/C0051/C0048/C0055/C0262/C0049/C0056/C0262/C0069/C0080/C0044 /C0084/C0080/C0083/C0051/C0051/C0048/C0055/C0262/C0051/C0051/C0262/C0069/C0080 /C0084/C0082/C0073/C0080/C0076/C0069 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0083 SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005

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0.5 − High-Level Output Voltage − V 1.5 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 2.5 IOH − High-Level Output Current − mA VOH 85°C −40°C VDD = 2 V MR = Open Figure 7 − High-Level Output Voltage − V HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT IOH − High-Level Output Current − mA VOH 3.5 4.5 6.5 −35 −40 −45 −50 85°C −40°C 5.5 2.5 1.5 0.5 VDD = 6 V MR = Open Figure 8 85°C −40°C VDD = 2 V MR = Open 0.5 0 0.5 1 1.5 2 3 3.5 − Low-Level Output Voltage − V 1.5 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 2.5 4 4.5 5.5 62.5 5 IOL − Low-Level Output Current − mA VOL Figure 9 3.5 1.5 00 5 10 15 20 30 35 4.5 5.5 6.5 40 50 55 60 85°C −40°C VDD = 6 V MR = Open − Low-Level Output Voltage − V LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT IOL − Low-Level Output Current − mA VOL 2.5 0.5 25 45

www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples TPS3307-18MDREP ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 30718E TPS3307-18MDREPG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 30718E TPS3307-33MDGNREP ACTIVE MSOP- PowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -55 to 125 BNP V62/03629-01XE ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 30718E V62/03629-02YE ACTIVE MSOP- PowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -55 to 125 BNP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 11-Apr-2013 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS3307-18-EP, TPS3307-33-EP :

• Catalog: TPS3307-18, TPS3307-33
• Automotive: TPS3307-18-Q1
• Military: TPS3307-18M NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPS3307-33MDGNREP MSOP- Power PAD PACKAGE MATERIALS INFORMATION www.ti.com 17-Feb-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS3307-18MDREP SOIC D 8 2500 367.0 367.0 38.0 TPS3307-33MDGNREP MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 17-Feb-2016 Pack Materials-Page 2

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