TLV2464A-EP TI | Alldatasheet
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/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Controlled Baseline − One Assembly/Test Site, One Fabrication Site /C0068Extended Temperature Performance of −55°C to 125°C /C0068Enhanced Diminishing Manufacturing Sources (DMS) Support /C0068Enhanced Product Change Notification /C0068Qualification Pedigree† /C0068Rail-to-Rail Output Swing /C0068Gain Bandwidth Product. . . 6.4 MHz /C0068±80 mA Output Drive Capability † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. /C0068Supply Current. . . 500 µA/channel /C0068Input Offset Voltage. . . 100 µV /C0068Input Noise Voltage...1 1 n V /√Hz /C0068Slew Rate. . . 1.6 V/µs /C0068Micropower Shutdown Mode (TLV2460/3). . . 0.3 µA/Channel /C0068Universal Operational Amplifier EVM
description
The TLV246x is a family of low-power rail-to-rail input/output operational amplifiers specifically designed for portable applications. The input common-mode voltage range extends beyond the supply rails for maximum dynamic range in low-voltage systems. The amplifier output has rail-to-rail performance with high-output-drive capability, solving one of the limitations of older rail-to-rail input/output operational amplifiers. This rail-to-rail dynamic range and high output drive make the TLV246x ideal for buffering analog-to-digital converters. The operational amplifier has 6.4 MHz of bandwidth and 1.6 V/µs of slew rate with only 500 µA of supply current, providing good ac performance with low power consumption. Devices are available with an optional shutdown terminal, which places the amplifier in an ultralow supply current mode (I DD = 0.3 µA/ch). While in shutdown, the operational-amplifier output is placed in a high-impedance state. DC applications are also well served with an input noise voltage of 11 nV/√Hz and input offset voltage of 100 µV.
ORDERING INFORMATION
TA PACKAGE ‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 125°C D Tape and reel TLV2462AQDREP 2462AE −40°C to 125°C D Tape and reel TLV2463AQDREP V2463AQE D Tape and reel TLV2462AMDREP 2462AM −55°C to 125°C D Tape and reel TLV2464AMDREP V2464AME−55 C to 125C PW Tape and reel TLV2464AMPWREP 2464AME † Some of the TLV246x family, along with packaging options, are in the Product Preview stage of development. Contact the local Texas Instruments sales office for availability. ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2005, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NC IN− IN+ GND SHDN VDD + OUT NC TLV2460 D PACKAGE (TOP VIEW)
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NC − No internal connection 1OUT 1IN− 1IN+ GND NC 1SHDN NC VDD + 2OUT 2IN− 2IN+ NC 2SHDN NC (TOP VIEW) TLV2463 D or PW PACKAGE 1OUT 1IN− 1IN+ VDD + 2IN+ 2IN− 2OUT 4OUT 4IN− 4IN+ GND 3IN+ 3IN− 3OUT (TOP VIEW) TLV2464 D or PW PACKAGE 1OUT 1IN− 1IN+ GND VDD + 2OUT 2IN− 2IN+ TLV2462 D or PW PACKAGE (TOP VIEW) NC IN− IN+ GND NC VDD + OUT NC TLV2461 D or PW PACKAGE (TOP VIEW)
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to GND. informational purposes only. Figure 1. Wirebond Life Estimation Plot
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions MIN MAX UNIT Supply voltage, VDD Single supply 2.7 6 VSupply voltage, VDD Split supply ±1.35 ±3 V Common-mode input voltage range, VICR −0.2 VDD +0.2 V Shutdown on/off voltage level‡ VIH 2 VShutdown on/off voltage level‡ VIL 0.7 V Operating free-air temperature, TA −40 125 °C ‡ Relative to voltage on the GND terminal of the device.
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT VIO Input offset voltage 25°C 150 1500 VVIO Input offset voltage VDD = 3 V, V = 1.5 V, VIC = 1.5 V, R = 50 Full range 1700 µV αVIO Temperature coefficient of input offset voltage VDD = 3 V, VO = 1.5 V, VIC = 1.5 V, R S = 50 Ω 2 µV/°C IIO Input offset current 25°C 2.8 7 nAIIO Input offset current VDD = 3 V, VIC = 1.5 V, Full range 75 nA IIB Input bias current VDD = 3 V, VO = 1.5 V, VIC = 1.5 V, R S = 50 Ω 25°C 4.4 14 nAIIB Input bias current VO = 1.5 V, R S = 50 Full range 75 nA IOH = −2.5 mA 25°C 2.9 VOH High-level output voltage IOH = −2.5 mA Full range 2.8 VVOH High-level output voltage IOH = −10 mA 25°C 2.7 V IOH = −10 mA Full range 2.5 VIC = 1.5 V, IOL = 2.5 mA 25°C 0.1 VOL Low-level output voltage VIC = 1.5 V, IOL = 2.5 mA Full range 0.2 VVOL Low-level output voltage VIC = 1.5 V, IOL = 10 mA 25°C 0.3 V VIC = 1.5 V, IOL = 10 mA Full range 0.5 Sourcing 25°C 50 IOS Short-circuit output current Sourcing Full range 20 mAIOS Short-circuit output current Sinking 25°C 40 mA Sinking Full range 20 IO Output current Measured 1 V from rail 25°C ±40 mA AVD Large-signal differential voltage R L = 10 kΩ 25°C 90 105 dBAVD Large-signal differential voltage amplification R L = 10 kΩ Full range 89 dB ri(d) Differential input resistance 25°C 109 Ω ci(c) Common-mode input capacitance f = 10 kHz 25°C 7 pF zo Closed-loop output impedance f = 100 kHz, AV = 10 25°C 33 Ω CMRR Common-mode rejection ratio VICR = 0 V to 3 V, 25°C 66 80 dBCMRR Common-mode rejection ratio VICR = 0 V to 3 V, R S = 50Ω Full range 60 dB VDD = 2.7 V to 6 V,VIC = VDD /2, 25°C 80 85 kSVR Supply voltage rejection ratio VDD = 2.7 V to 6 V, No load VIC = VDD /2, Full range 75 dBkSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 3 V to 5 V,VIC = VDD /2, 25°C 85 95 dB( VDD /VIO) VDD = 3 V to 5 V, No load VIC = VDD /2, Full range 80 IDD Supply current (per channels) VO = 1.5 V, No load 25°C 0.5 0.575 mAIDD Supply current (per channels) V O = 1.5 V, No load Full range 0.9 mA IDD(SHDN) Supply current in shutdown SHDN < 0.7 V, 25°C 0.3 AIDD(SHDN ) Supply current in shutdown (TLV2460, TLV2463) SHDN < 0.7 V, Per channel in shutdown Full range 2.5 µA † Full range is −40°C to 125°C for the Q suffix and −55°C to 125°C for the M suffix.
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT VO(PP) = 2 V, C L = 160 pF, 25°C 1 1.6 SR Slew rate at unity gain VO(PP) = 2 V, R L = 10 kΩ C L = 160 pF, Full range 0.8 V/µs Vn Equivalent input noise voltage f = 100 Hz 25°C 16 nV/√HzVn Equivalent input noise voltagef = 1 kHz 25°C 11 nV/√Hz In Equivalent input noise currentf = 1 kHz 25°C 0.13 pA/√Hz Total harmonic distortion plusVO(PP) = 2 V, AV = 1 0.006% THD + N Total harmonic distortion plus noise VO(PP) = 2 V, R L = 10 kΩ, f = 1 kHz AV = 10 25°C 0.02%THD + N noise R L = 10 kΩ, f = 1 kHz AV = 100 25 C 0.08% Both channels 7.6 t(on) Amplifier turnon time A V = 1, RL = 10 kΩ Channel 1 only, Channel 2 on 25°C 7.65 µs Both channels 333 t(off) Amplifier turnoff time A V = 1, RL = 10 kΩ Channel 1 only, Channel 2 on 25°C 328 nst(off) Amplifier turnoff time AV = 1, RL = 10 kΩ Channel 2 only, Channel 1 on 25 C 329 ns Gain-bandwidth product f = 10 kHz, CL = 160 pF R L = 10 kΩ, 25°C 5.2 MHz V(STEP)PP = 2 V, AV = −1, CL = 10 pF, 0.1% 1.47 ts Settling time (STEP)PP AV = −1, CL = 10 pF, R L = 10 kΩ 0.01% 25°C 1.78 sts Settling time V(STEP)PP = 2 V, AV = −1, CL = 56 pF, 0.1% 25°C 1.77 µs (STEP)PP AV = −1, CL = 56 pF, R L = 10 kΩ 0.01% 1.98 φm Phase margin at unity gain R L = 10 kΩ, C L = 160 pF 25°C 44° Gain margin R L = 10 kΩ, C L = 160 pF 25°C 7 dB † Full range is −40°C to 125°C for the Q suffix and −55°C to 125°C for the M suffix.
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT VIO Input offset voltage 25°C 150 1500 VVIO Input offset voltage VDD = 5 V, VIC = 2.5, R = 50 Full range 1700 µV VIO Temperature coefficient of input offset VDD = 5 V, VO = 2.5 V, VIC = 2.5, R S = 50 Ω 25°C 2 V/°CαVIO Temperature coefficient of input offset voltage VO = 2.5 V, R S = 50 25°C 2 µV/°C IIO Input offset current 25°C 0.3 7 nAIIO Input offset current VDD = 5 V, VIC = 2.5 V, Full range 60 nA IIB Input bias current VDD = 5 V, VO = 2.5 V, VIC = 2.5 V, R S = 50 Ω 25°C 1.3 14 nAIIB Input bias current VO = 2.5 V, R S = 50 Full range 60 nA IOH = −2.5 mA 25°C 4.9 VOH High-level output voltage IOH = −2.5 mA Full range 4.8 VVOH High-level output voltage IOH = −10 mA 25°C 4.8 V IOH = −10 mA Full range 4.7 VIC = 2.5 V, IOL = 2.5 mA 25°C 0.1 VOL Low-level output voltage VIC = 2.5 V, IOL = 2.5 mA Full range 0.2 VVOL Low-level output voltage VIC = 2.5 V, IOL = 10 mA 25°C 0.2 V VIC = 2.5 V, IOL = 10 mA Full range 0.3 Sourcing 25°C 145 IOS Short-circuit output current Sourcing Full range 60 mAIOS Short-circuit output current Sinking 25°C 100 mA Sinking Full range 60 IO Output current Measured at 1 V from rail 25°C ±80 mA AVD Large-signal differential voltage VIC = 2.5 V, R L = 10 kΩ, 25°C 92 109 dBAVD Large-signal differential voltage amplification VIC = 2.5 V, VO = 1 V to 4 V R L = 10 kΩ, Full range 90 dB ri(d) Differential input resistance 25°C 109 Ω ci(c) Common-mode input capacitance f = 10 kHz 25°C 7 pF zo Closed-loop output impedance f = 100 kHz, AV = 10 25°C 29 Ω CMRR Common-mode rejection ratio VICR = 0 V to 5 V, 25°C 71 85 dBCMRR Common-mode rejection ratio VICR = 0 V to 5 V, R S = 50Ω Full range 60 dB VDD = 2.7 V to 6 V,VIC = VDD /2, 25°C 80 85 dB kSVR Supply voltage rejection ratio VDD = 2.7 V to 6 V, No load VIC = VDD /2, Full range 75 dB kSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 3 V to 5 V,VIC = VDD /2, 25°C 85 95 dB ( VDD /VIO) VDD = 3 V to 5 V, No load VIC = VDD /2, Full range 80 dB IDD Supply current (per channel) VO = 2.5 V, No load, 25°C 0.55 0.65 mAIDD Supply current (per channel) V O = 2.5 V, No load, Full range 1 mA IDD(SHDN) Supply current in shutdown SHDN < 0.7 V, Per channels in 25°C 1 AIDD(SHDN ) Supply current in shutdown (TLV2460, TLV2463) SHDN < 0.7 V, Per channels in shutdown Full range 3 µA † Full range is −40°C to 125°C for the Q suffix and −55°C to 125°C for the M suffix.
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT VO(PP) = 2 V, C L = 160 pF, 25°C 1 1.6 SR Slew rate at unity gain VO(PP) = 2 V, R L = 10 kΩ C L = 160 pF, Full range 0.8 V/µs Vn Equivalent input noise voltage f = 100 Hz 25°C 14 nV/√HzVn Equivalent input noise voltage f = 1 kHz 25°C 11 nV/√Hz In Equivalent input noise current f = 100 Hz 25°C 0.13 pA/√Hz VO(PP) = 4 V, AV = 1 0.004% THD + N Total harmonic distortion plus noise VO(PP) = 4 V, R L = 10 kΩ, f = 10 kHz AV = 10 25°C 0.01%THD + N Total harmonic distortion plus noiseR L = 10 kΩ, f = 10 kHz AV = 100 25 C 0.04% Both channels 7.6 t(on) Amplifier turnon time A V = 1, RL = 10 kΩ Channel 1 only, Channel 2 on 25°C 7.65 µst(on) Amplifier turnon time AV = 1, RL = 10 kΩ Channel 2 only, Channel 1 on 25 C 7.25 µs Both channels 333 t(off) Amplifier turnoff time A V = 1, RL = 10 kΩ Channel 1 only, Channel 2 on 25°C 328 nst(off) Amplifier turnoff time AV = 1, RL = 10 kΩ Channel 2 only, Channel 1 on 25 C 329 ns Gain-bandwidth product f = 10 kHz, C L = 160 pF R L = 10 kΩ, 25°C 6.4 MHz V(STEP)PP = 2 V, AV = −1, 0.1% 1.53 ts Settling time AV = −1, C L = 10 pF, R L = 10 kΩ 0.01% 25°C 1.83 sts Settling time V(STEP)PP = 2 V, AV = −1, 0.1% 25°C 3.13 µs AV = −1, C L = 56 pF, R L = 10 kΩ 0.01% 3.33 φm Phase margin at unity gain R L = 10 kΩ, C L = 160 pF 25°C 45° Gain margin R L = 10 kΩ, C L = 160 pF 25°C 7 dB † Full range is −40°C to 125°C for the Q suffix and −55°C to 125°C for the M suffix.
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage vs Common-mode input voltage 1, 2 IIB Input bias current vs Free-air temperature 3, 4 IIO Input offset current vs Free-air temperature 3, 4 VOH High-level output voltage vs High-level output current 5, 6 VOL Low-level output voltage vs Low-level output current 7, 8 VO(PP) Peak-to-peak output voltage vs Frequency 9, 10 Open-loop gain vs Frequency 11, 12 Phase vs Frequency 11, 12 AVD Differential voltage amplification vs Load resistance 13 Capacitive load vs Load resistance 14 Zo Output impedance vs Frequency 15, 16 CMRR Common-mode rejection ratio vs Frequency 17 kSVR Supply-voltage rejection ratio vs Frequency 18, 19 IDD Supply current vs Supply voltage 20 IDD Supply current vs Free-air temperature 21 Amplifier turnon characteristics 22 Amplifier turnoff characteristics 23 Supply current turnon 24 Supply current turnoff 25 Shutdown supply current vs Free-air temperature 26 SR Slew rate vs Supply voltage 27 Vn Equivalent input noise voltage vs Frequency 28, 29 Vn Equivalent input noise voltage vs Common-mode input voltage 30, 31 THD Total harmonic distortion vs Frequency 32, 33 THD+N Total harmonic distortion plus noise vs Peak-to-peak signal amplitude 34, 35 vs Frequency 11, 12 φm Phase margin vs Load capacitance 36φm Phase margin vs Free-air temperature 37 Gain bandwidth product vs Supply voltage 38 Gain bandwidth product vs Free-air temperature 39 Large signal follower 40, 41 Small signal follower 42, 43 Inverting large signal 44, 45 Inverting small signal 46, 47
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
−0.2 −0.6 −0.4 −0.8 VICR − Common-Mode Input Voltage − V INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 10.5 1.5 30 2 2.5 VDD = 3 V TA = 25°C − Input Offset Voltage − mVVIO 0.8 0.4 0.6 0.2 Figure 3 −0.2 −0.6 −0.4 −0.8 VICR − Common-Mode Input Voltage − V INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 213504 VDD = 5 V TA = 25°C − Input Offset Voltage − mVVIO 0.8 0.4 0.6 0.2 Figure 4 TA − Free-Air Temperature − °C INPUT BIAS AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE 2.5 1.5 0.5 −0.5 −35 5 −15 25 125 4.5 −55 45 65 3.5 85 105 VDD = 3 V VI = 1.5 V IIB and IIO − Input Bias and Input Offset Current − nA IIB IIO Figure 5 TA − Free-Air Temperature − °C INPUT BIAS AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE −35 5 −15 25 125−55 45 65 85 105 IIB and IIO − Input Bias and Input Offset Current − nA IIB IIO VDD = 5 V VI = 2.5 V
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY 10k 100k 10M f − Frequency − Hz 2.5 1.5 0.5 VO(PP) − Peak-to-Peak Output Voltage − V VDD = 3 V AV = −10 THD = 1% R L = 10 kΩ Figure 11 PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY 10k 100k 10M f − Frequency − Hz 2.5 1.5 0.5 VO(PP) − Peak-to-Peak Output Voltage − V VDD = 5 V AV = −10 THD = 1% R L = 10 kΩ 3.5 5.5 4.5 OPEN-LOOP GAIN AND PHASE vs FREQUENCY −20 100 10k f − Frequency − Hz −10 1k 100k 1M −140° −200° −120° −100° −80° 100 −60° −40° −20° 20° 40° −180° −160° Open-Loop Gain − dB Phase 10M AVD Phase VDD = ±1.5 V R L = 10 kΩ C L = 0 TA = 25°C Figure 12
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
f − Frequency − Hz 0.1 0.01 1000 AV = 100 100 1k 10k 10M 1M100k − Output Impedance −Zo Ω 100 VDD = ±1.5 V TA = 25°C AV = 10 AV = 1 Figure 17 OUTPUT IMPEDANCE vs FREQUENCY f − Frequency − Hz 0.1 0.01 1000 AV = 100 100 1k 10k 10M 1M100k − Output Impedance −Zo Ω 100 VDD = ±2.5 V TA = 25°C AV = 10 AV = 1 CMRR − Common-Mode Rejection Ratio − dB COMMON-MODE REJECTION RATIO vs FREQUENCY f − Frequency − Hz 10 1k 10k 10M 1M100k VDD = 5 V VIC = 2.5 V 100 VDD = 3 V VIC = 1.5 V Figure 18
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t − Time − µs AMPLIFIER WITH A SHUTDOWN PULSE TURNON CHARACTERISTICS −3 1 −1 3 9 V SD − Shutdown Voltage − V VDD = 5 V R L = 10 kΩ AV = 1 TA = 25°C Shutdown Pin Amplifier Output Figure 24 t − Time − µs AMPLIFIER WITH A SHUTDOWN PULSE TURNOFF CHARACTERISTICS −3 1 −1 3 V SD − Shutdown Voltage − V VDD = 5 V R L = 10 kΩ AV = 1 TA = 25°C Shutdown Pin Amplifier Output VDD = 5 V VI = 2.5 V AV = 1 TA = 25°C 0.4 −0.2 0.2 −0.4 −0.2 0 0.6 t − Time − µs 0.40.2 SUPPLY CURRENT WITH A SHUTDOWN PULSE TURNON CHARACTERISTICS 0.8 0.6 Supply Current Shutdown Pin IDD − Supply Current − mA 4.5 5.5 2.5 3.5 0.5 1.5 −0.5 VSD − Shutdown Voltage − V Figure 25
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY 100 1k 100k f − Frequency − Hz 10k nV/ Hz− Equivalent Input Noise Voltage −Vn VDD = 3 V AV = 10 VI = 1.5 V TA = 25°C Figure 30 EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY 100 1k 100k f − Frequency − Hz 10k nV/ Hz− Equivalent Input Noise Voltage −Vn VDD = 5 V AV = 10 VI = 2.5 V TA = 25°C Figure 31 VICR − Common-Mode Input Voltage − V EQUIVALENT INPUT NOISE VOLTAGE vs COMMON-MODE INPUT VOLTAGE 0.5 1.5 3 0 2 2.5 VDD = 3 V AV = 10 f = 1 kHz TA = 25°C nV/ Hz− Equivalent Input Noise Voltage −Vn Figure 32 VICR − Common-Mode Input Voltage − V EQUIVALENT INPUT NOISE VOLTAGE vs COMMON-MODE INPUT VOLTAGE 0 45 VDD = 5 V AV = 10 f = 1 kHz TA = 25°C nV/ Hz− Equivalent Input Noise Voltage −Vn
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C L − Load Capacitance − pF PHASE MARGIN vs LOAD CAPACITANCE 100 1k 100 k 10 10k mφ − Phase Margin − degrees VDD = ±2.5 V TA = 25°C R L = 10 kΩ R null = 50 Ω R null = 20 Ω R null = 0 Ω Figure 38 TA − Free-Air Temperature − °C PHASE MARGIN vs FREE-AIR TEMPERATURE −35 5 −15 25 125−55 45 65 R L = 10 kΩ C L = 160 pF 85 105 VDD = ±2.5 V VDD = ±1.5 V mφ − Phase Margin − degrees Figure 39 VDD − Supply Voltage − V GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE 2.5 3 3.5 4 5.5 6 54.5 4.5 3.5 4.75 4.25 3.75 Gain Bandwidth Product − MHz C L = 160 pF R L = 10 kΩ f = 10 kHz TA = 25°C Figure 40 TA − Free-Air Temperature − °C GAIN BANDWIDTH PRODUCT vs FREE-AIR TEMPERATURE 4.5 3.5 −35 5 4.25 3.75 3.25 −15 25 125−55 45 65 R L = 10 kΩ C L = 160 pF 85 105 VDD = ±2.5 V VDD = ±1.5 V 4.75 Gain Bandwidth Product − MHz
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VO − Voltage − V VDD = 3 V VI(PP) = 1 V VI = 1.5 V R L = 10 kΩ C L = 160 pF AV = −1 TA = 25°C 1.1 0.5 0.9 0.7 −0.2 0 0.2 0.4 1 t − Time − µs 0.80.6 1.2 1.4 INVERTING LARGE SIGNAL 1.9 1.5 1.7 1.3 1.6 1.8 2.3
2.1 Input
VDD = 5 V VI(PP) = 2 V VI = 2.5 V R L = 10 kΩ C L = 160 pF AV = −1 TA = 25°C 2.5 1.5 −0.2 0 0.2 0.4 1 t − Time − µs 0.80.6 1.2 1.4 INVERTING LARGE SIGNAL 3.5 1.6 1.8 Input Output VO − Voltage − V Figure 47 VO − Voltage − V 1.5 1.4 1.45 −0.2 0 0.2 0.4 1 t − Time − µs 0.80.6 1.2 1.4 INVERTING SMALL SIGNAL 1.6 1.55 Input Output 1.6 1.8 VDD = 3 V VI(PP) = 100 mV VI = 1.5 V R L = 10 kΩ C L = 160 pF AV = −1 TA = 25°C Figure 48 VO − Voltage − V 2.5 2.4 2.45 −0.2 0 0.2 0.4 1 t − Time − µs 0.80.6 1.2 1.4 INVERTING SMALL SIGNAL 2.6 2.55 Input Output 1.6 1.8 VDD = 5 V VI(PP) = 100 mV VI = 2.5 V R L = 10 kΩ C L = 160 pF AV = −1 TA = 25°C
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 51). VI VO R G R F f–3dB /C00431 2/C0112R1C1 V O V I /C0043/C04661 /C0041 R F R G /C0467/C04661 1 /C0041sR1C1 /C0467 Figure 52. Single-Pole Low-Pass Filter task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. Figure 53. 2-Pole Low-Pass Sallen-Key Filter
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Two members of the TLV246x family (TLV2460/3) have a shutdown terminal for conserving battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.3 µA/channel, the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to V DD /2. Therefore, when operating the device with split supply voltages (e.g. ±2.5 V), the shutdown terminal needs to be pulled to VDD − (not GND) to disable the operational amplifier. The amplifier’s output with a shutdown pulse is shown in Figures 22, 23, 24, and 25. The amplifier is powered with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the single, dual, and quad are listed in the data tables. circuit layout considerations To achieve the levels of high performance of the TLV246x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. /C0068Ground planes − It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. /C0068Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. /C0068Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. /C0068Short trace runs/compact part placements − Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. /C0068Surface-mount passive components − Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible.
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
general power dissipation considerations For a given θJA, the maximum power dissipation is shown in Figure 53 and is calculated by the following formula: P D /C0043/C0466 TMAX –TA /C0113JA /C0467 Where: PD = Maximum power dissipation of THS246x IC (watts) TMAX = Absolute maximum junction temperature (150°C) TA = Free-ambient air temperature (°C) θJA = θJC + θCA θJC = Thermal coefficient from junction to case θCA = Thermal coefficient from case to ambient air (°C/W) 0.75 0.5 −55 −40 −25 −10 5 Maximum Power Dissipation − W 1.25 1.5 MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 1.75 20 35 50 0.25 TA − Free-Air Temperature − °C 65 80 95 110 125 Low-K Test PCB θJA = 260°C/W TJ = 150°CPDIP Package Low-K Test PCB θJA = 104°C/W Low-K Test PCB θJA = 176°C/W Low-K Test PCB θJA = 324°C/W NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 54. Maximum Power Dissipation vs Free-Air Temperature
/C0084/C0076/C0086/C0050/C0052/C0054/C0048/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0049/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0050/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0051/C0065/C0262/C0069/C0080 /C0084/C0076/C0086/C0050/C0052/C0054/C0052/C0065/C0262/C0069/C0080 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0073/C0078/C0080/C0085/C0084/C0047/C0079/C0085/C0084/C0080/C0085/C0084 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0072/C0085/C0084/C0068/C0079/C0087/C0078 /C0261 SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Macromodel information provided was derived using MicrosimParts Release 8, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 2) and subcircuit in Figure 54 are generated using the TLV246x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): /C0068Maximum positive output voltage swing /C0068Maximum negative output voltage swing /C0068Slew rate /C0068Quiescent power dissipation /C0068Input bias current /C0068Open-loop voltage amplification /C0068Unity-gain frequency /C0068Common-mode rejection ratio /C0068Phase margin /C0068DC output resistance /C0068AC output resistance /C0068Short-circuit output current limit Journal of Solid-State Circuits, SC-9, 353 (1974). − + .SUBCKT TLV246X 1 2 3 4 5 C1 11 12 2.46034E−12 C2 6 7 10.0000E−12 CSS 10 99 443.21E−15 DC 5 53 DY DE 54 5 DY DLP 90 91 DX DLN 92 90 DX D P 43D X FB 7 99 POLY (5) VB VC VE VLP + VLN 0 21.600E6 −1E3 1E3 22E6 −22E6 GA 6 0 11 12 345.26E−6 GCM 0 6 10 99 15.4226E−9 ISS 10 4 DC 18.850E−6 HLIM 90 0 VLIM 1K J1 11 2 10 JX1 J2 12 1 10 JX2 R2 6 9 100.00E3 RD1 3 11 2.8964E3 RD2 3 12 2.8964E3 R01 8 5 5.6000 R02 7 99 6.2000 RP 3 4 8.9127 RSS 10 99 10.610E6 VB 9 0 DC 0 VC 3 53 DC .7836 VE 54 4 DC .7436 VLIM 7 8 DC 0 VLP 91 0 DC 117 VLN 0 92 DC 117 .MODEL DX D (IS=800.00E−18) .MODEL DY D (IS=800.00E−18 Rs = 1m Cjo=10p) .MODEL JX1 NJF (IS=1.0000E−12 BETA=6.3239E−3 + VTO=−1) .MODEL JX2 NJF (IS=1.0000E−12 BETA=6.3239E−3 + VTO=−1) .ENDS VDD+ RP IN − IN+ GND RD1 J1 J2 RSSISS RD2 DP VD DC EGND FB HLIM DLP DLN VLNVLP CSS VE DE OUT R2 6 VB GA VLIM RO1 RO2 GCM Figure 55. Boyle Macromodels and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation.
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 54. Boyle Macromodels and Subcircuit (Continued)
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLV2462AMDREP Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 2462AM TLV2462AMDREP.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 2462AM TLV2462AQDREP Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2462AE TLV2462AQDREP.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2462AE TLV2464AMDREP Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 V2464AME TLV2464AMDREP.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 V2464AME TLV2464AMDREPG4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 V2464AME TLV2464AMPWREP Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 2464AME TLV2464AMPWREP.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 2464AME V62/03619-03XE Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2462AE V62/03619-06XE Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 2462AM V62/03619-07YE Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 V2464AME V62/03619-07ZE Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 2464AME (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 1
www.ti.com 23-May-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV2462A-EP, TLV2462A-EP-Q, TLV2464A-EP :
- Catalog : TLV2462A , TLV2464A
- Automotive : TLV2462A-Q1 , TLV2462A-Q1 , TLV2464A-Q1
- Enhanced Product : TLV2462A-EP
- Military : TLV2462AM NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
- Enhanced Product - Supports Defense, Aerospace and Medical Applications
- Military - QML certified for Military and Defense Applications Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2462AMDREP SOIC D 8 2500 353.0 353.0 32.0 TLV2462AQDREP SOIC D 8 2500 340.5 338.1 20.6 TLV2464AMDREP SOIC D 14 2500 353.0 353.0 32.0 TLV2464AMPWREP TSSOP PW 14 2000 356.0 356.0 35.0 Pack Materials-Page 2
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