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TLC227X-EP TI1 | Alldatasheet

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/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131B − JULY 2002 − REVISED DECEMBER 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Controlled Baseline − One Assembly/Test Site, One Fabrication Site /C0068Extended Temperature Performance of −55°C to 125°C /C0068Enhanced Diminishing Manufacturing Sources (DMS) Support /C0068Enhanced Product Change Notification /C0068Qualification Pedigree† /C0068Output Swing Includes Both Supply Rails † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. /C0068Low Noise ...9 n V /√Hz Typ at f = 1 kHz /C0068Low Input Bias Current...1 p A T y p /C0068Fully Specified for Both Single-Supply and Split-Supply Operation /C0068Common-Mode Input Voltage Range Includes Negative Rail /C0068High-Gain Bandwidth. . . 2.2 MHz Typ /C0068High Slew Rate. . . 3.6 V/µs Typ /C0068Low Input Offset Voltage 950 µV Max at TA = 25°C /C0068Macromodel Included /C0068Performance Upgrades for the TS272, TS274, TLC272, and TLC274

description

The TLC2272A and TLC2274A are dual and quadruple operational amplifiers from Texas Instruments. Both devices exhibit rail-to-rail output performance for increased dynamic range in single- or split-supply applications. The TLC227xA family offers 2 MHz of bandwidth and 3 V/µs of slew rate for higher speed applications. These devices offer comparable ac performance while having better noise, input offset voltage, and power dissipation than existing CMOS operational amplifiers. The TLC227xA has a noise voltage of 9 nV/√Hz , two times lower than competitive solutions. The TLC227xA, exhibiting high input impedance and low noise, is excellent for small-signal conditioning for high-impedance sources, such as piezoelectric transducers. Because of the micro- power dissipation levels, these devices work well in hand-held monitoring and remote-sensing applications. In addition, the rail-to-rail output feature, with single- or split-supplies, makes this family a great choice when interfacing with analog-to-digital converters (ADCs). For precision applications, the TLC227xA family has a maximum input offset voltage of 950 µV. This family is fully characterized at 5 V and ±5 V. The TLC2272/4 also makes great upgrades to the TLC272/4 or TS272/4 in standard designs. They offer increased output dynamic range, lower noise voltage, and lower input offset voltage. This enhanced feature set allows them to be used in a wider range of applications. Copyright  2003 Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 /C0261 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Advanced LinCMOS is a trademark of Texas Instruments. |VDD ±| − Supply Voltage − V 46 8 10 12 14 16 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE TA = 25°C IO = ±50 µA IO = ±500 µA V(OPP) − Maximum Peak-to-Peak Output Voltage − VV O(PP) Copyright  2002 − 2003, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 /C0261 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Advanced LinCMOS is a trademark of Texas Instruments.

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

25°C SMALL OUTLINE (D) TSSOP (PW) −55°C to 125°C 950 µV TLC2272AMDREP TLC2272AMPWREP−55°C to 125°C 950 µV 2.5 mV TLC2272AMDREP TLC2272MDREP TLC2272AMPWREP TLC2272MPWREP −55°C to 125°C 950 µV TLC2274AMDREP TLC2274AMPWREP−55°C to 125°C 950 µV 2.5 mV TLC2274AMDREP TLC2274MDREP TLC2274AMPWREP TLC2274MPWREP 1OUT 1IN− 1IN+ VDD− /GND VDD+ 2OUT 2IN− 2IN+ TLC2272 D OR PW PACKAGE (TOP VIEW) 1OUT 1IN− 1IN+ VDD+ 2IN+ 2IN− 2OUT 4OUT 4IN− 4IN+ VDD− 3IN+ 3IN− 3OUT TLC2274 D OR PW PACKAGE (TOP VIEW)

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 equivalent schematic (each amplifier) Q3 Q6 Q9 Q12 Q14 Q16 Q2 Q5 Q7 Q8 Q10 Q11 Q17Q15Q13 Q4Q1 VDD+ IN+ IN− R3 R4 R1 R2 OUT VDD− ACTUAL DEVICE COMPONENT COUNT † COMPONENT TLC2272 TLC2274 Transistors 38 76 Resistors 26 52 Diodes 9 18 Capacitors 3 6 † Includes both amplifiers and all ESD, bias, and trim circuitry

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD −. 2. Differential voltages are at IN+ with respect to IN−. Excessive current will flow if input is brought below VDD− − 0.3 V. 3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. 4. Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C TA = 125°CPACKAGE TA ≤ 25C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70C POWER RATING TA = 85C POWER RATING TA = 125C POWER RATING D-8 725 mW 5.8 mW/°C 464 mW 337 mW 145 mW D-14 950 mW 7.6 mW/ °C 608 mW 494 mW 190 mW PW-8 525 mW 4.2 mW/ °C 336 mW 273 mW 105 mW PW-14 700 mW 5.6 mW/°C 448 mW 364 mW — recommended operating conditions MIN MAX UNITMIN MAX UNIT Supply voltage, VDD ± ±2.2 ±8 V Input voltage, VI VDD− VDD+ −1.5 V Common-mode input voltage, VIC VDD− VDD+ −1.5 V Operating free-air temperature, TA −55 125 °C

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC2272-EP electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † TLC2272-EP TLC2272A-EP UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT VIO Input offset voltage 25°C 300 2500 300 950 µVVIO Input offset voltage Full range 3000 1500 µV αVIO Temperature coefficient 25°C 2 2 µV/°CαVIO Temperature coefficient of input offset voltage 25 C to 125°C 2 2 µV/°C Input offset voltage long- term drift (see Note 5) VIC = 0 V, VO = 0 V, VDD ± = ±2.5 V, R S = 50 Ω 25°C 0.002 0.002 µV/mo IIO Input offset current VO = 0 V, R S = 50 Ω 25°C 0.5 60 0.5 60 pAIIO Input offset current Full range 800 800 pA IIB Input bias current 25°C 1 60 1 60 pAIIB Input bias current Full range 800 800 pA VICR Common-mode input R S = 50 Ω |VIO |≤ 5 mV 25°C 0 to 4 −0.3 to 4.2 to 4 −0.3 to 4.2 VVICR Common-mode input voltage R S = 50 Ω, |VIO | ≤ 5 mV Full range 0 to 3.5 to 3.5 V IOH = −20 µA 25°C 4.99 4.99 High-level output IOH = −200 µA 25°C 4.85 4.93 4.85 4.93 VOH High-level output voltage IOH = −200 µA Full range 4.85 4.85 VVOH voltage IOH = −1 mA 25°C 4.25 4.65 4.25 4.65 V IOH = −1 mA Full range 4.25 4.25 VIC = 2.5 V, IOL = 50 µA 25°C 0.01 0.01 VIC = 2.5 V, IOL = 500 µA 25°C 0.09 0.15 0.09 0.15 VOL Low-level output voltage VIC = 2.5 V, IOL = 500 µA Full range 0.15 0.15 VVOL Low-level output voltage VIC = 2.5 V, IOL = 5 /C0109A 25°C 0.9 1.5 0.9 1.5 V VIC = 2.5 V, IOL = 5 /C0109A Full range 1.5 1.5 Large-signal VIC = 2.5 V, R L = 10 kΩ‡ 25°C 10 35 10 35 AVD Large-signal differential voltage VIC = 2.5 V, VO = 1 V to 4 V R L = 10 kΩ‡ Full range 10 10 V/mVAVD differential voltage amplification VO = 1 V to 4 V R L = 1 mΩ‡ 25°C 175 175 V/mV rid Differential input resistance 25°C 1012 1012 Ω ri Common-mode input resistance 25°C 1012 1012 Ω ci Common-mode input capacitance f = 10 kHz, P package 25°C 8 8 pF zo Closed-loop output impedance f = 1 MHz, AV = 10 25°C 140 140 Ω CMRR Common-mode rejection VIC = 0 V to 2.7 V, 25°C 70 75 70 75 dBCMRR Common-mode rejection ratio VIC = 0 V to 2.7 V, VO = 2.5 V, R S = 50Ω Full range 70 70 dB kSVR Supply-voltage rejectionVDD = 4.4 V to 16 V, 25°C 80 95 80 95 dBkSVR Supply-voltage rejection ratio (∆VDD/ ∆VIO) VDD = 4.4 V to 16 V, VIC = VDD /2, No load Full range 80 80 dB IDD Supply current VO = 2.5 V, No load 25°C 2.2 3 2.2 3 mAIDD Supply current VO = 2.5 V, No load Full range 3 3 mA † Full range is −55°C to 125°C for M level part. ‡ Referenced to 2.5 V NOTE 5: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2272-EP operating characteristics at specified free-air temperature, VDD = 5 V PARAMETER TEST CONDITIONS TA † TLC2272-EP TLC2272A-EP UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT Slew rate at VO = 1.25 V to 2.75 V, 25°C 2.3 3.6 2.3 3.6 SR Slew rate at unity gain VO = 1.25 V to 2.75 V, R L = 10 kΩ‡, C L = 100 pF‡ Full 1.7 1.7 V/µsSR unity gain R L = 10 kΩ‡, C L = 100 pF‡ Full range 1.7 1.7 V/µs Vn Equivalent inputf = 10 Hz 25°C 50 50 nV/√HzVn Equivalent input noise voltage f = 1 kHz 25°C 9 9 nV/√Hz VNPP Peak-to-peak equivalent input f = 0.1 Hz to 1 Hz 25°C 1 1 VVNPP equivalent input noise voltage f = 0.1 Hz to 10 Hz 25°C 1.4 1.4 µV In Equivalent input noise current 25°C 0.6 0.6 fA/√Hz Total harmonic VO = 0.5 V to 2.5 V,AV = 1 0.0013% 0.0013% THD + N Total harmonic distortion plus noise VO = 0.5 V to 2.5 V, f = 20 kHz, R = 10 k‡, AV = 10 25°C 0.004% 0.004%THD + N distortion plus noise f = 20 kHz, R L = 10 kΩ‡, AV = 100 25 C 0.03% 0.03% Gain-bandwidth f = 10 kHz, R L = 10 kΩ‡, 25°C 2.18 2.18 MHzGain-bandwidth product f = 10 kHz, C L = 100 pF‡ R L = 10 kΩ‡, 25°C 2.18 2.18 MHz BOM Maximum output- VO(PP) = 2 V, AV = 1, ‡ 25°C 1 1 MHzBOM Maximum output- swing bandwidth VO(PP) = 2 V, R L = 10 kΩ‡, AV = 1, C L = 100 pF‡ 25°C 1 1 MHz ts Settling time AV = −1, Step = 0.5 V to 2.5 V, To 0.1% 25°C 1.5 1.5 sts Settling time Step = 0.5 V to 2.5 V, R L = 10 kΩ‡, ‡ To 0.01% 25°C 2.6 2.6 µss R L = 10 kΩ‡, C L = 100 pF‡ To 0.01% 2.6 2.6 φm Phase margin at unity gain R L = 10 kΩ‡, C L = 100 pF‡ 25°C 50° 50° Gain margin R L = 10 kΩ‡, C L = 100 pF‡ 25°C 10 10 dB † Full range is −55°C to 125°C for M level part. ‡ Referenced to 2.5 V

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC2272-EP electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † TLC2272-EP TLC2272A-EP UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT VIO Input offset voltage 25°C 300 2500 300 950 µVVIO Input offset voltage Full range 3000 1500 µV αVIO Temperature coefficient of 25°C 2 2 µV/°CαVIO Temperature coefficient of input offset voltage 25 C to 125°C 2 2 µV/°C Input offset voltage long-term drift (see Note 5) VIC = 0 V, R S = 50 Ω VO = 0 V, 25°C 0.002 0.002 µV/mo IIO Input offset current S 25°C 0.5 60 0.5 60 pAIIO Input offset current Full range 800 800 pA IIB Input bias current 25°C 1 60 1 60 pAIIB Input bias current Full range 800 800 pA Common-mode input 25°C −5 to 4 −5.3 to 4.2 to 4 −5.3 to 4.2VICR Common-mode input R S = 50 Ω |VIO |≤ 5 mV 25 C to 4 to 4.2 to 4 to 4.2 VVICR Common-mode input voltage R S = 50 Ω, |VIO | ≤ 5 mV Full range −5 −5 VVICR voltage R S = 50 , |VIO | 5 mV Full range −5 to 3.5 to 3.5 V Full range to 3.5 to 3.5 IO = −20 µA 25°C 4.99 4.99 Maximum positive peak IO = −200 µA 25°C 4.85 4.93 4.85 4.93 VOM+ Maximum positive peak output voltage IO = −200 µA Full range 4.85 4.85 VVOM+ output voltage IO = −1 mA 25°C 4.25 4.65 4.25 4.65 V IO = −1 mA Full range 4.25 4.25 VIC = 0 V, IO = 50 µA 25°C −4.99 −4.99 Maximum negative peak VIC = 0 V, IO = 500 µA VOM− Maximum negative peak output voltage VIC = 0 V, IO = 500 µA Full range −4.85 −4.85 VVOM− output voltage VIC = 0 V, IO = 5 /C0109A V VIC = 0 V, IO = 5 /C0109A Full range −3.5 −3.5 Large-signal differential R L = 10 kΩ 25°C 20 50 20 50 AVD Large-signal differential voltage amplification VO = ±4 V R L = 10 kΩ Full range 20 20 V/mVAVD voltage amplification VO = ±4 V R L = 1 mΩ 25°C 300 300 V/mV rid Differential input resistance 25°C 1012 1012 Ω ri Common-mode input resistance 25°C 1012 1012 Ω ci Common-mode input capacitance f = 10 kHz, P package 25°C 8 8 pF zo Closed-loop output impedance f = 1 MHz, AV = 10 25°C 130 130 Ω CMRR Common-mode rejection VIC = −5 V to 2.7 V, 25°C 75 80 75 80 dBCMRR Common-mode rejection ratio VIC = −5 V to 2.7 V, VO = 0 V, R S = 50Ω Full range 75 75 dB kSVR Supply-voltage rejectionVDD = ±2.2 V to ±8 V, 25°C 80 95 80 95 dBkSVR Supply-voltage rejection ratio (∆VDD ±/∆VIO) VDD = ±2.2 V to ±8 V, VIC = 0 V, No load Full range 80 80 dB IDD Supply current VO = 2.5 V, No load 25°C 2.4 3 2.4 3 mAIDD Supply current VO = 2.5 V, No load Full range 3 3 mA † Full range is −55°C to 125°C for M level part. NOTE 5: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2272-EP operating characteristics at specified free-air temperature, VDD ± = ±5 V PARAMETER TEST CONDITIONS TA † TLC2272-EP TLC2272A-EP UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT Slew rate at VO = ±1 V, R L = 10 kΩ, 25°C 2.3 3.6 2.3 3.6 SR Slew rate at unity gain VO = ±1 V, R L = 10 kΩ, C L = 100 pF Full 1.7 1.7 V/µsSR unity gain C L = 100 pF Full range 1.7 1.7 V/µs Vn Equivalent inputf = 10 Hz 25°C 50 50 nV/√HzVn Equivalent input noise voltage f = 1 kHz 25°C 9 9 nV/√Hz VNPP Peak-to-peak equivalent input f = 0.1 Hz to 1 Hz 25°C 1 1 VVNPP equivalent input noise voltage f = 0.1 Hz to 10 Hz 25°C 1.4 1.4 µV In Equivalent input noise current 25°C 0.6 0.6 fA/√Hz Total harmonic VO = ±2.3 V AV = 1 0.0011% 0.0011% THD + N Total harmonic distortion plus noise VO = ±2.3 V R L = 10 kΩ, f = 20 kHz AV = 10 25°C 0.004% 0.004%THD + N distortion plus noise R L = 10 kΩ, f = 20 kHz AV = 100 25 C 0.03% 0.03% Gain-bandwidth f = 10 kHz, R L = 10 kΩ, 25°C 2.25 2.25 MHzGain-bandwidth product f = 10 kHz, C L = 100 pF R L = 10 kΩ, 25°C 2.25 2.25 MHz BOM Maximum output-swing VO(PP) = 4.6 V, AV = 1, 25°C 0.54 0.54 MHzBOM output-swing bandwidth VO(PP) = 4.6 V, R L = 10 kΩ, AV = 1, C L = 100 pF 25°C 0.54 0.54 MHz ts Settling time AV = −1, Step = −2.3 V to 2.3 V,To 0.1% 25°C 1.5 1.5 sts Settling time Step = −2.3 V to 2.3 V, R L = 10 kΩ, To 0.01% 25°C 3.2 3.2 µss R L = 10 kΩ, C L = 100 pF To 0.01% 3.2 3.2 φm Phase margin at unity gain R L = 10 kΩ, C L = 100 pF 25°C 52° 52° Gain margin R L = 10 kΩ, C L = 100 pF 25°C 10 10 dB † Full range is −55°C to 125°C for M level part.

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC2274-EP electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † TLC2274-EP TLC2274A-EP UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT VIO Input offset voltage 25°C 300 2500 300 950 µVVIO Input offset voltage Full range 3000 1500 µV αVIO Temperature coefficient 25°C 2 2 µV/°CαVIO Temperature coefficient of input offset voltage 25 C to 125°C 2 2 µV/°C Input offset voltage long-term drift (see Note 5) VDD ± = ±2.5 V, VO = 0 V, VIC = 0 V, R S = 50 Ω 25°C 0.002 0.002 µV/mo IIO Input offset current O S 25°C 0.5 60 0.5 60 pAIIO Input offset current Full range 800 800 pA IIB Input bias current 25°C 1 60 1 60 pAIIB Input bias current Full range 800 800 pA 25 C 0 −0.3 0 −0.3 Common-mode input 25°C 0 to 4 −0.3 to 4.2 to 4 −0.3 to 4.2VICR Common-mode input R S = 50 Ω |VIO |≤ 5 mV 25 C to 4 to 4.2 to 4 to 4.2 VVICR Common-mode input voltage R S = 50 Ω, |VIO | ≤ 5 mV Full range 0 to 0 to VVICR voltage R S = 50 , |VIO | 5 mV Full range 0 to 3.5 0 to 3.5 V Full range 3.5 3.5 IOH = −20 µA 25°C 4.99 4.99 High-level output IOH = −200 µA 25°C 4.85 4.93 4.85 4.93 VOH High-level output voltage IOH = −200 µA Full range 4.85 4.85 VVOH voltage IOH = −1 mA 25°C 4.25 4.65 4.25 4.65 V IOH = −1 mA Full range 4.25 4.25 VIC = 2.5 V, IOL = 50 µA 25°C 0.01 0.01 VOL Low-level output voltage VIC = 2.5 V, IOL = 500 µA Full range 0.15 0.15 VVOL voltage VIC = 2.5 V, IOL = 5 /C0109A 25°C 0.9 1.5 0.9 1.5 V VIC = 2.5 V, IOL = 5 /C0109A Full range 1.5 1.5 Large-signal differentialVIC = 2.5 V, R L = 10 kΩ‡ 25°C 10 35 10 35 AVD Large-signal differential voltage amplification VIC = 2.5 V, VO = 1 V to 4 V R L = 10 kΩ‡ Full range 10 10 V/mVAVD voltage amplificationVO = 1 V to 4 V R L = 1 MΩ‡ 25°C 175 175 V/mV rid Differential input resistance 25°C 1012 1012 Ω ri Common-mode input resistance 25°C 1012 1012 Ω ci Common-mode input capacitance f = 10 kHz, N package 25°C 8 8 pF zo Closed-loop output impedance f = 1 MHz, AV = 10 25°C 140 140 Ω CMRR Common-mode VIC = 0 V to 2.7 V, 25°C 70 75 70 75 dBCMRR Common-mode rejection ratio VIC = 0 V to 2.7 V, VO = 2.5 V, R S = 50Ω Full range 70 70 dB kSVR Supply-voltage rejectionVDD = 4.4 V to 16 V, 25°C 80 95 80 95 dBkSVR Supply-voltage rejection ratio (∆VDD /∆VIO) VDD = 4.4 V to 16 V, VIC = VDD /2, No load Full range 80 80 dB IDD Supply current VO = 2.5 V, No load 25°C 4.4 6 4.4 6 mAIDD Supply current VO = 2.5 V, No load Full range 6 6 mA † Full range is −55°C to 125°C for M level part. ‡ Referenced to 2.5 V NOTE 5: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2274-EP operating characteristics at specified free-air temperature, VDD = 5 V PARAMETER TEST CONDITIONS TA † TLC2274-EP TLC2274A-EP UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT SR Slew rate at unity gain VO = 0.5 V to 2.5 V, R L = 10 kΩ‡, C L = 100 pF‡ Full 1.7 1.7 V/µsSR gain R L = 10 kΩ‡, Full range 1.7 1.7 V/µs Vn Equivalent inputf = 10 Hz 25°C 50 50 nV/√HzVn Equivalent input noise voltage f = 1 kHz 25°C 9 9 nV/√Hz VN(PP) Peak-to-peak equivalent input f = 0.1 Hz to 1 Hz 25°C 1 1 VVN(PP) equivalent input noise voltage f = 0.1 Hz to 10 Hz 25°C 1.4 1.4 µV In Equivalent input noise current 25°C 0.6 0.6 fA/√Hz Total harmonic VO = 0.5 V to 2.5 V,AV = 1 0.0013% 0.0013% THD + N Total harmonic distortion plus noise VO = 0.5 V to 2.5 V, f = 20 kHz, R = 10 k‡ AV = 10 25°C 0.004% 0.004%THD + N distortion plus noise f = 20 kHz, R L = 10 kΩ‡ AV = 100 25 C 0.03% 0.03% Gain-bandwidth f = 10 kHz, R L = 10 kΩ‡, 25°C 2.18 2.18 MHzGain-bandwidth product f = 10 kHz, C L = 100 pF‡ R L = 10 kΩ‡, 25°C 2.18 2.18 MHz BOM Maximum out- put-swing band- VO(PP) = 2 V, AV = 1, ‡ 25°C 1 1 MHzBOM put-swing band- width VO(PP) = 2 V, R L = 10 kΩ‡, AV = 1, C L = 100 pF‡ 25°C 1 1 MHz ts Settling time AV = −1, Step = 0.5 V to 2.5 V, To 0.1% 25°C 1.5 1.5 sts Settling time Step = 0.5 V to 2.5 V, R L = 10 kΩ‡, ‡ To 0.01% 25°C 2.6 2.6 µss R L = 10 kΩ‡, C L = 100 pF‡ To 0.01% 2.6 2.6 φm Phase margin at unity gain R L = 10 kΩ‡, C L = 100 pF‡ 25°C 50° 50° Gain margin R L = 10 kΩ‡, C L = 100 pF‡ 25°C 10 10 dB † Full range is −55°C to 125°C for M level part. ‡ Referenced to 2.5 V

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC2274-EP electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † TLC2274-EP TLC2274A-EP UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT VIO Input offset voltage 25°C 300 2500 300 950 VVIO Input offset voltage Full range 3000 1500 µV VIO Temperature coefficient of 25°C 2 2 V/°CαVIO Temperature coefficient of input offset voltage 25 C to 125°C 2 2 µV/°C Input offset voltage long- term drift (see Note 5) VIC = 0 V, R S = 50 Ω VO = 0 V, 25°C 0.002 0.002 µV/mo IIO Input offset current R S = 50 Ω 25°C 0.5 60 0.5 60 pAIIO Input offset current Full range 800 800 pA IIB Input bias current 25°C 1 60 1 60 pAIIB Input bias current Full range 800 800 pA −5 −5.3 −5 −5.3 Common-mode input 25°C −5 to 4 −5.3 to 4.2 to 4 −5.3 to 4.2 VICR Common-mode input R S = 50 Ω |VIO |≤ 5 mV 25°C to 4 to 4.2 to 4 to 4.2 VVICR Common-mode input voltage R S = 50 Ω, |VIO | ≤ 5 mV −5 −5 VVICR voltage R S = 50 , |VIO | 5 mV Full range −5 to 3.5 to 3.5 V Full range to 3.5 to 3.5 IO = −20 µA 25°C 4.99 4.99 Maximum positive peak IO = −200 A 25°C 4.85 4.93 4.85 4.93 VOM+ Maximum positive peak output voltage IO = −200 µA Full range 4.85 4.85 VVOM+ output voltage IO = −1 mA 25°C 4.25 4.65 4.25 4.65 V IO = −1 mA Full range 4.25 4.25 VIC = 0 V, IO = 50 µA 25°C −4.99 −4.99 Maximum negative peak VIC = 0 V, IO = 500 A VOM− Maximum negative peak output voltage VIC = 0 V, IO = 500 µA Full range −4.85 −4.85 VVOM− output voltage VIC = 0 V, IO = 5 /C0109A V VIC = 0 V, IO = 5 /C0109A Full range −3.5 −3.5 Large-signal differential R L = 10 kΩ 25°C 20 50 20 50 AVD Large-signal differential voltage amplification VO = ±4 V R L = 10 kΩ Full range 20 20 V/mVAVD voltage amplification VO = ±4 V R L = 1 MΩ 25°C 300 300 V/mV rid Differential input resistance 25°C 1012 1012 Ω ri Common-mode input resistance 25°C 1012 1012 Ω ci Common-mode input capacitance f = 10 kHz,N package 25°C 8 8 pF zo Closed-loop output impedance f = 1 MHz, AV = 10 25°C 130 130 Ω CMRR Common-mode rejection VIC = −5 V to 2.7 V 25°C 75 80 75 80 dBCMRR Common-mode rejection ratio VIC = −5 V to 2.7 V VO = 0 V, R S = 50Ω Full range 75 75 dB kSVR Supply-voltage rejectionVDD ± = ± 2.2 V to ±8 V, 25°C 80 95 80 95 dBkSVR Supply-voltage rejection ratio (∆VDD ±/∆VIO) VDD ± = ± 2.2 V to ±8 V, VIC = 0 V, No load Full range 80 80 dB IDD Supply current VO = 0 V, No load 25°C 4.8 6 4.8 6 mAIDD Supply current VO = 0 V, No load Full range 6 6 mA † Full range is −55°C to 125°C for M level part. NOTE 5: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2274-EP operating characteristics at specified free-air temperature, VDD ± = ±5 V PARAMETER TEST CONDITIONS TA † TLC2274-EP TLC2274A-EP UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT Slew rate at unityVO = ±2.3 V, R L = 10 kΩ, 25°C 2.3 3.6 2.3 3.6 SR Slew rate at unity gain VO = ±2.3 V, C L = 100 pF R L = 10 kΩ, Full 1.7 1.7 V/µsSR gain C L = 100 pF Full range 1.7 1.7 V/µs Vn Equivalent input f = 10 Hz 25°C 50 50 nV/√HzVn Equivalent input noise voltage f = 1 kHz 25°C 9 9 nV/√Hz VN(PP) Peak-to-peak equivalent input f = 0.1 Hz to 1 Hz 25°C 1 1 VVN(PP) equivalent input noise voltage f = 0.1 Hz to 10 Hz 25°C 1.4 1.4 µV In Equivalent input noise current 25°C 0.6 0.6 fA/√Hz Total harmonic VO = ±2.3 V, AV = 1 0.0011% 0.0011% THD + N Total harmonic distortion plus noise VO = ±2.3 V, R L = 10 kΩ, f = 20 kHz AV = 10 25°C 0.004% 0.004%THD + N distortion plus noise R L = 10 kΩ, f = 20 kHz AV = 100 25 C 0.03% 0.03% Gain-bandwidth f = 10 kHz, R L = 10 kΩ, 25°C 2.25 2.25 MHzGain-bandwidth product f = 10 kHz, C L = 100 pF R L = 10 kΩ, 25°C 2.25 2.25 MHz BOM Maximum output-swing VO(PP) = 4.6 V, AV = 1, 25°C 0.54 0.54 MHzBOM output-swing bandwidth VO(PP) = 4.6 V, R L = 10 kΩ, AV = 1, C L = 100 pF 25°C 0.54 0.54 MHz ts Settling time AV = −1, Step = −2.3 V to 2.3 V,To 0.1% 25°C 1.5 1.5 sts Settling time Step = −2.3 V to 2.3 V, R L = 10 kΩ, To 0.01% 25°C 3.2 3.2 µss R L = 10 kΩ, C L = 100 pF To 0.01% 3.2 3.2 φm Phase margin at unit gain R L = 10 kΩ, C L = 100 pF 25°C 52° 52° Gain margin R L = 10 kΩ, C L = 100 pF 25°C 10 10 dB † Full range is −55°C to 125°C for M level part.

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution 1 − 4VIO Input offset voltage Distribution vs Common-mode voltage 1 − 4 5, 6 αVIO Input offset voltage temperature coefficientDistribution 7 − 10 IIB/IIO Input bias and input offset current vs Free-air temperature 11 VI Input voltage vs Supply voltage 12VI Input voltage vs Supply voltage vs Free-air temperature VOH High-level output voltage vs High-level output current 14 VOL Low-level output voltage vs Low-level output current 15, 16 VOM+ Maximum positive peak output voltage vs Output current 17 VOM− Maximum negative peak output voltage vs Output current 18 VO(PP) Maximum peak-to-peak output voltage vs Frequency 19 IOS Short-circuit output current vs Supply voltage 20IOS Short-circuit output current vs Supply voltage vs Free-air temperature VO Output voltage vs Differential input voltage22, 23 Large-signal differential voltage amplificationvs Load resistance 24 AVD Large-signal differential voltage amplification and phase margin vs Frequency 25, 26 Large-signal differential voltage amplificationvs Free-air temperature 27, 28 zo Output impedance vs Frequency 29, 30 CMRR Common-mode rejection ratio vs Frequency 31CMRR Common-mode rejection ratio vs Frequency vs Free-air temperature kSVR Supply-voltage rejection ratio vs Frequency 33, 34kSVR Supply-voltage rejection ratio vs Frequency vs Free-air temperature 33, 34 IDD Supply current vs Supply voltage 36, 37IDD Supply current vs Supply voltage vs Free-air temperature 36, 37 38, 39 SR Slew rate vs Load capacitance 40SR Slew rate vs Load capacitance vs Free-air temperature Inverting large-signal pulse response 42, 43 VO Voltage-follower large-signal pulse response 44, 45 VO Inverting small-signal pulse response 46, 47 Voltage-follower small-signal pulse response 48, 49 Vn Equivalent input noise voltage vs Frequency 50, 51 Noise voltage over a 10-second period 52 Integrated noise voltage vs Frequency 53 THD + N Total harmonic distortion plus noise vs Frequency 54 Gain-bandwidth product vs Supply voltage 55Gain-bandwidth product vs Supply voltage vs Free-air temperature φm Phase margin vs Load capacitance 57 Gain margin vs Load capacitance 58 NOTE: For all graphs where VDD = 5 V, all loads are referenced to 2.5 V.

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VIO − Input Offset Voltage − mV Percentage of Amplifiers − % DISTRIBUTION OF TLC2272 INPUT OFFSET VOLTAGE

891 Amplifiers From

−0.8 −0.4

2 Wafer Lots

VDD = ±2.5 V TA = 25°C Figure 1 VIO − Input Offset Voltage − mV Percentage of Amplifiers − % DISTRIBUTION OF TLC2272 INPUT OFFSET VOLTAGE VDD = ±5 V TA = 25°C Figure 2 Figure 3 VIO − Input Offset Voltage − mV Percentage of Amplifiers − % DISTRIBUTION OF TLC2274 INPUT OFFSET VOLTAGE 0 0.4 0.8 1.2 1.6

992 Amplifiers From

VDD = ±2.5 V Figure 4 VIO − Input Offset Voltage − mV Percentage of Amplifiers − % DISTRIBUTION OF TLC2274 INPUT OFFSET VOLTAGE 0 0.4 0.8 1.2 1.6 VDD = ±5 V

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS 0.5 −1 0 1 VIO − Input Offset Voltage − mV 234 5 VIO VIC − Common-Mode Voltage − V VDD = 5 V TA = 25°C R S = 50 Ω −0.5 INPUT OFFSET VOLTAGE vs COMMON-MODE VOLTAGE Figure 5 0.5 −1 0 1 VIO − Input Offset Voltage − mV 234 5 INPUT OFFSET VOLTAGE vs COMMON-MODE VOLTAGE VIC − Common-Mode Voltage − V VIO−0.5 VDD = ±5 V TA = 25°C R S = 50 Ω Figure 6 −1 0 1 Percentage of Amplifiers − % 2345 DISTRIBUTION OF TLC2272 vs INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT † αVIO − Temperature Coefficient − µV/°C

128 Amplifiers From

VDD = ±2.5 V P Package 25°C to 125°C −5 −4 −3 −2 Figure 7 −5 −4 −3 −2 −1 0 1 Percentage of Amplifiers − % 2345 DISTRIBUTION OF TLC2272 vs INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT † αVIO − Temperature Coefficient − µV/°C VDD = ±5 V P Package 25°C to 125°C Figure 8 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Percentage of Amplifiers − % 2345 DISTRIBUTION OF TLC2274 vs INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT † αVIO − Temperature Coefficient − µV/°C VDD = ±2.5 V N Package TA = 25°C to 125°C Figure 9 Percentage of Amplifiers − % DISTRIBUTION OF TLC2274 vs INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT † αVIO − Temperature Coefficient − µV/°C VDD = ±2.5 V N Package TA = 25°C to 125°C Figure 10 25 45 65 85 105 125 INPUT BIAS AND INPUT OFFSET CURRENT † vs FREE-AIR TEMPERATURE TA − Free-Air Temperature − °C VDD = ±2.5 V VIC = 0 V VO = 0 V R S = 50 Ω IIB IIO IIB and IIO − Input Bias and Input Offset Currents − pAIBI IIO Figure 11 − 2 − 6 − 8 − 10 − 4 2345678 − Input Voltage − V INPUT VOLTAGE vs SUPPLY VOLTAGE |VDD ±| − Supply Voltage − V V I TA = 25°C R S = 50 Ω |VIO| ≤ 5mV Figure 12 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

− Maximum Positive Peak Output Voltage − V MAXIMUM POSITIVE PEAK OUTPUT VOLTAGE † vs OUTPUT CURRENT |IO | − Output Current − mA TA = −55°C TA = 25°C TA = 125°C VDD ± = ±5 V V OM + Figure 17 0 12345 6 IO − Output Current − mA MAXIMUM NEGATIVE PEAK OUTPUT VOLTAGE † vs OUTPUT CURRENT VDD = ±5 V VIC = 0 V TA = 125°C TA = 25°C TA = −55°C −3.8 −4.2 −4.4 −4.6 −4.8 − Maximum Negative Peak Output Voltage − VV OM − Figure 18 Figure 19 10 k 100 k 1 M f − Frequency − Hz 10 M MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY V(OPP) − Maximum Peak-to-Peak Output Voltage − VV O(PP) VDD = 5 V VDD = ±5 V R L = 10 kΩ TA = 25°C Figure 20 23 4 567 8 IOS − Short-Circuit Output Current − mAOSI |VDD ±| − Supply Voltage − V SHORT-CIRCUIT OUTPUT CURRENT vs SUPPLY VOLTAGE VID = 100 mV VO = 0 V TA = 25°C VID = −100 mV † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE MARGIN vs FREQUENCY f − Frequency − Hz 10 M om − Phase Margin φm VDD = 5 V R L = 10 kΩ C L = 100 pF TA = 25°C −20 −40 −90° −45° 45° 90° 135° 180° AVD − Large-Signal Differential ÁÁ ÁÁ ÁÁ A VD Voltage Amplification − dB Figure 25 1 k 10 k 100 k 1 M LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE MARGIN vs FREQUENCY f − Frequency − Hz 10 M VDD = ±5 V R L = 10 kΩ C L = 100 pF TA = 25°C om − Phase Margin φm −20 −40 −90° −45° 45° 90° 135° 180° AVD − Large-Signal Differential ÁÁ ÁÁ ÁÁ A VD Voltage Amplification − dB Figure 26

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

COMMON-MODE REJECTION RATIO vs FREQUENCY 10 100 1 k 10 k CMRR − Common-Mode Rejection Ratio − dB 100 100 k 1 M f − Frequency − Hz VDD = ±5 V VDD = 5 V 10 M TA = 25°C Figure 31 TA − Free-Air Temperature − °C CMRR − Common-Mode Rejection Ratio − dB COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE −75 −50 −25 0 25 50 75 100 125 VDD = ±5 V VDD = 5 V VIC = 0 V to 2.7 V VIC = −5 V to 2.7 V Figure 32 10 100 1 k kSVR − Supply-Voltage Rejection Ratio − dB f − Frequency − Hz 100 10 k 100 k 1 M 10 M SUPPLY-VOLTAGE REJECTION RATIO vs FREQUENCY kSVR VDD = 5 V TA = 25°C kSVR+ kSVR− −20 Figure 33 10 100 1 k kSVR − Supply-Voltage Rejection Ratio − dB f − Frequency − Hz 100 10 k 100 k 1 M 10 M SUPPLY-VOLTAGE REJECTION RATIO vs FREQUENCY kSVR VDD = ±5 V TA = 25°C kSVR+ kSVR− −20 Figure 34

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

−75 −50 −25 0 25 50 75 100 125 1.2 2.4 3.6 4.8 TA − Free-Air Temperature − °C IDD − Supply Current − mADDI VDD = 5 V VO = 2.5 V VDD = ±5 V VO = 0 V TLC2274 SUPPLY CURRENT † vs FREE-AIR TEMPERATURE µ sSR − Slew Rate − V/ C L − Load Capacitance − pF SLEW RATE vs LOAD CAPACITANCE 10 k1 k10010 SR + SR − VDD = 5 V AV = −1 TA = 25°C Figure 40 µsSR − Slew Rate − V/ −75 −50 −25 0 25 50 75 100 125 TA − Free-Air Temperature − °C SLEW RATE † vs FREE-AIR TEMPERATURE VDD = 5 V R L = 10 kΩ C L = 100 pF AV = 1 SR + SR − Figure 41 INVERTING LARGE-SIGNAL PULSE RESPONSE 12345 6789 VO − Output Voltage − mVVO t − Time − µs VDD = 5 V R L = 10 kΩ C L = 100 pF TA = 25°C AV = −1 Figure 42 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

−100 0 0.5 1 1.5 2 100 2.5 3 3.5 4 VO − Output Voltage − mVVO t − Time − µs INVERTING SMALL-SIGNAL PULSE RESPONSE VDD = ±5 V R L = 10 kΩ C L = 100 pF TA = 25°C AV = 1 −50 Figure 47 VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE 2.5 2.45 2.4 2.55 2.6 0 0.5 1 1.5 VO − Output Voltage − VVO t − Time − µs 2.65 VDD = 5 V R L = 10 kΩ C L = 100 pF TA = 25°C AV = 1 Figure 48 VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE −50 −100 100 0 0.5 1 1.5 VO − Output Voltage − mVVO t − Time − µs VDD = ±5 V R L = 10 kΩ C L = 100 pF TA = 25°C AV = 1 Figure 49 10 100 1 k Vn − Equivalent Input Noise Voltage − nV Hz f − Frequency − Hz 10 k EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY Vn nV/ Hz VDD = 5 V TA = 25°C R S = 20 Ω Figure 50

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Gain-Bandwidth Product − MHz2.1 012345 2.2 2.3 67 8 |VDD ±| − Supply Voltage − V 2.4 2.5 GAIN-BANDWIDTH PRODUCT vs SUPPLY VOLTAGE f = 10 kHz R L = 10 kΩ C L = 100 pF TA = 25°C Figure 56 −75 −50 −25 0 25 50 75 100 125 TA − Free-Air Temperature − °C Gain-Bandwidth Product − MHz GAIN-BANDWIDTH PRODUCT † vs FREE-AIR TEMPERATURE 1.8 1.6 1.4 2.4 2.2 2.6 2.8 VDD = 5 V f = 10 kHz R L = 10 kΩ C L = 100 pF om − Phase Margin 10000 C L − Load Capacitance − pF φ m PHASE MARGIN vs LOAD CAPACITANCE 1000100 VDD = ±5 V TA = 25°C R null = 20 Ω R null = 10 Ω R null = 0 75° 60° 45° 30° 15° 10 kΩ 10 kΩ VDD − VDD + R null C L VI R null = 100 Ω R null = 50 Ω Figure 57 Figure 58 Gain Margin − dB 10000 C L − Load Capacitance − pF GAIN MARGIN vs LOAD CAPACITANCE 1000100 VDD = 5 V AV = 1 R L = 10 kΩ TA = 25°C † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

/C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0262/C0069/C0080/C0044 /C0084/C0076/C0067/C0050/C0050/C0055/C0120/C0065/C0262/C0069/C0080 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 /C0261 SGLS131A − JULY 2002 − REVISED NOVEMBER 2003 29POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Macromodel information provided was derived using MicrosimParts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 6) and subcircuit in Figure 59 were generated using the TLC227x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): /C0068Maximum positive output voltage swing /C0068Maximum negative output voltage swing /C0068Slew rate /C0068Quiescent power dissipation /C0068Input bias current /C0068Open-loop voltage amplification /C0068Unity gain frequency /C0068Common-mode rejection ratio /C0068Phase margin /C0068DC output resistance /C0068AC output resistance /C0068Short-circuit output current limit of Solid-State Circuits, SC-9, 353 (1974). OUT − + .SUBCKT TLC227x 1 2 3 4 5 C1 11 1214E−12 C2 6 760.00E−12 DC 5 53DX DE 54 5DX DLP 90 91DX DLN 92 90DX DP 4 3DX FB 99 0POLY (5) VB VC VE VLP VLN 0 + 984.9E3 −1E6 1E6 1E6 −1E6 GA 6 011 12 377.0E−6 GCM 0 6 10 99 134E−9 ISS 3 10DC 216.OE−6 HLIM 90 0VLIM 1K J1 11 210 JX J2 12 110 JX R2 6 9100.OE3 RD1 60 112.653E3 RD2 60 122.653E3 R01 8 550 R02 7 9950 RP 3 44.310E3 RSS 10 99925.9E3 VAD 60 4−.5 VB 9 0DC 0 VC 3 53 DC .78 VE 54 4DC .78 VLIM 7 8DC 0 VLP 91 0DC 1.9 VLN 0 92DC 9.4 .MODEL DX D (IS=800.0E−18) .MODEL JX PJF (IS=1.500E−12BETA=1.316E-3 + VTO=−.270) .ENDS VCC+ RP IN − IN+ VCC− VAD RD1 J1 J2 RSS ISS RD2 VE DE DP VC DC EGND VB FB GCM GA VLIM RO1 RO2 HLIM DIP DIN VINVIP Figure 59. Boyle Macromodel and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation.

www.ti.com 17-Dec-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLC2272AMDREP ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2272AE TLC2272AMDREPG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2272AE TLC2274AMDREP ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2274AME TLC2274AMPWREP ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2274AME TLC2274MDREP ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2274ME V62/03618-01XE ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2272AE V62/03618-02UE ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2274AME V62/03618-02YE ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2274AME V62/03618-04YE ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2274ME (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

www.ti.com 17-Dec-2015 Addendum-Page 2 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLC2272A-EP, TLC2274-EP, TLC2274A-EP :

Catalog: TLC2272A , TLC2274 , TLC2274A
Automotive: TLC2272A-Q1 , TLC2274-Q1 , TLC2274A-Q1
Military: TLC2272AM , TLC2274M , TLC2274AM NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Military - QML certified for Military and Defense Applications

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 17-Feb-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC2272AMDREP SOIC D 8 2500 367.0 367.0 38.0 TLC2274AMDREP SOIC D 14 2500 333.2 345.9 28.6 TLC2274AMPWREP TSSOP PW 14 2000 367.0 367.0 35.0 TLC2274MDREP SOIC D 14 2500 333.2 345.9 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 17-Feb-2016 Pack Materials-Page 2

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Product Information

V62/03618-01XE specifications and overview.

Summary

ADVANCED LINCMOS RAIL TO RAIL OPERATIONAL AMPLIFIERS

Description

ADVANCED LINCMOS RAIL TO RAIL OPERATIONAL AMPLIFIERS

Source title V62/03618-01XE Datasheet(PDF) - Texas Instruments

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