V61C31161024

V61C31161024 MOSEL | Alldatasheet

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Technical content

Features

n High-speed: 10, 12, 15 ns n All inputs and outputs directly TTL compatible n Three state outputs n Single 3.3V 10% Power Supply n Packages – 44-pin TSOP (Standard) – 44-pin 400 mil SOJ n Low Power Consumption – Active: 140mA – Standby: 2mA (CMOS)

Description

The V61C31161024 is a 1,048,576-bit static random-access memory organized as 65,536 words by 16 bits. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Device Usage Chart Operating Temperature Range Package Outline Access Time (ns) Temperature MarkT K 10 12 15 C to 70 Functional Block Diagram Row Decoder Memory Array Input Data Circuit Column I/O Column Decoder Control Circuit VCC GND 6131161024-01 I/O0 I/O15 LBE OE WE UBE A0 A10 A15 CE

V61C31161024 Rev. 0.5 August 1999 MOSEL VITELIC V61C31161024 Pin Descriptions A Address Inputs These 16 address inputs select one of the 64K x 16 bit segments in the RAM. CE Chip Enable Input CE is active LOW. It must be active to read from or write to the device. If chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when deselected. OE Output Enable Input The output enable input is active LOW. When OE is Low with CE Low and WE High, data will be pre- sented on the I/O pins. The I/O pins will be in the high impedance state when OE is High. UBE , LEB Byte Enable Active low inputs. These inputs are used to enable the upper or lower data byte. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip enabled, when WE is HIGH and OE is LOW, output data will be present at the I/O pins; when WE is LOW and OE is HIGH, the data present on the I/O pins will be written into the selected memory locations. I/O –I/O Data Input and Data Output Ports These 16 bidirectional ports are used to read data from and write data into the RAM. V CC Power Supply GND Ground Pin Configurations (Top View) 44-Pin SOJ 44-Pin TSOP-II (Standard) 14 4 6131161024-02 2 43 3 42 44 1 54 0 6 39 7 38 83 7 93 6 10 35 11 34 12 33 13 32 14 31 15 30 16 29 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE OE UBE LBE I/O I/O14 I/O13 I/O12 VCC GND I/O11 I/O10 I/O9 I/O8 17 28 A15 NC 18 27 A14 19 26 A13 20 25 A12 A10 21 24 NC A11 22 23 NC A5 A4 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC OE/CR UBE/CR LBE/CR I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A10 A11 NC 6131161024-03

V61C31161024 Rev. 0.5 August 1999 Part Number Information Absolute Maximum Ratings (1) NOTE: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol Parameter Commercial Units V IN Input Voltage -0.5 to V CC +0.5 V P T Power Dissipation 1.0 W T BIAS Temperature Under Bias -10 to +85 C T STG Storage Temperature -65 to +150 C SRAM FAMILY C = CMOS PROCESS 61 = HIGH SPEED 31 = 3.3V OPERATING VOLTAGE 1024K ORGANIZATION PKGSPEED 6131161024-04

61 C 16 31 1024 –

V 16 = 16-bit 10 ns 12 ns 15 ns TEMP. BLANK = 0°C to 70°C T = TSOP STANDARD K = 400 mil SOJ DENSITY PWR. BLANK = STANDARD POWER Capacitance* T A = 25 C, f = 1.0MHz NOTE: 1. This parameter is guaranteed and not tested. Symbol Parameter Conditions Max. Unit C IN Input Capacitance V IN = 0V 6 pF C OUT Output Capacitance V I/O = 0V 8 pF Truth Table NOTE: X = Don’t Care, L = LOW, H = HIGH Mode CE OE WE UBE LBE I/O 8-15 Operation I/O 0-7 Operation Standby H X X X X High Z High Z Output Disable L X X H H High Z High Z Output Disable L H H X X High Z High Z Read L L H L L D OUT D OUT Read L L H L H D OUT High Z Read L L H H L High Z D OUT Write L X L L L D IN D IN Write L X L L H D IN High Z Write L X L H L High Z D IN

V61C31161024 Rev. 0.5 August 1999 MOSEL VITELIC V61C31161024 (over all temperature ranges, V CC = 3.3V 10%) NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. V IL (Min.) = -3.0V for pulse width < 20ns. 3. f MAX = 1/t RC 4. Maximum values. Symbol Parameter Test Conditions -10 -12 -15 I IL Input Leakage Current V CC = MAX, V IN = GND to V CC —5 —5 — 5 m A I OL Output Leakage Current CE = V IH , V CC = Max, V OUT = GND to V CC —5 —5 — 5 m A I CC Operating Power Supply Current CE = V IL , I OUT = 0, f = f max — 140 — 130 — 120 mA ISB Standby Power Supply Current (TTL Level) CE = V IH , f = f max — 25 — 20 — 20 m A I SB1 Standby Power Supply Current (CMOS Level) CE V CC – 0.2V, f = 0, V IN 0.2V or V IN > V CC – 0.2V —2 —2 — 2 m A V IL Input Low Voltage (1,2) V IH Input High Voltage (1) 2.2 V CC + 0.3 2.2 V CC + 0.3 2.2 V CC + 0.3 V V OL Output Low Voltage I OL V OH Output High Voltage I OH AC Test Conditions Key to Switching Waveforms AC Test Loads and Waveforms Input Pulse Levels 0 to 3V Input Rise and Fall Times 3 ns Timing Reference Levels 1.5V Output Load see below W AVEFORM INPUTS OUTPUTS MUST BE STEA DY WILL BE STEA DY M AY CHANGE FR OM H TO L WILL BE CHANGING FR OM H TO L M AY CHANGE FR OM L TO H WILL BE CHANGING FR OM L TO H DON'T CARE: ANY CHANGE PERMITTED CHANGING: STATE UNKN O WN DOES N O T APP LY CENTER LINE IS HIGH IMPE DANCE “OFF” STATE +3.3V 480 Ω 255 Ω I/O Pins C L = 30 pF* +3.3V 480 Ω 255 Ω * Includes scope and jig capacitance I/O Pins for tCLZ , tCHZ , tOLZ , tWHZ , tOW , and tOHZ C L = 5pF* 6131161024-05

V61C31161024 Rev. 0.5 August 1999 (over all temperature ranges) Read Cycle Write Cycle Parameter Name Parameter -10 -12 -15 t RC Read Cycle Time 10 — 12 — 15 — ns t AA Address Access Time — 10 — 12 — 15 ns t ACS Chip Enable Access Time — 10 — 12 — 15 ns t BA UBE , LBE Access Time —5—6—7n s t OE Output Enable to Output Valid —5—6—7n s t CLZ Chip Enable to Output in Low Z 2—3—3— n s t BLZ UBE , LBE to Output in Low Z 0—0—0— n s t OLZ Output Enable to Output in Low Z 0—0—0— n s t CHZ Chip Disable to Output in High Z 050607 n s t OHZ Output Disable to Output in High Z 050607 n s t BHZ UBE , LBE to Output in High Z 050607 n s t OH Output Hold from Address Change 2—3—3— n s Parameter Name Parameter -10 -12 -15 tWC Write Cycle Time 10 — 12 — 15 — ns tCW Chip Enable to End of Write 7—8— 1 0 — n s tAS Address Setup Time 0—0—0— n s tAW Address Valid to End of Write 7—8— 1 0 — n s tWP Write Pulse Width 7—8— 1 0 — n s tAH Address Hold from End of Write 0—0—0— n s tWHZ Write to Output High-Z 050607 n s tWLZ Write to Output Low Z 3—3—5— n s tDW Data Setup to End of Write 5—6—7— n s tDH Data Hold from End of Write 0—0—0— n s tBW UBE , LBE to End of Write 7—8— 1 0 — n s

6V61C31161024 Rev. 0.5 August 1999 MOSEL VITELIC V61C31161024 Switching Waveforms (Read Cycle) Read Cycle 1(1, 2) Read Cycle 2(1, 2, 4) Read Cycle 3(1, 3, 4) NOTES: 1. WE = VIH. 2. CE 1 = VIL. 3. Address valid prior to or coincident with CE transition LOW. 4. OE = VIL. 5. Transition is measured –500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested. 6. UBE = VIL, LBE = VIL. ADDRESS 6131161024-06 OE I/O UBE, LBE tRC tAA tOE tBHZ tOLZ tBLZ tBA tOHZ (5) ADDRESS I/O 6131161024-07 tRC tAAtOH tOH ADDRESS 6131161024-08 I/O CE tACS tCLZ (5) tCHZ (5)

MOSEL VITELIC V61C31161024 7V61C31161024 Rev. 0.5 August 1999 Switching Waveforms (Write Cycle) Write Cycle 1 (WE Controlled)(4) Write Cycle 2 (CE Controlled)(4) NOTES: 1. The internal write time of the memory is defined by the overlap of CE active and WE low. All signals must be active to initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. t AH is measured from the earlier of CE or WE going high. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention. 5. If CE is LOW during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 6. t CW is measured from CE going low to the end of write. ADDRESS OUTPUT INPUT CE WE 6131161024-09 tWC tCW (6) tDW tDH tAW tAH (2) tWHZ (3) tWP (1) tAS UBE, LBE tBW ADDRESS OUTPUT INPUT CE WE UBE, LBE 6131161024-10 tWC tDW tDH tAW tAH (2) Hi-Z tAS (5) tCW (6) tBW

8V61C31161024 Rev. 0.5 August 1999 MOSEL VITELIC V61C31161024 Package Diagrams 44-pin 400 mil TSOP-II 0.741[18.81] MAX 0.725 – 0.004 [18.41 – 0.10] 0.031 [0.80]0.032 [0.80]

0.004 MAX

0.047 [1.20] MAX Unit in inches [mm] 0.400 [10.16] 0.463 – 0.008 [11.76 – 0.20] 0.014 – 0.004 [0.35 – 0.10] 0.000 [0.0] MIN +0.004 -0.002 0°–5° 0.020 – 0.006 [0.50 – .019] 0.006 +0.01 -0.050.15

MOSEL VITELIC V61C31161024 9V61C31161024 Rev. 0.5 August 1999 Package Diagrams 44-pin 400 mil SOJ (450 mil pin-to-pin) 1.131+0.008 -0.014 28.73+0.2 -0.36 0.008+0.004 -0.002 0.20 0.033 [0.85] +0.10 -0.05 0.050 [1.27] 0.004 [0.10] 0.31 [0.8] MIN 0.102 [2.6] 0.091 [2.3–0.2] 0.138 – 0.008 [3.5 – 0.2] 0.005 [0.12]M 0.400 [10.16] 0.440 – 0.008 [11.18 – 0.20] 0.370 – 0.008 [9.4 – 0.20] Unit in inches [mm] 0.029 [0.74] 0.016+0.004 –0.005 0.041 [1.03 – 0.15] [0.40 – 0.10] +.006 –.007+.008 –.007

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