V61C16

V61C16 ETC | Alldatasheet

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HIGH PERFORMANCE LOW POWER 2K x 8 BIT CMOS STATIC RAM Features Description «= High Speed The V61C16 is a high speed, low power, + Maximum access time of 45/55/70 ns 2048-word by 8-bit CMOS static RAM tabricated + Equal access and cycle times using high-performance CMOS process technology. = Low Power This high reliability process, coupled with innovative + 200 mW typical operating circuit design techniques, yields access times of + 0.5 uW typical standby 45 ns maximum. + 0.1 pW typical data retention When the chip select is high, the device assumes. = Battery backup a standby mode in which the device power dissipa- * 2 volt data retention (L version) tion is reduced to 0.5 yW (typically). The low power = Six transistor CMOS memory cell version has a data retention mode that guarantees = CMOS process virtually eliminates alpha particle _that datawill remain valid ataminimum power supply induced soft errors without die coating voltage of 2.0 volts. = Fully static operation Using CMOS technology, supply voltages from 2.0 + No clock or refresh required to 5.5 volts have little effect on supply current in data = Pin Compatible with standard 16K static RAMS retention mode. Reducing the supply voltage to and EPROMS in 300 and 600 mil DIP minimize current drain is unnecessary with the = TTL compatible V61C16 family. Package Std] Skinny | Pin Count v61C16 PlasticDIP_ | OP S| 24 cr ot | SOIC (Mini Flat Pack) | F 24 Fay Deuce Package Speed Power Device Usage Chart “Overaing [Package Ouine [—_Aecessrime(ne) Power _ |” Temperature “ge ese] @ [| = | ~ [tw [sa] wn VerCi6 Rev.01 690 : 6-41

24 Pin DIP/SOIC Logic Symbol

Top View x iO. ow, ard: 24D Vo ne io, As 2 23 Ag A Os As 3 221 Ag A We Ags < *pPWe A vO? A305 @ 2» OE Os . Ao U6 rel 19D Ato ‘A ad7 & who¢s a Ao 8 oa 17D WO. vo; 9 16) VO7 d cs vO G10 15D WO. d we vos Gs 4B vos q Vss G12 13 vO, OE soos ot Functional Block Diagram Ao > AY =a +—Voo Ae > Row 1 +—Vss As P=—| _ pecoder mere 28, As > As > As > WO va FE] come | : Input b bata, Column Decoder ‘ee a AAS AY AS Ar As As Ato w <q es to = a WE 1006 02 .

——< rr Vv VITELIC V61C16 Absolute Maximum Ratings” Recommended Operating Conditions Srl] Paneer [ag [Om Smo] eon pt [om with Respect to V, : vs [ 00 T, | Operating Temperature | -85t0 +125 | °C Under Bias Vy; | Input High Voltage | 22 | 35] Yoo | v ts = efron 5] = feo] y in [seams * .3.5V for 20 ns pulse. NoTE: 1. Operation at or above absolute maximum ratings may affect device reliability. AC Test Conditions Signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.0 to 3.0V, output loading as shown in diagrams below. Voo Voo

480 OHMS 480 OHMS

Pour Pour 6 |

255 OHMS 30pF* 255 OHMS 5pF*

‘Output Load (A) Output Load (8) * including scope and jig Truth Table Capacitance T, = 25°C, f= 1.0 MHz we [ SRE WE] voopenan “mmol ar [aia Standby Pu | x | x | High Z Cy | input Capacitance | Yw=ov | 6 | pF Read pete fe] Dour Cyq | InputOutput Vyo = OV pF Ceoaci NOTE: Write Ow ‘These parameters are sampled and not 100% tested.

Commercial Temperature Range DC Characteristics Ty = 0°C to 70°C, Vpn = SV + 10%, Veg = OV, unless otherwise noted. a ea Ri [atanage Gare Vanes Van | | |? . Ihot Output Leakage Current CS = Vy, or OF = Vi, pA Wo Vss © Vpn loo ‘Operating Power Supply Current CS = Vy ly = 0.0mA mA Duty Cycle = 100% ‘ ‘Standby Power Supply Current Son ue ‘andby Power Supply Curren = pets | " Fancaw ree [=| + foe to Low Power DC Characteristics T, = 0°C to 70°C, Vpn = BV + 10%, Vig = OV, unless otherwise noted. ee ss Ihol Output Leakage Current CS=V,, or OE = Vi, BA Vio = Ves *° Yop lop Operating Power Supply Current CS = Vy hig = 0.0mA mA Duty Cycle = 100% ‘ea [eevee tm Standby Power Supply Current = i [ese 0va woe | = | or | | om vq [Samaitowvene fete = = fe dv Low V,, Data Retention Characteristics For low power versions only, T, = 0°C to 70°C, Vay = SV + 10%, Veg = OV, unless otherwise noted. Parometer eros Tm] um | ‘Test Conditions Data retention supply votage | Yooon | 20 | — | 85] ¥ | Vy=0010 Vo S2Vyq-02V Data retention supply current loon BA | Voy = 3.0V, Viy = 0.0 10 Vinny E$2Vpp-0.2V Seaminamaminie [eee [= [=| | Ope Se fe Le" = T= T= | NOTE: 1. tag = Read Cycle Time

Low V,, Data Retention Waveform Data Retention Mode ‘ey = ta aay cy = SF . Vor CS EV pp -0.2V cs woe OOO 1008 04 AC Characteristics At recommended operating conditions Read Cycle ne ee Symbol [win [Max [Min Max. | Min] Max. | Unit te [Rede | T= Te TT Te fT = | Read Cycle 1 (1) tre Aasress CO) TAA o (WMA LIVTTITLLT 10E ton _ t os WAS “ _ pee tacs’ i tonz 9) toi 1) | tong (" i Dour \\( Cn 0 1008 05 6-5

Read Cycle 2 (1, 6) Read Cycle 3 (1, 6) Dour en 7 | le X Write Cycle 1(1) son 7} oe rs SANNA cs (AAA EITTTTILLLLL Soy we SANNNANN con SSFSEISESIED ~

—- rr Vv VITELIC V61C16 AC Characteristics (1) At recommended operating conditions unless otherwise noted. Write Cycle [_vercieas | vercress [| vercie70_— Symbo! ee Unit tye [wieceetme | | | eT Tm T= | few | Swsaecionoeraowie | ss | = [| f # | = [s Ee LO me [winreoerie fe | |e [= fs | Te ‘ona | Output Disable to Outputin High Z =—j*® ),-|* |-/s [= eet conditions assume signal transition times if 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified loon ‘and 30 pF load capacitance, as in Output Load (A). Write Cycle 2 9 we 6 nates —_ ei os (IANA a we Bw: vo doer 3333339555555 VD WV, TITLLTTTTTTTTITTT TT TTT TT ALY DW. ‘OH (9) Din 1008 08 67 .

NoTES: 1. WE must be high during all address transitions. 2. Awrite occurs during the overlap (typ) of a low GS and a low WE. 3. twp is measured from the earlier of CS or WE going high to the end of the write cycle. 4. During this period, VO pins are in the output state and the input signals of opposite phase to the outputs must not be applied. 5. _ If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state. 6. OE is continuously low (OE < V,,), 7. Doyr is the same phase of write data of this write cycle. 8. Dou is the read data of next address. 9. It CS is low during this period, VO pins are in the output state and the data input signals of opposite phase to the outputs must ‘ot be applied to them. 10. Transition is measured +500mV from steady state. This parameter is sampled and not 100% tested. . 11. tyyuz is tested with C, = 5 pF as in Output Load (8). 6-8