V6170

V6170 ETC1 | Alldatasheet

Document overview

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Technical content

Features

n Standby mode, maximum current 35 mA n Reset output guaranteed for VDD voltage down to 1.2 V n Comparator for voltage monitoring, voltage reference 1.17 V n ±1.5% voltage reference accuracy at + 25 °C ±3% voltage reference accuracy for -40 to +85 °C n Programmable reset voltage monitoring n Voltage window, high threshold 5.9 V n Programmable power-on reset (POR) delay n Watchdog with programmable time window guarantees a minimum time and a maximum time between software clearing of the watchdog n Time base accuracy ± 10% n System enable (EN) output offers added security n 3 chip select feed-thru circuit controlled by EN n TTL / CMOS compatible n -40 to +85 °C temperature range n DIP8 and SO8 packages

Description

The V6170 offers a high level of integration by voltage monitoring and software monitoring in an 8 lead package. A comparator monitors the voltage applied at the V IN input comparing it with an internal 1.17 V reference. The power-on reset function is initialized after VIN reaches 1.17 V and takes the reset output inactive after T POR depending of external resistance. The reset output goes active low when the V IN voltage is less than 1.17 V or when VDD is higher than 5.9 V. The RES and EN outputs are guaranteed to be in a correct state for a supply voltage as low as 1.2 V. The watchdog function monitors software cycle time and execution. If the software clears the watchdog too quickly (incorrect cycle time) or too slowly (incorrect execution), it will cause the system to be reset. The system enable output prevents critical control functions being activated until software has successfully cleared the watchdog three times. Such a security could be used to prevent motor controls being energized on repeated resets of a faulty system.

Applications

n Battery powered products n Automotive electronics Typical Operating Configuration Pin Assignment R VSS EN TCL VIN VDD Fig. 1 100 nFV6170 RES GND DIP8 / SO8 VDD R TCL RES EN Fig. 2 V6170 VSS VIN NC

Parameter Symbol Conditions Maximum voltage at VDD Minimum voltage at VDD Max. voltage at any signal pin Min. voltage at any signal pin Storage temperature Electrostatic discharge max. to MIL-STD-883C method 3015 Max. soldering conditions VDDmax VDDmin VMAX VMIN TSTO VSmax TSmax VSS + 8 V VSS − 0.3 V VDD + 0.3 V VSS − 0.3 V -65 to+150 °C 1000 V 250 °C x 10 s Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level. Operating Conditions Parameter Symbol Min. Typ. Max. Units sOperating temperature Supply voltage1) & guaranteed2) Comparator input voltage RC-oscillator programming TA VDD VDD VIN R -40 1.2 1.2 +85 VDD 1000 V V V kΩ Table 21) A 100 nF decoupling capacitor is required on the supply voltage VDD for stability.2) RES must be pulled up externally to V DD even if it is unused. (Note: RES and EN are used as inputs by EM test )

Electrical Characteristics

3 ≤ VDD ≤ 5.5 V, C = 100 nF, TA = -40 to +85 °C, unless otherwise specified Parameter Symbol Test Conditions Min. Typ. Max. Units Supply current in standby mode Supply current and Output Low Voltage Output High Voltage and VIN and Input Low Level and Input High Level Leakage current input VIN input resistance Comparator reference 1) Comparator hysteresis 1) Level detector of VDD Hysteresis2) ISS ISS VOL VOL VOL VOL VOH VOH VOH VIL VIH ILI RVIN VREF VREF VREF VHY1 VHIGH VHIGH VHY2 REXT = don’t care, TCL = VDD, VIN = 0 V REXT = 100 kΩ , I/Ps at VDD, O/Ps 1 MΩ to VDD VDD = 4.5 V, IOL = 20 mA VDD = 4.5 V, IOL = 8 mA VDD = 2.0 V, IOL = 4 mA VDD = 1.2 V, IOL = 0.5 mA VDD = 4.5 V, IOH = −1 mA VDD = 2.0 V, IOH = −100 µA VDD = 1.2 V, IOH = −30 µA 3V ≤ VDD ≤ 5.5 V 3V ≤ VDD ≤ 5.5 V VSS ≤ VTCL ≤ VDD TA = +25 °C TA = −20 to +70 °C TA = +25 °C TA = −40 to +70 °C 3.5 1.8 1.0 VSS 2.0 1.148 1.123 1.123 5.78 5.60 0.4 0.2 0.2 0.06 4.1 1.9 1.1 0.05 100 1.170 5.95 100 0.4 0.4 0.2 0.8 VDD 1.200 1.218 1.222 6.12 6.30 µA µA V V V V V V V V V µA MΩ V V V mV V V mV 1) The comparator reference is the power-down reset threshold. The power-on reset threshold equals the comparator Table 3 reference voltage plus the comparator hysteresis (see Fig. 5).2) The level detector of V DD (VHIGH) is the level when VDD is rising. The level detector when V DD is falling equals VHIGH minus the hysteresis (V HY2) (see Fig. 5). RES EN EN TCL TCL TCL TCL RES EN

ISS Standby versus at VDD = 5.5 V Timing Characteristics VDD = 5.0 V ± 3%, C = 100 nF, TA = −40 to +85 °C, unless otherwise specified Parameter Symbol Test Conditions Min. Typ. Max. Units Propagation delays: TCL to Output Pins VIN sensitivity Logic Transition Times on all Output Pins Power-on Reset delay Watchdog Time Open Window Percentage Closed Window Time Open Window Time Watchdog Reset Pulse TCL Input Pulse Width TDIDO TSEN TTR TPOR TWD OWP TCW TCW TOW TOW TWDR TWDR TTCL Load 10 kΩ , 50 pF REXT = 118 kΩ , ±1% REXT = 118 kΩ , ±1% REXT = 118 kΩ , ±1% REXT = 118 kΩ , ±1% REXT = 118 kΩ , ±1% 150 250 100 100 ±0.2 TWD

0.8 TWD

0.4 TWD

2.5 500 100 110 110 ns µs ns ms ms ms ms ms ns Table 4 Timing Waveforms Watchdog Timeout Period 30ISS [µA] −10 0−20−30−40 10 20 30 40 50 60 70 80 TA [°C] Fig. 3 TWD = TPOR TCW – closed window TOW – open window Watchdog timer reset Condition: REXT = 118 kΩ − OWP − 20% + OWP + 20% 80 100 120 Fig. 4 t [ms]

Combined Voltage and Timer Reaction V Condition: VDD ≥ 3 V Fig. 5RES TPOR VREF VHIGH No timeout TPOR TPOR VHY1 VHY2 TSEN TSEN TSEN TSEN TSEN TSEN TSEN TTCL TOW Fig. 6- Watchdog timer reset Condition: VIN > VREF after power-up sequence TCL RES EN EN 3 correct TCL services goes active low 1 2 3 Timeout TCW+TOW TCWTCW+TOWTCW TCW+TOWTCWTOW TWOR TCW+TOW TPOR=TWD TOW TCW VIN VREF Condition: VDD ≥ 3 V Fig. 7 TCL TCL RES EN too early 3 correct TCL service EN goes active low - Watchdog timer reset 1 2 3

R VIN Push-pull active low enable output Open drain active low reset output. RES must be pulled up to VDD even if unused Watchdog timer clear input signal GND terminal No connection Voltage supply REXT input for RC oscillator tuning Voltage comparator input Table 5 Functional Description VIN Monitoring The power-on reset and the power-down reset are generated as a response to the external voltage level on the V IN input. The external voltage level is typically obtained from a voltage divider as shown in Fig. 9. The user defines an external voltage divider to set the desired threshold level for power-on reset and power- down reset in his system. The internal comparator reference voltage is typically 1.17 V. At power-up the reset output (RES) is held low (see Fig. 5). When VIN becomes greater than V REF, the RES output is held low for an additional power-on reset (POR) delay wich is equal to the watchdog time TWD (typically 100 ms with an external resistor of 11 8 kW connected at R pin). The POR delay prevents repeated toggling of RES even if VIN and the INPUT voltage drops out and recovers. The POR delay allows the microprocessor’s crystal oscillator time to start and stabilize and ensures correct recognition of the reset signal to the microprocessor. The RES output goes active low generating the power- down reset whenever VIN falls below V REF. The sensitivity or reaction time of the internal comparator to the voltage level on VIN is typically 5 ms. Voltage Window The reset output (RES) is inactive when VIN is higher than VREF and when V DD is lower than V HIGH. If V IN is less than VREF or VDD higher than VHIGH, the reset output goes active low (see Fig. 5). Timer Programming The on-chip oscillator needs an external resistor R EXT connected between the R pin and VSS (see Fig. 9). It allows the user to adjust the power-on reset (POR) delay, watchdog time T WD and with this also the closed and open time windows as well as the watchdog reset pulse width (TWD/40). With REXT = 118 kW, the typical delays are: - Power-on reset delay: TPOR is 100 ms - Watchdog time: TWD is 100 ms - Closed window: TCW is 80 ms - Open window: TOW is 40 ms - Watchdog reset: TWOR is 2.5 ms Note the current consumption increases as the frequen- cy increases. Watchdog Timeout Period Description The watchdog timeout period is divided into two parts, a “closed” window and an “open” window (see Fig. 4) and is defined by two parameters, TWD and the Open Window Percentage (OWP). The closed window starts just after the watchdog timer EN RES TCL RES EN TCL Fig. 8 VREF R VIN Open drain output RES Current Controlled Oscillator Voltage Reference Enable Logic Timer Reset Control− Comparator Comparator

resets and is defined by TCW = TWD − OWP(TWD). The open window starts after the closed time window finishes and lasts till TWD + OWP(TWD). The open window time is defined by TOW = 2 x OWP(TWD). For example if T WD = 100 ms (actual value) and OWP = ± 20% this means the closed window lasts during first the 80 ms (TCW = 80 ms = 100 ms − 0.2 (100 ms)) and the open window the next 40 ms (TOW = 2 x 0.2 (100 ms) = 40 ms). The watchdog can be serviced between 80 ms and 120 ms after the timer reset. However as the time base is ± 10% accurate, software must use the following calculation for servicing signal TCL during the open window: Related to curves (Fig. 10 to Fig. 2 0), especially Fig. 19 and Fig. 2 0, the relation between T WD and R EXT could easily be defined. Let us take an example describing the variations due to production and temperature: 1. Choice, TWD = 26 ms. 2. Related to Fig. 20, the coefficient (TWD to REXT) is 1.125 where REXT is in kW and TWD in ms. 4. 26 ms at +25 °C Typical TCL period of The ratio between T WD = 26 ms and the (TCL period) = 25.4 ms is 0.975. Then the relation over the production and the full temperature range is, TCL period = 0.975 x TWD or TCL period = , as typical value. a) While PRODUCTION value unknown for the custo- mer when REXT ¹ 118 kW. b) While operating TEMPERATURE range 5. If you fixed a TCL period = 26 ms ÞREXT = 30 kW If during your production the T WD time can be measured, at TA = +25 °C and the mC can adjust the TCL period, then the TCL period range will be much larger for the full operating temperature. Timer Clearing and RES Action The watchdog circuit monitors the activity of the processor. If the user’s software does not send a pulse to the TCL input within the programmed open window timeout period, a short watchdog RES pulse is generated which is equal to T WD/40 = 2.5 ms typically (see Fig. 6). With the open window constraint, new security is added to conventional watchdogs by monitoring both software cycle time and execution. Should software clear the watchdog too quickly (incorrect cycle time) or too slowly (incorrect execution), it will cause the system to be reset. If the software is stuck in a loop which includes the routine to clear the watchdog, a conventional watchdog will not reset the system even though the software is malfunctioning; the V6170 will generate a system reset because the watchdog is cleared too quickly. If no TCL signal is applied before the closed and open windows expire, RES will start to generate square waves of period (TCW + TOW + TWDR). The watchdog will remain in this state until the next TCL falling edge appears during an open window, or until a fresh power-up sequence. The system enable output, EN, can be used to prevent critical control functions being activated in the event of the system going into this failure mode (see section “Enable - EN Output”). The RES output must be pulled up to V DD even if the output is not used by the system (see Fig. 9). Combined Voltage and Timer Action The combination of voltage and timer actions is illustrated by the sequence of events shown in Fig. 7. On power-up, when the voltage at V IN reaches V REF, the power-on-reset, POR, delay is initialized and holds RES active for the time of the POR delay. A TCL pulse will have no effect until this power-on reset delay is completed. After the POR delay has elapsed, RES goes inactive and the watchdog timer starts acting. If no TCL pulse occurs, RES goes active low for a short time T WDR after each closed and open window period. A TCL pulse coming during the open window clears the watchdog timer. When the TCL pulse occurs too early (during the closed window), RES goes active and a new timeout sequence starts. A voltage drop below the V REF level for longer than typically 5 ms, overrides the timer and immediately forces RES active and EN inactive. Any further TCL pulse has no effect until the next power-up sequence has completed. Enable -- EN Output The system enable output, EN, is inactive always when RES is active and remains inactive after a RES pulse until the watchdog is serviced correctly 3 consecutive times (ie. the TCL pulse must come in the open window). After three consecutive services of the watchdog with TCL during the open window, the EN goes active low. A malfunctioning system would be repeatedly reset by the watchdog. In a conventional system critical motor controls could be energized each time reset goes inactive (time allowed for the system to restart) and in this way the electrical motors driven by the system could function out of control. The V617 0 prevents the above failure mode by using the EN output to disable the motor controls until software has successfully cleared the watchdog three times (ie. the system has correctly restarted after a reset condition). 0.975 x REXT 1.125 26 x 1.125 0.975

R VSS EN TCL VIN VDD GND Fig. 9 100 nF V6170 RES RES EN Motor Controls Address Decoder100 kΩ 100 kΩ µP Supply voltage

TWD versus Temperature at 5 V TWD versus R at 5 V TWD versus VDD at TA = ++25 °°C TWD versus R at TA = ++25 °°C +85 Fig. 10 −40 −20 +25 TA [°C] 10’000 1000 100 TWD [ms] R = 10 MΩ R = 1 MΩ R = 100 kΩ R = 10 kΩ −40 to 85 °C 10’000100010010 10’000 1000 100 TWD [ms] R [kΩ] Fig. 11 Fig. 12 10’000 1000 100 3.0 4.0 5.0 VDD [V] TWD [ms] R = 10 MΩ R = 1 MΩ R = 100 kΩ R = 10 kΩ 10’000 1000 100 10 100 1000 10’000 R [kΩ ] Fig. 13 TWD [ms] 3 V 4.5 V 5 V 5.5 V

TWD versus R at TA = +25 °°C 10’000 1000 100 10 100 1000 10’000 R [kΩ ] Fig. 14 TWD [ms] 3 V 4.5 V 5 V 5.5 V

TWD versus VDD at TA = ++85 °°C TWD versus R at TA = ++85 °°C TWD versus VDD at TA = --40 °°C TWD versus R at TA = --40 °°C Fig. 15 10’000 1000 100 10 3.0 4.0 5.0 VDD [V] R = 10 MΩ R = 1 MΩ R = 100 kΩ R = 10 kΩ TWD [ms] 10’000 1000 100 10 100 1000 10’000 R [kΩ] Fig. 16 TWD [ms] 3 V 4.5 V 5 V 5.5 V 10’000 1000 100 3.0 4.0 5.0 VDD [V] Fig. 17 TWD [ms] R = 10 MΩ R = 1 MΩ R = 100 kΩ R = 10 kΩ 10’000 1000 100 10 100 1000 10’000 R [kΩ] Fig. 18 TWD [ms] 3 V 4.5 V 5 V 5.5 V

TWD Coefficient versus REXT at TA = ++25 °°C REXT Coefficient versus TWD at TA = ++25 °°C 1.00 0.98 0.96 0.94 0.92 0.90 0.88 0.86 0.84 0.82 0.80 TWD Coefficient 10 1000100 REXT [kΩ ] Fig. 19 Fig. 20 1.24 1.22 1.20 1.18 1.16 1.14 1.12 1.10 1.08 1.06 1.04 1.02 1.00 REXT Coefficient 10 100 1000 TWD [ms]

Ordering Information

The V6170 is available in the following packages Type Package V6170 8P DIP8 V6170 8S SO8 When ordering please specify complete part number. © 2000 EM Microelectronic-Marin SA, 10/00, Rev. D/334 EM Microelectronic-Marin SA cannot assume any responsibility for use of any circuitry described other than entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. EM Microelectronic-Marin SA, CH - 2074 Marin, Switzerland, Tel. (+41) 32 - 755 51 11, Fax (+41) 32 - 755 54 03