V437432E24VXTG-75

V437432E24V MOSEL | Alldatasheet

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Technical content

Features

■ 168 Pin Registered ECC 33,554,432 x 72 bit Oganization SDRAM Modules ■ Utilizes High Performance 32M x 8 SDRAM in TSOPII-54 Packages ■ Fully PC Board Layout Compatible to INTEL’S Rev 1.0 Module Specification ■ Single +3.3V (± 0.3V) Power Supply ■ Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) ■ Auto Refresh (CBR) and Self Refresh ■ All Inputs, Outputs are LVTTL Compatible ■ 8192 Refresh Cycles every 64 ms ■ Serial Presence Detect (SPD)

Description

The V437432E24V memory module is organized 33,554,432 x 72 bits in a 168 pin dual in line memory module (DIMM). The 32M x 72 registered DIMM uses 9 Mosel-Vitelic 32M x 8 ECC SDRAM. The x72 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Part Number Speed Grade Configuration V437432E24VXTG-75PC -75PC, CL=2,3 (133 MHz) 32M x 72 V437432E24VXTG-75 -75, CL=3 (133 MHz) 32M x 72 V437432E24VXTG-10PC -10PC, CL=2,3 (100 MHz) 32M x 72

2V437432E24V Rev. 1.0 January 2002 M OS EL V ITE LIC V437432E24V Pin Configurations (Front Side/Back Side) Notes: Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO* CB1* VSS NC NC VCC WE DQM0 DQM1 CS0 DU VSS A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2* CB3* VSS I/O17 I/O18 I/O19 I/O20 VCC I/O21 NC DU CKE1 VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2 NC WP SDA SCL VCC 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4* CB5* VSS NC NC VCC CAS DQM4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 DQM5 CS1 RAS VSS BA0 A11 VCC CLK1 A12 VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6* CB7* VSS I/O49 I/O50 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 I/O51 I/O52 VCC I/O53 NC DU NC VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3 NC SA0 SA1 SA2 VCC Pin Names A0–A12 Address Inputs I/O1–I/O64 Data Inputs/Outputs RAS Row Address Strobe CAS Column Address Strobe WE Read/Write Input BA0, BA1 Bank Selects CKE0 , CKE1 Clock Enable CS 0–CS 3 Chip Select CLK0–CLK3 Clock Input DQM0–DQM7 Data Mask VCC Power (+3.3 Volts) VSS Ground SCL Clock for Presence Detect SDA Serial Data OUT for Presence Detect SA0–A2 Serial Data IN for Presence Detect CB0–CB7 Check Bits (x72 Organization) NC No Connection DU Don’t Use

M OS EL V ITE LIC V437432E24V 3V437432E24V Rev. 1.0 January 2002 Module Part Number Information V 4 3 74 32 E 2 4 V X T G -X X SDRAM 3.3V WIDTH DEPTH

168 PIN Registered

COMPONENT A=0.17u, B=0.14u REV LEVEL COMPONENT PACKAGE, T = TSOP LEAD FINISH G=G O L D SPEED 75PC = PC133 CL3,2MOSEL VITELIC MANUFACTURED 75 = PC133 CL3 10PC = PC100 CL3,2

4V437432E24V Rev. 1.0 January 2002 M OS EL V ITE LIC V437432E24V Block Diagram RDQM0 I/O1–I/O8 RCS0R RWE WE RDQM4 I/O40–I/O33 DQM1 I/O9–I/O16 RDQM5 I/O48–I/O41 RDQM2 I/O17–I/O24 RCS2 RDQM6 I/O49–I/O56 RDQM3 I/O25–I/O32 RDQM7 I/O57–I/O64 C0-C17 D0-D7, Reg DLL D0-D7, Reg DLL VCC VSS SCL0 SA2 SA1 SA0 SDA WP E 2PROM SPD (256 WORD X 8 BITS) 47K DQM I/O1–I/O8 CS DQM I/O1–I/O8 CS DQM I/O1–I/O8 CS DQM I/O1–I/O8 CS DQM I/O1–I/O8 CS DQM I/O1–I/O8 CS DQM I/O1–I/O8 CS DQM I/O1–I/O8 CS WE WE WE BC0–7 DQM I/O1–I/O8 CSWE WE WE WE WE CS0–CS2 DQM0–7 BA0, BA1 A0–A12 RAS CAS CKEO WE RCS0–RCS2 VCC REGE 10K REGISTER RDQM0–7 RBA0–RBA1 RA0–RA12 SDRAMD0–8 SDRAMD0–8 SDRAMD0–8 SDRAMD0–8 SDRAMD0–8 SDRAMD0–8 CLK0 RRAS RCAS RCKE0 RWE 12 pF SDRAMD–D8 CLK1, CLK2, CLK3 12 pF PLL

M OS EL V ITE LIC V437432E24V 5V437432E24V Rev. 1.0 January 2002 Serial Presence Detect Information A serial presence detect storage device – E2PROM – is assembled onto the module. Informa- tion about the module configuration, speed, etc. is w r i t t e ni n t ot h eE2PROM device during module pro- duction using a serial presence detect protocol (I2C synchronous 2-wire bus) SPD-Table for modules: Byte Number Function Described SPD Entry Value Hex Value -75PC -75 -10PC

0 Number of SPD bytes 128 80 80 80

1 Total bytes in Serial PD 256 08 08 08

2 Memory Type SDRAM 04 04 04

3 Number of Row Addresses (without BS bits) 13 0D 0D 0D

4 Number of Column Addresses (for x8

SDRAM) 10 0A 0A 0A

5 Number of DIMM Banks 1 01 01 01

6 Module Data Width 72 48 48 48

7 Module Data Width (continued) 0 00 00 00

8 Module Interface Levels LVTTL 01 01 01

9 SDRAM Cycle Time at CL=3 7.5 ns/10.0 ns 75 75 A0 10 SDRAM Access Time from Clock at CL=3 5.4 ns/6.0 ns 54 54 60 11 Dimm Config (Error Det/Corr.) ECC 02 02 02 12 Refresh Rate/Type Self-Refresh, 7.8 µs8 2 8 2 8 2

13 SDRAM width, Primary x8 08 08 08

14 Error Checking SDRAM Data Width n/a / x8 08 08 08

1 5 M i n i m u mC l o c kD e l a yf r o mB a c kt oB a c k Random Column Address t ccd =1C L K 0 1 0 1 0 1

16 Burst Length Supported 1, 2, 4, 8 0F 0F 0F

17 Number of SDRAM Banks 4 04 04 04

18 Supported CAS

Latencies CL = 2,3 06 06 06

19 CS Latencies CS Latency = 0 01 01 01

20 WE Latencies WL = 0 01 01 01

21 SDRAM DIMM Module Attributes Registered/Buffered. 1F 1F 1F

22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 0E 0E

23 Minimum Clock Cycle Time at CAS

7.5 ns /10.0 ns 75 A0 A0

24 Maximum Data Access Time from Clock for

CL = 2 5.4 ns/6.0 ns 54 60 60

25 Minimum Clock Cycle Time at CL = 1 Not Supported 00 00 00

26 Maximum Data Access Time from Clock at

CL = 1 Not Supported 00 00 00

27 Minimum Row Precharge Time 15 ns/20 ns 0F 14 14

6V437432E24V Rev. 1.0 January 2002 M OS EL V ITE LIC V437432E24V

28 Minimum Row Active to Row Active Delay

14 ns/15 ns/16 ns 0E 0F 10

29 Minimum RAS to CAS Delay tRCD 15 ns/20 ns 0F 14 14

30 Minimum RAS Pulse Width t RAS 42 ns/45 ns 2A 2D 2D

31 Module Bank Density (Per Bank) 256 MByte 40 40 40

32 SDRAM Input Setup Time 1.5 ns/2.0 ns 15 15 20 33 SDRAM Input Hold Time 0.8 ns/1.0 ns 08 08 10 34 SDRAM Data Input Setup Time 1.5 ns/2.0 ns 15 15 20 35 SDRAM Data Input Hold Time 0.8 ns/1.0 ns 08 08 10 36-61 Superset Information (May be used in Fu- ture) 00 00 00

63 Checksum for Bytes 0 - 62 2E 73 E1

64 Manufacturer’s JEDEC ID Code Mosel Vitelic 40 40 40

65-71 Manufacturer’s JEDEC ID Code (cont.) 00 00 00

72 Manufacturing Location

73-90 Module Part Number (ASCII) V437432E24V 91-92 PCB Identification Code

93 Assembly Manufacturing Date (Year)

94 Assembly Manufacturing Date (Week)

95-98 Assembly Serial Number 99-125 Reserved 00 00 00

126 Intel Specification for Frequency 64 64 64

127 Reserved

128+ Unused Storage Location 00 00 00 SPD-Table for modules: (Continued) Byte Number Function Described SPD Entry Value Hex Value -75PC -75 -10PC

M OS EL V ITE LIC V437432E24V 7V437432E24V Rev. 1.0 January 2002 DC Characteristics TA =0 °Ct o7 0°C; VSS =0V ;V DD ,VDDQ =3 . 3 V± 0.3V Capacitance TA =0 °Ct o7 0°C; VDD =3 . 3 V± 0.3V, f = 1 MHz Symbol Parameter Limit Values UnitMin. Max. V IH Input High Voltage 2.0 V CC +0.3 V V IL Input Low Voltage –0.5 0.8 V V OH Output High Voltage (IOUT = –4.0 mA) 2.4 — V V OL Output Low Voltage (IOUT =4 . 0m A ) — 0 . 4 V II(L) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) –10 10 µA IO(L) Output leakage current (DQ is disabled, 0V < VOUT <V CC ) –10 10 µA Symbol Parameter Limit Values Unit C I1 Input Capacitance (A0 to A11, RAS,C A S,W E)8 5 p F C I2 Input Capacitance (CS0-CS3)3 0 p F C ICL Input Capacitance (CLK0-CLK3) 22 pF C I3 Input Capacitance (CKE0, CKE1) 50 pF C I4 Input Capacitance (DQM0-DQM7) 20 pF C IO Input/Output Capacitance (I/O1-I/064) 20 pF C SC Input Capacitance (SCL, SA0-2) 8 pF C SD Input/Output Capacitance 18 pF

8V437432E24V Rev. 1.0 January 2002 M OS EL V ITE LIC V437432E24V Absolute Maximum Ratings Standby and Refresh Currents1 TA =0 °Ct o7 0°C, VCC =3 . 3 V± 0.3V Parameter Max. Units V o l t a g eo nV D DS u p p l yR e l a t i v et oVSS -1 to 4.6 V V o l t a g eo nI n p u tR e l a t i v et oVSS -1 to 4.6 V Operating Temperature 0t o+ 7 0 ° C Storage Temperature - 5 5t o1 2 5 ° C Power Dissipation 7.2 W Sym- bol Parameter Test Conditions -75PC/75 -10PC Unit Note ICC 1 Operating Current Burst length = 4, CL = 3 tRC >=t RC (min), tCK >=t CK (min), IO = 0 mA

2 Bank Interleave Operation

2070 1890 mA 1,2 ICC 2P Precharged Standby Current in Power Down Mode CKE< = VIL(max), tCK >=t CK (min) 18 18 mA ICC 2N Precharged Standby Current in Non-Power Down Mode CKE> = VIH(min), tCK >=t CK (min), In- put changed once in 3 cycles 360 315 mA CS = High ICC 3P Active Standby Current in Power Down Mode CKE< = VIL(max), tCK >=t CK (min) 90 90 mA ICC 3N Active Standby Current in Non-Pow- er Down Mode CKE> = V IH(min), tCK >=t CK (min), In- put changed one time 450 405 mA CS = High ICC 4 Burst Operating Current t RC = Infinite, CL = 3, tCK >=t CK (min), IO = 0 mA

2 Banks Activated

1350 1080 mA 1, 2 ICC 5 Auto Refresh Current t RC >= tRC (min) 2160 1980 mA 1,2 ICC 6 Self Refresh Current CKE = <0.2 V Standard 27 27 mA 1,2 L-version 15.3 15.3

M OS EL V ITE LIC V437432E24V 9V437432E24V Rev. 1.0 January 2002 AC Characteristics3,4 TA =0 °t o7 0°C; VSS =0 V ;VCC =3 . 3 V± 0.3V, tT =1n s # Symbol Parameter Limit Values Unit Note -75PC -75 -10PC Clock and Clock Enable 1t CK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 7.5 7.5 7.5 ns ns 2f CK System frequency CAS Latency = 3 CAS Latency = 2 133 133 133 100 100 100 MHz MHz 3t AC Clock Access Time CAS Latency = 3 CAS Latency = 2 5.4 5.4 ns ns 4,5 4t CH Clock High Pulse Width 2.5 – 2.5 – 3 – ns 6 5t CL Clock Low Pulse Width 2.5 – 2.5 – 3 – ns 6 6t CS Input Setup time 1.5 – 1.5 – 2 – ns 7 7t CH Input Hold Time 0.8 – 0.8 – 1 – ns 7 8t CKSP C K E S e t u p T i m e ( P o w e r d o w n m o d e ) 2 . 5 –2–2– n s 8 9t CKSR C K E S e t u p T i m e ( S e l f R e f r e s h E x i t ) 8–8–8– n s 9 10 t T T r a n s i t i o n t i m e ( r i s e a n d f a l l ) 1–1–1– n s Common Parameters 11 t RCD RAS to CAS d e l a y 1 5–2 0–2 0–n s 12 t RC C y c l e T i m e 6 01 2 0 k7 01 2 0 k7 01 2 0 kn s 13 t RAS A c t i v e C o m m a n d P e r i o d 4 2–4 5–4 5–n s 14 t RP P r e c h a r g e T i m e 2 0–2 0–2 0–n s 15 t RRD B a n k t o B a n k D e l a y T i m e 1 6–1 5–2 0–n s 16 t CCD CAS to CAS delay time(same bank) 1–1–1– C L K Refresh Cycle 17 t SREX Self Refresh Exit Time 10 – 10 – 10 –n s9 18 t REF R e f r e s h P e r i o d ( 8 1 9 2 c y c l e s ) 6 4–6 4–6 4–m s 8 Read Cycle 19 t OH D a t a O u t H o l d T i m e 3–3–3– n s 4 20 t LZ D a t a O u t t o L o w I m p e d a n c e T i m e 0–0–0– n s 21 t HZ Data Out to High Impedance Time 3 7.5 3 7.5 3 8 ns 10 22 t DQZ D Q M D a t a O u t D i s a b l e L a t e n c y 2–2–2– C L K Write Cycle 23 t DPL D a t a i n p u t t o P r e c h a r g e ( w r i t e r e c o v e r y ) 2–2–1– C L K 24 t DAL D a t a I n t o A c t i v e / r e f r e s h 5–5–5– C L K 1 1 25 t DQW D Q M W r i t e M a s k L a t e n c y 0–0–0– C L K

10V437432E24V Rev. 1.0 January 2002 M OS EL V ITE LIC V437432E24V Notes: 1. The specified values are valid when addresses are changed no more than once during tCK (min.) and when No Operation commands are registered on every rising clock edge during tRC (min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during tRC (min.). 3. All AC characteristics are shown for device level. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V. 5. If clock rising time is longer than 1 ns, a time (t T/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If t T is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. tDAL is equivalent to tDPL +tRP . 1.4V 1.4V tSETUP tHOLD tAC tAC tLZ tOH tHZ CLOCK INPUT OUTPUT 50 pF I/O Z=50 Ohm +1 . 4V

50 Ohm

2.4V 0.4V tT tCL tCH I/O Measurement conditions for tac and toh 50 pF

M OS EL V ITE LIC V437432E24V 11V437432E24V Rev. 1.0 January 2002 Package Dimensions 127.35 133.37 42.18 D 63.68 3.0 1.27 ± 0.100 All measurements in mm 43.15 11 0 1 1 4 0 4 1 8 4 85 94 95 124 125 168 17.80 BA 6.35 2.26 RADIUS 1.27 + 0.10 Detail A 3.125 4.45 2.0 6.35 3.175 Detail B 3.125 2.0 1.0 ± 0.051.27 Detail C 2.50 0.2 ± 0.15 4.0 Tolerances: ± (0.13) unless otherwise specified. (2.63)

12V437432E24V Rev. 1.0 January 2002 M OS EL V ITE LIC V437432E24V Label Information C L= 3 or 2 (CLK) tRCD = 3 or 2 (CLK) tRP = 3 or 2 (CLK) -XXXR REGISTERED DIMM PC133 54 V437432E24VXXX-XX 256MB CLX PC133R-XXX-542-A XXXX-XXXXXXX Assembly in Taiwan A Gerber file Intel PC100 x8 Based MOSEL VITELIC Part Number Module Density DIMM manufacture date code Criteria of PC100 or PC133 (refer to MVI datasheet) tAC = 5.4 ns CAS Latency 2=CL2 3=CL3

M OS EL V ITE LIC V437432E24V 13V437432E24V Rev. 1.0 January 2002 WORLDWIDE OFFICES © Copyright , MOSEL VITELIC Corp. Printed in U.S.A. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep cur- rent the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. U.S. SALES OFFICES U.S.A.

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