V437216C04VDTG-10PC

V437216C04VDTG-10PC MOSEL | Alldatasheet

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Technical content

Features

I

168 Pin Registered ECC 16,777,216 x 72 bit

I Utilizes High Performance 16M x 4 SDRAM in TSOPII-54 Packages I Fully PC Board Layout Compatible to INTEL’S Rev 1.2 Module Specification I Single +3.3V (± 0.3V) Power Supply I Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) I Auto Refresh (CBR) and Self Refresh I All Inputs, Outputs are LVTTL Compatible I

4096 Refresh Cycles every 64 ms

I Serial Present Detect (SPD)

Description

The V437216C04VDTG-10PC memory module is organized 16,777,216 x 72 bits in a 168 pin dual in line memory module (DIMM). The 16M x 72 registered DIMM uses 18 Mosel-Vitelic 16M x 4 ECC SDRAM. The x72 registered modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. I SDRAM Performance I Module Frequency vs AC Parameter Key Component Timing Parameters -8PC Units t CK Clock Frequency (max.) 125 MHz t AC Clock Access Time CAS Latency = 3 Latency = 2 ns ns Frequency CL (CAS Latency) t RCD t RP t RC Unit V437216C04VDTG-10PC

100 MHz (PC)

V437216C04VDTG-10PC Rev. 1.3 July 2001 MOSEL VITELIC V437216C04VDTG-10PC Pin Configurations (Front Side/Back Side) Notes: * These pins are not used in this module. Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO CB1 VSS NC NC VCC WE DQM0 DQM1 CS0 DU VSS A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2 CB3 VSS I/O17 I/O18 I/O19 I/O20 VCC I/O21 NC DU CKE1* VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2* NC WP SDA SCL VCC 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4 CB5 VSS NC NC VCC CAS DQM4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 DQM5 CS1 RAS VSS BA0 A11 VCC CLK1* A12 VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6 CB7 VSS I/O49 I/O50 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 I/O51 I/O52 VCC I/O53 NC DU REGE VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3* NC SA0 SA1 SA2 VCC Pin Names A0–A11 Address Inputs I/O1–I/O64 Data Inputs/Outputs RAS Row Address Strobe CAS Column Address Strobe WE Read/Write Input BA0, BA1 Bank Selects CKE0 Clock Enable CS0, CS2 Chip Select CLK0–CLK3 Clock Input DQM0–DQM7 Data Mask VCC Power (+3.3 Volts) VSS Ground SCL Clock for Presence Detect SDA Serial Data OUT for Presence Detect SA0–A2 Serial Data IN for Presence Detect CB0–CB4 Check Bits (x72 Organization) NC No Connection REGE Register Enable DU Don’t Use

V437216C04VDTG-10PC Rev. 1.3 July 2001 Module Part Number Information Block Diagram SDRAM 3.3V MOSEL-VITELIC MANUFACTURED V

168 PIN REGISTERED

C REFRESH RATE 4K DEPTH

4 BANKS

V D VERSION D GOLD G 10PC- -10PC PC100 2-2-2 T RQM0 I/O1–I/O4 10Ω RCS0 CS D0–D17RAS R E G I S T E R VDD RRAS D0–D17CAS RCAS D0–D17WE RWE CKE0 R0CKE0, R1CKE0 DQM0–DQM7 RDQM0–RDQM7 CS0, CS RC0, RCS2 D0–D17A0–A11 RA0–RA11 D0–D17BA0, BA1 PLL CLK PLL RBA0, RBA1 CLK1–CLK3 REGE D0–D17 12pF 10K 10K DQM I/O1–I/O4 D0 I/O5–I/O8 10Ω CSDQM I/O1–I/O4 D1 RQM4 I/O33–I/O36 10Ω CSDQM I/O1–I/O4 D9 I/O37–I/O40 10Ω CSDQM I/O1–I/O4D10 RQM1 I/O9–I/O12 10Ω CSDQM I/O1–I/O4 D2 I/O13–I/O16 10Ω CSDQM I/O1–I/O4 D3 RQM5 I/O41–I/O44 10Ω CS RQM2 I/O17–I/O20 10Ω CSDQM I/O1–I/O4 D5 I/O21–I/O24 10Ω CSDQM I/O1–I/O4 D6 RQM6 I/O49–I/O52 10Ω CSDQM I/O1–I/O4D14 I/O53–I/O56 10Ω CSDQM I/O1–I/O4D15 RQM3 I/O25–I/O28 10Ω CSDQM I/O1–I/O4 D7 I/O29–I/O32 10Ω CSDQM I/O1–I/O4 D8 RQM7 I/O57–I/O60 10Ω CSDQM I/O1–I/O4D16 I/O61–I/O64 10Ω CSDQM I/O1–I/O4D17 DQM I/O1–I/O4D11 I/O45–I/O48 10Ω CSDQM I/O1–I/O4D12 CB1–CB3 10Ω CSDQM I/O1–I/O4 D4 CB4–CB7 10Ω CSDQM I/O1–I/O4D13 RCS2 CLK0 12pF 10K

V437216C04VDTG-10PC Rev. 1.3 July 2001 MOSEL VITELIC V437216C04VDTG-10PC Serial Presence Detect Information A serial presence detect storage device – E PROM – is assembled onto the module. Informa- tion about the module configuration, speed, etc. is written into the E PROM device during module pro- duction using a serial presence detect protocol (I C synchronous 2-wire bus) SPD-Table for -10PC modules: Byte Number Function Described SPD Entry Value Hex Value 16Mx72

0 Number of SPD bytes 128 80

1 Total bytes in Serial PD 256 08

2 Memory Type SDRAM 04

3 Number of Row Addresses (without BS bits) 12 0C

4 Number of Column Addresses (for x4 SDRAM) 10 0A

5 Number of DIMM Banks 1 01

6 Module Data Width 72 48

7 Module Data Width (continued) 0 00

8 Module Interface Levels LVTTL 01

9 SDRAM Cycle Time at CL=3 10.0 ns A0 10 SDRAM Access Time from Clock at CL=3 6.0 ns 60 11 Dimm Config (Error Det/Corr.) ECC 02 12 Refresh Rate/Type Self-Refresh, 15.8 µ s8 0

13 SDRAM width, Primary x4 04

14 Error Checking SDRAM Data Width x4 04

15 Minimum Clock Delay from Back to Back Random

t ccd = 1 CLK 01

16 Burst Length Supported 1, 2, 4, 8, full page 8F

17 Number of SDRAM Banks 4 04

18 Supported CAS

Latencies CL = 2, 3 06

19 CS Latencies CS Latency = 0 01

20 WE Latencies WL = 0 01

21 SDRAM DIMM Module Attributes Registered/Buffered 1F

22 SDRAM Device Attributes: General Vcc tol ± 10% 0E

23 Minimum Clock Cycle Time at CAS

Latency = 2 10.0 ns A0 24 Maximum Data Access Time from Clock for CL = 2 6.0 ns 60

25 Minimum Clock Cycle Time at CL = 1 Not Supported 00

26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00

27 Minimum Row Precharge Time 20 ns 14

28 Minimum Row Active to Row Active Delay t

29 Minimum RAS to CAS Delay t

30 Minimum RAS Pulse Width t

V437216C04VDTG-10PC Rev. 1.3 July 2001 DC Characteristics T A = 0 C to 70 C; V SS = 0 V; V DD , V DDQ = 3.3V 0.3V

31 Module Bank Density (Per Bank) 128 MByte 20

32 SDRAM Input Setup Time 2 ns 20

33 SDRAM Input Hold Time 1 ns 10

34 SDRAM Data Input Setup Time 2 ns 20

35 SDRAM Data Input Hold Time 1 ns 10

62-61 Superset Information (May be used in Future) 00

63 Checksum for Bytes 0 - 62 36

64 Manufacturer ’s JEDEC ID Code Mosel Vitelic 40

65-71 Manufacturer ’s JEDEC ID Code (cont.) 00

72 Manufacturing Location

73-90 Module Part Number (ASCII) V437216C04VDTG-10PC 91-92 PCB Identification Code

93 Assembly Manufacturing Date (Year)

94 Assembly Manufacturing Date (Week)

95-98 Assembly Serial Number 99-125 Reserved 00

126 Intel Specification for Frequency 100 MHz 64

127 Detailed 100 MHz Information 8F

128+ Unused Storage Location 00 Symbol Parameter Limit Values UnitMin. Max. V IH Input High Voltage 2.0 V CC +0.3 V V IL Input Low Voltage –0.3 0.8 V V OH Output High Voltage (I OUT = –4.0 mA) 2.4 — V V OL Output Low Voltage (I OUT = 4.0 mA) — 0.4 V I I(L) Input Leakage Current, any input (0 V < V IN < 3.6 V, all other inputs = 0V) –10 10 µ A I O(L) Output leakage current (DQ is disabled, 0V < V OUT < V CC –10 10 µ A SPD-Table for -10PC modules: (Continued) Byte Number Function Described SPD Entry Value Hex Value 16Mx72

V437216C04VDTG-10PC Rev. 1.3 July 2001 MOSEL VITELIC V437216C04VDTG-10PC Capacitance T A = 0 C to 70 C; V DD = 3.3V 0.3V, f = 1 MHz Absolute Maximum Ratings Symbol Parameter Limit Values UnitMin. Max. C Input Capacitance (A0 to A11, RAS, CAS, WE) 8 15 pF C Input Capacitance (CS0-CS3) 8 15 pF C ICL Input Capacitance (CLK0) — 20 pF C Input Capacitance (CKE0) 8 15 pF C Input Capacitance (DQM0-DQM7) 8 15 pF C IO Input/Output Capacitance (I/O1-I/064) 9 16 pF C SC Input Capacitance (SCL, SA0-2) — 8p F Parameter Max. Units Voltage on VDD Supply Relative to V SS -1 to 4.6 V Voltage on Input Relative to V SS -1 to 4.6 V Operating Temperature 0 to +70 °C Storage Temperature -55 to 125 °C Power Dissipation 8W

V437216C04VDTG-10PC Rev. 1.3 July 2001 Standby and Refresh Currents T A = 0 C to 70 C, V CC = 3.3V 0.3V Symbol Parameter Test Conditions 16M x 72 Unit Note I CC

1 Operating Current Burst length = 4, CL = 3

t RC > = t RC (min), t CK > = t CK (min), IO = 0 mA

2 Bank Interleave Operation

2340 mA 1,2 I CC 2P Precharged Standby Current in Power Down Mode CKE< = V IL (max), t CK > = t CK (min) 36 mA I CC 2N Precharged Standby Current in Non-Power Down Mode CKE> = V IH (min), t CK > = t CK (min), Input changed once in 3 cycles 630 mA CS = High I CC 3P Active Standby Current in Power Down Mode CKE< = V IL (max), t CK > = t CK (min) 144 mA I CC 3N Active Standby Current in Non-Power Down Mode CKE> = V IH (min), t CK > = t CK (min), Input changed one time 810 mA CS = High I CC

4 Burst Operating Current t

= Infinite, CL = 3, t CK > = t CK (min), IO = 0 mA

2 Banks Activated

1980 mA 1, 2 ICC5 Auto Refresh Current t RC>= tRC(min) 2340 mA 1,2 ICC6 Self Refresh Current CKE = <0,2 V Standard 18 mA 1,2 L-version 7.2

8V437216C04VDTG-10PC Rev. 1.3 July 2001 MOSEL VITELIC V437216C04VDTG-10PC AC Characteristics 3,4 TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns # Symbol Parameter Limit Values Unit Note -10PC Min. Max. Clock and Clock Enable 1t CK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 ns ns 2f CK System frequency CAS Latency = 3 CAS Latency = 2 100 100 MHz MHz 3t AC Clock Access Time CAS Latency = 3 CAS Latency = 2 ns ns 2, 4 4t CH Clock High Pulse Width 3 – ns 6 5t CL Clock Low Pulse Width 3 – ns 6 6t CS Input Setup time 2 – ns 7 7t CH Input Hold Time 1 – ns 7 8t CKSP CKE Setup Time (Power down mode) 2.5 – ns 8 9t CKSR CKE Setup Time (Self Refresh Exit) 8 – ns 9 10 t T Transition time (rise and fall) 1 – ns Common Parameters 11 t RCD RAS to CAS delay 20 – ns 6 12 t RC Cycle Time 70 120K ns 6 13 t RAS Active Command Period 45 – ns 6 14 t RP Precharge Time 20 – ns 6 15 t RRD Bank to Bank Delay Time 16 – ns 6 16 t CCD CAS to CAS delay time (same bank) 1 – CLK Refresh Cycle 17 t SREX Self Refresh Exit Time 10 – ns 18 t REF Refresh Period (8192 cycles) 64 – ms Read Cycle 19 t OH Data Out Hold Time 3 – ns 2, 4 20 t LZ Data Out to Low Impedance Time 0 – ns 21 t HZ Data Out to High Impedance Time 3 9 ns 10 22 t DQZ DQM Data Out Disable Latency 2 – CLK Write Cycle 23 t DPL Data input to Precharge (write recovery) 2 – CLK 24 t DQW DQM Write Mask Latency 0 – CLK 11

MOSEL VITELIC V437216C04VDTG-10PC 9V437216C04VDTG-10PC Rev. 1.3 July 2001 Notes: 1. The specified values are valid when addresses are changed no more than once during t CK(min.) and when No Operation commands are registered on every rising clock edge during t RC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ ’s) are stable during tRC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. time is measured between V IH and V IL. All AC measurements assume t T = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V. 5. If clock rising time is longer than 1 ns, a time (t T/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If t T is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. t DAL is equivalent to tDPL + tRP. 1.4V 1.4V tSETUP tHOLD tAC tAC tLZ tOH tHZ CLOCK INPUT OUTPUT 50 pF I/O Z=50 Ohm + 1.4 V

50 Ohm

2.4V 0.4V tT tCL tCH I/O Measurement conditions for tac and toh 50 pF

10V437216C04VDTG-10PC Rev. 1.3 July 2001 MOSEL VITELIC V437216C04VDTG-10PC Package Diagram L-DIM-168-30 SDRAM DIMM Module Package 127.35 133.37 42.18 D 63.68 3.0 1.27 ± 0.100 All measurements in mm 43.15 11 0 1 1 4 0 4 1 8 4 85 94 95 124 125 168 17.80 BA 6.35 2.26 RADIUS 1.27 + 0.10 Detail A 3.125 4.45 2.0 6.35 3.175 Detail B 3.125 2.0 1.0 ± 0.051.27 Detail C 2.50 0.2 ± 0.15 4.0 Tolerances: ± (0.13) unless otherwise specified. (4.0 max)

MOSEL VITELIC V437216C04VDTG-10PC 11V437216C04VDTG-10PC Rev. 1.3 July 2001 Label Information CL = 2 (CLK) tRCD = 2 (CLK) tRP = 2 (CLK) tAC = 6 ns 222R Registered DIMM PC100 6 V437216C04VDTG-10PC PC100R-222-612-A Taiwan XXXX-XXXXXXX A Gerber file Intel® PC100 x 4 Based -- - MOSEL VITELIC Part Number DIMM manufacture date code Trace Code Criteria of PC100 or PC133 (refer to MVI datasheet)

MOSEL VITELIC WORLDWIDE OFFICES V437216C04VDTG-10PC © Copyright 2001, MOSEL VITELIC Inc. 7/01 Printed in U.S.A. MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461 The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep cur- rent the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. U.S. SALES OFFICES U.S.A.

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