V436632Z24V

V436632Z24V MOSEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 12

Technical content

Features

■ JEDEC-standard 144 pin, Small-Outline, Dual in line Memory Module (SODIMM) ■ Serial Presence Detect with E2PROM ■ Nonbuffered ■ Fully Synchronous, All Signals Registered on Positive Edge of System Clock ■ Single +3.3V (± 0.3V) Power Supply ■ All Device Pins are LVTTL Compatible ■ 8192 Refresh Cycles every 64 ms ■ Self-Refresh Mode ■ Internal Pipelined Operation; Column Address can be changed every System Clock ■ Programmable Burst Lengths: 1, 2, 4, 8 ■ Auto Precharge and Piecharge all Banks by A10 ■ Data Mask Function by DQM ■ Mode Register Set Programming ■ Programmable (CAS Latency:2, 3 Clocks)

Description

The V436632Z24V memory module is organized 33,554,432 x 64 bits in a 144 pin SODIMM. The 32M x 64 memory module uses 8 Mosel-Vitelic 32M x 8 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Part Number Speed Grade Configuration V436632Z24VXTG-75PC -75PC, CL=2,3 (133 MHz) 32M x 64 V436632Z24VXTG-75 -75, CL=3 (133 MHz) 32M x 64 V436632Z24VXTG-10PC -10PC, CL=2,3 (100 MHz) 32M x 64 Pin 2 on Backside Pin 144 on Backside 59 61 143 32M x 8 32M x 8 32M x 8 32M x 8

2V436632Z24V Rev. 1.1 February 2002 M OS EL V ITE LIC V436632Z24V Pin Configurations (Front Side/Back Side) Note: 1. RAS , CAS, WE CAS x, CSx are active low signals. Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back VSS VSS DQ0 DQ32 DQ1 DQ33 DQ2 DQ34 DQ3 DQ35 VDD VDD DQ4 DQ36 DQ5 DQ37 DQ6 DQ38 DQ7 DQ39 VSS VSS DQMB0 DQMB4 DQMB1 DQMB5 VDD VDD VSS VSS DQ8 DQ40 DQ9 DQ41 DQ10 DQ42 DQ11 DQ43 VDD VDD DQ12 DQ44 DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 VSS VSS NC NC NC NC CLK0 CKE0 VDD VDD RAS CAS WE CKE1 CS0 A12 CS1 NC NC CLK1 VSS VSS NC NC NC NC VDD VDD DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 VSS VSS DQ20 DQ52 DQ21 DQ53 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 DQ22 DQ54 DQ23 DQ55 VDD VDD BA0 VSS VSS BA1 A10 A11 VDD VDD DQMB2 DQMB6 DQMB3 DQMB7 VSS VSS 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 DQ24 DQ56 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 VDD VDD DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63 VSS VSS SDA SCL VDD VDD Pin Names A0–A12, BA0, BA1 Address, Bank Select DQ0–DQ63 Data Inputs/Outputs RAS Row Address Strobes CAS Column Address Strobes WE Write Enable CS 0, CS1 Chip Select DQMB0–DQMB7 Output Enable CKE0, CKE1 Clock Enable CLK0, CLK1 Clock SDA Serial Input/Output SCL Serial Clock VDD Power Supply VSS Ground NC No Connect (Open)

M OS EL V ITE LIC V436632Z24V 3V436632Z24V Rev. 1.1 February 2002 Part Number Information Block Diagram V 4 3 66 32 Z 2 4 V X X G - XX SDRAM 3.3V WIDTH DEPTH

144 PIN Unbuffered

COMPONENT A=0.17u B=0.14u REV LEVEL COMPONENT PACKAGE, T = TSOP LEAD FINISH G = GOLD SPEED 75PC = PC133 CL3,2MOSEL VITELIC MANUFACTURED 75 = PC133 CL3 10PC = PC133 CL3,2 WE CSO U0–U7A0–A12, BA0, BA1 VDD U0–U3CKE0 U4–U7CKEI U0–U7RAS U0–U7CAS U0–U7 U0, U1 CLK0 VSS U2, U3 SCL SDA U4, U5 CLKI U6, U7 SPD A0 A1 A2 DQMB4 DQ32–3 9 DQ40–47 DQM DQMB0 DQ0–7 DQ8–15 DQM DQMB5 DQM DQMB1 DQ16–23 DQ24–31 DQM CSWE CSWE CSWE CSWE DQMB6 DQ48–55DQM DQMB2 DQM DQMB7 DQ56–6 3DQM DQMB3 C1–C4 DQM CSWE CSWE CSWE CSWE

4V436632Z24V Rev. 1.1 February 2002 M OS EL V ITE LIC V436632Z24V Serial Presence Detect Information A serial presence detect storage device - E2PROM - is assembled onto the module. Informa- tion about the module configuration, speed, etc. is written into the E2PROM device during module pro- duction using a serial presence detect protocol (I2C synchronous 2-wire bus) SPD-Table Byte Number Function Described SPD Entry Value Hex Value -75PC -75 -10PC

0 Number of SPD bytes 128 80 80 80

1 Total bytes in Serial PD 256 08 08 08

2 Memory Type SDRAM 04 04 04

3 Number of Row Addresses (without BS bits) 13 0D 0D 0D

4 Number of Column Addresses (for x8

SDRAM) 10 0A 0A 0A

5 Number of DIMM Banks 1 01 01 01

6 Module Data Width 64 40 40 40

7 Module Data Width (continued) 0 00 00 00

8 Module Interface Levels LVTTL 01 01 01

9 SDRAM Cycle Time at CL=3 7.5 ns/10.0 ns 75 75 A0 10 SDRAM Access Time from Clock at CL=3 5.4 ns/6.0 ns 54 54 60 11 Dimm Config (Error Det/Corr.) none 00 00 00 12 Refresh Rate/Type Self-Refresh,7.8 µs8 2 8 2 8 2

13 SDRAM width, Primary x8 08 08 08

14 Error Checking SDRAM Data Width n/a / x8 00 00 00

15 Minimum Clock Delay from Back to Back

t ccd = 1 CLK 01 01 01

16 Burst Length Supported 1, 2, 4 & 8 0F 0F 0F

17 Number of SDRAM Banks 4 04 04 04

18 Supported CAS

Latencies CL =2, 3 06 06 06

19 CS Latencies CS Latency = 0 01 01 01

20 WE Latencies WL = 0 01 01 01

21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00 00 00

22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 0E 0E

23 Minimum Clock Cycle Time at CAS

= 2 7.5 ns/10.0 ns 75 A0 A0

24 Maximum Data Access Time from Clock for

CL = 2 5.4 ns/6.0 ns 54 60 60

25 Minimum Clock Cycle Time at CL = 1 Not Supported 00 00 00

26 Maximum Data Access Time from Clock at

CL = 1 Not Supported 00 00 00

27 Minimum Row Precharge Time 15 ns/20 ns 0F 14 14

M OS EL V ITE LIC V436632Z24V 5V436632Z24V Rev. 1.1 February 2002

28 Minimum Row Active to Row Active Delay

14 ns/15 ns/16 ns 0E 0F 10

29 Minimum RAS to CAS Delay tRCD 15 ns/20 ns 0F 14 14

30 Minimum RAS Pulse Width t RAS 42 ns/45 ns 2A 2D 2D

31 Module Bank Density (Per Bank) 256 Mbyte 40 40 40

32 SDRAM Input Setup Time 1.5 ns/2.0 ns 15 15 20 33 SDRAM Input Hold Time 0.8 ns/1.0 ns 08 08 10 34 SDRAM Data Input Setup Time 1.5 ns/2.0 ns 15 15 20 35 SDRAM Data Input Hold Time 0.8 ns/1.0 ns 08 08 10 62-61 Superset Information (May be used in Fu- ture) 00 00 00

63 Checksum for Bytes 0 - 62 FD 42 B0

64 Manufacturer’s JEDEC ID Code Mosel Vitelic 40 40 40

65-71 Manufacturer’s JEDEC ID Code (cont.) 00 00 00

72 Manufacturing Location 1 = US, 2 = Taiwan

73-90 Module Part Number (ASCII) V436632Z24V 91-92 PCB Identification Code Current PCB Revision

93 Assembly Manufacturing Date (Year) Binary Coded year (BCD)

94 Assembly Manufacturing Date (Week) Binary Coded week (BCD)

95-98 Assembly Serial Number byte 95 = LSB, byte 98 = MSB 99-125 Reserved 00 00 00

126 Intel Specification for Frequency 64 64 64

127 Reserved 00 00 00

128+ Unused Storage Location 00 00 00 SPD-Table Byte Number Function Described SPD Entry Value Hex Value -75PC -75 -10PC

6V436632Z24V Rev. 1.1 February 2002 M OS EL V ITE LIC V436632Z24V DC Characteristics TA = 0°C to 70°C; VSS = 0 V; VDD , VDDQ = 3.3V ± 0.3V Capacitance TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz Symbol Parameter Limit Values UnitMin. Max. V IH Input High Voltage 2.0 V CC +0.3 V V IL Input Low Voltage –0.5 0.8 V V OH Output High Voltage (IOUT = –4.0 mA) 2.4 — V V OL Output Low Voltage (IOUT = 4.0 mA) — 0.4 V II(L) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) –10 10 µA IO(L) Output leakage current (DQ is disabled, 0V < VOUT < VCC ) –10 10 µA Symbol Parameter Limit Values (Max.) Unit C I1 Input Capacitance (A0 to A11, RAS, CAS, WE)4 0 p F C I2 Input Capacitance (CS0, CSI)2 5 p F C ICL Input Capacitance (CLK0-CLK1) 28 pF C I3 Input Capacitance (CKE0, CKEI) 20 pF C I4 Input Capacitance (DQMB0-DQMB7) 10 pF C SC Input Capacitance (SCL, SA0-2) 8 pF C IO Input/Output Capacitance 18 pF

M OS EL V ITE LIC V436632Z24V 7V436632Z24V Rev. 1.1 February 2002 Absolute Maximum Ratings Standby and Refresh Currents1 TA = 0°C to 70°C, VCC = 3.3V ± 0.3V Parameter Max. Units Voltage on VDD Supply Relative to VSS -1 to 4.6 V Voltage on Input Relative to VSS -1 to 4.6 V Operating Temperature 0 to +70 °C Storage Temperature -55 to 125 °C Power Dissipation 6.3 W Symbol Parameter Test Conditions -75PC/75 -10PC Unit Note ICC 1 Operating Current Burst length = 4, CL = 3 tRC > = tRC (min), tCK > = tCK (min), IO = 0 mA

2 Bank Interleave Operation

1840 1680 mA 1,2 ICC 2P Precharged Standby Current in Pow- er Down Mode CKE< = VIL(max), tCK > = tCK (min) 16 16 mA ICC 2N Precharged Standby Current in Non-Power Down Mode CKE> = VIH(min), tCK > = tCK (min), Input changed once in 3 cycles 360 280 mA CS = High ICC 3P Active Standby Current in Power Down Mode CKE< = VIL(max), tCK > = tCK (min) 80 80 mA ICC 3N Active Standby Current in Non-Power Down Mode CKE> = VIH(min), tCK > = tCK (min), Input changed one time 440 360 mA CS = High ICC 4 Burst Operating Current Burst length = Full Page, tRC = Infinite, CL = 3, tCK > = tCK (min), IO = 0 mA

2 Banks Activated

1200 960 mA 1, 2 ICC 5 Auto Refresh Current t RC >= tRC (min) 1920 1760 mA 1,2 ICC 6 Self Refresh Current CKE = <0,2 V Standard 24 24 mA 1,2 L-Version 14 14

8V436632Z24V Rev. 1.1 February 2002 M OS EL V ITE LIC V436632Z24V AC Characteristics 3,4 TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns # Symbol Parameter Limit Values Unit Note -75PC -75 -10PC Clock and Clock Enable 1t CK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 7.5 7.5 7.5 ns ns 2f CK System frequency CAS Latency = 3 CAS Latency = 2 133 133 133 100 100 100 MHz MHz 3t AC Clock Access Time CAS Latency = 3 CAS Latency = 2 5.4 5.4 ns ns 4,5 4t CH Clock High Pulse Width 2.5 – 2.5 – 3 – ns 6 5t CL Clock Low Pulse Width 2.5 – 2.5 – 3 – ns 6 6t CS Input Setup time 1.5 – 1.5 – 2 – ns 7 7t CH Input Hold Time 0.8 – 0.8 – 1 – ns 7 8t CKSP CKE Setup Time (Power down mode) 2.5 – 2.5 – 2 – ns 8 9t CKSR CKE Setup Time (Self Refresh Exit) 8 – 8 – 8 – ns 9 10 t T Transition time (rise and fall) 1 – 1 – 1 – ns Common Parameters 11 t RCD RAS to CAS d e l a y 2 0–2 0–2 0–n s 12 t RC Cycle Time 70 120k 70 120k 70 120k ns 13 t RAS Active Command Period 42 – 45 – 45 – ns 14 t RP Precharge Time 15 – 20 – 20 – ns 15 t RRD Bank to Bank Delay Time 14 – 15 – 20 – ns 16 t CCD CAS to CAS delay time (same bank) 1–1–1– C L K Refresh Cycle 17 t SREX Self Refresh Exit Time 10 – 10 – 10 –n s9 18 t REF Refresh Period (8192 cycles) 64 – 64 – 64 – ms 8 Read Cycle 19 t OH D a t a O u t H o l d T i m e 3–3–3– n s 4 20 t LZ Data Out to Low Impedance Time 0 – 0 – 0 – ns 21 t HZ Data Out to High Impedance Time 3 7.5 3 7.5 3 8 ns 10 22 t DQZ DQM Data Out Disable Latency 2 - 2 - 2 - CLK Write Cycle 23 t DPL Data input to Precharge (write recovery) 2 – 2 – 1 – CLK 24 t DAL Data In to Active/refresh 5 – 5 – 5 – CLK 11 25 t DQW D Q M W r i t e M a s k L a t e n c y 0–0–0– C L K

M OS EL V ITE LIC V436632Z24V 9V436632Z24V Rev. 1.1 February 2002 Notes: 1. The specified values are valid when addresses are changed no more than once during tCK (min.) and when No Operation commands are registered on every rising clock edge during tRC (min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during tRC (min.). 3. All AC characteristics are shown for device level. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V. 5. If clock rising time is longer than 1 ns, a time (t T/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If t T is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. tDAL is equivalent to tDPL + tRP . 1.4V 1.4V tSETUP tHOLD tAC tAC tLZ tOH tHZ CLOCK INPUT OUTPUT 50 pF I/O Z=50 Ohm + 1.4 V

50 Ohm

2.4V 0.4V tT tCL tCH I/O Measurement conditions for tac and toh 50 pF

10V436632Z24V Rev. 1.1 February 2002 M OS EL V ITE LIC V436632Z24V Package Diagram

144 Pin SODIMM

2.661 1.25 0.039 0.140 0.787 Pin 2 on Backside 3.3V Pin 144 on Backside 59 61 143 N OTE: 1. All dimensions in inches. Tolerances ±0.005 unless otherwise specified.

M OS EL V ITE LIC V436632Z24V 11V436632Z24V Rev. 1.1 February 2002 Module Label Information C L= 3 or 2 (CLK) tRCD = 3 or 2 (CLK) tRP = 3 or 2 (CLK) -XXXU UNBUFFERED SODIMM PC133 54 V436632Z24VXXX-XX 256MB CLX PC133U-XXX-542-A XXXX-XXXXXXX Assembly in Taiwan A Gerber file Intel PC100 x8 Based MOSEL VITELIC Part Number Module Density D IMM manufacture date code Criteria of PC100 or PC133 (refer to MVI datasheet) tAC = 5.4 ns CAS Latency 2=CL2 3=CL3

12V436632Z24V Rev. 1.1 February 2002 M OS EL V ITE LIC V436632Z24V WORLDWIDE OFFICES © Copyright , MOSEL VITELIC Corp. Printed in U.S.A. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep cur- rent the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality contr ol sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. U.S. SALES OFFICES U .S.A.

3910 NORTH FIRST STREET

SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 TAIWAN 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 SINGAPORE

10 ANSON ROAD #23-13

PHONE: 65-3231801 FAX: 65-3237013 JAPAN ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402 UK & IRELAND SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516 GERMANY (CONTINENTAL EUROPE & ISRAEL) BENZSTRASSE 32

71083 HERRENBERG

PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 W EST SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 CENTRAL / EAST

604 FIELDWOOD CIRCLE

RICHARDSON, TX 75081 PHONE: 214-352-3775 FAX: 214-904-9029