V436616R24VATG-75L

V436616R24VL MOSEL | Alldatasheet

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Technical content

Features

I 168 Pin Unbuffered 16, 777, 216 x 64 bit Oganization SDRAM DIMM I Utilizes High Performance 256 Mbit, 16M x 16 SDRAM in TSOPII-54 Packages I Fully PC Board Layout Compatible to INTEL’S Rev 1.0 Module Specification I Single +3.3V (± 0.3V) Power Supply I Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) I Auto Refresh (CBR) and Self Refresh I All Inputs, Outputs are LVTTL Compatible I 8192 Refresh Cycles every 64 ms I Serial Present Detect (SPD) I SDRAM Performance I Supported Latencies at 133 MHz Operation for Module

Description

The V436616R24V(L) memory module is organized 16, 777, 216 x 64 bits in a 168 pin dual in line memory module (DIMM). The 16M x 64 memory module uses 4 Mosel-Vitelic 16M x 16 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Component Used -7 Units tCK Clock Frequency (max.) CL=3 143 MHz CL=2 100 MHz tAC Clock Access Time CAS Latency CL=3 5.4 ns CL=2 6 ns CL t RCD tRP tRC

3338 C L K

2V436616R24V(L) Rev. 1.0 November 2001 M OS EL V ITE LIC V436616R24V(L) Pin Configurations (Front Side/Back Side) Notes: * These pins are not used in this module. Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO* CB1* VSS NC NC VCC WE DQM0 DQM1 CS0 DU VSS A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2* CB3* VSS I/O17 I/O18 I/O19 I/O20 VCC I/O21 NC DU CKE1 VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2 NC WP SDA SCL VCC 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4* CB5* VSS NC NC VCC CAS DQM4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 DQM5 CS1 RAS VSS BA0 A11 VCC CLK1 A12 VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6* CB7* VSS I/O49 I/O50 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 I/O51 I/O52 VCC I/O53 NC DU NC VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3 NC SA0 SA1 SA2 VCC Pin Names A0–A12 Address Inputs I/O1–I/O64 Data Inputs/Outputs RAS Row Address Strobe CAS Column Address Strobe WE Read/Write Input BA0, BA1 Bank Selects CKE0 , CKE1 Clock Enable CS 0–CS 3 Chip Select CLK0–CLK3 Clock Input DQM0–DQM7 Data Mask VCC Power (+3.3 Volts) VSS Ground SCL Clock for Presence Detect SDA Serial Data OUT for Presence Detect SA0–A2 Serial Data IN for Presence Detect CB0–CB7 Check Bits (x72 Organization) NC No Connection DU Don’t Use

M OS EL V ITE LIC V436616R24V(L) 3V436616R24V(L) Rev.1.0 November 2001 Part Number Information Functional Block Diagram Part Number Description V436616R24VATG-75L 128 MB, 16M x 64, 133 MHz, CL3 V436616R24VATG-10PCL 128 MB, 16M x 64, 100 MHz, CL2 DQM0 I/O1–I/O8 CS0 CS2 WE WE WE: SDRAM D0 –D3 CKE: SDRAM D0 –D3 RAS: SDRAM D0 –D3 A(12:0): SDRAM D0–D3 BA0, BA1: SDRAM D0–D3 CKE0 RAS CAS WE A(12:0) BA0, BA1 CAS: SDRAM D0 –D3 C0 –C7 Two 0.1µF capacitors per each SDRAM D0 –D3 D0 –D3 VCC VSS SCL0 SA2 SA1 SA0 CLK0/2 SDA WP D0/D2 D1/D3 E 2PROM SPD (256 WORD X 8 BITS) 47K LDQM I/O1–I/O8 UDQM I/O9–I/O16 CS DQM1 I/O9–I/O16 DQM4 I/O33–I/O40 WE LDQM I/O1–I/O8 UDQM I/O9–I/O16 CS DQM5 I/O41–I/O48 DQM2 I/O17–I/O24 WE LDQM I/O1–I/O8 UDQM I/O9–I/O16 CS DQM3 I/O25–I/O32 DQM6 I/O49–I/O56 WE LDQM I/O1–I/O8 UDQM I/O9–I/O16 CS DQM7 I/O57–I/O64 CLK1/3 3.3pF 3.3pF V 4 3 66 16 R 2 4 V A T G -X X (L) SDRAM 3.3V WIDTH DEPTH

168 PIN Unbuffered

PACKAGE, T = TSOP LEAD FINISH G=G O L D SPEED 75PC = PC133 CL3,2MOSEL VITELIC MANUFACTURED 75 = PC133 CL3 10PC = PC133 CL3,2 LOW RPROFILE

4V436616R24V(L) Rev. 1.0 November 2001 M OS EL V ITE LIC V436616R24V(L) Serial Presence Detect Information A serial presence detect storage device - E2PROM - is assembled onto the module. Informa- tion about the module configuration, speed, etc. is w r i t t e ni n t ot h eE2PROM device during module pro- duction using a serial presence detect protocol (I2C synchronous 2-wire bus) SPD-Table: Byte Number Function Described SPD Entry Value Hex Value 16Mx64

0 Number of SPD bytes 128 80

1 Total bytes in Serial PD 256 08

2 Memory Type SDRAM 04

3 Number of Row Addresses (without BS bits) 13 0D

4 Number of Column Addresses (for x16 SDRAM) 9 09

5 Number of DIMM Banks 1 01

6 Module Data Width 64 40

7 Module Data Width (continued) 0 00

8 Module Interface Levels LVTTL 01

9 SDRAM Cycle Time at CL=3 7.5 ns 75 10 SDRAM Access Time from Clock at CL=3 5.4 ns 54 11 Dimm Config (Error Det/Corr.) none 00 12 Refresh Rate/Type Self-Refresh, 7.8 µs8 2

13 SDRAM width, Primary x16 10

14 Error Checking SDRAM Data Width n/a / x16 00

15 Minimum Clock Delay from Back to Back Random

t ccd =1C L K 0 1

16 Burst Length Supported 1, 2, 4, 8 0F

17 Number of SDRAM Banks 4 04

18 Supported CAS

Latencies CL =2, 3 06

19 CS Latencies CS Latency = 0 01

20 WE Latencies WL = 0 01

21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00

22 SDRAM Device Attributes: General Vcc tol ± 10% 0E

2 3 M i n i m u mC l o c kC y c l eT i m ea tC A SLatency = 2 10.0 ns A0 24 Maximum Data Access Time from Clock for CL = 2 6.0 ns 60

25 Minimum Clock Cycle Time at CL = 1 Not Supported 00

26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00

27 Minimum Row Precharge Time 20 ns 14

28 Minimum Row Active to Row Active Delay t

29 Minimum RAS to CAS Delay tRCD 20 ns 14

30 Minimum RAS Pulse Width t RAS 45 ns 2D

M OS EL V ITE LIC V436616R24V(L) 5V436616R24V(L) Rev.1.0 November 2001 DC Characteristics TA =0 °Ct o7 0°C; VSS =0V ;V DD ,VDDQ =3 . 3 V± 0.3V

31 Module Bank Density (Per Bank) 128 MByte 20

32 SDRAM Input Setup Time 1.5 ns 15 33 SDRAM Input Hold Time 0.8 ns 08 34 SDRAM Data Input Setup Time 1.5 ns 15 35 SDRAM Data Input Hold Time 0.8 ns 08 62-61 Superset Information (May be used in Future) 00

63 Checksum for Bytes 0 - 62 29

64 Manufacturer ’s JEDEC ID Code Mosel Vitelic 40

65-71 Manufacturer ’s JEDEC ID Code (cont.) 00

72 Manufacturing Location

73-90 Module Part Number (ASCII) V436616R24V(L) 91-92 PCB Identification Code

93 Assembly Manufacturing Date (Year)

94 Assembly Manufacturing Date (Week)

95-98 Assembly Serial Number 99-125 Reserved 00

126 Intel Specification for Frequency 64

127 Supported Features 8D

128+ Unused Storage Location 00 Symbol Parameter Limit Values UnitMin. Max. V IH Input High Voltage 2.0 V CC +0.3 V V IL Input Low Voltage –0.5 0.8 V V OH Output High Voltage (IOUT = –2.0 mA) 2.4 — V V OL Output Low Voltage (IOUT =2 . 0m A ) — 0.4 V II(L) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) –40 40 µA IO(L) Output leakage current (DQ is disabled, 0V < VOUT <V CC ) –40 40 µA SPD-Table: (Continued) Byte Number Function Described SPD Entry Value Hex Value 16Mx64

6V436616R24V(L) Rev. 1.0 November 2001 M OS EL V ITE LIC V436616R24V(L) Capacitance TA =0 °Ct o7 0°C; VDD =3 . 3 V± 0.3V, f = 1 MHz Absolute Maximum Ratings Symbol Parameter Limit Values UnitMax. 16M x 64 C I1 Input Capacitance (A0 to A11, RAS,C A S,W E)6 0 p F C I2 Input Capacitance (CS0-CS3)3 0 p F C ICL Input Capacitance (CLK0-CLK3) 22 pF C I3 Input Capacitance (CKE0, CKE1) 50 pF C I4 Input Capacitance (DQM0-DQM7) 15 pF C IO Input/Output Capacitance (I/O1-I/064) 15 pF C SC Input Capacitance (SCL, SA0-2) 8 pF C SD Input/Output Capacitance (SA0-SA2) 10 pF Parameter Max. Units V o l t a g eo nV D DS u p p l yR e l a t i v et oVSS -1 to 4.6 V V o l t a g eo nI n p u tR e l a t i v et oVSS -1 to 4.6 V Operating Temperature 0t o+ 7 0 °C Storage Temperature - 5 5t o1 2 5 °C Power Dissipation 3.2 W Operating Currents TA =0 °Ct o7 0°C, VCC =3 . 3 V± 0.3V (Recommended operating conditions otherwise noted) Symbol Parameter & Test Condition Max. Unit Note ICC1 Operating Current tRC =tRCMIN. ,tCK =tCKMIN . Active-precharge command cycling, without Burst Operation 1 bank operation 920 mA 7 ICC2P Precharge Standby Current in Power Down Mode CS =V IH,C K E≤ VIL(max) tCK =m i n . 1 2 m A 7 ICC2PS t CK = Infinity 8 mA 7 ICC2N Precharge Standby Current in Non-Power Down Mode CS =V IH,C K E≥ VIL(max) tCK =m i n . 1 6 0 m A ICC2NS t CK = Infinity 20 mA ICC3 No Operating Current tCK =m i n ,C S=V IH(min) bank ; active state ( 4 banks) CKE > VIH(MIN.) 200 mA ICC3P CKE < VIL(MAX.) (Power down mode) 40 mA ICC4 Burst Operating Current tCK =m i n Read/Write command cycling 600 mA 7,8

M OS EL V ITE LIC V436616R24V(L) 7V436616R24V(L) Rev.1.0 November 2001 Notes: 1. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC . Input signals are changed one time during tCK . 2. These parameter depend on output loading. Specified values are obtained with output open. ICC5 Auto Refresh Current tCK =m i n Auto Refresh command cycling 960 mA 7 ICC6 Self Refresh Current Self Refresh Mode, CKE<0.2V 12 mA L-version 6.8 mA AC Characteristics TA =0 °to 70°C; VSS =0 V ;VCC =3 . 3 V± 0.3V, tT =1n s # Symbol Parameter Limit Values Unit NoteMin. Max. Clock and Clock Enable 1t CK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 7.5 s ns ns CK Clock Frequency CAS Latency = 3 CAS Latency = 2 133 100 MHz MHz 3t AC Access Time from Clock CAS Latency = 3 CAS Latency = 2 5.4 6.0 ns ns 2, 4 4t CH Clock High Pulse Width 2.5 – ns 5t CL Clock Low Pulse Width 2.5 – ns 6t T Transition Tim 0.3 1.2 ns Setup and Hold Times 7t IS Input Setup Time 1.5 – ns 5 8t IH Input Hold Time 0.8 – ns 5 9t CKS Input Setup Time 1.5 – ns 5 10 t CKH CKE Hold Time 0.8 – ns 5 11 t RSC Mode Register Set-up Time 14 – ns 12 t SB Power Down Mode Entry Time 0 7.5 ns Operating Currents TA =0 °Ct o7 0°C, VCC =3 . 3 V± 0.3V (Recommended operating conditions otherwise noted) (Continued) Symbol Parameter & Test Condition Max. Unit Note

8V436616R24V(L) Rev. 1.0 November 2001 M OS EL V ITE LIC V436616R24V(L) Common Parameters 13 t RCD Row to Column Delay Time 15 – ns 6 14 t RP Row Precharge Time 15 – ns 6 15 t RAS Row Active Time 42 100K ns 6 16 t RC Row Cycle Time 60 – ns 6 17 t RRD Activate(a) to Activate(b) Command Period 15 – ns 6 18 t CCD CAS (a) to CAS(b) Command Period 1 – CLK Refresh Cycle 19 t REF Refresh Period (8192 cycles) — 64 ms 20 t SREX Self Refresh Exit Time 1 CLK Read Cycle 21 t OH Data Out Hold Time 3 – ns 2 22 t LZ Data Out to Low Impedance Time 1 – ns 23 t HZ D a t aO u tt oH i g hI m p e d a n c eT i m e 3 7 n s 7 24 t DQZ DQM Data Out Disable Latency – 2C L K Write Cycle 25 t WR Write Recovery Time 2 – CLK 26 t DQW DQM Write Mask Latency 0 – CLK AC Characteristics TA =0 °to 70°C; VSS =0 V ;VCC =3 . 3 V± 0.3V, tT = 1 ns (Continued) # Symbol Parameter Limit Values Unit NoteMin. Max.

M OS EL V ITE LIC V436616R24V(L) 9V436616R24V(L) Rev.1.0 November 2001 Notes: 1. The specified values are valid when addresses are changed no more than once during tCK (min.) and when No Operation commands are registered on every rising clock edge during tRC (min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during tRC (min.). 3. All AC characteristics are shown for device level. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V. 5. If clock rising time is longer than 1 ns, a time (t T/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If t T is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to“wake-up”the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. tDAL is equivalent to tDPL +tRP . 1.4V 1.4V tSETUP tHOLD tAC tAC tLZ tOH tHZ CLOCK INPUT OUTPUT 50 pF I/O Z=50 Ohm +1 . 4V

50 Ohm

2.4V 0.4V tT tCL tCH I/O Measurement conditions for tac and toh 50 pF

10V436616R24V(L) Rev. 1.0 November 2001 M OS EL V ITE LIC V436616R24V(L) Package Diagram SDRAM DIMM Module Package 0.250 (6.350) Detail A 0.123 ± .005 (3.125 ± .125) 0.250 (6.350) Detail B 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) 0.079 ± 0.004 (2.000 ± 0.100) Tolerances : ± 0.005(.13) unless otherwise specified

0.100 Max

0.050 ± 0.0039 (1.270 ± 0.10)

0.200 Min

(5.08 Min) (2.54 Max) 5.250 5.014 R 0.079 (R 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.118 (3.000) 0.350

0.100 Min

(2.540 Min) 0.700 (17.780) .118DIA ± 0.004 (3.000DIA ± 0.100) (8.890) A B C 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 ± 0.004 (4.000 ± 0.100) 0.089 (2.26) (127.350) (133.350) 1.000 (25.40) 0.118 (3.000) 0.050 0.008 ± 0.006 (0.200 ± 0.150) (1.270) (2.540 Min) Detail C 0.039 ± 0.002 (1.000 ± 0.050)

M OS EL V ITE LIC V436616R24V(L) 11V436616R24V(L) Rev.1.0 November 2001 Label Information C L= 3 or 2 (CLK) tRCD = 3 or 2 (CLK) tRP = 3 or 2 (CLK) -XXXU UNBUFFERED DIMM PC133 54 V436616R24XXXX-XX(L)128MB CLX PC133U-XXX-542-A XXXX-XXXXXXX Assembly in Taiwan A Gerber file Intel PC100 x16 Based MOSEL VITELIC Part Number Module Density DIMM manufacture date code Criteria of PC100 or PC133 (refer to MVI datasheet) tAC = 5.4 ns CAS Latency 2=CL2 3=CL3

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