V436516S04VATG-75PC

V436516S04VATG-75PC MOSEL | Alldatasheet

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Technical content

Features

I 168 Pin Unbuffered 16,777,216 x 64 bit Oganization SDRAM DIMM I Utilizes High Performance 128 Mbit, 16M x 8 SDRAM in TSOPII-54 Packages I Fully PC Board Layout Compatible to INTEL’S Rev 1.0 Module Specification I Single +3.3V (± 0.3V) Power Supply I Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) I Auto Refresh (CBR) and Self Refresh I All Inputs, Outputs are LVTTL Compatible I 4096 Refresh Cycles every 64 ms I Serial Present Detect (SPD) I SDRAM Performance I Supported Latencies at 133 MHz Operation

Description

The V436516S04VATG-75PC memory module is organized 16,777,216 x 64 bits in a 168 pin dual in line memory module (DIMM). The 16M x 64 memory module uses 8 Mosel-Vitelic 16M x 8 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Component Used -7PC Units tCK Clock Frequency (max.) CL=3 143 MHz CL=2 133 MHz tAC Clock Access Time CAS Latency CL=3 5.4 ns CL=2 5.4 ns CL t RCD tRP tRC

3338 C L K

2228 C L K

M OS EL V ITE LIC V436516S04VATG-75PC V436516S04VATG-75PC Rev. 1.4 September 2001 Pin Configurations (Front Side/Back Side) Notes: * These pins are not used in this module. Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO* CB1* VSS NC NC VCC WE DQM0 DQM1 CS0 DU VSS A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2* CB3* VSS I/O17 I/O18 I/O19 I/O20 VCC I/O21 NC DU CKE1 VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2 NC WP SDA SCL VCC 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4* CB5* VSS NC NC VCC CAS DQM4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 DQM5 CS1 RAS VSS BA0 A11 VCC CLK1 NC VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6* CB7* VSS I/O49 I/O50 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 I/O51 I/O52 VCC I/O53 NC DU NC VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3 NC SA0 SA1 SA2 VCC Pin Names A0–A11 Address Inputs I/O1–I/O64 Data Inputs/Outputs RAS Row Address Strobe CAS Column Address Strobe WE Read/Write Input BA0, BA1 Bank Selects CKE0 , CKE1 Clock Enable CS 0–CS 3 Chip Select CLK0–CLK3 Clock Input DQM0–DQM7 Data Mask VCC Power (+3.3 Volts) VSS Ground SCL Clock for Presence Detect SDA Serial Data OUT for Presence Detect SA0–A2 Serial Data IN for Presence Detect CB0–CB7 Check Bits (x72 Organization) NC No Connection DU Don’t Use

M OS EL V ITE LIC V436516S04VATG-75PC 3V436516S04VATG-75PC Rev. 1.4 September 2001 Part Number Information Block Diagram SDRAM 3.3V MOSEL-VITELIC MANUFACTURED V

168 PIN UNBUFFERED

S REFRESH RATE 4K DEPTH

4 BANKS

V GOLD G -

133 MHz

(PC133 3-3-3) (PC133 2-2-2) 75PCT A VERSION A DQM0 I/O1–I/O8 CS0 WE WE DQM4 I/O40–I/O33 DQM1 I/O9–I/O16 DQM5 I/O48–I/O41 DQM2 I/O17–I/O24 CS2 DQM6 I/O49–I/O56 DQM3 I/O25–I/O32 DQM7 I/O57–I/O64 WE: SDRAM D0-D7 CKE: SDRAM D0-D7 RAS: SDRAM D0-D7 A(11:0): SDRAM D0-D7 BA0, BA1: SDRAM D0-D7 CKE0 RAS CAS WE A(11:0) BA0, BA1 CAS: SDRAM D0-D7 C0-C15 D0-D7 D0-D7 VCC VSS SCL0 SA2 SA1 SA0 SDA WP E 2PROM SPD (256 WORD X 8 BITS) 47K CLOCK WIRING CLOCK INPUT LOAD CLK0 4 SDRAMS +3.3pF Cap CLK1 Termination CLK2 4 SDRAMS +3.3pF Cap CLK3 Termination DQM I/O1–I/O8 CS DQM I/O1–I/O8 CS DQM I/O1–I/O8 CS DQM I/O1–I/O8 CS DQM I/O1–I/O8 CS DQM I/O1–I/O8 CS DQM I/O1–I/O8 CS DQM I/O1–I/O8 CS WE WE WE WE WE WE WE

M OS EL V ITE LIC V436516S04VATG-75PC V436516S04VATG-75PC Rev. 1.4 September 2001 Serial Presence Detect Information A serial presence detect storage device - E2PROM - is assembled onto the module. Informa- tion about the module configuration, speed, etc. is w r i t t e ni n t ot h eE2PROM device during module pro- duction using a serial presence detect protocol (I2C synchronous 2-wire bus) SPD-Table for PC133 modules: Byte Number Function Described SPD Entry Value Hex Value 16Mx64

0 Number of SPD bytes 128 80

1 Total bytes in Serial PD 256 08

2 Memory Type SDRAM 04

3 Number of Row Addresses (without BS bits) 12 0C

4 Number of Column Addresses (for x8 SDRAM) 10 0A

5 Number of DIMM Banks 1 01

6 Module Data Width 64 40

7 Module Data Width (continued) 0 00

8 Module Interface Levels LVTTL 01

9 SDRAM Cycle Time at CL=3 7.5 ns 75 10 SDRAM Access Time from Clock at CL=3 5.4 ns 54 11 Dimm Config (Error Det/Corr.) none 00 12 Refresh Rate/Type Self-Refresh, 15.6 µs8 0

13 SDRAM width, Primary x8 08

1 4 E r r o rC h e c k i n gS D R A MD a t aW i d t h n / a/x 8 0 0

15 Minimum Clock Delay from Back to Back Random

t ccd =1C L K 0 1

16 Burst Length Supported 1, 2, 4, 8 0F

17 Number of SDRAM Banks 4 04

18 Supported CAS

Latencies CL = 3, 2 06

19 CS Latencies CS Latency = 0 01

20 WE Latencies WL = 0 01

21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00

22 SDRAM Device Attributes: General Vcc tol ± 10% 0E

2 3 M i n i m u mC l o c kC y c l eT i m ea tC A SLatency = 2 7.5 ns 75 24 Maximum Data Access Time from Clock for CL = 2 5.4 ns 54

25 Minimum Clock Cycle Time at CL = 1 Not Supported 00

26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00

27 Minimum Row Precharge Time 15 ns 0F

28 Minimum Row Active to Row Active Delay t

29 Minimum RAS to CAS Delay tRCD 15 ns 0F

30 Minimum RAS Pulse Width t RAS 42 ns 2A

M OS EL V ITE LIC V436516S04VATG-75PC 5V436516S04VATG-75PC Rev. 1.4 September 2001 DC Characteristics TA =0 °Ct o7 0°C; VSS =0V ;V DD ,VDDQ =3 . 3 V± 0.3V

31 Module Bank Density (Per Bank) 128 MByte 20

32 SDRAM Input Setup Time 1.5 ns 15 33 SDRAM Input Hold Time 0.8 ns 08 34 SDRAM Data Input Setup Time 1.5 ns 15 35 SDRAM Data Input Hold Time 0.8 ns 08 62-61 Superset Information (May be used in Future) 00

63 Checksum for Bytes 0 - 62 DA

64 Manufacturer ’s JEDEC ID Code Mosel Vitelic 40

65-71 Manufacturer ’s JEDEC ID Code (cont.) 00

72 Manufacturing Location

73-90 Module Part Number (ASCII) V436516S04VATG75PC 91-92 PCB Identification Code

93 Assembly Manufacturing Date (Year)

94 Assembly Manufacturing Date (Week)

95-98 Assembly Serial Number 99-125 Reserved 00

126 Intel Specification for Frequency 64

127 Reserved AD

128+ Unused Storage Location 00 Symbol Parameter Limit Values UnitMin. Max. V IH Input High Voltage 2.0 V CC +0.3 V V IL Input Low Voltage –0.5 0.8 V V OH Output High Voltage (IOUT = –2.0 mA) 2.4 — V V OL Output Low Voltage (IOUT =2 . 0m A ) — 0.4 V II(L) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) –40 40 µA IO(L) Output leakage current (DQ is disabled, 0V < VOUT <V CC ) –40 40 µA SPD-Table for PC133 modules: (Continued) Byte Number Function Described SPD Entry Value Hex Value 16Mx64

M OS EL V ITE LIC V436516S04VATG-75PC V436516S04VATG-75PC Rev. 1.4 September 2001 Capacitance TA =0 °Ct o7 0°C; VDD =3 . 3 V± 0.3V, f = 1 MHz Absolute Maximum Ratings Symbol Parameter Limit Values UnitMax. 16M x 64 C I1 Input Capacitance (A0 to A11, RAS,C A S,W E)6 0 p F C I2 Input Capacitance (CS0-CS3)3 0 p F C ICL Input Capacitance (CLK0-CLK3) 22 pF C I3 Input Capacitance (CKE0, CKE1) 50 pF C I4 Input Capacitance (DQM0-DQM7) 15 pF C IO Input/Output Capacitance (I/O1-I/064) 15 pF C SC Input Capacitance (SCL, SA0-2) 8 pF C SD Input/Output Capacitance (SA0-SA2) 10 pF Parameter Max. Units V o l t a g eo nV D DS u p p l yR e l a t i v et oVSS -1 to 4.6 V V o l t a g eo nI n p u tR e l a t i v et oVSS -1 to 4.6 V Operating Temperature 0t o+ 7 0 °C Storage Temperature - 5 5t o1 2 5 °C Power Dissipation 6W Operating Currents TA =0 °Ct o7 0°C, VCC =3 . 3 V± 0.3V (Recommended operating conditions otherwise noted) Symbol Parameter & Test Condition Max. Unit Note-75PC ICC1 Operating Current tRC =tRCMIN. ,tRC =tCKMIN . Active-precharge command cycling, without Burst Operation 1 bank operation 1040 mA 7 ICC2P Precharge Standby Current in Power Down Mode CS =V IH,C K E≤ VIL(max) tCK =m i n . 1 6 m A 7 ICC2PS t CK = Infinity 8 mA 7 ICC2N Precharge Standby Current in Non-Power Down Mode CS =V IH,C K E≥ VIL(max) tCK =m i n . 4 0 0 m A ICC2NS t CK = Infinity 40 mA ICC3 No Operating Current tCK =m i n ,C S=V IH(min) bank ; active state ( 4 banks) CKE ≥ VIH(MIN.) 540 mA ICC3P CKE ≥ VIL(MAX.) (Power down mode) 64 mA

M OS EL V ITE LIC V436516S04VATG-75PC 7V436516S04VATG-75PC Rev. 1.4 September 2001 Notes: 1. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC . Input signals are changed one time during tCK . 2. These parameter depend on output loading. Specified values are obtained with output open. ICC4 Burst Operating Current tCK =m i n Read/Write command cycling 1800 mA 7,8 ICC5 Auto Refresh Current tCK =m i n Auto Refresh command cycling 2000 mA 7 ICC6 Self Refresh Current Self Refresh Mode, CKE=0.2V 36 mA L-version 16 mA AC Characteristics TA =0 °to 70°C; VSS =0 V ;VCC =3 . 3 V± 0.3V, tT =1n s # Symbol Parameter Limit Values Unit Note -75PC Min. Max. Clock and Clock Enable 1t CK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 7.5 7.5 s ns ns 2t CK Clock Frequency CAS Latency = 3 CAS Latency = 2 133 133 MHz MHz 3t AC Access Time from Clock CAS Latency = 3 CAS Latency = 2 5.4 5.4 ns ns 2, 4 4t CH Clock High Pulse Width 2.5 – ns 5t CL Clock Low Pulse Width 2.5 – ns 6t T Transition Tim 0.3 1.2 ns Setup and Hold Times 7t IS Input Setup Time 1.5 – ns 5 8t IH Input Hold Time 0.8 – ns 5 9t CKS Input Setup Time 1.5 – ns 5 10 t CKH CKE Hold Time 0.8 – ns 5 11 t RSC Mode Register Set-up Time 15 – ns 12 t SB Power Down Mode Entry Time 0 7.5 ns Operating Currents TA =0 °Ct o7 0°C, VCC =3 . 3 V± 0.3V (Recommended operating conditions otherwise noted) (Continued) Symbol Parameter & Test Condition Max. Unit Note-75PC

M OS EL V ITE LIC V436516S04VATG-75PC V436516S04VATG-75PC Rev. 1.4 September 2001 Common Parameters 13 t RCD Row to Column Delay Time 15 – ns 6 14 t RP Row Precharge Time 15 – ns 6 15 t RAS Row Active Time 42 100K ns 6 16 t RC Row Cycle Time 60 – ns 6 17 t RRD Activate(a) to Activate(b) Command Period 14 – ns 6 18 t CCD CAS (a) to CAS(b) Command Period 1 – CLK Refresh Cycle 19 t REF Refresh Period (4096 cycles) — 64 ms 20 t SREX Self Refresh Exit Time 10 ns Read Cycle 21 t OH Data Out Hold Time 2.7 – ns 2 22 t LZ Data Out to Low Impedance Time 1 – ns 23 t HZ D a t aO u tt oH i g hI m p e d a n c eT i m e – 5.4 ns 7 24 t DQZ DQM Data Out Disable Latency – 2C L K Write Cycle 25 t WR Write Recovery Time 1 – CLK 26 t DQW DQM Write Mask Latency 0 – CLK AC Characteristics TA =0 °to 70°C; VSS =0 V ;VCC =3 . 3 V± 0.3V, tT = 1 ns (Continued) # Symbol Parameter Limit Values Unit Note -75PC Min. Max.

M OS EL V ITE LIC V436516S04VATG-75PC 9V436516S04VATG-75PC Rev. 1.4 September 2001 Notes: 1. The specified values are valid when addresses are changed no more than once during tCK (min.) and when No Operation commands are registered on every rising clock edge during tRC (min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during tRC (min.). 3. All AC characteristics are shown for device level. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V. 5. If clock rising time is longer than 1 ns, a time (t T/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If t T is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to“wake-up”the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. tDAL is equivalent to tDPL +tRP . 1.4V 1.4V tSETUP tHOLD tAC tAC tLZ tOH tHZ CLOCK INPUT OUTPUT 50 pF I/O Z=50 Ohm +1 . 4V

50 Ohm

2.4V 0.4V tT tCL tCH I/O Measurement conditions for tac and toh 50 pF

M OS EL V ITE LIC V436516S04VATG-75PC V436516S04VATG-75PC Rev. 1.4 September 2001 Package Diagram SDRAM DIMM Module Package 127.35 133.35 42.18 D 66.68 3.0 35.00 17.7811 0 1 1 4 0 4 1 8 4 85 94 95 124 125 168 BA 6.35 2.26 RADIUS 1.27 + 0.10 Detail A 3.1258.25 4.45 2.0 C 6.35 Detail B 3.125 2.0 1.0 + 0.51.27 Detail C Tolerances: ± (0.13) unless otherwise specified. (2.54 max) All measurements in mm 1.27 ± 0.100

M OS EL V ITE LIC V436516S04VATG-75PC 11V436516S04VATG-75PC Rev. 1.4 September 2001 Label Information C L = 2 (CLK) tRCD = 2 (CLK) tRP = 2 (CLK) tAC = 5.4 ns 222U UNBUFFERED DIMM PC133 54 V436516S04VATG-75PC PC133U-222-542-A Taiwan XXXX-XXXXXXX A Gerber file Intel® PC100 x 8 Based -- - MOSEL VITELIC Part Number DIMM manufacture date code Trace Code Criteria of PC100 or PC133 (refer to MVI datasheet)

M OS EL V ITE LIC WORLDWIDE OFFICES V436516S04VATG-75PC © Copyright 2001, MOSEL VITELIC Inc. 9/01 Printed in U.S.A. M OSEL VI TEL IC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461 The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep cur- rent the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. U.S. SALES OFFICES U.S.A.

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