V436416S04V MOSEL | Alldatasheet
Document overview
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Technical content
Features
n
168 Pin Unbuffered 16,777,216 x 64 bit
n Utilizes High Performance 8M x 8 SDRAM in TSOPII-54 Packages n Fully PC Board Layout Compatible to INTEL’S Rev 1.0 Module Specification n Single +3.3V ( 0.3V) Power Supply n Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) n Auto Refresh (CBR) and Self Refresh n All Inputs, Outputs are LVTTL Compatible n
4096 Refresh Cycles every 64 ms
n Serial Present Detect (SPD)
Description
The V436416S04V(C)TG-10PC memory module is organized 16,777,216 x 64 bits in a 168 pin dual in line memory module (DIMM). The 16M x 64 un- buffered DIMM uses 16 Mosel-Vitelic 8M x 8 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. n SDRAM Performance n Module Frequency vs AC Parameter Key Component Timing Parameters -8PC Units t CK Clock Frequency (max.) 125 MHz t AC Clock Access Time CAS Latency = 3 6n s t AC Latency = 2 6 ns Frequency CL (CAS Latency) t RCD t RP t RC Unit V436416S04V(C)TG-10PC
100 MHz (PC)
V436416S04V(C)TG-10PC-01
V436416S04V(C)TG-10PC Rev. 1.2 June 2000 MOSEL VITELIC V436416S04V(C)TG-10PC Pin Configurations (Front Side/Back Side) Notes: * These pins are not used in this module. Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO* CB1* VSS NC NC VCC WE DQM0 DQM1 CS0 DU VSS A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2* CB3* VSS I/O17 I/O18 I/O19 I/O20 VCC I/O21 NC DU CKE1 VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2 NC WP SDA SCL VCC 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4* CB5* VSS NC NC VCC CAS DQM4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 DQM5 CS1 RAS VSS BA0 A11 VCC CLK1 NC VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6* CB7* VSS I/O49 I/O50 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 I/O51 I/O52 VCC I/O53 NC DU NC VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3 NC SA0 SA1 SA2 VCC Pin Names A0–A11 Address Inputs I/O1–I/O64 Data Inputs/Outputs RAS Row Address Strobe CAS Column Address Strobe WE Read/Write Input BA0, BA1 Bank Selects CKE0 , CKE1 Clock Enable CS 0–CS 3 Chip Select CLK0–CLK3 Clock Input DQM0–DQM7 Data Mask VCC Power (+3.3 Volts) VSS Ground SCL Clock for Presence Detect SDA Serial Data OUT for Presence Detect SA0–A2 Serial Data IN for Presence Detect CB0–CB7 Check Bits (x72 Organization) NC No Connection DU Don’t Use
V436416S04V(C)TG-10PC V436416S04V(C)TG-10PC Rev. 1.2 June 2000 Module Part Number Information Block Diagram SDRAM 3.3V V436416S04V(C)TG-10PC-02 MOSEL-VITELIC MANUFACTURED V
168 PIN UNBUFFERED
S REFRESH RATE 4K DEPTH
4 BANKS
V GOLD G 10PC- -10PC PC100 2-2-2 T COMPONENT REVISION LEVEL BLANK = B REV. C = C REV. C DQM0 I/O1–I/O8 CS0 10Ω 10Ω 10Ω 10Ω CS1 CS3 CS DQM4 I/O33–I/O40 DQM1 I/O9–I/O16 DQM5 I/O41–I/O48 DQM2 I/O17–I/O24 CS2 10Ω 10Ω 10Ω 10Ω DQM6 I/O49–I/O56 DQM3 I/O25–I/O32 DQM7 I/O57–I/O64 V436416S04V(C)TG-10PC-03 D0-D15 D0-D15 D0-D15 D0-D7 A11-A0, BA0, BA1 VDD VCC 10K RAS, CAS, WE CKE0 CKE1 D0-D7 C0-C31 D9-D15 VSS SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA WP E 2PROM SPD (256 WORD X 8 BIT) 47K CLOCK WIRING 16M X 64 CLK0 4 SDRAM +3.3pF CLK1 4 SDRAM +3.3pF CLK2 4 SDRAM +3.3pF CLK3 4 SDRAM +3.3pF DQM I/O1–I/O8 D0 DQM I/O1–I/O8 D1 DQM I/O1–I/O8 D2 DQM I/O1–I/O8 D3 CS CS CS CSDQM I/O1–I/O8 D8 DQM I/O1–I/O8 D9 DQM I/O1–I/O8D10 DQM I/O1–I/O8D11 CS CS CS CSDQM I/O1–I/O8 D4 DQM I/O1–I/O8 D5 DQM I/O1–I/O8 D6 DQM I/O1–I/O8 D7 CS CS CSDQM I/O1–I/O8D12 DQM I/O1–I/O8D13 DQM I/O1–I/O8D14 DQM I/O1–I/O8D15 CS CS CSCS
V436416S04V(C)TG-10PC Rev. 1.2 June 2000 MOSEL VITELIC V436416S04V(C)TG-10PC Serial Presence Detect Information A serial presence detect storage device - E PROM - is assembled onto the module. Informa- tion about the module configuration, speed, etc. is written into the E PROM device during module pro- duction using a serial presence detect protocol (I C synchronous 2-wire bus) SPD-Table: Byte Number Function Described SPD Entry Value Hex Value
100 MHz
-10PC
0 Number of SPD bytes 128 80
1 Total bytes in Serial PD 256 08
2 Memory Type SDRAM 04
3 Number of Row Addresses (without BS bits) 12 0C
4 Number of Column Addresses (for x8 SDRAM) 9 09
5 Number of DIMM Banks 2 02
6 Module Data Width 64 40
7 Module Data Width (continued) 0 00
8 Module Interface Levels LVTTL 01
9 SDRAM Cycle Time at CL=3 10.0 ns A0 10 SDRAM Access Time from Clock at CL=3 6.0 ns 60 11 Dimm Config (Error Det/Corr.) none 00 12 Refresh Rate/Type Self-Refresh, 15.6 m s 80
13 SDRAM width, Primary x8 08
14 Error Checking SDRAM Data Width n/a / x8 00
15 Minimum Clock Delay from Back to Back
t ccd = 1 CLK 01
16 Burst Length Supported 1, 2, 4, 8 & full Page 8F
17 Number of SDRAM Banks 4 04
18 Supported CAS Latencies CL = 2 & 3 06
19 CS Latencies CS Latency = 0 01
20 WE Latencies WL = 0 01
21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00
22 SDRAM Device Attributes: General Vcc tol
10% 0E 23 Minimum Clock Cycle Time at CAS Latency = 2 10.0 ns A0 24 Maximum Data Access Time from Clock for CL = 2 6.0 ns 60
25 Minimum Clock Cycle Time at CL = 1 Not Supported 00
26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00
27 Minimum Row Precharge Time t
28 Minimum Row Active to Row Active Delay t
29 Minimum RAS to CAS Delay t
V436416S04V(C)TG-10PC V436416S04V(C)TG-10PC Rev. 1.2 June 2000 DC Characteristics T A = 0 C to 70 C; V SS = 0 V; V DD , V DDQ = 3.3V 0.3V
30 Minimum RAS Pulse Width t
31 Module Bank Density (Per Bank) 64 MByte 10
32 SDRAM Input Setup Time 2 ns 20
33 SDRAM Input Hold Time 1 ns 10
34 SDRAM Data Input Setup Time 2 ns 20
35 SDRAM Data Input Hold Time 1 ns 10
36-61 Superset Information (May be used in Future) 00
63 Checksum for Bytes 0 - 62 FD
64-125 Manufacturers’s Information (Optional) (FFh if not used) XX 126 Max. Frequency Specification 100 MHz 64 127 100 MHz Support Details AF 128+ Unused Storage Location 00 Symbol Parameter Limit Values UnitMin. Max. V IH Input High Voltage 2.0 V CC +0.3 V V IL Input Low Voltage –0.5 0.8 V V OH Output High Voltage (I OUT = –2.0 mA) 2.4 — V V OL Output Low Voltage (I OUT = 2.0 mA) — 0.4 V I I(L) Input Leakage Current, any input (0 V < V IN < 3.6 V, all other inputs = 0V) –40 40 m A I O(L) Output leakage current (DQ is disabled, 0V < V OUT < V CC –40 40 m A SPD-Table: (Continued) Byte Number Function Described SPD Entry Value Hex Value -10PC
V436416S04V(C)TG-10PC Rev. 1.2 June 2000 MOSEL VITELIC V436416S04V(C)TG-10PC Capacitance T A = 0 C to 70 C; V DD = 3.3V 0.3V, f = 1 MHz Standby and Refresh Currents T A = 0 C to 70 C, V CC = 3.3V 0.3V Symbol Parameter Limit Values Unit C Input Capacitance (A0 to A11, RAS , CAS , WE ) 80 pF C Input Capacitance (CS0 -CS3 ) 30 pF C ICL Input Capacitance (CLK0-CLK3) 22 pF C Input Capacitance (CKE0, CKE1) 50 pF C Input Capacitance (DQM0-DQM7) 20 pF C IO Input/Output Capacitance (I/O1-I/064) 20 pF C SC Input Capacitance (SCL, SA0-2) 8 pF C SD Input/Output Capacitance 10 pF Symbol Parameter Test Conditions 16M x 64 Unit Note I CC
1 Operating Current Burst length = 4, CL = 3
t RC > = t RC (min), t CK > = t CK (min), IO = 0 mA
2 Bank Interleave Operation
800 mA 1,2 I CC 2P Precharged Standby Current in Power Down Mode CKE< = V IL (max), t CK > = t CK (min) 48 mA I CC 2PS CKE< = V IL (max), t CK = Infinite 32 mA I CC 2N Precharged Standby Current in Non-Power Down Mode CKE> = V IH (min), t CK > = t CK (min), Input changed once in 3 cycles 160 mA CS = High I CC 2NS CKE> = V IH (min), t CK = Infinite, No Input change 80 mA I CC 3P Active Standby Current in Power Down Mode CKE< = V IL (max), t CK > = t CK (min) 48 mA I CC 3PS CKE< = V IL (max), tCK = Infinite 32 mA ICC 3N Active Standby Current in Non-Power Down Mode CKE> = VIH(min), tCK > = tCK (min), Input changed one time 200 mA CS = High ICC 3NS CKE> = VIH(min), tCK = Infinite, No Input change 120 mA ICC 4 Burst Operating Current Burst length = Full Page, tRC = Infinite, CL = 3, tCK > = tCK (min), IO = 0 mA
2 Banks Activated
760 mA 1, 2 ICC 5 Auto Refresh Current tRC >= tRC (min) 720 mA 1,2 ICC 6 Self Refresh Current CKE = <0,2 V 8 mA 1,2
MOSEL VITELIC V436416S04V(C)TG-10PC 7V436416S04V(C)TG-10PC Rev. 1.2 June 2000 AC Characteristics 3,4 TA = 0° to 70°C; VSS = 0V; VCC = 3.3V – 0.3V, tT = 1 ns # Symbol Parameter Limit Values Unit Note -10PC Min. Max. Clock and Clock Enable 1 tCK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 ns ns 2 fCK System frequency CAS Latency = 3 CAS Latency = 2 100 100 MHz MHz 3 tAC Clock Access Time CAS Latency = 3 CAS Latency = 2 ns ns 4,5 4 tCH Clock High Pulse Width 3 – ns 6 5 tCL Clock Low Pulse Width 3 – ns 6 6 tCS Input Setup time 2 – ns 7 7 tCH Input Hold Time 1 – ns 7 8 tCKSP CKE Setup Time (Power down mode) 2.5 – ns 8 9 tCKSR CKE Setup Time (Self Refresh Exit) 8 – ns 9 10 tT Transition time (rise and fall) 1 – ns Common Parameters 11 tRCD RAS to CAS delay 20 – ns 12 tRC Cycle Time 70 120k ns 13 tRAS Active Command Period 45 – ns 14 tRP Precharge Time 20 – ns 15 tRRD Bank to Bank Delay Time 16 – ns 16 tCCD CAS to CAS delay time (same bank) 1 – CLK Refresh Cycle 17 tSREX Self Refresh Exit Time 10 – ns 9 18 tREF Refresh Period (4096 cycles) 64 – ms 8 Read Cycle 19 tOH Data Out Hold Time 3 – ns 4 20 tLZ Data Out to Low Impedance Time 0 – ns 21 tHZ Data Out to High Impedance Time 3 9 ns 10 22 tDQZ DQM Data Out Disable Latency 2 – CLK Write Cycle 23 tDPL Data input to Precharge (write recovery) 2 – CLK 24 tDAL Data In to Active/refresh 5 – CLK 11 25 tDQW DQM Write Mask Latency 0 – CLK
8V436416S04V(C)TG-10PC Rev. 1.2 June 2000 MOSEL VITELIC V436416S04V(C)TG-10PC Notes: 1. The specified values are valid when addresses are changed no more than once during tCK (min.) and when No Operation commands are registered on every rising clock edge during tRC (min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during tRC (min.). 3. All AC characteristics are shown for device level. An initial pause of 100 ms is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V. 5. If clock rising time is longer than 1 ns, a time (t T/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. tDAL is equivalent to tDPL + tRP . 1.4V 1.4V tSETUP tHOLD tAC tAC tLZ tOH tHZ CLOCK INPUT OUTPUT 50 pF I/O Z=50 Ohm + 1.4 V
50 Ohm
2.4V 0.4V tT tCL tCH I/O Measurement conditions for tac and toh 50 pF
MOSEL VITELIC V436416S04V(C)TG-10PC 9V436416S04V(C)TG-10PC Rev. 1.2 June 2000 Package Diagram L-DIM-168-30 SDRAM DIMM Module Package V436416S04V(C)TG-10PC-04 127.35 133.37 42.18 D 63.68 3.0 1.27 – 0.100 All measurements in mm 35.00 1 10 11 40 41 84 85 94 95 124 125 168 17.80 BA 6.35 2.26 RADIUS 1.27 + 0.10 Detail A 3.125 4.45 2.0 6.35 3.175 Detail B 3.125 2.0 1.0 – 0.051.27 Detail C 2.50 0.2 – 0.15 4.0 Tolerances: – (0.13) unless otherwise specified. (4.0 max)
10V436416S04V(C)TG-10PC Rev. 1.2 June 2000 MOSEL VITELIC V436416S04V(C)TG-10PC Label Information C L = 2 (CLK) tRCD = 2 (CLK) tRP = 2 (CLK) tAC = 6 ns 222U UNBUFFERED DIMM PC100 6 Intel SPD Revision 1.2 V436416S04VCTG-10PC PC100U-222-612-A Taiwan XXXX-XXXXXXX A Gerber file Intel® PC100 x 8 Based - - - MOSEL VITELIC Part Number DIMM manufacture date code Trace Code Criteria of PC100 or PC133 (refer to MVI datasheet)
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