V320MTC

V320 FAIRCHILD | Alldatasheet

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■ Independent registers for A and B buses ■ Multiplexed real-time and stored data ■ Guaranteed output skew ■ Guaranteed MOS (Multiple Output Switching) Specifica- tions ■ Output switching specified for both 50 pF and 250 pF, and 500 pF loads ■ Guaranteed simultaneous switching noise level (VOLP / VOLV ) and dynamic threshold performance (VIHD/VILD) ■ Glitch free power up/down high impedance for live inser- tion ■ BiCMOS technology for high drive and low power dissi- pation ■ −40°C to 85°C commercial temperature and VCC specifi- cations ■ Modified specifications across VCC and temperature (VCC = 5.0V ±1%, T = 25°C ± 20°C) present more realis- tic system conditions ■ Available in TSSOP (MTC) Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Order Number Package Number Package Description V320MTC MTC24 24-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4mm Wide Pin Names Description D Direction A-to-B (High) B-to A (Low) OE Output Enable (Active LOW) CLKAB/SELAB A-to-B Clock/Select CLKBA/SELBA B-to-A Clock/Select A0–7 A Inputs/Outputs (TTL) B0–7 B Inputs/Outputs (TTL)

www.fairchildsemi.com 2 V320 Functional Table L = Low H = High LH = Low to High transition X = Don't Care Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. OE D SELAB SELBA CLKAB CLKBA A 0–A 7 B 0–B 7 Function H X X X H or L H or L Isolation H X X X LH X Input Input CLK A Data into A HXXXX L H C L K B D a t a i n t o A R e g . LHLXXX A to B – Transparent L H L X LH X CLK A Data into A Reg. L H H X H or L X Input Output A Reg. to B (Storage) L H H X LH X CLK A Data into A Reg. and B output L L X L X X B to A – Transparent L L X L X LH CLK B Data into B Reg. L L X H X H or L Output Input B Reg. to A (Storage) L L X H X LH CLK B Data into B Reg.and A output

3 www.fairchildsemi.com V320 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Over Recommended Operating Free-Air Temperature Range (Unless Otherwise Noted) Note 3: Extended Characteristics (4.95 > VCC > 5.05, T = 25°C ± 20°C) DC Input Voltage (VI) −0.5V to +7.0V DC Output Voltage (VO ) Outputs 3-STATE −0.5V to +7.0V Outputs Active (Note 2) −0.5V to VCC +0.5V DC Output Sink Current into A-port/B-port IOL 64 mA DC Output Source Current from A-port/B-port IOH −32 mA DC Input Diode Current (IIK) V I < 0V −30 mA to +5.0 mA ESD Rating typical > 2000V Storage temperature (TSTG ) −65° C to +15°C Max IOL (Current Applied to a LOW Output) 2 X I OL Spec. Supply Voltage VCC Operating VCC 4.5V to 5.5V Minimum Input Edge Rate Data Input 50 mV/ns Enable 20 mV/ns Clock 100 mV/ns Operating Temperature (T A) −40°C to +85°C Symbol Parameter VCC (V) Min Typ Max Units Conditions VIH B-Port/A-Port HIGH Level Input Voltage 4.5–5.5 2.0 V Recognized HIGH Signal 4.95–5.05 1.8 (Note 3) VIL B-Port/A-Port LOW Level Input Voltage 4.5–5.5 0.8 V Recognized LOW Signal 4.95–5.05 1.2 (Note 3) VOH B-Port/A-Port HIGH Level Output Voltage 4.5 2.5 V −3 mA 4.5 2.0 −32 mA IOH B-Port/A-Port High Level Output Current Drive 4.5 −32 mA V OH = 2.0V VOL B-Port/A-Port LOW Level Output Voltage 4.5 0.55 V 64 mA IOL B-Port/A-Port Low Level Output Current Drive (Sink) 4.5 64 mA V OL = 0.55V IOS B-Port/A-Port Short Circuit Current 5.5 −100 −275 mA V OUT = 0.0V IOFF A-Port and Control Pins Power-OFF Leakage Current 0.0 100uA uA V OUT = 5.5V, All Others GND ICCH B-Port/A-Port Quiescent Power Supply Current 5.5 250 uA All Outputs HIGH ICCI B-Port/A-Port B-Port/A-Port 5.5 30 mA All Outputs LOW ICCZ B-Port/A-Port 3-STATE Power Supply Current 5.5 50 uA All Outputs 3-STATE

www.fairchildsemi.com 4 V320 Capacitance and Dynamic Switching Characteristics Over Recommended Operating Free-Air Temperature Range (Unless Otherwise Noted) AC Operating Requirements Over recommended ranges of supply voltage and operating free-air temperature Note 4: C L = 50 pF Symbol Parameter Min Typ Max Units Conditions TA = 25°C C IN Input Capacitance (Control Pin) 5 pF V CC = 5.0V VI = VCC or 0 C I/O Output Capacitance (A and B ports) 11 pF V CC = 5.0V VI = VCC or 0 Output Switching Noise (Ground Bounce) VOLP Quiet Output Dynamic Peak VOL 0.8 V V CC = 5.0V, T= 25°C VOLV Quiet Output Dynamic Valley VOL −1.2 V C L = 50 pF VOHV Quiet Output Dynamic Valley VOH 2.5 V Input Noise Immunity (Dynamic Threshold) V IHD High Level Threshold Movement 2.2 V V CC = 5.0V, T= 25°C VILD Low Level Threshold Movement 0.5 V C L = 50 pF Symbol Min Typ Max Units fCLOCK Max Clock Frequency 200 (Note 4) MHz tWIDTH Pulse Duration HIGH or LOW 3.0 ns tSU Setup Time Bus to CLKAB/CLKBA 1.5 ns tHOLD Hold Time Bus to CLKAB/CLKBA 1.0 ns

5 www.fairchildsemi.com V320 (−40°C to 85°C, VCC = 4.5V to 5.5V) 1 Output Switching Note 5: 3-STATE delays are dominated by the RC Network (500 Ω / 250 pF, or 500 Ω / 500 pF) on the output and thus have been excluded from this datasheet. Symbol From (Input) Mode To (Output) Min Typ Max Units Output Load: CL = 50 pF, RL= 500Ω , 1 Output Switching tPLH , tPHL CLKAB/CLKBA Register Bus A or B 1.7 5.6 ns tPLH , tPHL Bus A or B Transparent Bus A or B 1.5 4.8 ns tPLH , tPHL SELAB/SELBA Select Bus Bus A or B 1.5 5.9 ns tPLZ , tPHZ OE Output Disable Bus A or B 1.5 6.0 ns tPZH , tPZL OE Output Enable Bus A or B 1.5 6.3 ns tPLZ , tPHZ Direction (D) Dir. Disable Bus A or B 1.5 6.0 ns tPZH , tPZL Direction (D) Dir. Enable Bus A or B 1.5 6.3 ns tRISE Transition Time, Outputs (1V to 2V) 0.3 1.2 ns tFALL Transition Time, Outputs (1V to 2V) 0.3 1.4 ns Output Load: CL = 250 pF, RL = 500Ω , 1 Output Switching tPLH , tPHL CLKAB/CLKBA Register Bus A or B 2.0 7.5 ns tPLH , tPHL Bus A or B Transparent Bus A or B 2.0 7.0 ns tPLH , tPHL SELAB/SELBA Select Bus Bus A or B 2.0 7.5 ns tPLZ , tPHZ OE Output Disable Bus A or B (Note 5) (Note 5) ns tPZH , tPZL OE Output Enable Bus A or B 2.0 8.0 ns tPLZ , tPHZ Direction (D) Dir. Disable Bus A or B (Note 5) (Note 5) ns tPZH , tPZL Direction (D) Dir. Enable Bus A or B 2.0 8.3 ns tRISE Transition Time, Outputs (1V to 2V) 1.7 3.9 ns tFALL Transition Time, Outputs (1V to 2V) 0.8 3.1 ns Output Load: CL = 500 pF, RL = 500Ω , Output Switching tPLH tPHL CLKAB/CLKBA Register Bus A or B 3.0 12.2 ns tPLH tPHL Bus A or B Transparent Bus A or B 3.0 11.6 ns tPLH tPHL SELAB/SELBA Select Bus Bus A or B 3.0 12.4 ns tPLZ , tPHZ OE Output Disable Bus A or B (Note 5) (Note 5) ns tPZH , tPZL OE Output Enable Bus A or B 3.0 12.6 ns tPLZ , tPHZ Direction (D) Dir. Disable Bus A or B (Note 5) (Note 5) ns tPZH , tPZL Direction (D) Dir. Enable Bus A or B 6.3 13.2 ns tRISE Transition Time, Outputs (1V to 2V) 3.5 7.2 ns tFALL Transition Time, Outputs (1V to 2V) 1.4 5.1 ns

www.fairchildsemi.com 6 V320 (−40°C to 85°C, VCC = 4.5V to 5.5V) 8 Output Switching Note 6: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specifi- cation applies to outputs switching in the same direction also. Note 7: Device to Device Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs from any two devices. Note 8: 3-STATE delays are dominated by the RC Network (500 Ω / 250 pF, or 500 Ω / 500 pF) on the output and thus have been excluded from this datasheet. Symbol From (Input) Mode To (Output) Min Typ Max Units Output Load: CL = 50 pF, RL = 500Ω , 8 Outputs Switching tPLH , tPHL CLKAB/CLKBA Register Bus A or B 1.5 6.6 ns tPLH , tPHL Bus A or B Transparent Bus A or B 1.5 6.3 ns tPLH , tPHL SELAB/SELBA Select Bus Bus A or B 1.5 6.6 ns tPLZ , tPHZ OE Output Disable Bus A or B 1.5 6.6 ns tPZH , tPZL OE Output Enable Bus A or B 1.5 6.6 ns tPLZ , tPHZ Direction (D) Dir. Disable Bus A or B 1.5 6.6 ns tPZH , tPZL Direction (D) Dir. Enable Bus A or B 1.5 7.6 ns tOSHL Output to Output Skew (Note 6) 1.3 ns tOSHL Output to Output Skew (Note 6) 1.1 ns tRISE Transition Time, Outputs (1V to 2V) 0.5 1.5 ns tFALL Transition Time, Outputs (1V to 2V) 0.4 1.9 ns Output Load: CL = 250 pF, RL = 500Ω , 8 Outputs Switching tPLH , tPHL CLKAB/CLKBA Register Bus A or B 2.5 11.2 ns tPLH , tPHL Bus A or B Transparent Bus A or B 2.5 9.5 ns tPLH , tPHL SELAB/SELBA Select Bus Bus A or B 2.5 11.2 ns tPLZ , tPHZ OE Output Disable Bus A or B (Note 8) (Note 8) ns tPZH , tPZL OE Output Enable Bus A or B 2.5 11.5 ns tPLZ , tPHZ Direction (D) Dir. Disable Bus A or B (Note 8) (Note 8) ns tPZH , tPZL Direction (D) Dir. Enable Bus A or B 2.5 13.5 ns tOSHL Output to Output Skew (Note 8) 2.5 ns tOSLH Output to Output Skew (Note 8) 2.0 ns tRISE Transition Time, Outputs (1V to 2V) 2.0 5.5 ns tFALL Transition Time, Outputs (1V to 2V) 1.4 4.4 ns Output Load: CL = 500 pF, RL = 500Ω , 8 Outputs Switching tPLH , tPHL CLKAB/CLKBA Register Bus A or B 3.5 17.0 ns tPLH , tPHL Bus A or B Transparent Bus A or B 3.5 15.9 ns tPLH , tPHL SELAB/SELBA Select Bus Bus A or B 3.5 17.0 ns tPLZ , tPHZ OE Output Disable Bus A or B (Note 8) (Note 8) ns tPZH , tPZL OE Output Enable Bus A or B 3.5 18.5 ns tPLZ , tPHZ Direction (D) Dir. Disable Bus A or B (Note 8) (Note 8) ns tPZH , tPZL Direction (D) Dir. Enable Bus A or B 3.5 22.3 ns tOSHL Output to Output Skew (Note 6) 3.9 ns tOSLH Output to Output Skew (Note 6) 3.1 ns tRISE Transition Time, Outputs (1V to 2V) 4.4 7.8 ns tFALL Transition Time, Outputs (1V to 2V) 2.5 6.6 ns

7 www.fairchildsemi.com V320 Extended AC Electrical Characteristics (5°C to 45°C, VCC = 4.95V to 5.05V), 1 Output Switching Note 9: 3-STATE delays are dominated by the RC Network (500 Ω / 250 pF, or 500 Ω / 500 pF) on the output and thus have been excluded from this datasheet. Note 10: Device to Device Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs from any two devices. Symbol From (Input) Mode To (Output) Min Typ Max Units Output Load: CL = 50 pF, RL = 500Ω , 1 Output Switching tPLH , tPHL CLKAB/CLKBA Register Bus A or B 1.5 5.2 ns tPLH , tPHL Bus A or B Transparent Bus A or B 1.5 4.3 ns tPLH , tPHL SELAB/SELBA Select Bus Bus A or B 2.0 4.8 ns tPLZ , tPHZ OE Output Disable Bus A or B 1.5 6.0 ns tPZH , tPZL OE Output Enable Bus A or B 2.2 5.0 ns tPLZ , tPHZ Direction (D) Dir. Disable Bus A or B 1.5 6.0 ns tPZH , tPZL Direction (D) Dir. Enable Bus A or B 2.2 5.2 ns tPV Device to Device Skew (Note 10) 2.0 ns tRISE Transition Time, Outputs (1V to 2V) 3.0 1.2 ns tFALL Transition Time, Outputs (1V to 2V) 0.4 1.2 ns Output Load: CL = 250 pF, RL = 500Ω , 1 Output Switching tPLH , tPHL CLKAB/CLKBA Register Bus A or B 2.5 7.4 ns tPLH , tPHL Bus A or B Transparent Bus A or B 2.5 6.7 ns tPLH , tPHL SELAB/SELBA Select Bus Bus A or B 3.0 7.2 ns tPLZ , tPHZ OE Output Disable Bus A or B (Note 9) (Note 9) ns tPZH , tPZL OE Output Enable Bus A or B 3.2 7.2 ns tPLZ , tPHZ Direction (D) Dir. Disable Bus A or B (Note 9) (Note 9) ns tPZH , tPZL Direction (D) Dir. Enable Bus A or B 3.2 8.1 ns tPV Device to Device Skew (Note 10) 2.5 ns tRISE Transition Time, Outputs (1V to 2V) 2.1 3.5 ns tFALL Transition Time, Outputs (1V to 2V) 1.0 2.5 ns Output Load: CL = 500 pF, RL = 500Ω , 1 Output Switching tPLH , tPHL CLKAB/CLKBA Register Bus A or B 3.5 10.6 ns tPLH , tPHL Bus A or B Transparent Bus A or B 3.5 10.0 ns tPLH , tPHL SELAB/SELBA Select Bus Bus A or B 4.0 10.6 ns tPLZ , tPHZ OE Output Disable Bus A or B (Note 9) (Note 9) ns tPZH , tPZL OE Output Enable Bus A or B 4.2 10.5 ns tPLZ , tPHZ Direction (D) Dir. Disable Bus A or B (Note 9) (Note 9) ns tPZH , tPZL Direction (D) Dir. Enable Bus A or B 4.2 11.3 ns tPV Device to Device Skew 5.0 ns tRISE Transition Time, Outputs (1V to 2V) 3.8 6.4 ns tFALL Transition Time, Outputs (1V to 2V) 1.7 3.8 ns

www.fairchildsemi.com 8 V320 Extended AC Electrical Characteristics (5°C to 45°C, VCC = 4.95V to 5.05V), 8 Outputs Switching Note 11: 3-STATE delays are dominated by the RC Network (500 Ω / 250 pF, or 500 Ω / 500 pF) on the output and thus have been excluded from this datasheet. Note 12: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specifi- cation applies to outputs switching in the same direction also. Note 13: Device to Device Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs from any two devices. Symbol From (Input) Mode To (Output) Min Typ Max Units Output Load: CL = 50 pF, RL = 500Ω , 8 Outputs Switching tPLH , tPHL CLKAB/CLKBA Register Bus A or B 2.5 6.2 ns tPLH , tPHL Bus A or B Transparent Bus A or B 2.5 5.4 ns tPLH , tPHL SELAB/SELBA Select Bus Bus A or B 2.5 5.7 ns tPLZ , tPHZ OE Output Disable Bus A or B 1.5 6.0 ns tPZH , tPZL OE Output Enable Bus A or B 2.5 5.7 ns tPLZ , tPHZ Direction (D) Dir. Disable Bus A or B 1.5 6.0 ns tPZH , tPZL Direction (D) Dir. Enable Bus A or B 2.5 7.2 ns tOSHL Output to Output Skew (Note 12) 1.1 ns tOSLH Output to Output Skew (Note 12) 0.9 ns tPV Device to Device Skew (Note 13) 2.5 ns tRISE Transition Time, Outputs (1V to 2V) 0.5 1.3 ns tFALL Transition Time, Outputs (1V to 2V) 0.6 1.4 ns Output Load: CL = 250 pF, RL = 500Ω , 8 Outputs Switching tPLH , tPHL CLKAB/CLKBA Register Bus A or B 3.5 10.5 ns tPLH , tPHL Bus A or B Transparent Bus A or B 3.5 10.5 ns tPLH , tPHL SELAB/SELBA Select Bus Bus A or B 3.5 10.5 ns tPLZ , tPHZ OE Output Disable Bus A or B (Note 11) (Note 11) ns tPZH , tPZL OE Output Enable Bus A or B 3.5 10.5 ns tPLZ , tPHZ Direction (D) Dir. Disable Bus A or B (Note 11) (Note 11) ns tPZH , tPZL Direction (D) Dir. Enable Bus A or B 3.5 14.8 ns tOSHL Output to Output Skew (Note 12) 2.3 ns tOSLH Output to Output Skew (Note 12) 1.9 ns tPV Device to Device Skew(Note 13) 4.0 ns tRISE Transition Time, Outputs (1V to 2V) 2.7 4.7 ns tFALL Transition Time, Outputs (1V to 2V) 1.8 3.7 ns Output Load: CL = 500 pF, RL = 500Ω , 8 Outputs Switching tPLH , tPHL CLKAB/CLKBA Register Bus A or B 5.0 15.3 ns tPLH , tPHL Bus A or B Transparent Bus A or B 5.0 13.6 ns tPLH , tPHL SELAB/SELBA Select Bus Bus A or B 5.0 15.3 ns tPLZ , tPHZ OE Output Disable Bus A or B (Note 11) (Note 11) ns tPZH , tPZL OE Output Enable Bus A or B 5.0 15.1 ns tPLZ , tPHZ Direction (D) Dir. Disable Bus A or B (Note 11) (Note 11) ns tPZH , tPZL Direction (D) Dir. Enable Bus A or B 5.0 19.4 ns tOSHL Output to Output Skew (Note 12) 3.5 ns tOSLH Output to Output Skew (Note 12) 2.9 ns tPV Device to Device Skew 5.0 ns tRISE Transition Time, Outputs (1V to 2V) 4.6 7.0 ns tFALL Transition Time, Outputs (1V to 2V) 2.9 4.9 ns

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. V320 8-Bit Registered Bus Transceiver LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4mm Wide