V2S-CR5-1000A ARM | Alldatasheet

Document overview

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Technical content

Features

  • Processor Subsystem - Dual-core ARM Cortex-R5 with FPU r1p2 - L1 Cache 64KB Instruction and Data - TCM 64kB - 50MHz operation speed - Debug support: CoreSight ™ support ETM
  • AMBA® AXI™ Subsystem - Internal AMBA AXI: 50MHz - External AMBA AXI: Master port 25MHz - External AMBA AXI: Slave port 35MHz - PL34

1 DDR2 Memory Interface

  • PISMO2 512MB 32-bit @ 110MHz - PL354 Static Memory Bus Interface - 32-bit 40MHz to motherboard - Boot from NOR Flash on motherboard - HDCLD video controller
  • Expansion support - AMBA AXI: Master and slave links to expansion FPGA daugherboard
  • Peripheral set compatible with the Versatile family
  • Debug - ARM JTAG: 20-way DIL box header - ARM 32-bit parallel trace: dual 38-pin Mictors
  • Simplified configuration via motherboard - System appears as a USB flash drive on a PC - Fast programming and configuration - Configuration text files for system settings - Remote power control via RS232 Deliverables
  • LTE 3MG with encryption key
  • Encrypted SMM image for LTE 3MG
  • 512MB DDR2 PISMO2 module
  • Versatile Express SMM support CD.DVD
  • Example AMBA AXI design - Additional LTE 3MG required
  • SelfT est software The Versatile™ Express family development boards provide an excellent environment for prototyping the next generation system-on-chip designs. Through a range of plug-in options, hardware and software applications can be developed and debugged. The Soft Macro Model (SMM) for the ARM ® Cortex™-R5 processor is an encrypted FPGA image for use on the LTE 3MG. It offers:
  • Early access to the Cortex-R5 processor
  • Benchmarking capability
  • Early device driver and software development
  • User IP provided via second FPGA board
  • ARM JTAG and Trace connectors for debug support The implementation uses standard ARM CoreLink™ System IP components to implement a basic SoC design to mimic the test chip developments of our CoreTile Express products. A simple click through EULA is available to access the latest processor technology from ARM.

www.arm.com/ve All brand names or product names are the property of their respective holders. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given in good faith. All warranties implied or expressed, including but not limited to implied warranties of satisfactory quality or fitness for purpose are excluded. This document is intended only to provide information to the reader about the product. T o the extent permitted by local laws ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information. Copyright © 2011 ARM Ltd. ARM LogicTile Express CR5| 5.12 LogicTile Express for Cortex-R5 Architecture LogicTile Express for Cortex-R5 architecture diagram ARM Ltd. www.arm.com UK T: +44 1223 400400 FRANCE T: +33 1 39 30 47 89 JAPAN T: +8 1 45 477 5260 TAIWAN T: +886 2 2627 1681 CHINA T: +86 2 1 62351296 SINGAPORE +65 6728 0950 US T: + 1 408 576 1500 GERMANY T: +49 89 456040-20 KOREA T: +82 3 1 712 8234 ISRAEL T: +972 9 7632000 INDIA T: +9 1 80 5138 4000 When connected to a Versatile Express motherboard the configuration system enables programming and updating of the SMM Express R5x2. Configuration and operation parameters of the daughterboard are defined in a configuration file stored on the motherboard. The daugherboard communicates to the motherboard via the static memory interface for all peripheral and flash memory access. The exported AMBA AXI interfaces have dedicated routing for an optimal prototyping solution. PART NUMBER: V2S-CR5-1000A Trace/Debug Dual R5 ETM AXI Bus Matrix SMCDMC AXI M mux AXI S mux PISMO2 DDR2 32bit 512MB Soft Macro Model Trace/Debug Connector ClocksClock Generator SMM Config Daughterboard Configuration Controller AXI expansion AXI expansion PL111 DMA ZBT ctrl 16MB ZBTRAM SCU AXI Bus Matrix CPU0 CPU1 SCU LLPPCPU V2M-P1 Motherboard Timer SwitchesLEDs GPIO Real Time Clock Audio Codec Watchdog UART Kbd / Mouse SD Card CF Card EthernetNOR Flash DVI From HDLCD V2F-1XV5 Daughterboard