V29C51002T-55T

V29C51002T MOSEL | Alldatasheet

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Technical content

Features

I 256Kx8-bit Organization I Address Access Time: 55, 90 ns I Single 5V 10% Power Supply I Sector Erase Mode Operation I 16KB Boot Block (lockable) I 512 bytes per Sector, 512 Sectors – Sector-Erase Cycle Time: 10ms (Max) – Byte-Write Cycle Time: 20 µ s (Max) I Minimum 10,000 Erase-Program Cycles I Low power dissipation – Active Read Current: 20mA (Typ) – Active Program Current: 30mA (Typ) – Standby Current: 100 µ A (Max) I Hardware Data Protection I Low V CC Program Inhibit Below 3.5V I Self-timed write/erase operations with end-of-cy- cle detection – DATA Polling – Toggle Bit I CMOS and TTL Interface I Available in two versions – V29C51002T (Top Boot Block) – V29C51002B (Bottom Boot Block) I Packages: – 32-pin Plastic DIP – 32-pin TSOP-I – 32-pin PLCC

Description

The V29C51002T/V29C51002B is a high speed 262,144 x 8 bit CMOS flash memory. Writing or erasing the device is done with a single 5 Volt power supply. The device has separate chip enable CE , write enable WE, and output enable OE controls to eliminate bus contention. The V29C51002T/V29C51002B offers a combi- nation of: Boot Block with Sector Erase/Write Mode. The end of write/erase cycle is detected by DATA Polling of I/O or by the Toggle Bit I/O The V29C51002T/V29C51002B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. The device also supports full chip erase. Boot block architecture enables the device to boot from a protected sector located either at the top (V29C51002T) or the bottom (V29C51002B). All inputs and outputs are CMOS and TTL compatible. The V29C51002T/V29C51002B is ideal for applications that require updatable code and data storage. Device Usage Chart Operating Temperature Range Package Outline Access Time (ns) Temperature MarkPTJ 5 5 9 0 C to 70

V29C51002T/V29C51002B Rev. 2.1 October 2000 MOSEL VITELIC V29C51002T/V29C51002B OPERATING VOLTAGE 51: 5V DEVICE SPEED 51002-01 V 29 C 002 51 BOOT BLOCK LOCATION T: TOP B: BOTTOM T – 55: 55ns 90: 90ns BLANK (0 °C TO 70°C)P = PDIP T = TSOP-I J = PLCC TEMP.PKG. Pin Configurations N/C A16 A15 A12 I/O0 I/O1 I/O2 GND 32-Pin PDIP Top View VCC WE A17 A14 A13 A11 OE A10 CE I/O3 I/O4 I/O5 I/O6 I/O7 51002-02 I/O0 51002-03 A12 A15 A16 NC VCC WE A I/O2 GND I/O3 I/O4 I/O5 I/O6 A13 A11 OE A10 I/O7 CE A14 I/O1

32 Pin PLCC

A Address Inputs I/O –I/O Data Input/Output CE Chip Enable OE Output Enable WE Write Enable V CC 10% Power Supply GND Ground NC No Connect A11 A13 A14 A17 WE VCC N/C A16 A15 A12 32-Pin TSOP I Standard Pinout Top View OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 51002-04

V29C51002T/V29C51002B Rev. 2.1 October 2000 Functional Block Diagram Capacitance (1,2) NOTE: 1. Capacitance is sampled and not 100% tested. 2. T A = 25 C, V CC = 5V 10%, f = 1 MHz. Latch Up Characteristics (1) NOTE: 1. Includes all pins except V CC . Test conditions: V CC = 5V, one pin at a time. AC Test Load Symbol Parameter Test Setup Typ. Max. Units C IN Input Capacitance V IN = 0 6 8 pF C OUT Output Capacitance V OUT = 0 8 12 pF C IN2 Control Pin Capacitance V IN = 0 8 10 pF Parameter Min. Max. Unit Input Voltage with Respect to GND on A , OE -1 +13 V Input Voltage with Respect to GND on I/O, address or control pins -1 V CC + 1 V V CC Current -100 +100 mA Address buffer & latchesA0–A17 51002-07 I/O Buffer & Data Latches I/O0–I/O7 Y-Decoder 2,097,152 Bit Memory Cell ArrayX-Decoder Control Logic CE OE WE 51002-08 IN3064 or Equivalent IN3064 or Equivalent 2.7 kΩ 6.2 kΩ +5.0 V IN3064 or Equivalent IN3064 or Equivalent C L = 100 pF Device Under Test

V29C51002T/V29C51002B Rev. 2.1 October 2000 MOSEL VITELIC V29C51002T/V29C51002B Absolute Maximum Ratings (1) NOTE: 1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. No more than one output maybe shorted at a time and not exceeding one second long. (over the commercial operating range) Symbol Parameter Commercial Unit V IN Input Voltage (input or I/O pins) -2 to +7 V V IN Input Voltage (A pin, OE) -2 to +13 V V CC Power Supply Voltage -0.5 to +5.5 V T STG Storage Temerpature (Plastic) -65 to +125 C T OPR Operating Temperature 0 to +70 C I OUT Short Circuit Current (2) 200 (Max.) mA Parameter Name Parameter Test Conditions Min. Max. Unit V IL Input LOW Voltage V CC = V CC Min. — 0.8 V V IH Input HIGH Voltage V CC = V CC Max. 2 — V I IL Input Leakage Current V IN = GND to V CC , V CC = V CC Max. — µ A I OL Output Leakage Current V OUT = GND to V CC , V CC = V CC Max. — µ A V OL Output LOW Voltage V CC = V CC Min., I OL = 2.1mA — 0.4 V V OH Output HIGH Voltage V CC = V CC Min, I OH = -400 µ A 2.4 — V I CC1 Read Current CE = OE = V IL , WE = V IH , all I/Os open, Address input = V IL IH , at f = 1/t RC Min., V CC = V CC Max. — 40 mA I CC2 Write Current CE = WE = VIL, OE = V IH , V CC = V CC Max. — 50 mA I SB TTL Standby Current CE = OE = WE = V IH , V CC = V CC Max. — 2m A I SB1 CMOS Standby Current CE = OE = WE = V CC – 0.3V, V CC = V CC Max. — 100 µ A V H Device ID Voltage for A CE = OE = V IL, WE = VIH 11.5 12.5 V IH Device ID Current for A9 CE = OE = VIL, WE = VIH, A9 = VH Max. — 50 µA

MOSEL VITELIC V29C51002T/V29C51002B 5V29C51002T/V29C51002B Rev. 2.1 October 2000 (over all temperature ranges) Read Cycle Program (Erase/Program) Cycle Parameter Name Parameter -55 -90 UnitMin. Max. Min. Max. tRC Read Cycle Time 55 — 90 — ns tAA Address Access Time — 55 — 90 ns tACS Chip Enable Access Time — 55 — 90 ns tOE Output Enable Access Time — 25 — 45 ns tCLZ CE Low to Output Active 0 — 0 — ns tOLZ OE Low to Output Active 0 — 0 — ns tDF OE or CE High to Output in High Z 0 30 0 40 ns tOH Output Hold from Address Change 0 — 0 — ns Parameter Name Parameter -55 -90 tWC Write Cycle Time 55 —— 90 —— ns tAS Address Setup Time 0 —— 0 —— ns tAH Address Hold Time 35 —— 45 —— ns tCS CE Setup Time 0 —— 0 —— ns tCH CE Hold Time 0 —— 0 —— ns tOES OE Setup Time 0 —— 0 —— ns tOEH OE High Hold Time 0 —— 0 —— ns tWP WE Pulse Width 30 —— 45 —— ns tWPH WE Pulse Width High 20 —— 30 —— ns tDS Data Setup Time 25 —— 30 —— ns tDH Data Hold Time 0 —— 0 —— ns tWHWH1 Programming Cycle —— 20 —— 20 µs tWHWH2 Sector Erase Cycle —— 10 —— 10 ms tWHWH3 Chip Erase Cycle — 2 —— 2 — sec

6V29C51002T/V29C51002B Rev. 2.1 October 2000 MOSEL VITELIC V29C51002T/V29C51002B Waveforms of Read Cycle Waveforms of WE Controlled-Program Cycle NOTES: 1. I/O 7: The output is the complement of the data written to the device. 2. PA: The address of the memory location to be programmed. 3. PD: The data at the byte address to be programmed. tRC tAA tCE tOE tCLZ tOH tAA tOLZ tDF ADDRESS CE OE WE I/O VALID DATA OUT VALID DATA OUT HIGH-Z 51002-09 HIGH-Z tWC tAS PA5555H tWHWH1 tWPHtCS tRCtAH tDS tDH tWPtOES tDF tOH tOE D OUTI/O7(1)PD (3)A0H 51002-10 ADDRESS CE OE WE I/O 3rd bus cycle PA (2) tCH

MOSEL VITELIC V29C51002T/V29C51002B 7V29C51002T/V29C51002B Rev. 2.1 October 2000 Waveforms of CE Controlled-Program Cycle Waveforms of Erase Cycle(1) NOTES: 1. PA: The address of the memory location to be programmed. 2. PD: The data at the byte address to be programmed. 3. SA: The sector address for Sector Erase. tWC tAS tWHWH1 tWPHtOES tRC tAH tDS tDH tWP tDF tOH tOE D OUTI/O7PD (2)A0H 51002-11 ADDRESS 5555H PA PA (1) WE OE CE I/O tWC tAS tWPH tWHWH 2 ADDRESS CE OE WE I/O 5555H 5555H 5555H2AAAH 2AAAH SA (5555H for Chip Erase) AAH 55H 80H AAH 55H 30H (10H for Chip Erase) 51002-12 tAH tWP tDS tDH tCS

8V29C51002T/V29C51002B Rev. 2.1 October 2000 MOSEL VITELIC V29C51002T/V29C51002B Waveforms of DATA Polling Cycle Waveforms of Toggle Bit Cycle tOEH tCE tWHWH1 (2 or 3) tOH tDF tCH CE OE WE I/O7 I/O7 I/O7 VALID DATA OUT HIGH-Z tOE 51002-13 I/O0-I/O6I/O0-I/O6 INVALID VALID DATA OUT HIGH-Z 51002-14 CE WE OE tOEH stop toggling I/O6 tWHWH1 (2 or 3)

must be HIGH prior to CE and OE going LOW. for the read to complete (see Table 1). sequence, for example Address: 5555H, Data FFH. can be CE controlled or WE controlled.

512 Byte

Table 1. Operation Modes Decoding

1. X = Don ’t Care, VIH = HIGH, VIL = LOW, VH = 12.5V Max.
2. PD: The data at the byte address to be programmed.

determined via DATA polling or toggle bit status. and the chip erase command (see Table 2). and terminates when the data on DQ7 is “1”. polling to indicate the end of a program cycle. bit may begin at any time during a program cycle. HIGH or LOW. This is shown in table 1. status, device ID and manufacturer ID. Table 2. Command Codes

1. PA: The address of the memory location to be programmed.
2. PD: The data at the byte address to be programmed.

unprotected. This is also shown is table 3. Boot Block device (see Table 3). 5ns will not initiate a program cycle. HIGH or WE HIGH inhibits a program cycle. Table 3. Autoselect Decoding

1. X = Don ’t Care, VIH = HIGH, VIL = LOW.

12V29C51002T/V29C51002B Rev. 2.1 October 2000 MOSEL VITELIC V29C51002T/V29C51002B Byte Program Algorithm Chip/Sector Erase Algorithm Write Byte-Write Command Sequence Add/Data 5555H/AAH 2AAAH/55H 5555H/A0H Four Bus Cycle Sequence PA/PD Data Polling or Toggle bit successfully completed or tWTWH (2 or 3) timeout Data Polling or Toggle bit successfully completed or tWTWH (2 or 3) timeout Writing Completed Write Erase Command Sequence Add/Data 5555H/AAH 2AAAH/55H 5555H/80H Six Bus Cycle Sequence 5555H/AAH 2AAAH/55H 5555H/10H (Chip Erase) SA/30H (Sector Erase) Erase Completed 51002-16

MOSEL VITELIC V29C51002T/V29C51002B 13V29C51002T/V29C51002B Rev. 2.1 October 2000 DATA Polling Algorithm Toggle Bit Algorithm NOTE: 1. PBA: The byte address to be programmed. Read I/O7 Address = PBA(1) Program Done Program Done I/O7 = DataNo Yes Read I/O6 No Yes I/O6 Toggle Read I/O6 51002-17

14V29C51002T/V29C51002B Rev. 2.1 October 2000 MOSEL VITELIC V29C51002T/V29C51002B Package Diagrams 32-pin Plastic DIP 32-pin PLCC 15° MAX 0.545/0.555 INDEX-1 .047+.012 – 0

0.210 MAX

0.120 MIN

0.010 MIN

.600 TYP 1.660 MAX. .050 MAX .100 TYP .032 +.012 – 0 .018 +.006 – .002 .010 +.004 – .0004 INDEX-2 EJECTOR MARK 3° - 6° .017 30° .136 ± .003 .110 .046 ± .003 .025 .050 TYP .450 ± .003 .490 ± .005 .045X45° .590 ± .005 .550 ± .003 20 19 18 17 16 15 14 29 30 31 32 1 2 3 4

MOSEL VITELIC V29C51002T/V29C51002B 15V29C51002T/V29C51002B Rev. 2.1 October 2000 32-pin TSOP-I 0.032 TYP.

0.020 SBC

0.003 MAX

0.020 MAX. 0.024 ± 0.004 SEATING PLANE 0.010 See Detail “A” Detail “A ” 0.724 TYP. (0.728 MAX.) 0.787 ± 0.008 0.009 ± 0.002 0.315 TYP. (0.319 MAX.) 0.035 ± 0.002 0.047 MAX. 0.005 MIN. 0.007 MAX. Units in inches

MOSEL VITELIC WORLDWIDE OFFICES V29C51002T/V29C51002B MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461 The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep cur- rent the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. © Copyright 2000, MOSEL VITELIC Inc. 10/00 Printed in U.S.A. U.S. SALES OFFICES U.S.A.

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