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DP8573A_11 TI1 | Alldatasheet

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DP8573A Real Time Clock (RTC) Literature Number: SNAS561

DP8573A Real Time Clock (RTC) May 1993 DP8573A Real Time Clock (RTC) General Description The DP8573A is intended for use in microprocessor based systems where information is required for multi-tasking, data logging or general time of day/date information. This device is implemented in low voltage silicon gate microCMOS tech- nology to provide low standby power in battery back-up en- vironments. The circuit’s architecture is such that it looks like a contiguous block of memory or I/O ports organized as one block of 32 bytes. This includes the Control Registers, the Clock Counters, the Alarm Compare RAM, and the Time Save RAM. Time and date are maintained from 1/100 of a second to year and leap year in a BCD format, 12 or 24 hour modes. Day of week and day of month counters are provided. Time is controlled by an on-chip crystal oscillator requiring only the addition of the 32.768 kHz crystal and two capacitors. Power failure logic and control functions have been integrat- ed on chip. This logic is used by the RTC to issue a power fail interrupt, and lock out the mP interface. The time power fails may be logged into RAM automatically when V BB l VCC. Additionally, two supply pins are provided. When V BB l VCC, internal circuitry will automatically switch from the main supply to the battery supply. The DP8573A’s interrupt structure provides three basic types of interrupts: Periodic, Alarm/Compare, and Power Fail. Interrupt mask and status registers enable the masking and easy determination of each interrupt.

Features

Y Full function real time clock/calendar Ð 12/24 hour mode timekeeping Ð Day of week counter Ð Parallel resonant oscillator Y Power fail features Ð Internal power supply switch to external battery Ð Power Supply Bus glitch protection Ð Automatic log of time into RAM at power failure Y On-chip interrupt structure Ð Periodic, alarm, and power fail interrupts Block Diagram TL/F/9981–1 FIGURE 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

Absolute Maximum Ratings (Notes1&2 ) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (V CC) b0.5V to a7.0V DC Input Voltage (V IN) b0.5V to V CC a0.5V DC Output Voltage (V OUT) b0.5V to V CC a 0.5V Storage Temperature Range b65§Ct o a150§C Power Dissipation (PD) 500 mW Lead Temperature (Soldering, 10 sec.) 260 Operation Conditions Min Max Unit Supply Voltage (V CC) (Note 3) 4.5 5.5 V Supply Voltage (V BB) (Note 3) 2.2 V CCb0.4 V DC Input or Output Voltage 0.0 V CC V(VIN,V OUT) Operation Temperature (T A) b40 a85 §C Electr-Static Discharge Rating 1 kV Transistor Count 10,300 Typical Values i JA DIP Board 59 §C/W Socket 65 §C/W iJA PLCC Board 80 §C/W Socket 88 §C/W VCC e 5V g10%, V BB e 3V, V PFAIL l VIH,C L e 100 pF (unless otherwise specified) Symbol Parameter Conditions Min Max Units VIH High Level Input Voltage Any Inputs Except OSC IN, 2.0 V (Note 4) OSC IN with External Clock V BB b0.1 V VIL Low Level Input Voltage All Inputs Except OSC IN 0.8 V OSC IN with External Clock 0.1 V VOH High Level Output Voltage I OUT eb 20 mAV CC b0.1 V (Excluding OSC OUT) I OUT eb 4.0 mA 3.5 V VOL Low Level Output Voltage I OUT e 20 mA 0.1 V (Excluding OSC OUT) I OUT e 4.0 mA 0.25 V IIN Input Current (Except OSC IN) V IN e VCC or GND g1.0 mA IOZ Output TRI-STATE É Current V OUT e VCC or GND g5.0 mA ILKG Output High Leakage Current V OUT e VCC or GND g5.0 mAT1, MFO, INTR Pins Outputs Open Drain ICC Quiescent Supply Current F OSC e 32.768 kHz (Note 6) V IN e VCC or GND (Note 5) 250 mA VIN e VCC or GND (Note 6) 1.0 mA VIN e VIH or V IL (Note 6) 12.0 mA ICC Quiescent Supply Current V BB e GND (Single Supply Mode) V IN e VCC or GND 40 mA (Note 7) F OSC e 32.768 kHz IBB Standby Mode Battery V CC e GND 10 mASupply Current OSC OUT e open circuit, (Note 7) other pins e GND FOSC e 32.768 kHz IBLK Battery Leakage 2.2V s VBB s 4.0V other pins at GND VCC e GND 1.5 mA VCC e 5.5V b5 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: In battery backed mode, V BB s VCC b 0.4V. Single Supply Mode: Data retention voltage is 2.2V min. In single Supply Mode (Power connected to V CC pin) 4.5V s VCC s 5.5V. Note 4: This parameter (V IH) is not tested on all pins at the same time. Note 5: This specification tests I CC with all power fail circuitry disabled, by setting D7 of Interrupt Control Register 1 to 0. Note 6: This specification tests I CC with all power fail circuitry enabled, by setting D7 of Interrupt Control Register 1 to 1. Note 7: OSC IN is driven by a signal generator. Contents of the Test Register e 00(H) and the MFO pin is not configured as buffered oscillator out.

VCC e 5V g10%, V BB e 3V, V PFAIL l VIH,C L e 100 pF (unless otherwise specified) Symbol Parameter Min Max Units READ TIMING tAR Address Valid Prior to Read Strobe 20 ns tRW Read Strobe Width (Note 8) 80 ns tCD Chip Select to Data Valid Time 80 ns tRAH Address Hold after Read (Note 9) 3 ns tRD Read Strobe to Valid Data 70 ns tDZ Read or Chip Select to TRI-STATE 60 ns tRCH Chip Select Hold after Read Strobe 0 ns tDS Minimum Inactive Time between Read or Write Accesses 50 ns WRITE TIMING tAW Address Valid before Write Strobe 20 ns tWAH Address Hold after Write Strobe (Note 9) 3 ns tCW Chip Select to End of Write Strobe 90 ns tWW Write Strobe Width (Note 10) 80 ns tDW Data Valid to End of Write Strobe 50 ns tWDH Data Hold after Write Strobe (Note 9) 3 ns tWCH Chip Select Hold after Write Strobe 0 ns INTERRUPT TIMING tROLL Clock rollover to INTR out typically 16.5 ms Note 8: Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low. Hence read commences when both signals are low and terminates when either signal returns high. Note 9: Hold time is guaranteed by design but not production tested. This limit is not used to calculate outgoing quality levels. Note 10: Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low. Hence write commences when both signals are low and terminates when either signal returns high. AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise and Fall Times 6 ns (10%–90%) Input and Output 1.3VReference Levels TRI-STATE Reference Active High a0.5V Levels (Note 12) Active Low b0.5V Note 11: CL e 100 pF, includes jig and scope capacitance. Note 12: S1 e VCC for active low to high impedance measurements. S1 e GND for active high to high impedance measurements. S1 e open for all other timing measurements. Capacitance (TA e 25§C, f e 1 MHz) Symbol Parameter Typ Units(Note 14) CIN Input Capacitance 5 pF COUT Output Capacitance 7 pF Note 13: This parameter is not 100% tested. Note 14: Output rise and fall times 25 ns max (10%–90%) with 100 pF load. TL/F/9981–2

TL/F/9981–3 Write Timing Diagram TL/F/9981–4 Pin Description CS,R D ,W R (Inputs): These pins interface to mP control lines. The CS pin is an active low enable for the read and write operations. Read and Write pins are also active low and enable reading or writing to the RTC. All three pins are disabled when power failure is detected. However, if a read or write is in progress at this time, it will be allowed to com- plete its cycle. A0–A4 (Inputs): These 5 pins are for register selection. They individually control which location is to be accessed. These inputs are disabled when power failure is detected. OSC IN (Input): OSC OUT (Output): These two pins are used to connect the crystal to the internal parallel resonant oscillator. The oscillator is always running when power is applied to V BB and V CC. MFO (Output): The multi-function output can be used as a second interrupt (Power fail) output for interrupting the mP. This pin can also provide an output for the oscillator. The MFO output is configured as push-pull, active high for nor- mal or single power supply operation and as an open drain during standby mode (V BB l VCC). If in battery backed mode and a pull-up resistor is attached, it should be con- nected to a voltage no greater than V BB. INTR (Output): The interrupt output is used to interrupt the processor when a timing event or power fail has occurred and the respective interrupt has been enabled. The INTR output is permanently configured active low, open drain. If in battery backed mode and a pull-up resistor is attached, it should be connected to a voltage no greater than V BB. The output is a DC voltage level. To clear the INTR, writ ea1t o the appropriate bit(s) in the Main Status Register. D0–D7 (Input/Output): These 8 bidirectional pins connect to the host mP’s data bus and are used to read from and write to the RTC. When the PFAIL pin goes low and a write is not in progress, these pins are at TRI-STATE. PFAIL (Input): In battery backed mode, this pin can have a digital signal applied to it via some external power detection logic. When PFAIL e logic 0 the RTC goes into a lockout mode, in a minimum of 30 ms or a maximum of 63 ms unless lockout delay is programmed. In the single power supply mode, this pin is not useable as an input and should be tied to V CC. Refer to section on Power Fail Functional Descrip- tion. VBB (Battery Power Pin): This pin is connected to a back- up power supply. This power supply is switched to the inter- nal circuitry when the V CC becomes lower than V BB. Utiliz- ing this pin eliminates the need for external logic to switch in and out the back-up power supply. If this feature is not to be used then this pin must be tied to ground, the RTC pro- grammed for single power supply only, and power applied to the V CC pin. VCC: This is the main system power pin. GND: This is the common ground power pin for both V BB and V CC.

FIGURE 5. Interrupt Control Logic Overview

Functional Description (Continued) ternal interrupt will be issued. Note that the linear power fail circuitry is switched off automatically when using V BB in standby mode. INITIAL POWER ON DETECT AND POWER FAIL TIME SAVE There are two other functions provided on the DP8573A to ease power supply control. These are an initial Power On detect circuit, which also can be used as a time keeping failure detect, and a time save on power failure. On initial power up the Oscillator Fail Flag will be set to a one and the real time clock start bit reset to a zero. This indicates that an oscillator fail event has occurred, and time keeping has failed. The Oscillator Fail flag will not be reset until the real-time clock is started. This allows the system to discriminate be- tween an initial power-up and recovery from a power failure. If the battery backed mode is selected, then bit D6 of the Periodic Flag Register must be written low. This will not af- fect the contents of the Oscillator Fail Flag. To relieve CPU overhead for saving time upon power failure, the Time Save Enable bit is provided to do this automatical- ly. (See also Reading the Clock: Latched Read.) The Time Save Enable bit, when set, causes the Time Save RAM to follow the contents of the clock. This bit can be reset by software, but if set before a power failure occurs, it will auto- matically be reset when the clock switches to the battery supply (not when a power failure is detected by the PFAIL pin). Thus, writing a one to the Time Save bit enables both a software write or power fail write. SINGLE POWER SUPPLY APPLICATIONS The DP8573A can be used in a single power supply applica- tion. To achieve this, the V BB pin must be connected to ground, and the power connected to V CC. The Oscillator Failed/Single Supply bit in the Periodic Flag Register should be set to a logic 1, which will disable the oscillator battery reference circuit. The power fail interrupt should also be dis- abled. This will turn off the linear power fail detection cir- cuits, and will eliminate any quiescent power drawn through these circuits. DETAILED REGISTER DESCRIPTION There are 5 external address bits: Thus, the host microproc- essor has access to 28 locations at one time. An internal switching scheme provides a total of 30 locations. The only register that does not get switched is the Main Status Register. It contains the register select bit as well as status information. A memory map is shown in Figure 2 and register addressing in Table III. They show the name, address and page loca- tions for the DP8573A. TABLE III. Register/Counter/RAM Addressing for DP8573A A0-4 RS Description(Note 1) CONTROL REGISTERS

00 X Main Status Register

03 0 Periodic Flag Register 04 0 Time Save Control Register 01 1 Real Time Mode Register 02 1 Output Mode Register 03 1 Interrupt Control Register 0 04 1 Interrupt Control Register 1 COUNTERS (CLOCK CALENDAR)

05 X 1/100, 1/10 Seconds (0–99)

06 X Seconds (0–59)

07 X Minutes (0–59)

08 X Hours (1–12, 0–23)

09 X Days of Month (1–28/29/30/31)

0A X Months (1–12) 0B X Years (0–99) 0C X RAM 0D X D0, D1 bits only 0E X Day of Week (1–7) 0F X N/A

10 X N/A

11 X N/A

12 X N/A

13 X Sec Compare RAM (0–59)

14 X Min Compare RAM (0–59)

15 X Hours Compare RAM (1–12, 0–23)

16 X DOM Compare RAM (1–28/29/30/31)

17 X Months Compare RAM (1–12)

18 X DOW Compare RAM (1–7)

19 X Seconds Time Save RAM

1A X Minutes Time Save RAM 1B X Hours Time Save RAM 1C X Day of Month Time Save RAM 1D X Months Time Save RAM 1E 1 RAM 1F X RAM/Test Mode Register Note 1: RSÐRegister Select (Bit D6 of Main Status Register)

Functional Description (Continued) MAIN STATUS REGISTER TL/F/9981–12 The Main Status Register is always located at address 0 regardless of the register block selected. D0: This read only bit is a general interrupt status bit that is taken directly from the interrupt pins. The bit is a one when an interrupt is pending on either the INTR pin or the MFO pin (when configured as an interrupt). This is unlike D3 which can be set by an internal event but may not cause an interrupt. This bit is reset when the interrupt status bits in the Main Status Register are cleared. D1–D3: These three bits of the Main Status Register are the main interrupt status bits. Any bit may be a one when any of the interrupts are pending. Once an interrupt is asserted the mP will read this register to determine the cause. These interrupt status bits are not reset when read. Except for D1, to reset an interrupt a one is written back to the correspond- ing bit that is being tested. D1 is reset whenever the PFAIL pin e logic 1. This prevents loss of interrupt status when reading the register in a polled mode. D1 and D3 are set regardless of whether these interrupts are masked or not by bits D6 and D7 of Interrupt Control Registers 0 and 1. D4, D5 and D7: General purpose RAM bits. D6: Bit D6 controls the register block to be accessed (see memory map). PERIODIC FLAG REGISTER TL/F/9981–13 The Periodic Flag Register has the same bit for bit corre- spondence as Interrupt Control Register 0 except for D6 and D7. For normal operation (i.e., not a single supply appli- cation) this register must be written to on initial power up or after an oscillator fail event. D0–D5 are read only bits, D6 and D7 are read/write. D0–D5: These bits are set by the real time rollover events: (Time Change e 1). The bits are reset when the register is read and can be used as selective data change flags. D6: This bit performs a dual function. When this bit is read, a one indicates that an oscillator failure has occurred and the time information may have been lost. Some of the ways an oscillator failure might be caused are: failure of the crystal, shorting OSC IN or OSC OUT to GND or V CC, removal of crystal, removal of battery when in the battery backed mode (when a ‘‘0’’ is written to D6), lowering the voltage at the V BB pin to a value less than 2.2V when in the battery backed mode. Bit D6 is automatically set to 1 on initial pow- er-up or an oscillator fail event. The oscillator fail flag is reset by writing a one to the clock start/stop bit in the Real Time Mode Register, with the crystal oscillating. When D6 is written to, it defines whether the TCP is being used in battery backed (normal) or in a single supply mode application. When set to a one this bit configures the TCP for single power supply applications. This bit is automatically set on initial power-up or an oscillator fail event. When set, D6 disables the oscillator reference circuit. The result is that the oscillator is referenced to V CC. When a zero is written to D6 the oscillator reference is enabled, thus the oscillator is referenced to V BB. This allows operation in standard battery standby applications. At initial power on, if the DP8573A is going to be pro- grammed for battery backed mode, the V BB pin should be connected to a potential in the range of 2.2V to V CC b 0.4V. For single supply mode operation, the V BB pin should be connected to GND and the PFAIL pin connected to V CC. D7: Writing a one to this bit enables the test mode register at location 1F (see Table III). This bit should be forced to zero during initialization for normal operation. If the test mode has been entered, clear the test mode register before leaving test mode. (See separate test mode application note for further details.) TIME SAVE CONTROL REGISTER TL/F/9981–14 D0–D5: General purpose RAM bits. D6: Not Available, appears as logic 0 when read. D7: Time Save Enable bit controls the loading of real-time- clock data into the Time Save RAM. When a one is written to this bit the Time Save RAM will follow the corresponding clock registers, and when a zero is written to this bit the time in the Time Save RAM is frozen. This eliminates any syn- chronization problems when reading the clock, thus negat- ing the need to check for a counter rollover during a read cycle. This bit must be set to a one prior to power failing to enable the Time Save feature. When the power fails this bit is auto- matically reset and the time is saved in the Time Save RAM. REAL TIME MODE REGISTER TL/F/9981–15

Functional Description (Continued) D0–D1: These are the leap year counter bits. These bits are written to set the number of years from the previous leap year. The leap year counter increments on December 31st and it internally enables the February 29th counter state. This method of setting the leap year allows leap year to occur whenever the user wishes to, thus providing flexibility in implementing Japanese leap year function. LY1 LY0 Leap Year Counter 0 0 Leap Year Current Year 0 1 Leap Year Last Year 1 0 Leap Year 2 Years Ago 1 1 Leap Year 3 Years Ago D2: The count mode for the hours counter can be set to either 24 hour mode or 12 hour mode with AM/PM indicator. A one will place the clock in 12 hour mode. D3: This bit is the master Start/Stop bit for the clock. When a one is written to this bit the real time counter’s prescaler and counter chain are enabled. When this bit is reset to zero the contents of the real time counter is stopped. When the RTC is initially powered up this bit will be held at a logic 0 until the oscillator starts functioning correctly after which this bit may be modified. If an oscillator fail event occurs, this bit will be reset to logic 0. D4: This bit controls the operation of the interrupt output in standby mode. If set to a one it allows Alarm, Periodic, and Power Fail interrupts to be functional in standby mode. Note that the MFO pin is configured as open drain in standby mode. If bit D4 is set to a zero then bits D0–D5 of Interrupt Control Register 0 and bits D6 and D7 of Interrupt Control Register 1 will be reset when the RTC enters the standby mode. They will have to be re-configured when system (V CC) pow- er is restored. D5–D7: General purpose RAM bits. OUTPUT MODE REGISTER TL/F/9981–16 D0–D6: General purpose RAM bits. D7: This bit is used to program the signal appearing at the MFO output, as follows: D7 MFO Output Signal

0 Power Fail Interrupt

1 Buffered Crystal Oscillator

INTERRUPT CONTROL REGISTER 0 TL/F/9981–17 D0–D5: These bits are used to enable one of the selected periodic interrupts by writing a one into the appropriate bit. These interrupts are issued at the rollover of the clock. For example, the minutes interrupt will be issued whenever the minutes counter increments. In all likelihood the interrupt will be enabled asynchronously with the real time change. Therefore, the very first interrupt will occur in less than the periodic time chosen, but after the first interrupt all subse- quent interrupts will be spaced correctly. These interrupts are useful when minute, second, real time reading, or task switching is required. When all six bits are written to a 0 this disables periodic interrupts from the Main Status Register and the interrupt pin. If battery backed mode is selected and the DP8573A is in standby (V BB l VCC), then these bits are controlled by D4 of the Real Time Mode Register. D6 and D7: General purpose RAM. INTERRUPT CONTROL REGISTER 1 TL/F/9981–18 D0–D5: Each of these bits are enable bits which will enable a comparison between an individual clock counter and its associated compare RAM. If any bit is a zero then that clock-RAM comparator is set to the ‘‘always equal’’ state and the associated TIME COMPARE RAM byte can be used as general purpose RAM. However, to ensure that an alarm interrupt is not generated at bit D3 of the Main Status Regis- ter, all bits must be written to a logic zero. D6: In order to generate an external alarm compare inter- rupt to the mP from bit D3 of the Main Status Register, this bit must be written to a logic 1. If battery backed mode is selected and the DP8573A is in standby (V BB l VCC), then this bit is controlled by D4 of the Real Time Mode Register. D7: The MSB of this register is the enable bit for the Power Fail Interrupt. When this bit is set to a one an interrupt will be generated to the mP when V BB l VCC. If battery backed mode is selected and the DP8573A is in standby (V BB l VCC), then this bit is controlled by D4 of the Real Time Mode Register.

Control and Status Register Address Bit Map D7 D6 D5 D4 D3 D2 D1 D0 1. Reset byMain Status Register PS e XR S e X ADDRESS e 00H writingR/W R/W R/W R/W R/W 1 R/W1 R2 R3 1 to bit. RAM Register RAM RAM Alarm Periodic Power Fail Interrupt 2. Set/reset bySelect Interrupt Interrupt Interrupt Status voltage at PFAIL pin. 3. Reset when all pending interrupts are removed. Periodic Flag Register PS e 0R S e 0 Address e 03H 4. Read Osc failR/W R/W 4 R5 R5 R5 R5 R5 R5 Write 0 Batt- Test Osc. Fail/ 1 ms 10 ms 100 ms Seconds 10 Second Minute Backed Mode Mode Single Supply Flag Flag Flag Flag Flag Flag Write 1 Single Supply Mode 5. Reset by positive edge of read. Time Save Control Register PS e 0R S e 0 Address e 04H Time Save N/A RAM RAM RAM RAM RAM RAM All Bits R/WEnable Real Time Mode Register PS e 0R S e 1 Address e 01H RAM RAM RAM Interrupt EN Clock 12/24 Hr. Leap Year Leap Year All Bits R/Won Back-Up Start/Stop Mode MSB LSB Output Mode Register PS e 0R S e 1 Address e 02H MFO as RAM RAM RAM RAM RAM RAM RAM All Bits R/WCrystal Interrupt Control Register 0 PS e 0R S e 1 Address e 03H 1 ms 10 ms 100 ms Seconds 10 Second Minute RAM RAM Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt All Bits R/W Enable Enable Enable Enable Enable Enable Interrupt Control Register 1 PS e 0R S e 1 Address e 04H Power Fail Alarm DOW Month DOM Hours Minute Second Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt All Bits R/W Enable Enable Enable Enable Enable Enable Enable Enable Application Hints Suggested Initialization Procedure for DP8573A in Bat- tery Backed Applications that use the V BB Pin 1. Enter the test mode by writin ga1t ob i tD 7i nt h e Period- ic Flag Register. 2. Write zero to the RAM/TEST mode Register located in page 0, address HEX 1F. 3. Leave the test mode by writin ga0t ob i tD 7i nt h e Peri- odic Flag Register. Steps 1, 2, 3 guarantee that if the test mode had been entered during power on (due to random pulses from the system), all test mode condi- tions are cleared. Most important is that the OSC Fail Disable bit is cleared. Refer to AN-589 for more informa- tion on test mode operation. 4. Enter a software loop that does the following: Set a 3 second(approx) software counter. The crystal oscillator may take 1 second to start.

4.1 Writ ea1t ob i tD 3i nt h e Real Time Mode Register (try

to start the clock). Under normal operation, this bit can be set only if the oscillator is running. During the soft- ware loop, RAM, real time counters, output configura- tion, interrupt control and timer functions may be initial- ized.

Application Hints (Continued) 5. Test bit D6 in the Periodic Flag Register: I Fa1 , go to 4.1. If this bit remain s a 1 after 3 seconds, then abort and check hardware. The crystal may be de- fective or not installed. There may be a short at OSC IN or OSC OUT to V CC or GND, or to some impedance that is less than 10 M X. I Fa0 , then the oscillator is running, go to step 7. 6. Writ ea0t ob i tD 6i nt h e Periodic Flag Register. This action puts the clock chip in the battery backed mode. This mode can be entered only if the OSC fail flag (bit D6 of the Periodic Flag Register) is a 0. Reminder, bit D6 is a dual function bit. When read, D6 returns oscillator status. When written, D6 causes either the Battery Backed Mode, or the Single Supply Mode of operation. The only method to ensure the chip is in the battery backed mode is to measure the waveform at the OSC OUT pin. If the battery backed mode was selected suc- cessfully, then the peak to peak waveform at OSC OUT is referenced to the battery voltage. If not in battery backed mode, the waveform is referenced to V CC. The measurement should be made with a high impedance low capacitance probe (10 M X, 10 pF oscilloscope probe or better). Typical peak to peak swings are within 0.6V of V CC and ground respectively. 7. Writ ea1t ob i tD 7o f Interrupt Control Register 1. This action enables the PFAIL pin and associated circuitry. 8. Writ ea1t ob i tD 4o ft h e Real Time Mode Register. This action ensures that bit D7 of Interrupt Control Register 1 remains a 1 when V BB l VCC (Standby Mode). 9. Initialize the rest of the chip as needed. Typical Application TL/F/9981–19 *These components may be necessary to meet UL requirements for lithium batteries. Consult battery manufacturer.

Typical Performance Characteristics Operating Current vs Supply Voltage (Single Supply Mode F OSC e 32.768 kHz) TL/F/9981–20 Operating Current vs Supply Voltage (Battery Backed Mode F OSC e 32.768 kHz) TL/F/9981–21 Standby Current vs Power Supply Voltage OSC e 32.768 kHz) TL/F/9981–22 Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number DP8573AN

DP8573A Real Time Clock (RTC) Physical Dimensions inches (millimeters) (Continued) Plastic Chip Carrier Package (V) Order Number DP8573AV LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor Corporation GmbH Japan Ltd. Hong Kong Ltd. Do Brazil Ltda. (Australia) Pty, Ltd. 2900 Semiconductor Drive Livry-Gargan-Str. 10 Sumitomo Chemical 13th Floor, Straight Block, Rue Deputado Lacorda Franco Building 16 P.O. Box 58090 D-82256 F 4urstenfeldbruck Engineering Center Ocean Centre, 5 Canton Rd. 120-3A Business Park Drive Santa Clara, CA 95052-8090 Germany Bldg. 7F Tsimshatsui, Kowloon Sao Paulo-SP Monash Business Park Tel: 1(800) 272-9959 Tel: (81-41) 35-0 1-7-1, Nakase, Mihama-Ku Hong Kong Brazil 05418-000 Nottinghill, Melbourne TWX: (910) 339-9240 Telex: 527649 Chiba-City, Tel: (852) 2737-1600 Tel: (55-11) 212-5066 Victoria 3168 Australia Fax: (81-41) 35-1 Ciba Prefecture 261 Fax: (852) 2736-9960 Telex: 391-1131931 NSBR BR Tel: (3) 558-9999 Tel: (043) 299-2300 Fax: (55-11) 212-1181 Fax: (3) 558-9998 Fax: (043) 299-2500 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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