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DP8392C,DP8392C-1 DP8392C DP8392C-1 CTI Coaxial Transceiver Interface Literature Number: SNLS078A
DP8392C/DP8392C-1 CTI Coaxial Transceiver Interface October 1995 DP8392C/DP8392C-1 CTI Coaxial Transceiver Interface General Description The DP8392C Coaxial Transceiver Interface (CTI) is a coax- ial cable line driver/receiver for Ethernet/Thin Ethernet (Cheapernet) type local area networks. The CTI is connect- ed between the coaxial cable and the Data Terminal Equip- ment (DTE). In Ethernet applications the transceiver is usu- ally mounted within a dedicated enclosure and is connected to the DTE via a transceiver cable. In Cheapernet applica- tions, the CTI is typically located within the DTE and con- nects to the DTE through isolation transformers only. The CTI consists of a Receiver, Transmitter, Collision Detector, and a Jabber Timer. The Transmitter connects directly to a 50 ohm coaxial cable where it is used to drive the coax when transmitting. During transmission, a jabber timer is ini- tiated to disable the CTI transmitter in the event of a longer than legal length data packet. Collision Detection circuitry monitors the signals on the coax to determine the presence of colliding packets and signals the DTE in the event of a collision. The CTI is part of a three chip set that implements the com- plete IEEE 802.3 compatible network node electronics as shown below. The other two chips are the DP8391 Serial Network Interface (SNI) and the DP8390 Network Interface Controller (NIC). The SNI provides the Manchester encoding and decoding functions; whereas the NIC handles the Media Access Pro- tocol and the buffer management tasks. Isolation between the CTI and the SNI is an IEEE 802.3 requirement that can be easily satisfied on signal lines using a set of pulse trans- formers that come in a standard DIP. However, the power isolation for the CTI is done by DC-to-DC conversion through a power transformer.
Features
Y Compatible with Ethernet II, IEEE 802.3 10Base5 and 10Base2 (Cheapernet) Y Integrates all transceiver electronics except signal & power isolation Y Innovative design minimizes external component count Y Jabber timer function integrated on chip Y Externally selectable CD Heartbeat allows operation with IEEE 802.3 compatible repeaters Y Precision circuitry implements receive mode collision detection Y Squelch circuitry at all inputs rejects noise Y Designed for rigorous reliability requirements of IEEE 802.3 Y Standard Outline 16-pin DIP uses a special leadframe that significantly reduces the operating die temperature Table of Contents
1.0 System Diagram
2.0 Block Diagram
3.0 Functional Description
3.1 Receiver Functions
3.2 Transmitter Functions
3.3 Collision Functions
3.4 Jabber Functions
4.0 Typical Applications
5.0 Connection Diagrams
6.0 Pin Descriptions
7.0 Absolute Maximum Ratings
8.0 DP8392C Electrical Characteristics
9.0 DP8392C-1 Electrical Characteristics
10.0 Switching Characteristics
11.0 Timing and Load Diagram
TL/F/11085–1 IEEE 802.3 Compatible Ethernet/Cheapernet Local Area Network Chip Set C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A. Obsolete
FIGURE 1. DP8392C Block Diagram pacitance to minimize loading and reflections on the coax. sponse at the signal frequencies to minimize jitter. squelch and the collision detection circuits. Figure 2 illustrates the Receiver timing. ing current in the isolation transformer.
3.0 Functional Description (Continued)
low operation with repeaters. FIGURE 2. Receiver Timing FIGURE 3. Transmitter Timing
4.0 Typical Application
TL/F/11085–5 Note 1: T1 is a 1:1 pulse transformer, L e 100 mH FIGURE 4Pulse Engineering (San Diego) Part No. 64103 Valor Electronics (San Diego) Part No. LT6003 or equivalent TL/F/11085–6 Order Number DP8392CV See NS Package Number V28A TL/F/11085–16 Top View Order Number DP8392CN See NS Package Number N16E FIGURE 5 Obsolete
28-Pin PLCC 16-Pin DIP Name I/O Description 21 C Da* O Collision Output. Balanced differential line driver outputs from the collision detect circuitry. The 10 MHz signal from the internal oscillator is transferred to these32 C D b outputs in the event of collision, excessive transmission (jabber), or during CD Heartbeat condition. These outputs are open emitters; pulldown resistors to VEE are required. When operating into a 78 X transmission line, these resistors should be 500 X. In Cheapernet applications, where the 78 X drop cable is not used, higher resistor values (up to 1.5k) may be used to save power. 43 R Xa* O Receive Output. Balanced differential line driver outputs from the Receiver. These outputs also require 500 X pulldown resistors.12 6 RX b 13 7 TX a* I Transmit Input. Balanced differential line receiver inputs to the Transmitter. The common mode voltage for these inputs is determined internally and must not be14 8 TX b externally established. Signals meeting Transmitter squelch requirements are waveshaped and output at TXO. 15 9 HBE I Heartbeat Enable. This input enables CD Heartbeat when grounded, disables it when connected to VEE. 18 11 RR a I External Resistor. A fixed 1k 1% resistor connected between these pins establishes internal operating currents.19 12 RR b 26 14 RXI I Receive Input. Connects directly to the coaxial cable. Signals meeting Receiver squelch requirements are equalized for inter-symbol distortion, amplified, and outputted at RX 28 15 TXO O Transmit Output. Connects either directly (Cheapernet) or via an isolation diode (Ethernet) to the coaxial cable. 1 16 CDS I Collision Detect Sense. Ground sense connection for the collision detect circuit. This pin should be connected separately to the shield to avoid ground drops from altering the receive mode collision threshold. 16, 17 10 GND Positive Supply Pin. A 0.1 mF ceramic decoupling capacitor must be connected across GND and VEE as close to the device as possible. 5–11 4 VEE Negative Supply Pins. In order to make full use of the 3.5W power dissipation capability of this package, these pins should be connected to a large metal frame20–25 5 area on the PC board. Doing this will reduce the operating die temperature of the13 device thereby increasing the long term reliability. *IEEE names for CD g e CIg,R X g e DIg,T X g e DOg 6.1 P.C. BOARD LAYOUT The DP8392C package is uniquely designed to ensure that the device meets the 1 million hour Mean Time Between Failure (MTBF) requirement of the IEEE 802.3 standard. In order to fully utilize this heat dissipation design, the three V EE pins are to be connected to a copper plane which should be included in the printed circuit board layout. There are two basic considerations in designing a PCB for the DP8392C and C-1 CTI. The first is ensuring that the layout does not degrade the electrical characteristics of the DP8392, and enables the end product to meet the IEEE 802.3 specifications. The second consideration is meeting the thermal requirements to the DP8392. Since the DP8392 is highly integrated the layout is actually quite simple, and there are just a few guidelines: 1. Ensure that the parasitic capacitance added to the RXI and TXO pins is minimized. To do this keep these signal traces short, and remove any power planes under these signals, and under any components that connect to these signals. Figure 6 shows the component placement for the DIP package. The PLCC component placement would be similar, as shown in Figure 7 . 2. The power supply layout to the CTI should be relatively clean. Usually the CTI’s power is supplied directly by a DC-DC converter. The power should be routed either through separate isolated planes, or via thick PCB traces. For the second consideration, the packaged DP8392 must have a thermal resistance of 40 §C–45 §C/W to meet the full 0§C–70 §C temperature range. The CTI dissipates more power when transmitting than while it is idle. In order to do this the thermal resistance of the device must be 40 §C– 45§C/W. To meet this requirement during transmission, it is recommended that a small printed circuit board plane be connected to all V EE pins on the solder side of the PCB. The size of the trace plane depends on the package used and the duty cycle of transmissions. For the DIP package the plane should be connected to pins 4–5, 13, and the size should be approximately 0.2 square inches for applications where the duty cycle of the transmitter is very low ( k10%). This would be typical of adapter or motherboard applica- tions. In applications where the transmitter duty cycle may be large (repeaters and external transceivers) the total area should be increased to 0.4 in 2. Figure 6 illustrates a recom- mended component side layout for these planes. Obsolete
6.0 Pin Descriptions (Continued)
a recommended component side layout for these planes. FIGURE 6. Typical Layout Considerations FIGURE 7. Recommended Layout and Dissipation Planes for DP8392CV (Not to Scale)
7.0 Absolute Maximum Ratings (Note 1)
Supply Voltage (V EE) b12V Package Power Rating at 25 §C 3.5 Watts* (PC Board Mounted) See Section 5 Derate linearly at the rate of 28.6 mW/ §C Input Voltage 0 to b12V Storage Temperature b65§ to 150 §C Lead Temp. (Soldering, 10 seconds) 260§C *For actual power dissipation of the device please refer to section 7.0. Recommended Operating Conditions Supply Voltage (V EE) b9v g5% Ambient Temperature 0 § to 70 §C If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
8.0 DP8392C Electrical Characteristics VEE eb 9V g5%, T A e 0§ to 70 §C (Notes2&3 )
All parameters with respect to CD g and RX g are measured after the pulse transformer except V OC. Symbol Parameter Min Typ Max Units IEE1 Supply current out of V EE pinÐnon transmitting b85 b130 mA IEE2 Supply current out of V EE pinÐtransmitting b125 b180 mA IRXI Receive input bias current (RXI) b2 a25 mA ITDC Transmit output dc current level (TXO) 37 41 45 mA ITAC Transmit output ac current level (TXO) g28 ITDC mA VCD Collision threshold (Receive mode) b1.45 b1.53 b1.58 V VOD Differential output voltage (RX g,C D g) g550 g1200 mV VOC Common mode output voltage (RX g,C D g) b1.5 b2.0 b2.5 V VOB Diff. output voltage imbalance (RX g,C D g) g40 mV VTS Transmitter squelch threshold (TX g) b175 b225 b300 mV CX Input capacitance (RXI) 1.2 pF RRXI Shunt resistanceÐnon transmitting (RXI) 100 KX RTXO Shunt resistanceÐtransmitting (TXO) 10 KX
9.0 DP8392C-1 Electrical Characteristics VEE eb 9V g5%, T A e 0§ to 70 §C (Notes2&3 )
All parameters with respect to CD g and RX g are measured after the pulse transformer except V OC. Symbol Parameter Min Typ Max Units IEE1 Supply current out of V EE pinÐnon transmitting b85 b130 mA IEE2 Supply current out of V EE pinÐtransmitting b125 b180 mA IRXI Receive input bias current (RXI) b2 a25 mA ITDC Transmit output dc current level (TXO) 37 41 45 mA ITAC Transmit output ac current level (TXO) g28 ITDC mA VCD Collision threshold (Receive mode) b1.45 b1.53 b1.58 V VOD Differential output voltage (RX g,C D g) g550 g1200 mV VOC Common mode output voltage (RX g,C D g) b1.5 b2.0 b2.5 V VOB Diff. output voltage imbalance (RX g,C D g) g40 mV VTS Transmitter squelch threshold (TX g) b175 b225 b275 mV CX Input capacitance (RXI) 1.2 pF RRXI Shunt resistanceÐnon transmitting (RXI) 100 KX RTXO Shunt resistanceÐtransmitting (TXO) 7.5K 10 KX Note 1: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. Note 2: All currents into device pins are positive, all currents out of device pins are negative. All voltages referenced to ground unless otherwise specified. Note 3: All typicals are given for V EE eb 9V and T A e 25§C. Obsolete
10.0 DP8392C Switching Characteristics VEE eb 9V g5%, T A e 0§ to 70 §C (Note 3)
Symbol Parameter Fig Min Typ Max Units tRON Receiver startup delay (RXI to RX g) 8 & 14 4 bits tRd Receiver propagation delay (RXI to RX g) 8&1 4 1 5 5 0 n s tRr Differential outputs rise time (RX g,C D g) 8&1 4 4 n s tRf Differential outputs fall time (RX g,C D g) 8&1 4 4 n s tRJ Receiver & cable total jitter 13 g2n s tTST Transmitter startup delay (TX g to TXO) 9 & 14 1 bits tTd Transmitter propagation delay (TX g to TXO) 9 & 14 25 50 ns tTr Transmitter rise time Ð10% to 90% (TXO) 9 & 14 25 ns tTf Transmitter fall time Ð90% to 10% (TXO) 9 & 14 25 ns tTM tTr and t Tf mismatch 0.5 ns tTS Transmitter skew (TXO) g0.5 ns tTON Transmit turn-on pulse width at V TS (TXg) 9&1 4 2 0 n s tTOFF Transmit turn-off pulse width at V TS (TXg) 9 & 14 250 ns tCON Collision turn-on delay 10 & 14 7 bits tCOFF Collision turn-off delay 10 & 14 20 bits fCD Collision frequency (CD g) 10 & 14 8.0 12.5 MHz tCP Collision pulse width (CD g) 1 0&1 4 3 5 7 0 n s tHON CD Heartbeat delay (TX g to CD g) 11 & 14 0.6 1.6 ms tHW CD Heartbeat duration (CD g) 11 & 14 0.5 1.0 1.5 ms tJA Jabber activation delay (TX g to TXO and CD g) 1 2&1 4 2 0 2 9 6 0 m s tJR Jabber reset unjab time (TX g to TXO and CD g) 12 & 14 250 500 750 ms DP8392C-1 Switching Characteristics VEE eb 9V g5%, T A e 0§ to 70 §C (Note 3) Symbol Parameter Fig Min Typ Max Units tRON Receiver startup delay (RXI to RX g) 8 & 14 4 5 bits tRd Receiver propagation delay (RXI to RX g) 8&1 4 1 5 5 0 n s tRr Differential outputs rise time (RX g,C D g) 8&1 4 4 7 n s tRf Differential outputs fall time (RX g,C D g) 8&1 4 4 7 n s tRJ Receiver & cable total jitter 13 g2n s tTST Transmitter startup delay (TX g to TXO) 9 & 14 1 2 bits tTd Transmitter propagation delay (TX g to TXO) 9 & 14 5 25 50 ns tTr Transmitter rise time Ð10% to 90% (TXO) 9 & 14 20 25 30 ns tTf Transmitter fall time Ð90% to 10% (TXO) 9 & 14 20 25 30 ns tTM tTr and t Tf mismatch 0.5 ns tTS Transmitter skew (TXO) g0.5 ns tTON Transmit turn-on pulse width at V TS (TXg) 9 & 14 5 20 40 ns tTOFF Transmit turn-off pulse width at V TS (TXg) 9 & 14 110 270 ns tCON Collision turn-on delay 10 & 14 7 13 bits tCOFF Collision turn-off delay 10 & 14 20 bits fCD Collision frequency (CD g) 10 & 14 8.5 12.5 MHz tCP Collision pulse width (CD g) 1 0&1 4 3 5 7 0 n s tHON CD Heartbeat delay (TX g to CD g) 11 & 14 0.6 1.6 ms tHW CD Heartbeat duration (CD g) 11 & 14 0.5 1.0 1.5 ms tJA Jabber activation delay (TX g to TXO and CD g) 1 2&1 4 2 0 2 9 6 0 m s tJR Jabber reset unjab time (TX g to TXO and CD g) 12 & 14 250 500 750 ms Note 1: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. Note 2: All currents into device pins are positive, all currents out of device pins are negative. All voltages referenced to ground unless otherwise specified. Note 3: All typicals are given for V EE eb 9V and T A e 25§C. Obsolete
11.0 Timing and Load Diagrams
FIGURE 8. Receiver Timing FIGURE 9. Transmitter Timing FIGURE 10. Collision Timing FIGURE 11. Heartbeat Timing
11.0 Timing and Load Diagrams (Continued)
FIGURE 12. Jabber Timing FIGURE 13. Receive Jitter Timing FIGURE 14. Test Loads
12.0 Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package (N) Order Number DP8392CN or DP8392CN-1 Obsolete
DP8392C/DP8392C-1 CTI Coaxial Transceiver Interface 12.0 Physical Dimensions inches (millimeters) (Continued) Lit. Ý103054 28-Lead Plastic Chip Carrier Order Number DP8392CV or DP8392CV-1 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.
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