V103A RENESAS | Alldatasheet

Document overview

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Technical content

Features

  • Pin compatible with THine THC63LVD103
  • Wide pixel clock range: 8 - 135 MHz
  • Guaranteed operation over -20 to +85° C ambient temperature
  • Supports a wide range of video and graphics modes including VGA, SVGA, XGA, SXGA, SXGA+, NTSC, PAL, SDTV, and HDTV up to 1080I or 720P
  • Internal PLL requires no external loop filter
  • Selectable rising or falling clock edge for data alignment
  • Compatible with Spread Spectrum clock source
  • Reduced LVDS output voltage swing mode selectable) to minimize EMI
  • CMOS/TTL data inputs can be configured for reduced input voltage swing
  • Single 3.3 V supply
  • Low power consumption CMOS design
  • Power down mode
  • 64-pin TQFP lead free package Block Diagram TA+ Parallel to Serial TA0-6 TA- TB+ TB- TC+ TC- TD+ TD- TE+ TE- PLL TB0-6 TC0-6 TE0-6 CLKIN (8 to 135 MHz) /PWDN TD0-6 RS R/F TCLK+ TCLK-

TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO V103A Pin Assignment TD5 GND 64-pin TQFP TD6 TE0 TE2 VCC TE3 TE1 TE4 GND TE5 CLKIN /PWDN PLLGND PLLVCC TE6 TA0 TA2 TA1 TA3 RS TB2 TA4 TA5 GND TA6 TB0 TB1 TB3 TB4 GND TB5 LVDSGND TE+ TE- TD+ TD- TCLK+ TCLK- TC+ TC- LVDSVCC TB+ LVDSGND LVDSGND TA- TB- TA+ TB6 TC0 VCC TC1 TC2 TC3 TC4 GND TC5 TC6 TD0 R/F TD1 TD2 TD3 TD4

TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO V103A Pin Descriptions RS Input Voltage Configuration to set LVDS Output Swing and Data Input Swing Note 1: Refer to DC Electrical Characteristics. Pin Number Pin Name Pin Type Pin Description 30, 31 TA+, TA- LVDS OUT LVDS Serial Data Output Pairs 28, 29 TB+, TB- 24, 25 TC+, TC- 20, 21 TD+, TD- 18, 19 TE+, TE- 22, 23 TCLK+, TCLK- LVDS OUT LVDS Reference Clock Output Pair 33, 34, 35, 36, 37, 38, 40 TA0 ~ TA6 IN CMOS/TTL (or small signal) Data Bit Inputs 41, 42, 44, 45, 46, 48, 49 TB0 ~ TB6 50, 52, 53, 54, 55, 57, 58 TC0 ~ TC6 59, 61, 62, 63, 64, 1, 3 TD0 ~ TD6 4, 5, 6, 8, 9, 11, TE0 ~ TE6 13 /PWDN IN High: Normal device operation Low: Power down; all outputs become high impedance

43 RS IN Voltage level on this pin sets LVDS output swing voltage and data input

swing voltage; refer to the table at the bottom of this page. 60 R/F IN Input Clock triggering edge select. High: Rising edge; Low: Falling edge. 51, 7 VCC Power Power supply pins for TTL inputs and digital circuitry. 12 CLKIN IN Clock Input. 2, 10, 39, 47, GND Ground Ground pins for TTL inputs and digital circuitry. 27 LVDSVCC Power Power supply pins for LVDS outputs. 17, 26, 32 LVDSGND Ground Ground pins for LVDS outputs. 15 PLLVCC Power Power supply pin for PLL circuitry. 14 PLLGND Ground Ground pin for PLL circuitry. RS Input Voltage LVDS Output Swing CMOS/TTL Input Configuration (Input Voltage Swing) VCC 350 mV Standard Configuration 1 0.6 ~ 1.4 V (VREF1) 350 mV Small Input Swing Configuration 1 GND 200 mV Standard Configuration 1

TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO V103A External Components Decoupling capacitors should be used for all power pins. The V103A requires no other external components. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the V103A. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VCC -0.3 V to +4.0 V CMOS/TTL Input Voltage -0.3 V to VCC+0.3 V CMOS/TTL Output Voltage -0.3 V to VCC+0.3 V LVDS Driver Output Voltage -0.3 V to VCC+0.3 V Storage Temperature -55 to +150°C Junction Temperature 120°C Soldering Temperature (10 seconds) 260°C Maximum Power Dissipation @ 25°C 1.0 W Parameter Min. Typ. Max. Units Ambient Operating Temperature -20 +85 °C Power Supply Voltage (measured in respect to GND) +3.0 +3.3 +3.6 V

TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO V103A VDD=3.3 V ±10%, Ambient temperature -20 to +85°C Parameter Symbol Conditions Min. Typ. Max. Units CMOS/TTL Inputs, Standard Configuration Input High Voltage V IH RS=VCC or GND 2.00 VCC V Input Low Voltage VIL RS=VCC or GND GND 0.80 V Input Current IINC 0V<VIN<VCC ±10 µA CMOS/TTL Inputs, Small Input Swing Configuration Max Input Swing Voltage V DDQ VREF = VRS = VDDQ/2 1.2 2.8 V Input Reference Voltage into pin RS V REF VDDQ/2 V High Level Input Voltage (for small input swing condition) VSH

2 VREF=VDDQ/2 V DDQ/2

+0.1V V Low Level Input Voltage (for small input swing condition) V SL

2 VREF=VDDQ/2 VDDQ/2

-0.1V V Note 1: VDDQ voltage defines the max voltage of the small swing input and is not an actual input into the device. Note 2: Small input swing voltage is applied to TA[6:0], TB[6:0], TC[6:0], TD[6:0], TE[6:0], and CLKIN. LVDS Transmitter DC Specifications Differential Output Voltage, RL = 100Ω VOD Normal swing RS = VCC 250 350 450 mV Reduced swing RS = GND 100 200 300 mV Change in V OD Between Complimentary Output States DVOD RL = 100Ω 35 mV Common Mode Voltage V OC 1.125 1.250 1.375 V Change in VOC Between Complimentary Output States DVOC 35 mV Output Short Circuit Current I OS VOUT = 0V, RL = 100Ω -24 mA Output Tri-State Current I OZ /PWDN = 0V, V OUT = 0V to VCC ±10 µA Supply Current Transmitter Supply Current I TCCG RL = 100Ω, CL=5 pF, VCC = 3.3 V, RS = VCC Gray Scale Pattern f = 85 MHz 58 64 mA f =135 MHz 70 76 mA RL = 100Ω, CL=5 pF, VCC = 3.3 V, RS = GND Gray Scale Pattern f = 85 MHz 44 50 mA f =135 MHz 56 62 mA Transmitter Supply Current I TCCW RL = 100Ω, CL = 5 pF, VCC = 3.3 V, RS = VCC Worst Case Pattern f = 85 MHz 69 75 mA f =135 MHz 87 93 mA RL = 100Ω, CL= 5 pF, VCC = 3.3 V, RS = GND Worst Case Pattern f = 85 MHz 55 61 mA f =135 MHz 73 79 mA Transmitter Power Down Supply Current I TCCS /PWDN = L 10 µA

TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO V103A Gray Scale Pattern Worst Case Pattern CLKIN Tx 0 Tx 1 Tx 2 Tx 3 Tx 4 Tx 5 Tx 6 x = A, B, C, D, E CLKIN Tx 0 Tx 1 Tx 2 Tx 3 Tx 4 Tx 5 Tx 6 x = A, B, C, D, E

TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO V103A VDD=3.3 V ±10%, Ambient temperature -20 to +85°C Thermal Characteristics Parameter Symbol Min. Typ. Max. Units Switching Characteristics CLK IN Transition Time t TCIT 5n s CLK IN Period t TCP 7.4 125.0 ns CLK IN High Time tTCH 0.35tTCP 0.5tTCP 0.65tTCP ns CLK IN Low Time t TCL 0.35tTCP 0.5tTCP 0.65tTCP ns CLK IN to TCLK± Delay t TCD 3tTCP ns TTL Data Setup to CLK IN t TS 2.5 ns TTL Data Hold from CLK IN t TH 0n s LVDS Transition Time tLVT 0.6 1.5 ns Output Data Position0 t TOP1 -0.2 0.0 0.2 ns Output Data Position1 t TOP0 ns Output Data Position2 t TOP6 ns Output Data Position3 t TOP5 ns Output Data Position4 t TOP4 ns Output Data Position5 t TOP3 ns Output Data Position6 t TOP2 ns Phase Lock Loop Set t TPLL 10.0 ms Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 53 °C/W θJA 1 m/s air flow 40 °C/W θJA 3 m/s air flow 33 °C/W Thermal Resistance Junction to Case θJC 8 °C/W -0.2tTCP tTCP +0.2tTCP 2 -0.2tTCP 7 2 tTCP 7 2 +0.2tTCP 3 -0.2tTCP 7 3 tTCP 7 3 +0.2tTCP 4 -0.2tTCP 7 4 tTCP 7 4 +0.2tTCP 5 -0.2tTCP 7 5 tTCP 7 5 +0.2tTCP 6 -0.2tTCP 7 6 tTCP 7 6 +0.2tTCP

TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO V103A AC Timing Diagrams TTL Input tTCIT 5 pF 100 ohms LVDS Output 20% 20% 10% 10% 80% 80% 90% 90% tTCIT tLVT tLVT CLK IN VDIFF = (TA+) – (TA-) TA+ TA- CLK IN VCC/2 tTH tTCL tTS tTCH tTCP VCC/2 VCC/2 VCC/2 VCC/2 tTCD VOC Tx0-Tx6 TCLK+ TCLK- Note: CLK IN: for R/F = GND, denote as solid line. for R/F = VCC, denote as dashed line TTL Inputs

TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO V103A CLK IN tTH tTCL tTS tTCH tTCP tTCD VOC Tx0-Tx6 TCLK+ TCLK- Note: CLK IN: for R/F = GND, denote as solid line. for R/F = VCC, denote as dashed line Small Swing Inputs VREF VREF VDDQ VDDQ GND GND VDDQ/2 V DDQ/2 VDDQ/2 VDDQ/2VDDQ/2 tTOP1 TCLK OUT (Differential) TA6 TA5 TA4 TA3 TA2 TA1 TA0 TB6 TB5 TB4 TB3 TB2 TB1 TB0 TC6 TC5 TC4 TC3 TC2 TC1 TC0 TD6 TD5 TD4 TD3 TD2 TD1 TD0 TE6 TE5 TE4 TE3 TE2 TE1 TE0 LVDS Output VDIFF = 0V VDIFF = 0V TA+/- TB+/- TC+/- TD+/- TE+/- Previous Cycle Next Cycle t TOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2

TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO V103A Phase Lock Loop Set Time VDIFF = 0V /PWDN 3.6 V 3.0 V 2.0 V VCC CLKIN TCLKx+/- tTPLL

TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO V103A Package Outline and Package Dimensions (64-pin TQFP) Package dimensions are kept current with JEDEC Publication No. 95, variation ACD.

Ordering Information

The “LF” part number suffix denotes the device as Lead (Pb) Free and that the device is RoHS compliant. Part / Order Number Marking Shipping Packaging Package Temperature V103AYLF V103AYLF Tray (160 units per tray) 64-pin TQFP -20 to +85 ° C V103AYLFT V103AYLF Tape and Reel 64-pin TQFP -20 to +85 ° C SYMBOL MIN/MAX N6 4 A- - / 1 . 2 0 A1 0.05 / 0.15 A2 0.95 / 1.05 b 0.17 / 0.27 c 0.09 / 0.20 D 12.00 BASIC D1 10.00 BASIC D2 7.50 Ref. E 12.00 BASIC E1 10.00 BASIC E2 7.50 Ref. e 0.50 BASIC L 0.45 / 0.75 θ 0° / 7° ccc -- / 0.08 D3&E3 - ALL DIMENSIONS ARE IN MILLIMETERS.

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