UPSD3200 STMICROELECTRONICS | Alldatasheet

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Technical content

Complete data available onData-on-Disc CD-ROM or atwww.st.com. mable (ISP) via a JTAG ISP interface. Figure 1. Packages

µPSD3200 FAMILY SUMMARY DESCRIPTION n Dual bank Flash memories – Concurrent operation, read from memory one while erasing and writing the other. In-Appli- cation Programming (IAP) for remote updates – Large 128 KByte or 256 KByte main Flash memory for application code, operating sys- tems, or bit maps for graphic user interfaces – Large 32 KByte secondary Flash memory di- vided in small sectors. Eliminate external EE- PROM with software EEPROM emulation – Secondary Flash memory is large enough for sophisticated communication protocol (USB) during IAP while continuing critical system tasks n Large SRAM with battery back-up option – 8 KByte SRAM for RTOS, high-level languag- es, communication buffers, and stacks n Programmable Decode PLD for flexible address mapping of all memories – Place individual Flash and SRAM sectors on any address boundary – Built-in page register breaks restrictive 8032 limit of 64 KByte address space – Special register swaps Flash memory seg- ments between 8032 “program” space and “data” space for efficient In-Application Pro- gramming n High-speed clock standard 8032 core (12-cycle) – 40 MHz operation at 5 V, 24 MHz at 3.3 V – Two UARTs with independent baud rate, three 16-bit Timer/Counters and two External Interrupts n USB Interface (µPSD3234A-40U6 only) – Supports USB 1.1 Slow Mode (1.5 Mbit/s) – Control endpoint 0 and interrupt endpoints 1 and 2 n I2C interface for peripheral connections – Capable of master or slave operation n Five Pulse Width Modulator (PWM) channels – Four 8-bit PWM units – One 16-bit PWM unit n Standalone Display Data Channel (DDC) – For use in monitor, projector, and TV applica- tions – Compliant with VESA standards DDC1 and DDC2B – Eliminate external DDC PROM n Six I/O ports with up to 50 I/O pins – Multifunction I/O: GPIO, DDC, I2C, PWM, PLD I/O, supervisor, and JTAG – Eliminates need for external latches and logic n 3000 gate PLD with 16 macrocells – Create glue logic, state machines, delays, etc. – Eliminate external PALs, PLDs, and 74HCxx – Simple PSDsoft Express software ...Free n Supervisor functions – Generates reset upon low voltage or watch- dog time-out. Eliminate external supervisor device – Reset In pin n In-System Programming (ISP) via JTAG – Program entire chip in 10 - 25 seconds with no involvement of 8032 – Allows efficient manufacturing, easy product testing, and Just-In-Time inventory – Eliminate sockets and pre-programmed parts – Program with FlashLINK TM cable and any PC n Content Security – Programmable Security Bit blocks access of device programmers and readers n Zero-Power Technology – Memories and PLD automatically reach standby current between input changes n Packages – 52-pin TQFP – 80-pin TQFP: allows access to 8032 address/ data/control signals for connecting to external peripherals

µPSD3200 FAMILY Figure 2.µPSD3200 Family Functional Modules AI06619 Channel ADC 1Mb or 2Mb Main FlashDecode PLD 64Kb SRAM CPLD - 16 MACROCELLSJTAG ISP Port 1Port 3

2 UARTS

3 Timer /

256 Byte SRAM

8051 Core

Port 3, UART, Intr, Timers,I2C PSD Internal Bus

8032 Internal Bus

Port 1, Timers and 2nd UART and ADC DDC w/ 256 Byte SRAM PWM

5 Channels

Port A & B, PLD I/O and GPIO Port D GPIO Port C, JTAG, PLD I/O and GPIO VCC, GND, XTAL 256Kb Secondary Flash Dedicated Pins I2C Port 0, 2 Ext. Bus Reset Logic LVD & WDT Bus Interface ResetD0-D7A0-A15 RD,PSEN WR,ALE Page Register PSD MODULE MCU MODULE

Table 1. 80-Pin Package Pin Description

  1. Latched Address Out (A0-A7)
  2. Latched Address Out (A0-A7)
  3. SRAM stand by voltage input (VSTBY)
  4. JTAG Interface (TDI, TDO, TMS, TCK, TSTAT,
  5. SRAM battery-on indicator (PC4)
  6. Clock input to PLD and APD
  7. Chip select to PSD Module

Figure 3. TQFP52 Connections

33 VCC

32 XTAL2

31 XTAL1

Figure 4. TQFP80 Connections

  1. USB- needs a pull-up resistor (see the description of the USB function)

50 VCC

49 XTAL2

48 XTAL1

Table 2. Ordering Information Scheme

µPSD3200 FAMILY Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners  2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.