UPSD3213A-40U6T

UPSD323X STMICROELECTRONICS | Alldatasheet

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Technical content

µPSD323X TABLE OF CONTENTS

µ PSD323X

µPSD323X

µ PSD323X

µPSD323X

µ PSD323X

µPSD323X

µ PSD323X PSD MODULE Example, Typ. Power Calculation at V CC = 5.0V (Turbo Mode Off) (Table 107.). 144

µPSD323X V

µ PSD323X SUMMARY DESCRIPTION n Dual bank Flash memories – Concurrent operation, read from memory while erasing and writing the other. In-Appli- cation Programming (IAP) for remote updates – Large 128KByte or 256KByte main Flash memory for application code, operating sys- tems, or bit maps for graphic user interfaces – Large 32KByte secondary Flash memory di- vided in small sectors. Eliminate external EE- PROM with software EEPROM emulation – Secondary Flash memory is large enough for sophisticated communication protocol (USB) during IAP while continuing critical system tasks n Large SRAM with battery back-up option – 8KByte SRAM for RTOS, high-level languag- es, communication buffers, and stacks n Programmable Decode PLD for flexible address mapping of all memories – Place individual Flash and SRAM sectors on any address boundary – Built-in page register breaks restrictive 8032 limit of 64KByte address space – Special register swaps Flash memory seg- ments between 8032 “program” space and “data” space for efficient In-Application Pro- gramming n High-speed clock standard 8032 core (12-cycle) – 40MHz operation at 5V, 24MHz at 3.3V – 2 UARTs with independent baud rate, three 16-bit Timer/Counters and two External Inter- rupts n USB Interface (µPSD3234A-40 only) – Supports USB 1.1 Slow Mode (1.5Mbit/s) – Control endpoint 0 and interrupt endpoints 1 and 2 n I2C interface for peripheral connections – Capable of master or slave operation n 5 Pulse Width Modulator (PWM) channels – Four 8-bit PWM units – One 8-bit PWM unit with programmable peri- od n 4-channel, 8-bit Analog-to-Digital Converter (ADC) with analog supply voltage (V REF ) n Standalone Display Data Channel (DDC) – For use in monitor, projector, and TV applica- tions – Compliant with VESA standards DDC1 and DDC2B – Eliminate external DDC PROM n Six I/O ports with up to 50 I/O pins – Multifunction I/O: GPIO, DDC, I2C, PWM, PLD I/O, supervisor, and JTAG – Eliminates need for external latches and logic n 3000 gate PLD with 16 macrocells – Create glue logic, state machines, delays, etc. – Eliminate external PALs, PLDs, and 74HCxx – Simple PSDsoft Express software ...Free n Supervisor functions – Generates reset upon low voltage or watch- dog time-out. Eliminate external supervisor device – RESET Input pin; Reset output via PLD n In-System Programming (ISP) via JTAG – Program entire chip in 10 - 25 seconds with no involvement of 8032 – Allows efficient manufacturing, easy product testing, and Just-In-Time inventory – Eliminate sockets and pre-programmed parts – Program with FlashLINK TM cable and any PC n Content Security – Programmable Security Bit blocks access of device programmers and readers n Zero-Power Technology – Memories and PLD automatically reach standby current between input changes n Packages – 52-pin TQFP – 80-pin TQFP: allows access to 8032 address/ data/control signals for connecting to external peripherals

Figure 3. TQFP52 Connections Note: 1. Pull-up resistor required on pin 5 (2kΩ for 3V devices, 7.5kΩ for 5V devices) for all 52-pin devices, with or without USB function.

33 VCC

32 XTAL2

31 XTAL1

Figure 4. TQFP80 Connections

1. Pull-up resistor required on pin 8 (2kΩ for 3V devices, 7.5kΩ for 5V devices) for all 82-pin devices, with or without USB function.

50 VCC

49 XTAL2

48 XTAL1

Table 2. 80-Pin Package Pin Description

µ PSD323X P4.3 PWM0 27 I/O General I/O port pin 8-bit Pulse Width Modulation output 0 P4.4 PWM1 25 I/O General I/O port pin 8-bit Pulse Width Modulation output 1 P4.5 PWM2 23 I/O General I/O port pin 8-bit Pulse Width Modulation output 2 P4.6 PWM3 19 I/O General I/O port pin 8-bit Pulse Width Modulation output 3 P4.7 PWM4 18 I/O General I/O port pin Programmable 8-bit Pulse Width modulation output 4 USB- 8 I/O USB Pin Pull-up resistor required (2kΩ for 3V devices, 7.5kΩ for 5V devices) for all devices, with or without USB function. USB+ 10 I/O USB Pin AVREF 70 O Reference Voltage input for ADC RD_ 65 O READ signal, external bus WR_ 62 O WRITE signal, external bus PSEN_ 63 O PSEN signal, external bus ALE 4 O Address Latch signal, external bus RESET_ 68 I Active low RESET input XTAL1 48 I Oscillator input pin for system clock XTAL2 49 O Oscillator output pin for system clock PA0 35 I/O General I/O port pin 1. PLD Macro-cell outputs 2. PLD inputs 3. Latched Address Out (A0-A7) 4. Peripheral I/O Mode PA1 34 I/O General I/O port pin PA2 32 I/O General I/O port pin PA3 28 I/O General I/O port pin PA4 26 I/O General I/O port pin PA5 24 I/O General I/O port pin PA6 22 I/O General I/O port pin PA7 21 I/O General I/O port pin Port Pin Signal Name Pin No. In/Out Function Basic Alternate

µPSD323X

52 PIN PACKAGE I/O PORT

The 52-pin package members of theµPSD323X Devices have the same port pins as those of the 80-pin package except: n Port 0 (P0.0-P0.7, external address/data bus AD0-AD7) n Port 2 (P2.0-P2.3, external address bus A8- A11) n Port A (PA0-PA7) n Port D (PD2) n Bus control signal (RD,WR,PSEN,ALE) Pin 5 requires a pull-up resistor (2kΩ for 3V de- vices, 7.5kΩ for 5V devices) for all devices, with or without USB function. PB0 80 I/O General I/O port pin 1. PLD Macro-cell outputs 2. PLD inputs 3. Latched Address Out (A0-A7) PB1 78 I/O General I/O port pin PB2 76 I/O General I/O port pin PB3 74 I/O General I/O port pin PB4 73 I/O General I/O port pin PB5 72 I/O General I/O port pin PB6 67 I/O General I/O port pin PB7 66 I/O General I/O port pin PC0 TMS 20 I JTAG pin 1. PLD Macro-cell outputs 2. PLD inputs 3. SRAM stand by voltage input STBY ) 4. SRAM battery-on indicator (PC4) 5. JTAG pins are dedicated pins PC1 TCK 16 I JTAG pin PC2 VSTBY 15 I/O General I/O port pin PC3 TSTAT 14 I/O General I/O port pin PC4 TERR 9 I/O General I/O port pin PC5 TDI 7 I JTAG pin PC6 TDO 6 O JTAG pin PC7 5 I/O General I/O port pin PD1 CLKIN 3 I/O General I/O port pin 1. PLD I/O 2. Clock input to PLD and APD PD2 CSI 1 I/O General I/O port pin 1. PLD I/O 2. Chip select to PSD Module Vcc 12 Vcc 50 GND 13 GND 29 GND 69 NC 11 NC 17 NC 71 Port Pin Signal Name Pin No. In/Out Function Basic Alternate

Figure 9. PSW (Program Status Word) Register memory update or programming. is assigned a fixed location in Program Memory. terrupt locations, if other interrupts are in use. and 8K bytes (XRAM-PSD) in the PSD Module. locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. Figure 10. Interrupt Location of Program data to be retained in the event of a power lost. The battery is connected to the Port C PC2 pin.

8 Bytes

• Interrupt Location 0003h 000Bh 0013h 008Bh

time by the two bank select bits in the PSW. ed for reading look-up tables in Program memory. ing the Accumulator data to the base pointer. Figure 13. Indexed Addressing B register holding the bits that were shifted out. operation, to ensure that the result is also in BCD.

Table 4. Arithmetic Instructions will leave the Accumulator holding 00010001B. the <byte> operand are listed in Table 5. push it onto the stack in the service routine. right rotation, the LSB rolls into the MSB position. Accumulator, and the ones digit to the low nibble.

Table 5. Logical Instructions

(DPTR) for look-up tables in Program Memory. mulator and ad-dressed byte to exchange data. number one digit, using the XCHD instruction. Table 6. Data Transfer Instructions that Access Internal Data Memory Space

0s, the lost digit is moved to the Accumulator. Table 7. Shifting a BCD Number Two Digits to Table 8. Shifting a BCD Number Two Digits to Table 9. Shifting a BCD Number One Digit to the Right

Memory. Only indirect addressing can be used. is set up to point to the beginning of the table. PC contains the address of the RET instruction. Table 10. Data Transfer Instruction that Access External Data Memory Space Table 11. Lookup Table READ Instruction

any amount of byte-oriented software. the PSW register, which is bit-addressable. C instruction is jumped over. to the bit-test instructions. Table 12. Boolean Instructions arithmetic if the jump is executed.

which way the jump is en-coded. relative to the instruction following the SJMP. where in the 64K Program Memory space. bits in the PC. The high 5 bits stay the same. 2K block as the instruction following the AJMP. of range” message is written into the List file. does not care which way the address is encoded. then the RETI is functionally identical to RET. Table 13. Unconditional Jump Instructions

2Ah. The initial data in R1 was 2Eh. states and phases for various kinds of instructions. and the Program Counter is not incremented. the end of State 6 of this machine cycle. is the only time program retrievals are skipped. tion is shown in Figure 14, page 30 (d). Table 14. Conditional Jump Instructions

Figure 14. State Sequence inµPSD323X Devices

µ PSD323X µPSD3200 HARDWARE DESCRIPTION The µPSD323X Devices has a modular architec- ture with two main functional modules: the MCU Module and the PSD Module. The MCU Module consists of a standard 8032 core, peripherals and other system supporting functions. The PSD Mod- ule provides configurable Program and Data mem- ories to the 8032 CPU core. In addition, it has its own set of I/O ports and a PLD with 16 macrocells for general logic implementation. Ports A,B,C, and D are general purpose programmable I/O ports that have a port architecture which is different from Ports 0-4 in the MCU Module. The PSD Module communicates with the CPU Core through the internal address, data bus (A0- A15, D0-D7) and control signals (RD_, WR_, PSEN_ , ALE, RESET_). The user defines the De- coding PLD in the PSDsoft Development Tool and can map the resources in the PSD Module to any program or data address space. Figure 15.µPSD323X Devices Functional Modules AI06619C Channel ADC 1Mb or 2Mb Main FlashDecode PLD 64Kb SRAM CPLD - 16 MACROCELLSJTAG ISP Port 1Port 3

2 UARTs

3 Timer /

256 Byte SRAM

8032 Core

Port 3, UART, Intr, Timers,I2C PSD Internal Bus

8032 Internal Bus

Port 1, Timers and 2nd UART and ADC DDC w/ 256 Byte SRAM PWM Channels Port 4 PWM and DDC Dedicated USB Pins Port A & B, PLD I/O and GPIO Port D GPIO Port C, JTAG, PLD I/O and GPIO VCC, GND, XTAL 256Kb Secondary Flash Dedicated Pins I2C Port 0, 2 Ext. Bus Reset Logic LVD & WDT Bus Interface ResetD0-D7 A0-A15 RD,PSEN WR,ALE Page Register PSD MODULE MCU MODULE

Table 15. SFR Memory Map

98 SCON SBUF SCON2 SBUF2 9F

1 P1SFS P3SFS P4SFS ASCL ADAT ACON 97

88 TCON 1 TMOD TL0 TL1 TH0 TH1 8F

80 P0 1 SP DPL DPH PCON 87

Table 16. List of all SFR

80 P0 FF Port 0

81 SP 07 Stack Ptr

82 DPL 00 Data Ptr Low

83 DPH 00 Data Ptr

87 PCON SMOD SMOD1 LVREN ADSFINT RCLK1 TCLK1 PD IDLE 00 Power Ctrl

88 TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 Timer / Cntr

89 TMOD Gate C/T M1 M0 Gate C/T M1 M0 00

90 P1 FF Port 1

91 P1SFS P1S7 P1S6 P1S5 P1S4 00 Port 1 Select

93 P3SFS P3S7 P3S6 00 Port 3 Select

94 P4SFS P4S7 P4S6 P4S5 P4S4 P4S3 P4S2 P4S1 P4S0 00 Port 4 Select

95 ASCL 00

96 ADA T ADAT7 ADAT6 ADAT5 ADAT4 ADA T3 ADAT2 ADAT1 ADAT0 00 ADC Data

97 ACON ADEN ADS1 ADS0 ADST ADSF 00 ADC Control

98 SCON SM0 SM1 SM2 REN TB8 RB8 TI RI 00

99 SBUF 00 Serial Buffer

µPSD323X A2 PWM0 00 PWM0 Output Duty Cycle A3 PWM1 00 PWM1 Output Duty Cycle A4 PWM2 00 PWM2 Output Duty Cycle A5 PWM3 00 PWM3 Output Duty Cycle A6 WDRST 00 Watch Dog Reset A7 IEA EDDC ES2 EI2C EUSB 00 Interrupt Enable (2nd) A8 IE EA - ET2 ES ET1 EX1 ET0 EX0 00 Interrupt Enable AA PWM4P 00 PWM 4 Period AB PWM4W 00 PWM 4 Pulse Width AE WDKEY 00 Watch Dog Key Register B0 P3 FF Port 3 B1 PSCL0L 00 Prescaler 0 Low (8-bit) B2 PSCL0H 00 Prescaler 0 High (8-bit) B3 PSCL1L 00 Prescaler 1 Low (8-bit) B4 PSCL1H 00 Prescaler 1 High (8-bit) B7 IPA PDDC PS2 PI2C PUSB 00 Interrupt Priority (2nd) B8 IP PT2 PS PT1 PX1 PT0 PX0 00 Interrupt Priority C0 P4 FF New Port 4 C8 T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00 Timer 2 Control C9 T2MOD DCEN 00 Timer 2 Mode SFR Addr Reg Name Bit Register Name Reset Value Comments 7 6543210

µ PSD323X CA RCAP2L 00 Timer 2 Reload low CB RCAP2H 00 Timer 2 Reload High CC TL2 00 Timer 2 Low byte CD TH2 00 Timer 2 High byte D0 PSW CY AC FO RS1 RS0 OV P 00 Program Status Word D1 S1SETUP 00 DDC I2C (S1) Setup D2 S2SETUP 00 I2C (S2) Setup D4 RAMBUF XX DDC Ram Buffer D5 DDCDA T 00 DDC Data xmit register D6 DDCADR 00 Addr pointer register D7 DDCCON — EX_DA T SWENB DDC_AX DDCINT DDC1EN SWHINT M0 00 DDC Control Register D8 S1CON CR2 ENI1 STA STO ADDR AA CR1 CR0 00 DDC I2C Control Reg D9 S1STA GC Stop Intr TX-Md Bbusy Blost ACK_R SLV 00 DDC I2C Status DA S1DAT 00 Data Hold Register DB S1ADR 00 DDC I2C address DC S2CON CR2 EN1 STA STO ADDR AA CR1 CR0 00 I2C Bus Control Reg DD S2STA GC Stop Intr TX-Md Bbusy Blost ACK_R SLV 00 I2C Bus Status DE S2DAT 00 Data Hold Register DF S2ADR 00 I2C address E0 ACC 00 Accumulator E1 USCL 00 8-bit Prescaler for USB logic Data Xmit SFR Addr Reg Name Bit Register Name Reset Value Comments 7 6543210

µPSD323X Data Xmit E8 UISTA SUSPND — RSTF TXD0F RXD0F RXD1F EOPF RESUMF 00 USB Interrupt Status E9 UIEN SUSPNDI E RSTE RSTFIE TXD0IE RXD0IE TXD1IE EOPIE RESUMI E 00 USB Interrupt Enable EA UCON0 TSEQ0 STALL0 TX0E RX0E TP0SIZ3 TP0SiZ2 TP0SIZ1 TP0SIZ0 00 USB Endpt0 Xmit Control EB UCON1 TSEQ1 EP12SEL — FRESUM TP1SIZ3 TP1SiZ2 TP1SIZ1 TP1SIZ0 00 USB Endpt1 Xmit Control EC UCON2 — — — SOUT EP2E EP1E STALL2 STALL1 00 USB Control Register ED USTA RSEQ SETUP IN OUT RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 00 USB Endpt0 Status EE UADR USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 00 USB Address Register Data Recv F0 B 00 B Register SFR Addr Reg Name Bit Register Name Reset Value Comments 7 6543210

Table 17. PSD Module Register Address Offset

00 Data In (Port A) Reads Port pins as input

04 Data Out (Port A) Latched data for output to Port pins, I/O Output Mode 00

Reads the status of the output enable control to the Port pin driver. Bit = 0 indicates pin is in input mode.

01 Data In (Port B)

03 Control (Port B) 00

05 Data Out (Port B) 00

07 Direction (Port B) 00

09 Drive (Port B) 00

10 Data In (Port C)

12 Data Out (Port C) 00

14 Direction (Port C) 00

16 Drive (Port C) 00

18 Input Macrocell

11 Data In (Port D) * * * * * * Only Bit 1 and

13 Data Out (Port D) * * * * * * 00 Only Bit 1 and

15 Direction (Port D) * * * * * * 00 Only Bit 1 and

17 Drive (Port D) * * * * * * 00 Only Bit 1 and

20 Output

µPSD323X Note: (Register address = csiop address + address offset; where csiop address is defined by user in PSDsoft) * indicates bit is not used and need to set to ’0.’

21 Output

22 Mask Macrocells

23 Mask Macrocells

Sec7_ Prot Sec6_ Prot Sec5_ Prot Sec4_ Prot Sec3_ Prot Sec2_ Prot Sec1_ Prot Sec0_ Prot Bit = 1 sector is protected C2 Secondary Flash Protection Security Prot Sec2_ Prot Sec1_ Prot Sec0_ Prot Security Bit = 1 device is secured B0 PMMR0 * * PLD Mcells clk PLD array- clk PLD Turbo * APD enable *0 0 Control PLD power consumption B4 PMMR2 * PLD array WRh PLD arrayAl e PLD array Cntl2 PLD array Cntl1 PLD array Cntl0 0 0 Blocking inputs to PLD array E0 Page 00 Page Register E2 VM Periph- mode FL_da ta Boot_ data FL_co de Boot_c ode SR_co de Configure

8032 Program

µ PSD323X INTERRUPT SYSTEM There are interrupt requests from 10 sources as follows. n INT0 external interrupt n 2nd USART interrupt n Timer0 interrupt n I2C interrupt n INT1 external interrupt (or ADC interrupt) n DDC interrupt n Timer1 interrupt n USB interrupt n USART interrupt n Timer2 interrupt External Int0 n The INT0 can be either level-active or transition- active depending on Bit IT0 in register TCON. The flag that actually generates this interrupt is Bit IE0 in TCON. n When an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated. n If the interrupt was level activated then the interrupt request flag remains set until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. Timer 0 and 1 Interrupts n Timer0 and Timer1 interrupts are generated by TF0 and TF1 which are set by an overflow of their respective Timer/Counter registers (except for Timer0 in Mode 3). n These flags are cleared by the internal hardware when the interrupt is serviced. Timer 2 Interrupt n Timer2 interrupt is generated by TF2 which is set by an overflow of Timer2. This flag has to be cleared by the software - not by hardware. n It is also generated by the T2EX signal (timer 2 external interrupt P1.1) which is controlled by EXEN2 and EXF2 Bits in the T2CON register. This is the definition of Timer 2 as per 90C320 definition. I 2C Interrupt n The interrupt of the I2C is generated by Bit INTR in the register S2STA. n This flag is cleared by hardware. External Int1 n The INT1 can be either level active or transition active depending on Bit IT1 in register TCON. The flag that actually generates this interrupt is Bit IE1 in TCON. n When an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated. n If the interrupt was level activated then the interrupt request flag remains set until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. n The ADC can take over the External INT1 to generate an interrupt on conversion being completed DDC Interrupt n The DDC interrupt is generated either by Bit INTR in the S1STA register for DC2B protocol or by Bit DDC interrupt in the DDCCON register for DDC1 protocol or by Bit SWHINT Bit in the DDCCON register when DDC protocol is changed from DDC1 to DDC2. n Flags except the INTR have to be cleared by the software. INTR flag is cleared by hardware. USB Interrupt n The USB interrupt is generated when endpoint0 has transmitted a packet or received a packet, when endpoint1 or endpoint2 has transmitted a packet, when the suspend or resume state is detected and every EOP received. n When the USB interrupt is generated, the corresponding request flag must be cleared by software. The interrupt service routine will have to check the various USB registers to determine the source and clear the corresponding flag. n Please see the dedicated interrupt control registers for the USB peripheral for more information.

(receive interrupt) OR TI (transmit interrupt). Figure 16. Interrupt System

Table 18. SFR Register sequence determines which request is serviced. Table 19. Priority Levels Table 20. Description of the IE Bits

5 ET2 Enable Timer2 interrupt

4 ES Enable USART interrupt

3 ET1 Enable Timer1 interrupt

2 EX1 Enable external interrupt (Int1)

1 ET0 Enable Timer0 interrupt

0 EX0 Enable external interrupt (Int0)

Table 21. Description of the IEA Bits Table 22. Description of the IP Bits Table 23. Description of the IPA Bits

7 EDDC Enable DDC interrupt

4 ES2 Enable 2nd USART interrupt

1 EI2C Enable I C interrupt

0 EUSB Enable USB interrupt

5 PT2 Timer2 interrupt priority level

4 PS USART interrupt priority level

3 PT1 Timer1 interrupt priority level

2 PX1 External interrupt (Int1) priority level

1 PT0 Timer0 interrupt priority level

0 PX0 External interrupt (Int0) priority level

7 PDDC DDC interrupt priority level

4 PS2 2nd USART interrupt priority level

1 PI2C I C interrupt priority level

0 PUSB USB interrupt priority level

level is already in progress. in the execution of the instruction in progress. membered. Every polling cycle is new. tored to as shown in Table 24. continues from where it left off. Table 24. Vector Addresses

consumption are implemented. The following Functions are Switched Off. Table 25. Power-Saving Mode Power Consumption software via the PCON register. Table 26. Pin Status During Idle and Power-down Mode Table 27. Description of the PCON Bits

7 SMOD Double baud data rate bit UART

6 SMOD1 Double baud data rate bit 2nd UART

5 LVREN LVR disable bit (active High)

4 ADSFINT Enable ADC interrupt

3 RCLK1

1 Received clock flag (UART 2)

2 TCLK1 1 Transmit clock flag (UART 2)

1 PD Activate Power-down Mode (High enable)

0 IDL Activate Idle Mode (High enable)

µ PSD323X Idle Mode The instruction that sets PCON.0 is the last in- struction executed in the normal operating mode before Idle Mode is activated. Once in the Idle Mode, the CPU status is preserved in its entirety: Stack pointer, Program counter, Program status word, Accumulator, RAM and All other registers maintain their data during Idle Mode. There are three ways to terminate the Idle Mode. n Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware terminating Idle mode. The interrupt is serviced, and following return from interrupt instruction RETI, the next instruction to be executed will be the one which follows the instruction that wrote a logic ’1’ to PCON.0. n External hardware reset: the hardware reset is required to be active for two machine cycle to complete the RESET operation. n Internal reset: the microcontroller restarts after 3 machine cycles in all cases. Power-Down Mode The instruction that sets PCON.1 is the last exe- cuted prior to going into the Power-down Mode. Once in Power-down Mode, the oscillator is stopped. The contents of the on-chip RAM and the Special Function Register are preserved. The Power-down Mode can be terminated by an external RESET.

not used may be used as normal bi-directional I/O. P1.3 are default to GPIO after reset. Table 28. I/O Port Functions Table 29. P1SFS (91H) Table 30. P3SFS (93H) Table 31. P4SFS (94H)

Figure 17. PORT Type and Description (Part 1)

Figure 18. PORT Type and Description (Part 2)

µPSD323X Each RESET source will cause an internal reset signal active. The CPU responds by executing an internal reset and puts the internal registers in a defined state. This internal reset is also routed as an active low reset input to the PSD Module. External Reset The RESET pin is connected to a Schmitt trigger for noise reduction. A RESET is accomplished by holding the RESET pin LOW for at least 1ms at power up while the oscillator is running. Refer to AC spec on other RESET timing requirements. Low V DD Voltage Reset An internal reset is generated by the LVR circuit when the VDD drops below the reset threshold. Af- ter VDD reaching back up to the reset threshold, the RESET signal will remain asserted for 10ms before it is released. On initial power-up the LVR is enabled (default). After power-up the LVR can be disabled via the LVREN Bit in the PCON Reg- ister. Note:The LVR logic is still functional in both the Idle and Power-down Modes. The reset threshold: n 5V operation: 4V +/- 0.25V n 3.3V operation: 2.5V +/-0.2V This logic supports approximately 0.1V of hystere- sis and 1µs noise-cancelling delay. Watchdog Timer Overflow The Watchdog timer generates an internal reset when its 22-bit counter overflows. See Watchdog Timer section for details. USB Reset The USB reset is generated by a detection on the USB bus RESET signal. A single-end zero on its upstream port for 4 to 8 times will set RSTF Bit in UISTA register. If Bit 6 (RSTE) of the UIEN Regis- ter is set, the detection will also generate the RESET signal to reset the CPU and other periph- erals in the MCU.

venting the processor running out of control. SFR and Watchdog Key Register (WDKEY). concerned with servicing it. value between 00-7EH to the WDRST register. generate a flexible Watchdog time out period. Writing a “00” to WDRST clears the counter. the function of the watchdog timer is needed. Table 32. Watchdog Timer Key Register (WDKEY: 0AEH) Table 33. Description of the WDKEY Bits Enable or disable watchdog timer.

The RESET pulse width is Tfosc x 12 x 215. Figure 21. RESET Pulse Width Table 34. Watchdog Timer Clear Register (WDRST: 0A6H) Table 35. Description of the WDRST Bits Note: The Watchdog Timer (WDT) is enabled at power-up or reset and must be served or disabled. To reset watchdog timer, write any value beteen 00h and 7Eh to this register. This value is loaded to the 7 most significant bits of the 22-bit counter.

Counter registers: Timer 0, Timer 1 and Timer2. 1/6 of the CPU clock frequency. erating modes are de-scribed in the following text. Table 36. Control Register (TCON) Table 37. Description of the TCON Bits

Mode 0 operation as it applies to Timer1. put /INT1, to facilitate pulse width measurements). run flag does not clear the registers. that the Timer register is being run with all 16 bits. Table 38. TMOD Register (TMOD) Table 39. Description of the TMOD Bits

7 Gate

6 C/T Timer or Counter selector, cleared for timer operation (input from internal system clock);

5 M1 (M1,M0)=(0,0): 13-bit Timer/Counter, TH1, with TL1 as 5-bit prescaler

(M1,M0)=(0,1): 16-bit Timer/Counter. TH1 and TL1 are cascaded. There is no prescaler.

3 Gate

2 C/T Timer or Counter selector, cleared for timer operation (input from internal system clock);

1 M1 (M1,M0)=(0,0): 13-bit Timer/Counter, TH0, with TL0 as 5-bit prescaler

(M1,M0)=(0,1): 16-bit Timer/Counter. TH0 and TL0 are cascaded. There is no prescaler.

Figure 24. Timer/Counter Mode 3: Two 8-bit Counters Mode 3. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. in any application not requiring an interrupt. lected by bits in the T2CON as shown in Table 41. ture Mode is illustrated in Figure 25. tions, which are selected by bit EXEN2 in T2CON.

Table 40. Timer/Counter 2 Control Register (T2CON) Table 41. Description of the T2CON Bits Note: 1. The RCLK1 and TCLK1 Bits in the PCON Register control UART 2, and have the same function as RCLK and TCLK.

5 RCLK 1

4 TCLK

3 EXEN2

a negative transition on T2EX if Timer 2 is not being used to clock the serial port.

0 CP/RL2

Table 42. Timer/Counter2 Operating Modes Figure 25. Timer 2 in Capture Mode

Figure 26. Timer 2 in Auto-Reload Mode

controlled by the SCON and SCON2 registers. at 1/6 the CPU clock frequency. SCON. The baud rate is variable. data bits are received. The 9th one goes into RB8. their business, ignoring the coming data bytes. RB8), and the Serial Port Interrupt Bits (TI and RI). Table 43. Serial Port Control Register (SCON)

Table 44. Description of the SCON Bits

6 SM1

5 SM2

= 1, the baud rate is 1/32 the oscillator frequency. they can be obtained from Timer 1. Counter 2 Control Register (T2CON)). the PCON register configure UART 2. Table 45. Timer 1-Generated Commonly Used Baud Rates

µPSD323X the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the ’1’ that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deac- tivate SEND and set TI. This occurs at the 10th di- vide-by-16 rollover after “WRITE to SBUF.” Reception is initiated by a detected 1-to-0 transi- tion at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been es- tablished. When a transition is detected, the di- vide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its roll-overs with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not ’0,’ the receive circuits are reset and the unit goes back to looking for an-other 1-to- 0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the re- set of the rest of the frame will proceed. As data bits come in from the right, ’1s’ shift out to the left. When the start bit arrives at the left-most position in the shift register (which in Mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generat- ed: 1. R1 = 0, and 2. Either SM2 = 0, or the received Stop Bit = 1. If either of these two conditions is not met, the re- ceived frame is irretrievably lost. If both conditions are met, the Stop Bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD. More About Modes 2 and 3.Eleven bits are transmitted (through TxD), or received (through RxD): a Start Bit (0), 8 data bits (LSB first), a pro- grammable 9th data bit, and a Stop Bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of ’0’ or ’1.’ On receive, the data bit goes into RB8 in SCON. The baud rate is programma- ble to either 1/16 or 1/32 the CPU clock frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1. Figure 31, page 67 and Figure 33, page 68 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The “WRITE to SBUF” signal also loads TB8 into the 9th bit po- sition of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next roll-over in the divide-by- 16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “WRITE to SBUF” signal.) The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a ’1’ (the Stop Bit) into the 9th bit position of the shift register. There-after, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the out-put position of the shift register, then the Stop Bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then de- activate SEND and set TI. This occurs at the 11th divide-by 16 rollover after “WRITE to SUBF.” Reception is initiated by a detected 1-to-0 transi- tion at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been es- tablished. When a transition is detected, the di- vide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of R-D. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not ’0,’ the receive circuits are reset and the unit goes back to looking for an- other 1-to-0 transition. If the Start Bit proves valid, it is shifted into the input shift register, and recep- tion of the rest of the frame will proceed. As data bits come in from the right, ’1s’ shift out to the left. When the Start Bit arrives at the left-most position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following con- ditions are met at the time the final shift pulse is generated:

1. Either SM2 = 0, or the received 9th data bit = 1

into RB8, and the first 8 data bits go into SBUF. a 1-to-0 transition at the RxD input. Figure 27. Serial Port Mode 0, Block Diagram

Figure 34. Serial Port Mode 3, Waveforms

Table 46. ADC SFR Memory Map Table 47. Description of the ACON Bits Table 48. ADC Clock Input

96 ADAT ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2 ADAT1 ADA T0 00 ADC Data

µPSD323X PULSE WIDTH MODULATION (PWM) The PWM block has the following features: n Four-channel, 8-bit PWM unit with 16-bit prescaler n One-channel, 8-bit unit with programmable frequency and pulse width n PWM Output with programmable polarity 4-channel PWM unit (PWM 0-3) The 8-bit counter of a PWM counts module 256 (i.e., from 0 to 255, inclusive). The value held in the 8-bit counter is compared to the contents of the Special Function Register (PWM 0-3) of the corre- sponding PWM. The polarity of the PWM outputs is programmable and selected by the PWML Bit in PWMCON register. Provided the contents of a PWM 0-3 register is greater than the counter val- ue, the corresponding PWM output is set HIGH (with PWML = 0). When the contents of this regis- ter is less than or equal to the counter value, the corresponding PWM output is set LOW (with PWML = 0). The pulse-width-ratio is therefore de- fined by the contents of the corresponding Special Function Register (PWM 0-3) of a PWM. By load- ing the corresponding Special Function Register (PWM 0-3) with either 00H or FFH, the PWM out- put can be retained at a constant HIGH or LOW level respectively (with PWML = 0). For each PWM unit, there is a 16-bit Prescaler that are used to divide the main system clock to form the input clock for the corresponding PWM unit. This prescaler is used to define the desired repeti- tion rate for the PWM unit. SFR registers B1h - B2h are used to hold the 16-bit divisor values. The repetition frequency of the PWM output is giv- en by: fPWM 8 =( fOSC / prescaler0) / (2 x 256) And the input clock frequency to the PWM counters is = fOSC / 2 / (prescaler data value + 1) See the I/O PORTS (MCU Module), page 46 for more information on how to configure the Port 4 pin as PWM output.

Figure 36. Four-Channel 8-bit PWM Block Diagram

Table 49. PWM SFR Memory Map

Figure 37. Programmable PWM 4 Channel Block Diagram

enable/disable and polarity of the PWM 4 channel. Figure 38. PWM 4 With Programmable Pulse Width and Frequency

sists of a data line (SDAx) and a clock line (SCLx). lines may require pull-up resistors. control arbitration are all controlled by hardware. handling and operates in 4 modes. These functions are controlled by the SFRs. used as a vector to various service routines. n SxDAT: data shift register. recognition is performed by On-Chip H/W. Figure 39. Block Diagram of the I

Table 50. Serial Control Register (SxCON: S1CON, S2CON) Table 51. Description of the SxCON Bits Table 52. Selection of the Serial Clock Frequency SCL in Master Mode repeated START condition when this bit is set.

4 STO

STOP flag. With this bit set while in Master Mode a STOP condition is generated. set, STOP condition in Master Mode is generated after 1 cycle interrupt period. 3 ADDR This bit is set when address byte was received. Must be cleared by software.

• Own slave address is received
• A data byte is received while the device is programmed to be a Master Receiver
• A data byte is received while the device is a selected Slave Receiver. When this bit is reset, no acknowledge is returned. SIO release SDA line as high during the acknowledge clock pulse. 1C R 1 These two bits along with the CR2 Bit determine the serial clock frequency when SIO is in the Master Mode.0C R 0 CR2 CR1 CR0 F OSC Divisor Bit Rate (kHz) at FOSC 12MHz 24MHz 36MHz 40MHz 0 0 0 16 375 750 X X 0 0 1 24 250 500 750 833 0 1 0 30 200 400 600 666 0 1 1 60 100 200 300 333 1 0 0 120 50 100 150 166 1 0 12 4 0 2 55 07 58 3 1 1 0 480 12.5 25 37.5 41 1 1 1 960 6.25 12.5 18.75 20

software and consequently that of the I2C-bus. bus interface are given Table 54. any of the following events occur.

1. Own slave address has been received during
2. The general call address has been received
3. A data byte has been received or transmitted in
4. A data byte has been received or transmitted as
5. A stop condition is received as selected slave

Table 53. Serial Status Register (SxSTA) Table 54. Description of the SxSTA Bits Note: 1. Interrupt Flag Bit (INTR, SxSTA Bit 5) is cleared by Hardware as reading SxSTA register.

1. I2C interrupt flag (INTR) can occur in below case. (except DDC2B Mode at SWENB=0)

Table 55. Data Shift Register (SxDAT: S1DAT, S2DAT)

7 GC General Call Flag

4 TX_MODE Transmission Mode Flag.

when programmed as a slave receive/transmitter. Table 56. Address Register (SxADR) Note: 1. SLA6 to SLA0: Own slave address. Table 57. Start /Stop Hold Time Detection Register (S1SETUP, S2SETUP) Table 58. System Cock of 40MHz Table 59. System Clock Setup Examples

µ PSD323X Programmer’s Guide for I2C and DDC2 The I2C serial I/O and DDC Interface operates in four modes. n Master transmitter n Master receiver n Slave transmitter n Slave receiver Master transmitter mode flow. 1. Read SxSTA. 2. If BBUSY == 1 then go to step1. Else then write slave address to SxDAT and set both ENI and STA, reset AA in SxCON. 3. Wait for interrupt. 4. Read SxSTA. If BLOST == 1 or /ACK_REP == 1* then write dummy data to SxDAT. Go to step1. Else then clear STA. 5. Perform required service routines. If this datum == LAST then set STO in SxCON and write last data to Sx- DAT. Go to step 6. Else then write next data to SxDAT. Go to step3. 6. Wait for interrupt. Write dummy data to SxDAT**. Note: 1. (*) If the master don’t receive the acknowledge from the slave, it generates the STOP condition and returns to the IDLE state. 2. (**) This action should be the last in service routine. Slave transmitter mode flow. 1. Write slave address to SxADR, set AA and ENI in SxCON. 2. Wait for interrupt. 3. Read SxSTA and write the first data to SxDAT*. Reset AA in SxCON. 4. Wait for interrupt. 5. Read SxSTA. If /ACK_REP == 1** then Go to step7. Else then write the next SxDAT*. Go to step5. 6. Write dummy data to SxDAT*. Note: 1. (*) These actions should be the last. 2. (**) If the master want to stop the current data requests, it don’t have to acknowledge to the slave transmitter. 3. If the slave does not receive the acknowledge from the master, it releases the SDA and enters the IDLE state, so if the master is to resume the data requests, it must re- generate the START condition.

µPSD323X Master receiver mode flow. 1. Read SxSTA. 2. If BBUSY == 1 then go to step1. Else then write slave address to SxDAT and set both ENI1 and STA, reset AA in SxCON. 3. Wait for interrupt. 4. Read SxSTA. If BLOST == 1 or /ACK_REP == 1 then write dummy data to SxDAT Go to step1. Else then clear STA and write FFH to SxDAT. Set AA in SxCON. 5. Wait for interrupt. 6. Read SxSTA. If this datum == LAST then reset AA* and read SxDAT. Go to step7. Else then read SxDAT. Go to step5. 7. Wait for interrupt. Read SxSTA. Read SxDAT**. Note: 1. (*) If the master want to terminate the current data re- quests, it don’t have to acknowledge to the slave. 2. (**) This action should be the last. Slave transmitter mode. 1. Write slave address to SxADR, set AA and ENI in SxCON. 2. Wait for interrupt. 3. Read SxSTA and write FFH to SxDAT*. 5. Wait for interrupt. 6. Read SxSTA. If STOP == 1 then Go to step7. Else then read data from SxDAT*. Go to step5. 7. Read dummy data from SxDAT*. Note: 1. (*) This action should be the last.

n Supports both DDC1 and DDC2b Modes. n DDC operates in Slave Mode only. Figure 40. DDC Interface Block Diagram

n 8-bit READ and WRITE register. n 8-bit READ and WRITE register. DDC2AB) and system operation. Table 60. DDC SFR Memory Map

Table 61. Description of the DDCON Register Bits

6 EX_DAT 0 = The SRAM has 128 bytes (Default)

5 SWENB

4 DDC_AX

1 = DDC2b I2C Address is AX. Least 3 significant address bits are ignored.

3 DDC1_Int

2 DDC1EN

0 = DDC1 Mode is disabled – VSYNC is ignored.

1 SWHINT

Set by hardware when the DDC unit switches from DDC1 to DDC2b Modes. Set by HW and should be cleared by SW interrupt service routine. Note1:This bit has no connection with SWENB. Mode until the DDC unit is disabled, or the system is reset.

Table 62. SWNEB Bit Function interrupt and no DDC activity will occur. space FF00h-FFFFh is dedicated to DDC SRAM. interrupt and no DDC activity will occur. FFFFh is dedicated to DDC SRAM.

n DDC2B+/DDC2AB(ACCESS .bus) host. Figure 41. Host Type Detection

DDC1 is primitive and a point to point interface. The monitor is always put at “Transmit only” mode. pin will be given for the internal synchronization.

1. Reset DDC1 enable (by default, DDC1 enable is

cleared as LOW after Power-on Reset).

1. Set SWENB as high (the default value is zero.)
2. Depending on the data size of EDID data, set
3. By using bulky moving commands (DDCADR,

Figure 42. Transmission Protocol in the DDC1 Interface

this protocol, address pointer is also used. the default address of monitors. proceeded in either byte or burst format. Figure 43. Conceptual Structure of the DDC Interface

clock frequency to be 12, 24, or 36MHz). with the physical layer of the Universal Serial Bus. data at low speed (1.5Mb/s). The SIE is the digital-front-end of the USB block. quency drift according to the USB specification. USB address and the USB endpoint. H/W could be of type control or interrupt. Table 63. USB Address Register (UADR: 0EEh) Table 64. Description of the UADR Bits

7 USBEN R/W

UADD0 R/W Specify the USB address of the device.

Table 65. USB Interrupt Enable Register (UIEN: 0E9h) Table 66. Description of the UIEN Bits Table 67. USB Interrupt Status Register (UISTA: 0E8h)

7 SUSPNDI R/W Enable SUSPND interrupt

6 RSTE R/W Enable USB Reset; also resets the CPU and PSD Modules when bit is

5 RSTFIE R/W Enable RSTF (USB Bus Reset Flag) Interrupt

4 TXD0IE R/W Enable TXD0 interrupt

3 RXD0IE R/W Enable RXD0 interrupt

2 TXD1IE R/W Enable TXD1 interrupt

1 EOPIE R/W Enable EOP interrupt

0 RESUMI R/W Enable USB resume interrupt when it is the Suspend Mode

Table 68. Description of the UISTA Bits

7 SUSPND R/W

other peripherals including the USB module.

4 TXD0F R/W

Endpoint0 Data Transmit Flag. been sent and an ACK handshake packet from the host is received. returned in the next IN transactions. RESET clears this bit.

3 RXD0F R/W

Endpoint0 Data Receive Flag. transaction. RESET clears this bit.

2 TXD1F R/W

Endpoint1 / Endpoint2 Data Transmit Flag. set of data is ready in the transmit buffers, software must clear this flag. IN transaction. RESET clears this bit.

1 EOPF R/W

and D-line. Software must clear this flag. RESET clears this bit.

0 RESUMF R/W

Software must clear this flag. RESET clears this bit.

Table 69. USB Endpoint0 Transmit Control Register (UCON0: 0EAh) Table 70. Description of the UCON0 Bits

7 TSEQ0 R/W

6 STALL0 R/W

5 TX0E R/W

USB will respond with a NAK handshake to any Endpoint 0 IN tokens.

4 RX0E R/W

NAK handshake to any Endpoint 0 OUT tokens. RESET clears this bit. TP0SIZ0 R/W The number of transmit data bytes. These bits are cleared by RESET.

Table 71. USB Endpoint1 (and 2) Transmit Control Register (UCON1: 0EBh) Table 72. Description of the UCON1 Bits

7 TSEQ1 R/W

sent during the next IN transaction directed to Endpoint 1 or Endpoint 2. Toggling of this bit must be controlled by software. RESET clears this bit.

6 EP12SEL R/W

5 TX1E R/W

Endpoint1 / Endpoint2 Transmit Enable. enable bit, EP1E or EP2E Bit in the UCON2 register, should also be set. must be cleared by software when no more data needs to be transmitted. handshake to any Endpoint 1 or Endpoint 2 directed IN token.

4 FRESUM R/W

cause the RESUMF Bit to set. TP1SIZ0 R/W The number of transmit data bytes. These bits are cleared by RESET.

Table 73. USB Control Register (UCON2: 0ECh) Table 74. Description of the UCON2 Bits Table 75. USB Endpoint0 Status Register (USTA: 0EDh) Table 76. Description of the USTA Bits Table 77. USB Endpoint0 Data Receive Register (UDR0: 0EFh) Table 78. USB Endpoint0 Data Transmit Register (UDT0: 0E7h) Table 79. USB Endpoint1 Data Transmit Register (UDT1: 0E6h)

4 SOUT R/W Status out is used to automatically respond to the OUT of a control

7 RSEQ R/W

is a SEPUP token, PID = b1101. This bit is set when the received token packet is an IN token. 4O U TR OUT Token Detect Bit. This bit is set when the received token packet is an OUT token.

Where Fosc is the MCU clock input frequency. ues for these frequencies are 0, 1, and 2. Table 80. USB SFR Memory Map

is in its high impedance state. Figure 44. Low Speed Driver Signal Waveforms

1.5 Mb/s

ceiver which is able to accept the USB data signal. Figure 45. Differential Input Sensitivity Over Entire Common Mode Range

Table 81. Transceiver DC Characteristics

1. Level guaranteed for range of VDD = 4.5V to 5.5V
2. With RPU, external idle resistor, 7.5κ± 2%, D- to VDD .
3. Measured at crossover point of differential data signals.
4. USB specification indicates 330ns

Table 82. Transceiver AC Characteristics

µPSD323X PSD MODULE n The PSD Module provides configurable Program and Data memories to the 8032 CPU core (MCU). In addition, it has its own set of I/O ports and a PLD with 16 macrocells for general logic implementation. n Ports A,B,C, and D are general purpose programmable I/O ports that have a port architecture which is different from the I/O ports in the MCU Module. n The PSD Module communicates with the MCU Module through the internal address, data bus (AO-A15, DO-D7) and control signals (RD, WR, PSEN, ALE, RESET). The user defines the Decoding PLD in the PSDsoft Development Tool and can map the resources in the PSD Module to any program or data address space. Figure 50 shows the functional blocks in the PSD Module. Functional Overview n 1 or 2 Mbit Flash memory. This is the main Flash memory. It is divided into eight equal- sized blocks that can be accessed with user- specified addresses. n Secondary 256 Kbit Flash boot memory. It is divided into four equal-sized blocks that can be accessed with user-specified addresses. This secondary memory brings the ability to execute code and update the main Flash concurrently. n 64 Kbit SRAM. The SRAM’s contents can be protected from a power failure by connecting an external battery. n CPLD with 1G Output Micro Cells (OMCs} and 24 Input Micro Cells (IMCs). The CPLD may be used to efficiently implement a variety of logic functions for internal and external control. Examples include state machines, loadable shift registers, and loadable counters. n Decode PLD (DPLD) that decodes address for selection of memory blocks in the PSD Module. n Configurable I/O ports (Port A,B,C and D) that can be used for the following functions: – MCU I/Os – PLD I/Os – Latched MCU address output – Special function I/Os. – I/O ports may be configured as open-drain outputs. n Built-in JTAG compliant serial port allows full- chip In-System Programmability (ISP). With it, you can program a blank device or reprogram a device in the factory or the field. n Internal page register that can be used to expand the 8032 MCU Module address space by a factor of 256. n Internal programmable Power Management Unit (PMU) that supports a low-power mode called Power-down Mode. The PMU can automatically detect a lack of the 8032 CPU core activity and put the PSD Module into Power-down Mode. n Erase/WRITE cycles: – Flash memory - 100,000 minimum – PLD - 1,000 minimum – Data Retention: 15 year minimum (for Main Flash memory, Boot, PLD and Configuration bits)

Figure 50. PSD MODULE Block Diagram

1 OR 2 MBIT PRIMARY

8 SECTORS

2 EXT CS TO PORT D

24 INPUT MACROCELLS

256 KBIT SECONDARY

4 SECTORS

64 KBIT BATTERY

16 OUTPUT MACROCELLS

8032 Bus

tional blocks of the PSD MODULE. Table 83. Methods of Programming Different Functional Blocks of the PSD MODULE

1. PSDsoft is available from our web site (the ad-

or other distribution channels. our web site for the current list. Figure 51. PSDsoft Express Development Tool atorial and registered logic in CPLD.

Table 84. Register Address Offset Note: 1. Other registers that are not part of the I/O ports. and/or Data space on an individual basis.

µ PSD323X PSD MODULE DETAILED OPERATION As shown in Figure 15, the PSD MODULE con- sists of five major types of functional blocks: n Memory Block n PLD Blocks n I/O Ports n Power Management Unit (PMU) n JTAG Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. MEMORY BLOCKS The PSD MODULE has the following memory blocks: – Primary Flash memory – Secondary Flash memory – SRAM The Memory Select signals for these blocks origi- nate from the Decode PLD (DPLD) and are user- defined in PSDsoft Express. Primary Flash Memory and Secondary Flash memory Description The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors. Each sector of either memory block can be separately protected from Program and Erase cycles. Flash memory may be erased on a sector-by-sec- tor basis. Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading. During a Program or Erase cycle in Flash memory, the status can be output on Ready/Busy (PC3). This pin is set up using PSDsoft Express Configu- ration. Memory Block Select Signals The DPLD generates the Select signals for all the internal memory blocks (see the section entitled “PLDs,” page 120). Each of the eight sectors of the primary Flash memory has a Select signal (FS0- FS7) which can contain up to three product terms. Each of the four sectors of the secondary Flash memory has a Select signal (CSBOOT0- CSBOOT3) which can contain up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped in Pro- gram or Data space. Ready/Busy (PC3).This signal can be used to output the Ready/Busy status of the Flash memo- ry. The output on Ready/Busy (PC3) is a ’0’ (Busy) when Flash memory is being written to, or when Flash memory is being erased. The output is a 1 (Ready) when no WRITE or Erase cycle is in progress. Memory Operation. The primary Flash memory and secondary Flash memory are addressed through the MCU Bus. The MCU can access these memories in one of two ways: n The MCU can execute a typical bus WRITE or READ operation. n The MCU can execute a specific Flash memory instruction that consists of several WRITE and READ operations. This involves writing specific data patterns to special addresses within the Flash memory to invoke an embedded algorithm. These instructions are summarized in Table 85. Typically, the MCU can read Flash memory using READ operations, just as it would read a ROM de- vice. However, Flash memory can only be altered using specific Erase and Program instructions. For example, the MCU cannot write a single byte di- rectly to Flash memory as it would write a byte to RAM. To program a byte into Flash memory, the MCU must execute a Program instruction, then test the status of the Program cycle. This status test is achieved by a READ operation or polling Ready/Busy (PC3). Flash memory can also be read by using special instructions to retrieve particular Flash device in- formation (sector protect status and ID).

µPSD323X Instructions An instruction consists of a sequence of specific operations. Each received byte is sequentially de- coded by the PSD MODULE and not executed as a standard WRITE operation. The instruction is ex- ecuted when the correct number of bytes are prop- erly received and the time between two consecutive bytes is shorter than the time-out pe- riod. Some instructions are structured to include READ operations after the initial WRITE opera- tions. The instruction must be followed exactly. Any in- valid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory resets the device logic into READ Mode (Flash memory is read like a ROM device). The Flash memory supports the instructions sum- marized in Table 85: Flash memory: n Erase memory by chip or sector n Suspend or resume sector erase n Program a Byte n RESET to READ Mode n Read primary Flash Identifier value n Read Sector Protection Status n Bypass These instructions are detailed in Table 85. For ef- ficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. The coded cycles consist of writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cy- cle. Address signals A15-A12 are Don’t Care dur- ing the instruction WRITE cycles. However, the appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) must be selected. The primary and secondary Flash memories have the same instruction set (except for Read Primary Flash Identifier). The Sector Select signals deter- mine which Flash memory is to receive and exe- cute the instruction. The primary Flash memory is selected if any one of Sector Select (FS0-FS7) is High, and the secondary Flash memory is selected if any one of Sector Select (CSBOOT0- CSBOOT3) is High.

Table 85. Instructions

1. All values are in hexadecimal:

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of WRITE Strobe (WR, CNTL0). PA is an even address for PSD in Word Programming Mode. erased, or verified, must be Active (High).

1. Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) signals are active High, and are defined in PSDsoft Express.
2. Only address BitsA11-A0 are used in instruction decoding.
3. No Unlock or instruction cycles are required when the device is in the READ Mode
4. The RESET instruction is required to return to the READ Mode after reading the Flash ID, or after reading the Sector Protection

Status, or if the Error Flag Bit (DQ5/DQ13) goes High.

1. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs.
2. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
3. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
4. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
5. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status

when in the Suspend Sector Erase Mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.

1. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase Mode.
2. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is

Status of the primary Flash memory.

µPSD323X Power-down Instruction and Power-up Mode Power-up Mode. The PSD MODULE internal logic is reset upon Power-up to the READ Mode. Sector Select (FS0-FS7 and CSBOOT0- CSBOOT3) must be held Low, and WRITE Strobe (WR, CNTL0) High, during Power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of WRITE Strobe (WR, CNTL0). Any WRITE cycle initiation is locked when VCC is below VLKO . READ Under typical conditions, the MCU may read the primary Flash memory or the secondary Flash memory using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to obtain status information about a Program or Erase cycle that is currently in progress. Lastly, the MCU may use instructions to read special data from these memory blocks. The following sections describe these READ functions. READ Memory Contents. Primary Flash memo- ry and secondary Flash memory are placed in the READ Mode after Power-up, chip reset, or a Reset Flash instruction (see Table 85, page 109). The MCU can read the memory contents of the pri- mary Flash memory or the secondary Flash mem- ory by using READ operations any time the READ operation is not part of an instruction. READ Primary Flash Identifier.The primary Flash memory identifier (E7h) is read with an in- struction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Ta- ble 85). During the READ operation, Address Bits A6, A1, and A0 must be ’0,’ ’0,’ and ’1,’ respective- ly, and the appropriate Sector Select (FS0-FS7) must be High. READ Memory Sector Protection Status.The primary Flash memory Sector Protection Status is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ opera- tion (see Table 85). During the READ operation, address Bits A6, A1, and A0 must be ’0,’ ’1,’ and ’0,’ respectively, while Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) designates the Flash memory sector whose protection has to be veri- fied. The READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (primary Flash memory or secondary Flash mem- ory) can also be read by the MCU accessing the Flash Protection registers in PSD I/O space. See the section entitled “Flash Memory Sector Pro- tect,” page 115, for register definitions. Reading the Erase/Program Status Bits.The Flash memory provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 86, page 111. The status bits can be read as many times as needed. For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See the section entitled “Programming Flash Memory,” page 112, for de- tails. Data Polling Flag (DQ7).When erasing or pro- gramming in Flash memory, the Data Polling Flag Bit (DQ7) outputs the complement of the bit being entered for programming/writing on the DQ7 Bit. Once the Program instruction or the WRITE oper- ation is completed, the true logic value is read on the Data Polling Flag Bit (DQ7) (in a READ opera- tion). n Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). It must be performed at the address being programmed or at an address within the Flash memory sector being erased. n During an Erase cycle, the Data Polling Flag Bit (DQ7) outputs a ’0.’ After completion of the cycle, the Data Polling Flag Bit (DQ7) outputs the last bit programmed (it is a ’1’ after erasing). n If the byte to be programmed is in a protected Flash memory sector, the instruction is ignored. n If all the Flash memory sectors to be erased are protected, the Data Polling Flag Bit (DQ7) is reset to ’0’ for about 100µs, and then returns to the previous addressed byte. No erasure is performed.

tempts to read any byte of the memory. accessible for a new READ or WRITE operation. returns to the previous addressed byte. condition while attempting to program a byte. grammed byte belongs must no longer be used. Other Flash memory sectors may still be used. Table 86. Status Bit

1. DQ7-DQ0 represent the Data Bus bits, D7-D0.
2. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.

ed. Figure 53 shows the Data Toggle algorithm. erased (not erased is logic ’0’). byte that was intended to be written. Flag Bit (DQ6) and the Error Flag Bit (DQ5). Figure 53. Data Toggle Flowchart

pass code, 20h (as shown in Table 85). ond cycle contains the program address and data. does this before erasing to 0FFh. Flash memory does not accept any instructions. Table 85. Additional Flash Sector Erase codes progress, and reset the device to READ Mode. gramming Flash Memory,” page 112. cle, terminates the time out period. that was being erased outputs invalid data.

erase cycle may be resumed with this instruction. JTAG Port or a Device Programmer. operation results in a READ of the protected data. Table 87. Sector Protection/Security Bit Definition – Flash Protection Register Sec<i>_Prot1 = Primary Flash memory or secondary Flash memory Sector <i> is write-protected. Sec<i>_Prot0 = Primary Flash memory or secondary Flash memory Sector <i> is not write-protected. Table 88. Sector Protection/Security Bit Definition – Secondary Flash Protection Register Sec<i>_Prot1 = Secondary Flash memory Sector <i> is write-protected. Sec<i>_Prot0 = Secondary Flash memory Sector <i> is not write-protected. Security_Bit0 = Security Bit in device has not been set. 1 = Security Bit in device has been set.

µPSD323X Reset Flash.The Reset Flash instruction con- sists of one WRITE cycle (see Table 85). It can also be optionally preceded by the standard two WRITE decoding cycles (writing AAh to 555h and 55h to AAAh). It must be executed after: – Reading the Flash Protection Status or Flash ID – An Error condition has occurred (and the device has set the Error Flag Bit (DQ5) to ’1’ during a Flash memory Program or Erase cycle. The Reset Flash instruction puts the Flash memo- ry back into normal READ Mode. If an Error condi- tion has occurred (and the device has set the Error Flag Bit (DQ5) to ’1’ the Flash memory is put back into normal READ Mode within 25µs of the Reset Flash instruction having been issued. The Reset Flash instruction is ignored when it is issued dur- ing a Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ Mode within 25µs. Reset (RESET) Signal.A pulse on Reset (RE- SET) aborts any cycle that is in progress, and re- sets the Flash memory to the READ Mode. When the reset occurs during a Program or Erase cycle, the Flash memory takes up to 25µs to return to the READ Mode. It is recommended that the Reset (RESET) pulse (except for Power-on RESET, as described on page 140) be at least 25µs so that the Flash memory is always ready for the MCU to retreive the bootstrap instructions after the reset cycle is complete. SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to Voltage Stand-by (V STBY , PC2). If you have an external battery connected to theµPSD3200, the contents of the SRAM are retained in the event of a power loss. The contents of the SRAM are re- tained so long as the battery voltage remains at 2V or greater. If the supply voltage falls below the bat- tery voltage, an internal power switch-over to the battery occurs. PC4 can be configured as an output that indicates when power is being drawn from the external bat- tery. Battery-on Indicator (V BATON , PC4) is High with the supply voltage falls below the battery volt- age and the battery on Voltage Stand-by (VSTBY , PC2) is supplying power to the internal SRAM. SRAM Select (RS0), Voltage Stand-by (VSTBY , PC2) and Battery-on Indicator (VBATON , PC4) are all configured using PSDsoft Express Configura- tion. Sector Select and SRAM Select Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of the DPLD. They are setup by writing equations for them in PSDsoft Express. The following rules ap- ply to the equations for these signals: 1. Primary Flash memory and secondary Flash memory Sector Select signals must notbe larg- er than the physical sector size. 2. Any primary Flash memory sector mustnotbe mapped in the same memory space as another Flash memory sector. 3. A secondary Flash memory sector mustnotbe mapped in the same memory space as another secondary Flash memory sector. 4. SRAM, I/O, and Peripheral I/O spaces must not overlap. 5. A secondary Flash memory sectormay overlap a primary Flash memory sector. In case of over- lap, priority is given to the secondary Flash memory sector. 6. SRAM, I/O, and Peripheral I/O spacesmay overlap any other memory sector. Priority is giv- en to the SRAM, I/O, or Peripheral I/O.

Table 90. DPLD and CPLD Inputs Note: 1. These inputs are not available in the 52-pin package. code PLD (DPLD), and the Complex PLD (CPLD). section entitled “Complex PLD (CPLD),” page 123. Figure 58 shows the configuration of the PLDs. memory, registers, and I/O ports. The AND Array is used to form product terms. These product terms are specified using PSDsoft. put signals are shown in Table 90. block MCU control signals from entering the PLDs.

Figure 58. PLD Diagram

24 INPUT MACROCELL

16 OUTPUT

2 PORT D INPUTS

Figure 59. DPLD Logic Array

1. Inputs from the MCU module

8 PRIMARY FLASH

(ECS1-ECS2), routed to Port D. D do not consume any Output Macrocells (OMC). standard PLD macrocell architectures. Figure 60. Macrocell and I/O Port

input can use up to two product terms. Table 91. Output Macrocell Port and Data Bit Assignments

terms and may borrow up to six more. Express performs this expansion as needed. Figure 61. CPLD Output Macrocell

(Mask Macrocell AB) with the value 0Fh. routed as an input to the AND Array. the Input Macrocells (IMC) is shown in Figure 62. one product term and 7-4 by another. Figure 62. Input Macrocell

n Individual Port functionality. that pin is no longer available for other purposes. and B only) and PSDsoft Express Configuration. all connected to the Port Data Buffer (PDB). Figure 63. General I/O Port Architecture

µPSD323X The Port pin’s tri-state output driver enable is con- trolled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CPLD output in the PSDsoft, then the Direction Register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the MCU. The Port Data Buffer (PDB) feedback path allows the MCU to check the contents of the registers. Ports A, B, and C have embedded Input Macro- cells (IMC). The Input Macrocells (IMC) can be configured as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by Address Strobe (ALE) or a product term from the PLD AND Array. The outputs from the Input Macrocells (IMC) drive the PLD input bus and can be read by the MCU. See the section entitled “In- put Macrocell,” page 126. Port Operating Modes The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft, some by the MCU writing to the Control Registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft must be pro- grammed into the device and cannot be changed unless the device is reprogrammed. The modes that can be changed by the MCU can be done so dynamically at run-time. The PLD I/O, Data Port, Address Input, and Peripheral I/O Modes are the only modes that must be defined before program- ming the device. All other modes can be changed by the MCU at run-time. See Application Note AN1171 for more detail. Table 92 summarizes which modes are available on each port. Table 95 shows how and where the different modes are configured. Each of the port operating modes are described in the following sections. MCU I/O Mode In the MCU I/O Mode, the MCU uses the I/O Ports block to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD MODULE are mapped into the MCU address space. The ad- dresses of the ports are listed in Table 84. A port pin can be put into MCU I/O Mode by writing a ’0’ to the corresponding bit in the Control Regis- ter. The MCU I/O direction may be changed by writing to the corresponding bit in the Direction Register, or by the output enable product term. See the section entitled “Peripheral I/O Mode,” page 128. When the pin is configured as an out- put, the content of the Data Out Register drives the pin. When configured as an input, the MCU can read the port input through the Data In buffer. See Figure 63, page 127. Ports C and D do not have Control Registers, and are in MCU I/O Mode by default. They can be used for PLD I/O if equations are written for them in PS- Dabel. PLD I/O Mode The PLD I/O Mode uses a port as an input to the CPLD’s Input Macrocells (IMC), and/or as an out- put from the CPLD’s Output Macrocells (OMC). The output can be tri-stated with a control signal. This output enable control signal can be defined by a product term from the PLD, or by resetting the corresponding bit in the Direction Register to ’0.’ The corresponding bit in the Direction Register must not be set to ’1’ if the pin is defined for a PLD input signal in PSDsoft. The PLD I/O Mode is specified in PSDsoft by declaring the port pins, and then writing an equation assigning the PLD I/ O to a port. Address Out Mode Address Out Mode can be used to drive latched MCU addresses on to the port pins. These port pins can, in turn, drive external devices. Either the output enable or the corresponding bits of both the Direction Register and Control Register must be set to a ’1’ for pins to use Address Out Mode. This must be done by the MCU at run-time. See Table 94 for the address output pin assignments on Ports A and B for various MCUs. Peripheral I/O Mode Peripheral I/O Mode can be used to interface with external peripherals. In this mode, all of Port A serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O Mode is enabled by set- ting Bit 7 of the VM Register to a ’1.’ Figure 64 shows how Port A acts as a bi-directional buffer for the MCU data bus if Peripheral I/O Mode is en- abled. An equation for PSEL0 and/or PSEL1 must be written in PSDsoft. The buffer is tri-stated when PSEL0 or PSEL1 is low (not active). The PSEN signal should be “ANDed” in the PSEL equations to disable the buffer when PSEL resides in the data space. JTAG In-System Programming (ISP) Port C is JTAG compliant, and can be used for In- System Programming (ISP). For more information on the JTAG Port, see the section entitled “PRO- GRAMMING IN-CIRCUIT USING THE JTAG SE- RIAL INTERFACE,” page 142.

Figure 64. Peripheral I/O Mode Table 92. Port Operating Modes Note: 1. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins.

1. Port A is not available in the 52-pin package.

Table 93. Port Operating Mode Settings

1. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product

term (.oe) from the CPLD AND Array. Table 94. I/O Port Latched Address Output Assignments

each bit in the register controls its respective pin. each register in Table 95 is 00h. and B have an associated Control Register. fault mode for all port pins is input. Register has sole control of a given pin’s direction. should be used for pins configured as Open Drain. ’1.’ The default pin drive is CMOS. ister is set to ’1.’ The default rate is slow slew. pins the slew rate can be set for. Table 95. Port Configuration Registers (PCR) Note: 1. See Table 99 for Drive Register Bit definition. Table 96. Port Pin Direction Control, Output Table 97. Port Pin Direction Control, Output Table 98. Port Direction Assignment Example

0 Input

1 Output

put is read through the Data In buffer. also be read back by the MCU. tion entitled “PLDs,” page 120. (IMC) can be used to latch or store external inputs. MCU. See the section entitled “PLDs,” page 120. and the pin is in input mode. Table 99. Drive Register Pin Assignment Note: 1. NA = Not Applicable. Table 100. Port Data Registers

McellBC0 can be connected to Port B or Port C. n CPLD Input – Via the Input Macrocells (IMC). address output as per Table 94. Figure 65. Port A and Port B Structure

can be connected to Port B or Port C. therefore no Control Register is required. Figure 66. Port C Structure

52-pin package). See Figure 67 and Figure 68. are used to configure pins PD2 and PD1. Figure 67. Port D Structure

term that can be configured active High or Low. Figure 68. Port D External Chip Select Signals

The PSD MODULE has a Turbo Bit in PMMR0. rent component and the AC component is higher. does not block CLKIN (PD1) from the APD Unit. Mode effects on PSD MODULE ports. that are independent of the Power-down Mode. setting bits in PMMR0 and PMMR2. Figure 70. Enable Power-down Flow Chart Table 101. Power-down Mode’s Effect on Ports

maximum rated clock frequency. cates when the VCC has dropped below VSTBY . when PSD Chip Select Input (CSI, PD2) is High. the clock should be disabled to save AC power. Table 102. Power Management Mode Registers PMMR0 Bit 0 X 0 Not used, and should be set to zero. 0 = off Automatic Power-down (APD) is disabled. 1 = on Automatic Power-down (APD) is enabled. Bit 2 X 0 Not used, and should be set to zero. 1 = offPLD Turbo Mode is off, saving power. 1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power. 0 = on CLKIN (PD1) input to the PLD macrocells is connected. 1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero.

Table 103. Power Management Mode Registers PMMR21 Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent RESET pulses do not clear the registers. Table 104. APD Counter Operation Bit 0 X 0 Not used, and should be set to zero. Bit 1 X 0 Not used, and should be set to zero. 0 = on WR input to the PLD AND Array is connected. 1 = off WR input to PLD AND Array is disconnected, saving power. 0 = on RD input to the PLD AND Array is connected. 1 = off RD input to PLD AND Array is disconnected, saving power. 0 = on PSEN input to the PLD AND Array is connected. 1 = off PSEN input to PLD AND Array is disconnected, saving power. 0 = on ALE input to the PLD AND Array is connected. 1 = off ALE input to PLD AND Array is disconnected, saving power. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero.

0 X Not Counting

1 Pulsing Not Counting

and sets the Flash memory into operating mode. automatically when VCC is below VLKO . termined by the PLD equations. Figure 71. Reset (RESET) Timing

Table 105. Status During Power-on RESET, Warm RESET and Power-down Mode Note: 1. The SR_cod and PeriphMode Bits in the VM Register are always cleared to ’0’ on Power-on RESET or Warm RESET.

used to speed up Program and Erase cycles. the basic JTAG signals TMS, TCK, TDI, and TDO. Table 106. JTAG Port Signals ten to the secondary Flash memory. Chip Erase command is allowed. set in PSDsoft Express Configuration.

Table 107. PSD MODULE Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off) pins being disconnected and IOUT = 0 mA.

Table 108. Absolute Maximum Ratings

Table 109. Operating Conditions (5V Devices) Table 110. Operating Conditions (3V Devices)

Table 111. AC Symbols for Timing Figure 74. Switching Waveforms – Key

Table 112. DC Characteristics (5V Devices)

µ PSD323X Note: 1. IPD (Power-down Mode) is measured with: XTAL1=V SS ; XTAL2=not connected; RESET=VCC ; Port 0 =VCC ; all other pins are disconnected. PLD not in Turbo Mode. 2. ICC_CPU (active mode) is measured with: XTAL1 driven with tCLCH ,tCHCL = 5ns, VIL =V SS +0.5V, VIH = Vcc – 0.5V, XTAL2 = not connected; RESET=VSS ; Port 0=VCC ; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately 1mA). 3. ICC_CPU (Idle Mode) is measured with: XTAL1 driven with tCLCH ,tCHCL = 5ns, VIL=V SS +0.5V, VIH =V CC – 0.5V, XTAL2 = not connected; Port 0 = VCC ; RESET=V CC ; all other pins are disconnected. 4. PLD is in non-Turbo Mode and none of the inputs are switching. 5. See Figure 72 for the PLD current calculation. 6. I/O current = 0 mA, all I/O pins are disconnected. ISTBY SRAM (PSD) Stand-by Current (VSTBY input) V CC =0 V 0.5 1 µA IIDLE SRAM (PSD) Idle Current (VSTBY input) V CC >V STBY –0.1 0.1 µA IRST Reset Pin Pull-up Current (RESET) V IN =V SS –10 –55 µA IFR XTAL Feedback Resistor Current (XTAL1) XTAL1 = VCC XTAL2 = VSS –20 –50 µA ILI Input Leakage Current V SS <V IN <V CC –1 1 µA ILO Output Leakage Current 0.45 < VOUT <V CC –10 10 µA IPD 1 Power-down Mode VCC = 5.5V LVD logic disabled 250 µA LVD logic enabled 380 µA ICC_CPU 2,3,6 Active (12MHz) V CC =5 V 20 30 mA Idle (12MHz) 8 10 mA Active (24MHz) V CC =5 V 30 38 mA Idle (24MHz) 15 20 mA Active (40MHz) V CC =5 V 40 62 mA Idle (40MHz) 20 30 mA ICC_PSD (DC)6 Operating Supply Current PLD Only PLD_TURBO = Off, f = 0MHz7 0 µA/PT5 PLD_TURBO = On, f = 0MHz 400 700 µA/PT Flash memory During Flash memory WRITE/Erase Only 15 30 mA Read-only, f = 0MHz 0 0 mA SRAM f = 0MHz 0 0 mA ICC_PSD (AC)6 PLD AC Base note5 Flash memory AC Adder 2.5 3.5 mA/ MHz SRAM AC Adder 1.5 3.0 mA/ MHz Symbol Parameter Test Condition (in addition to those in Table 109, page 146) Min. Typ. Max. Unit

Table 113. DC Characteristics (3V Devices)

µ PSD323X Note: 1. IPD (Power-down Mode) is measured with: XTAL1=V SS ; XTAL2=not connected; RESET=VCC ; Port 0 =VCC ; all other pins are disconnected. PLD not in Turbo mode. 2. ICC_CPU (active mode) is measured with: XTAL1 driven with tCLCH ,tCHCL = 5ns, VIL =V SS +0.5V, VIH = Vcc – 0.5V, XTAL2 = not connected; RESET=VSS ; Port 0=VCC ; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately 1mA). 3. ICC_CPU (Idle Mode) is measured with: XTAL1 driven with tCLCH ,tCHCL = 5ns, VIL=V SS +0.5V, VIH =V CC – 0.5V, XTAL2 = not connected; Port 0 = VCC ; RESET=V CC ; all other pins are disconnected. 4. PLD is in non-Turbo Mode and none of the inputs are switching. 5. See Figure 72 for the PLD current calculation. 6. I/O current = 0 mA, all I/O pins are disconnected. ITL Logic 1-to-0 Transition Current (Ports 1,2,3,4) VIN = 3.5V (2.5V for Port 4[pin 2]) –25 –250 µA ISTBY SRAM (PSD) Stand-by Current (VSTBY input) VCC = 0V 0.5 1 µA IIDLE SRAM (PSD) Idle Current (VSTBY input) VCC >V STBY –0.1 0.1 µA IRST Reset Pin Pull-up Current (RESET) VIN =V SS –10 –55 µA IFR XTAL Feedback Resistor Current (XTAL1) XTAL1 = VCC XTAL2 = VSS –20 –50 µA ILI Input Leakage Current VSS <V IN <V CC –1 1 µA ILO Output Leakage Current 0.45 < VOUT <V CC –10 10 µA IPD 1 Power-down Mode V CC = 3.6V LVD logic disabled 110 µA LVD logic enabled 180 µA ICC_CPU 2,3,6 Active (12MHz) V CC = 3.6V 81 0 m A Idle (12MHz) 4 5 mA Active (24MHz) V CC = 3.6V 15 20 mA Idle (24MHz) 8 10 mA ICC_PSD (DC)6 Operating Supply Current PLD Only PLD_TURBO = Off, f = 0MHz7 0 µA/ PT 5 PLD_TURBO = On, f = 0MHz 200 400 µA/ PT Flash memory During Flash memory WRITE/Erase Only 10 25 mA Read-only, f = 0MHz 0 0 mA SRAM f = 0MHz 0 0 mA ICC_PSD (AC)6 PLD AC Base note5 Flash memory AC Adder 1.5 2.0 mA/ MHz SRAM AC Adder 0.8 1.5 mA/ MHz Symbol Parameter Test Condition (in addition to those in Table 110, page 146) Min. Typ. Max. Unit

Figure 75. External Program Memory READ Cycle Table 114. External Program Memory AC Characteristics (with the 5V MCU Module)

1. Interfacing theµPSD323X Devices to devices with float times up to 20ns is permissible. This limited bus contention does not cause

any damage to Port 0 drivers.

Table 115. External Program Memory AC Characteristics (with the 3V MCU Module)

1. Interfacing theµPSD323X Devices to devices with float times up to 35ns is permissible. This limited bus contention does not cause

any damage to Port 0 drivers. Table 116. External Clock Drive (with the 5V MCU Module) Table 117. External Clock Drive (with the 3V MCU Module)

Table 118. External Data Memory AC Characteristics (with the 5V MCU Module)

Table 119. External Data Memory AC Characteristics (with the 3V MCU Module) Table 120. A/D Analog Specification CA IN Overall Accuracy ±2 l.s.b. N NLE Non-Linearity Error ±2 l.s.b. N DNLE Differential Non-Linearity Error ±2 l.s.b. N ZOE Zero-Offset Error ±2 l.s.b. N FSE Full Scale Error ±2 l.s.b.

Figure 78. Input to Output Disable / Enable Table 121. CPLD Combinatorial Timing (5V Devices)

1. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial

Table 122. CPLD Combinatorial Timing (3V Devices)

1. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial

Figure 79. Synchronous Clock Mode Timing – PLD Table 123. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.

1. CLKIN (PD1) tCLCL =tCH +tCL .

Table 124. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.

1. CLKIN (PD1) tCLCL =tCH +tCL .

Table 126. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)

Figure 82. Input Macrocell Timing (product term clock) Table 127. Input Macrocell Timing (5V Devices) Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX . Table 128. Input Macrocell Timing (3V Devices) Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX .

Table 129. Program, WRITE and Erase Times (5V Devices) Note: 1. Programmed to all zero before erase.

1. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

Table 130. Program, WRITE and Erase Times (3V Devices) Note: 1. Programmed to all zero before erase.

1. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

Figure 83. Peripheral I/O READ Timing Table 131. Port A Peripheral Data Mode READ Timing (5V Devices) Note: 1. Any input used to select Port A Data Peripheral Mode.

1. Data is already stable on Port A.

Table 132. Port A Peripheral Data Mode READ Timing (3V Devices) Note: 1. Any input used to select Port A Data Peripheral Mode.

1. Data is already stable on Port A.

Figure 84. Peripheral I/O WRITE Timing Table 133. Port A Peripheral Data Mode WRITE Timing (5V Devices) Note: 1. Data stable on Port 0 pins to data on Port A. Table 134. Port A Peripheral Data Mode WRITE Timing (3V Devices) Note: 1. Data stable on Port 0 pins to data on Port A.

Figure 85. Reset (RESET) Timing Table 135. Reset (RESET) Timing (5V Devices) Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

1. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

Table 136. Reset (RESET) Timing (3V Devices) Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

1. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

Table 137. VSTBYON Definitions Timing (5V Devices) Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms. Table 138. VSTBYON Timing (3V Devices) Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.

Figure 86. ISC Timing Table 139. ISC Timing (5V Devices) Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.

1. For Program or Erase PLD only.

Figure 93. TQFP52 – 52-lead Plastic Quad Flatpack Package Outline Note: Drawing is not to scale.

Table 142. TQFP52 – 52-lead Plastic Quad Flatpack Package Mechanical Data

Figure 94. TQFP80 – 80-lead Plastic Quad Flatpack Package Outline Note: Drawing is not to scale.

Table 143. TQFP80 – 80-lead Plastic Quad Flatpack Package Mechanical Data

Table 144. Ordering Information Scheme please contact your nearest ST Sales Office.

µ PSD323X

REVISION HISTORY

Table 145. Document Revision History Table 146. Device Functional Change History Note: Date Code is the 6th to the 9th digit of the Trace Code on top of the device. and the associated registers are added.Only PWM0-PWM3 channels are available.

1. Option to block USB generated reset

from resetting the MCU/PSD modules.

1. Allow USB Reset Flag (RSTF) to interrupt
2. Add RSTE and RSTFIE Bits to the UIEN

the USB and the MCU/PSD modules.

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