UPSD3212CV-24T1T

UPSD3212C STMICROELECTRONICS | Alldatasheet

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UPSD3212C, UPSD3212CV TABLE OF CONTENTS

UPSD3212C, UPSD3212CV

UPSD3212C, UPSD3212CV

UPSD3212C, UPSD3212CV

UPSD3212C, UPSD3212CV

UPSD3212C, UPSD3212CV

UPSD3212C, UPSD3212CV

UPSD3212C, UPSD3212CV PSD MODULE Example, Typ. Power Calculation at V CC = 5.0V (Turbo Mode Off) (Table 84.). . 120

UPSD3212C, UPSD3212CV V

UPSD3212C, UPSD3212CV SUMMARY DESCRIPTION ■ Dual bank Flash memories – Concurrent operation, read from memory while erasing and writing the other. In-Appli- cation Programming (IAP) for remote updates – Large 64KByte main Flash memory for appli- cation code, operating systems, or bit maps for graphic user interfaces – Large 16KByte secondary Flash memory di- vided in small sectors. Eliminate external EE- PROM with software EEPROM emulation – Secondary Flash memory is large enough for sophisticated communication protocol during IAP while continuing critical system tasks ■ Large SRAM with battery back-up option – 2KByte SRAM for RTOS, high-level languag- es, communication buffers, and stacks ■ Programmable Decode PLD for flexible address mapping of all memories – Place individual Flash and SRAM sectors on any address boundary – Built-in page register breaks restrictive 8032 limit of 64KByte address space – Special register swaps Flash memory seg- ments between 8032 “program” space and “data” space for efficient In-Application Pro- gramming ■ High-speed clock standard 8032 core (12-cycle) – 40MHz operation at 5V, 24MHz at 3.3V – 2 UARTs with independent baud rate, three 16-bit Timer/Counters and two External Inter- rupts ■ I2C interface for peripheral connections – Capable of master or slave operation ■ 5 Pulse Width Modulator (PWM) channels – Four 8-bit PWM units – One 8-bit PWM unit with programmable peri- od ■ 4-channel, 8-bit Analog-to-Digital Converter (ADC) with analog supply voltage (V REF ) ■ Six I/O ports with up to 46 I/O pins – Multifunction I/O: GPIO, I2C, PWM, PLD I/O, supervisor, and JTAG – Eliminates need for external latches and logic ■ 3000 gate PLD with 16 macrocells – Create glue logic, state machines, delays, etc. – Eliminate external PALs, PLDs, and 74HCxx – Simple PSDsoft Express software... Free ■ Supervisor functions – Generates reset upon low voltage or watch- dog time-out. Eliminate external supervisor device – RESET Input pin; Reset output via PLD ■ In-System Programming (ISP) via JTAG – Program entire chip in 10 - 25 seconds with no involvement of 8032 – Allows efficient manufacturing, easy product testing, and Just-In-Time inventory – Eliminate sockets and pre-programmed parts – Program with FlashLINKTM cable and any PC ■ Content Security – Programmable Security Bit blocks access of device programmers and readers ■ Zero-Power Technology – Memories and PLD automatically reach standby current between input changes ■ Packages – 52-pin TQFP – 80-pin TQFP: allows access to 8032 address/ data/control signals for connecting to external peripherals

Table 1. uPSD321X Devices Product Matrix Figure 3. TQFP52 Connections Note: 1. Pull-up resistor required on pin 5 (2kΩ for 3V devices, 7.5kΩ for 5V devices).

33 VCC

32 XTAL2

31 XTAL1

Figure 4. TQFP80 Connections Note: 1. Pull-up resistor required on pin 8 (2kΩ for 3V devices, 7.5kΩ for 5V devices).

50 VCC

49 XTAL2

48 XTAL1

Table 2. 80-Pin Package Pin Description

UPSD3212C, UPSD3212CV P4.4 PWM1 25 I/O General I/O port pin 8-bit Pulse Width Modulation output 1 P4.5 PWM2 23 I/O General I/O port pin 8-bit Pulse Width Modulation output 2 P4.6 PWM3 19 I/O General I/O port pin 8-bit Pulse Width Modulation output 3 P4.7 PWM4 18 I/O General I/O port pin Programmable 8-bit Pulse Width modulation output 4 PUP 8 I/O Pull-up resistor required (2kΩ for 3V devices, 7.5kΩ for 5V devices) AVREF 70 O Reference Voltage input for ADC RD_ 65 O READ signal, external bus WR_ 62 O WRITE signal, external bus PSEN_ 63 O PSEN signal, external bus ALE 4 O Address Latch signal, external bus RESET_ 68 I Active low RESET input XTAL1 48 I Oscillator input pin for system clock XTAL2 49 O Oscillator output pin for system clock PA0 35 I/O General I/O port pin 1. PLD Macro-cell outputs 2. PLD inputs 3. Latched Address Out (A0-A7) 4. Peripheral I/O Mode PA1 34 I/O General I/O port pin PA2 32 I/O General I/O port pin PA3 28 I/O General I/O port pin PA4 26 I/O General I/O port pin PA5 24 I/O General I/O port pin PA6 22 I/O General I/O port pin PA7 21 I/O General I/O port pin PB0 80 I/O General I/O port pin 1. PLD Macro-cell outputs 2. PLD inputs 3. Latched Address Out (A0-A7) PB1 78 I/O General I/O port pin PB2 76 I/O General I/O port pin PB3 74 I/O General I/O port pin PB4 73 I/O General I/O port pin PB5 72 I/O General I/O port pin PB6 67 I/O General I/O port pin PB7 66 I/O General I/O port pin Port Pin Signal Name Pin No. In/Out Function Basic Alternate

UPSD3212C, UPSD3212CV

52 PIN PACKAGE I/O PORT

The 52-pin package members of the uPSD321X Devices have the same port pins as those of the 80-pin package except: ■ Port 0 (P0.0-P0.7, external address/data bus AD0-AD7) ■ Port 2 (P2.0-P2.3, external address bus A8- A11) ■ Port A (PA0-PA7) ■ Port D (PD2) ■ Bus control signal (RD,WR,PSEN,ALE) Pin 5 requires a pull-up resistor (2kΩ for 3V de- vices, 7.5kΩ for 5V devices) for all devices. PC0 TMS 20 I JTAG pin 1. PLD Macro-cell outputs 2. PLD inputs 3. SRAM stand by voltage input (VSTBY ) 4. SRAM battery-on indicator (PC4) 5. JTAG pins are dedicated pins PC1 TCK 16 I JTAG pin PC2 VSTBY 15 I/O General I/O port pin PC3 TSTAT 14 I/O General I/O port pin PC4 TERR 9 I/O General I/O port pin PC5 TDI 7 I JTAG pin PC6 TDO 6 O JTAG pin PC7 5 I/O General I/O port pin PD1 CLKIN 3 I/O General I/O port pin 1. PLD I/O 2. Clock input to PLD and APD PD2 CSI 1 I/O General I/O port pin 1. PLD I/O 2. Chip select to PSD Module Vcc 12 Vcc 50 GND 13 GND 29 GND 69 NC 10 NC 11 NC 17 NC 71 Port Pin Signal Name Pin No. In/Out Function Basic Alternate

tails on mapping of the Flash memory. ternal and external) that can be read and written. isters can be accessed by Direct addressing only. Figure 5. Memory Map and Address Space

Figure 9. PSW (Program Status Word) Register is assigned a fixed location in Program Memory. locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. data to be retained in the event of a power lost. The battery is connected to the Port C PC2 pin. Figure 10. Interrupt Location of Program

8 Bytes

Table 4. Arithmetic Instructions will leave the Accumulator holding 00010001B. the <byte> operand are listed in Table 5. push it onto the stack in the service routine. right rotation, the LSB rolls into the MSB position. Accumulator, and the ones digit to the low nibble.

Table 5. Logical Instructions

(DPTR) for look-up tables in Program Memory. mulator and ad-dressed byte to exchange data. number one digit, using the XCHD instruction. Table 6. Data Transfer Instructions that Access Internal Data Memory Space

0s, the lost digit is moved to the Accumulator. Table 7. Shifting a BCD Number Two Digits to Table 8. Shifting a BCD Number Two Digits to Table 9. Shifting a BCD Number One Digit to the Right

Memory. Only indirect addressing can be used. is set up to point to the beginning of the table. PC contains the address of the RET instruction. Table 10. Data Transfer Instruction that Access External Data Memory Space Table 11. Lookup Table READ Instruction

any amount of byte-oriented software. the PSW register, which is bit-addressable. C instruction is jumped over. to the bit-test instructions. arithmetic if the jump is executed. Table 12. Boolean Instructions

which way the jump is en-coded. relative to the instruction following the SJMP. where in the 64K Program Memory space. bits in the PC. The high 5 bits stay the same. 2K block as the instruction following the AJMP. of range” message is written into the List file. does not care which way the address is encoded. then the RETI is functionally identical to RET. Table 13. Unconditional Jump Instructions

2Ah. The initial data in R1 was 2Eh. second, then the Carry Bit is cleared. states and phases for various kinds of instructions. and the Program Counter is not incremented. the end of State 6 of this machine cycle. is the only time program retrievals are skipped. tion is shown in Figure 14, page 30 (d). Table 14. Conditional Jump Instructions

Figure 14. State Sequence in uPSD321X Devices

Ports 0-4 in the MCU Module. program or data address space. Figure 15. uPSD321X Devices Functional Modules

2 UARTs

3 Timer /

256 Byte SRAM

8032 Core

8032 Internal Bus

Table 15. SFR Memory Map

98 SCON SBUF SCON2 SBUF2 9F

90 P1(1) P1SFS P3SFS P4SFS ASCL ADAT ACON 97

88 TCON (1) TMOD TL0 TL1 TH0 TH1 8F

80 P0(1) SP DPL DPH PCON 87

Table 16. List of all SFR

80 P0 FF Port 0

81 SP 07 Stack Ptr

82 DPL 00 Data Ptr Low

83 DPH 00 Data Ptr High

87 PCON SMOD SMOD1 LVREN ADSFINT RCLK1 TCLK1 PD IDLE 00 Power Ctrl

88 TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 Timer / Cntr

89 TMOD Gate C/T M1 M0 Gate C/T M1 M0 00 Timer / Cntr

90 P1 FF Port 1

91 P1SFS P1S7 P1S6 P1S5 P1S4 00 Port 1 Select

93 P3SFS P3S7 P3S6 00 Port 3 Select

94 P4SFS P4S7 P4S6 P4S5 P4S4 P4S3 P4S2 P4S1 P4S0 00 Port 4 Select

95 ASCL 00

96 ADAT ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2 ADAT1 ADAT0 00 ADC Data

97 ACON ADEN ADS1 ADS0 ADST ADSF 00 ADC Control

98 SCON SM0 SM1 SM2 REN TB8 RB8 TI RI 00 Serial Control

99 SBUF 00 Serial Buffer

UPSD3212C, UPSD3212CV A3 PWM1 00 PWM1 Output Duty Cycle A4 PWM2 00 PWM2 Output Duty Cycle A5 PWM3 00 PWM3 Output Duty Cycle A6 WDRST 00 Watch Dog Reset A7 IEA ES2 EI2C 00 Interrupt Enable (2nd) A8 IE EA - ET2 ES ET1 EX1 ET0 EX0 00 Interrupt Enable AA PWM4P 00 PWM 4 Period AB PWM4W 00 PWM 4 Pulse Width AE WDKEY 00 Watch Dog Key Register B0 P3 FF Port 3 B1 PSCL0L 00 Prescaler 0 Low (8-bit) B2 PSCL0H 00 Prescaler 0 High (8-bit) B3 PSCL1L 00 Prescaler 1 Low (8-bit) B4 PSCL1H 00 Prescaler 1 High (8-bit) B7 IPA PS2 PI2C 00 Interrupt Priority (2nd) B8 IP PT2 PS PT1 PX1 PT0 PX0 00 Interrupt Priority C0 P4 FF New Port 4 C8 T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00 Timer 2 Control C9 T2MOD DCEN 00 Timer 2 Mode CA RCAP2L 00 Timer 2 Reload low CB RCAP2H 00 Timer 2 Reload High SFR Addr Reg Name Bit Register Name Reset Value Comments 76 5 4 3 2 1 0

UPSD3212C, UPSD3212CV CC TL2 00 Timer 2 Low byte CD TH2 00 Timer 2 High byte D0 PSW CY AC FO RS1 RS0 OV P 00 Program Status Word D2 S2SETUP 00 I2C (S2) Setup DA DB DC S2CON CR2 EN1 STA STO ADDR AA CR1 CR0 00 I 2C Bus Control Reg DD S2STA GC Stop Intr TX-Md Bbusy Blost ACK_R SLV 00 I2C Bus Status DE S2DAT 00 Data Hold Register DF S2ADR 00 I2C address E0 ACC 00 Accumulator F0 B 00 B Register SFR Addr Reg Name Bit Register Name Reset Value Comments 76 5 4 3 2 1 0

Table 17. PSD Module Register Address Offset

00 Data In (Port A) Reads Port pins as input

04 Data Out (Port A) Latched data for output to Port pins, I/O Output Mode 00

Reads the status of the output enable control to the Port pin driver. Bit = 0 indicates pin is in input mode.

01 Data In (Port B)

03 Control (Port B) 00

05 Data Out (Port B) 00

07 Direction (Port B) 00

09 Drive (Port B) 00

10 Data In (Port C)

12 Data Out (Port C) 00

14 Direction (Port C) 00

16 Drive (Port C) 00

18 Input Macrocell

11 Data In (Port D) * * * * * * Only Bit 1 and

13 Data Out (Port D) * * * * * * 00 Only Bit 1 and

15 Direction (Port D) * * * * * * 00 Only Bit 1 and

17 Drive (Port D) * * * * * * 00 Only Bit 1 and

20 Output

UPSD3212C, UPSD3212CV Note: (Register address = csiop address + address offset; where csiop address is defined by user in PSDsoft) * indicates bit is not used and need to set to '0.'

21 Output

22 Mask Macrocells

23 Mask Macrocells

Sec3_ Prot Sec2_ Prot Sec1_ Prot Sec0_ Prot Bit = 1 sector is protected C2 Secondary Flash Protection Security Prot Sec0_ Prot Security Bit = 1 device is secured B0 PMMR0 * * PLD Mcells clk PLD array- clk PLD Turbo * APD enable *0 0 Control PLD power consumption B4 PMMR2 * PLD array Ale PLD array Cntl2 PLD array Cntl1 PLD array Cntl0 0 0 Blocking inputs to PLD array E0 Page 00 Page Register E2 VM Periph- mode FL_ data Boot_ data FL_ code Boot_ code SR_ code Configure

8032 Program

UPSD3212C, UPSD3212CV INTERRUPT SYSTEM There are interrupt requests from 10 sources as follows (see Figure 16, page 39). ■ INT0 External Interrupt ■ 2nd USART Interrupt ■ Timer 0 Interrupt ■ I2C Interrupt ■ INT1 External Interrupt (or ADC Interrupt) ■ Timer 1 Interrupt ■ USART Interrupt ■ Timer 2 Interrupt External Int0 – The INT0 can be either level-active or transition- active depending on Bit IT0 in register TCON. The flag that actually generates this interrupt is Bit IE0 in TCON. – When an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated. – If the interrupt was level activated then the inter- rupt request flag remains set until the requested interrupt is actually generated. Then it has to de- activate the request before the interrupt service routine is completed, or else another interrupt will be generated. Timer 0 and 1 Interrupts – Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1 which are set by an overflow of their respective Timer/Counter registers (except for Timer 0 in Mode 3). – These flags are cleared by the internal hard- ware when the interrupt is serviced. Timer 2 Interrupt – Timer 2 Interrupt is generated by TF2 which is set by an overflow of Timer 2. This flag has to be cleared by the software - not by hardware. – It is also generated by the T2EX signal (Timer 2 External Interrupt P1.1) which is controlled by EXEN2 and EXF2 Bits in the T2CON register. I 2C Interrupt – The interrupt of the I2C is generated by Bit INTR in the register S2STA. – This flag is cleared by hardware. External Int1 – The INT1 can be either level active or transition active depending on Bit IT1 in register TCON. The flag that actually generates this interrupt is Bit IE1 in TCON. – When an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated. – If the interrupt was level activated then the inter- rupt request flag remains set until the requested interrupt is actually generated. Then it has to de- activate the request before the interrupt service routine is completed, or else another interrupt will be generated. – The ADC can take over the External INT1 to generate an interrupt on conversion being com- pleted

Figure 16. Interrupt System

ceive Interrupt) OR TI (Transmit Interrupt). tional interrupt control registers (A7H, B7H). sequence determines which request is serviced. Table 18. Priority Levels Table 19. SFR Register

Table 20. Description of the IE Bits. Table 21. Description of the IEA Bits Table 22. Description of the IP Bits

5 ET2 Enable Timer 2 Interrupt

4 ES Enable USART Interrupt

3 ET1 Enable Timer 1 Interrupt

2 EX1 Enable External Interrupt (Int1)

1 ET0 Enable Timer 0 Interrupt

0 EX0 Enable External Interrupt (Int0)

4 ES2 Enable 2nd USART Interrupt

1 EI2C Enable I²C Interrupt

5 PT2 Timer 2 Interrupt priority level

4 PS USART Interrupt priority level

3 PT1 Timer 1 Interrupt priority level

2 PX1 External Interrupt (Int1) priority level

1 PT0 Timer 0 Interrupt priority level

0 PX0 External Interrupt (Int0) priority level

Table 23. Description of the IPA Bits level is already in progress. in the execution of the instruction in progress. membered. Every polling cycle is new. tored to as shown in Table 24. continues from where it left off. Table 24. Vector Addresses

4 PS2 2nd USART Interrupt priority level

1 PI2C I²C Interrupt priority level

consumption are implemented (see Table 25). The following Functions are Switched Off. maintain their data during Idle Mode. There are three ways to terminate the Idle Mode. complete the RESET operation. 3 machine cycles in all cases. cuted prior to going into the Power-down Mode. Special Function Register are preserved. Table 25. Power-Saving Mode Power Consumption Table 26. Pin Status During Idle and Power-down Mode

Table 27. Description of the PCON Bits tional special peripheral functions (see Table 28). Table 28. I/O Port Functions

7 SMOD Double Baud Data Rate Bit UART

6 SMOD1 Double Baud Data Rate Bit 2nd UART

5 LVREN LVR Disable Bit (active High)

4 ADSFINT Enable ADC Interrupt

3 RCLK1

2 TCLK1 (1) Transmit Clock Flag (UART 2)

1 PD Activate Power-down Mode (High enable)

0 IDL Activate Idle Mode (High enable)

P1.3 are default to GPIO after reset. Table 29. P1SFS (91H) Table 30. P3SFS (93H) Table 31. P4SFS (94H)

Figure 17. PORT Type and Description (Part 1)

■ Via the internal LVR Block. The RESET mechanism is illustrated in Figure 20. an active low reset input to the PSD Module. AC spec on other RESET timing requirements. sis and 1µs noise-cancelling delay. Figure 20. RESET

venting the processor running out of control. SFR and Watchdog Key Register (WDKEY). concerned with servicing it. value between 00-7EH to the WDRST register. generate a flexible Watchdog time out period. Writing a “00” to WDRST clears the counter. the function of the watchdog timer is needed. Table 32. Watchdog Timer Key Register (WDKEY: 0AEH) Table 33. Description of the WDKEY Bits Enable or disable Watchdog Timer.

frequency. The reset period is TfOSC x 12 x 222. The RESET pulse width is TfOSC x 12 x 215. Figure 21. RESET Pulse Width Table 34. Watchdog Timer Clear Register (WDRST: 0A6H) Table 35. Description of the WDRST Bits Note: The Watchdog Timer (WDT) is enabled at power-up or reset and must be served or disabled. To reset Watchdog Timer, write any value beteen 00h and 7Eh to this register. This value is loaded to the 7 most significant bits of the 22-bit counter.

Counter registers: Timer 0, Timer 1 and Timer 2. 1 have four operating modes from which to select. erating modes are de-scribed in the following text. Table 36. Control Register (TCON) Table 37. Description of the TCON Bits

Table 38. TMOD Register (TMOD) Table 39. Description of the TMOD Bits

5 M1 (M1,M0)=(0,0): 13-bit Timer/Counter, TH1, with TL1 as 5-bit prescaler

(M1,M0)=(0,1): 16-bit Timer/Counter. TH1 and TL1 are cascaded. There is no prescaler.

1 M1 (M1,M0)=(0,0): 13-bit Timer/Counter, TH0, with TL0 as 5-bit prescaler

(M1,M0)=(0,1): 16-bit Timer/Counter. TH0 and TL0 are cascaded. There is no prescaler.

Mode 0 operation as it applies to Timer 1. put /INT1, to facilitate pulse width measurements). run flag does not clear the registers. that the Timer register is being run with all 16 bits. Figure 22. Timer/Counter Mode 0: 13-bit Counter

tions which are selected by Bit EXEN2 in T2CON. ture Mode is illustrated in Figure 24, page 56. tions, which are selected by bit EXEN2 in T2CON. conjunction with the serial port. Figure 23. Timer/Counter Mode 2: 8-bit Auto-reload Table 40. Timer/Counter 2 Control Register (T2CON)

Table 41. Timer/Counter 2 Operating Modes Table 42. Description of the T2CON Bits Note: 1. The RCLK1 and TCLK1 Bits in the PCON Register control UART 2, and have the same function as RCLK and TCLK.

5 RCLK

4 TCLK (1)

3 EXEN2

of a negative transition on T2EX if Timer 2 is not being used to clock the serial port.

0 CP/RL 2

Mode 3. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. in any application not requiring an interrupt. Figure 26. Timer/Counter Mode 3: Two 8-bit Counters

UPSD3212C, UPSD3212CV STANDARD SERIAL INTERFACE (UART) The uPSD321X Devices provides two standard 8032 UART serial ports. The first port is connected to pin P3.0 (RX) and P3.1 (TX). The second port is connected to pin P1.2 (RX) and P1.3(TX). The op- eration of the two serial ports are the same and are controlled by the SCON and SCON2 registers. The serial port is full duplex, meaning it can trans- mit and receive simultaneously. It is also receive- buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF (or SBUF2 for the second serial port). Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0. Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are trans- mitted/received (LSB first). The baud rate is fixed at 1/12 the f OSC . Mode 1. 10 bits are transmitted (through TxD) or received (through RxD): a start Bit (0), 8 data bits (LSB first), and a Stop Bit (1). On receive, the Stop Bit goes into RB8 in Special Function Register SCON. The baud rate is variable. Mode 2. 11 bits are transmitted (through TxD) or received (through RxD): start Bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a Stop Bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of '0' or '1.' Or, for example, the Parity Bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCON, while the Stop Bit is ignored. The baud rate is pro- grammable to either 1/32 or 1/64 the oscillator fre- quency. Mode 3. 11 bits are transmitted (through TxD) or received (through RxD): a Start Bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a Stop Bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination regis- ter. Reception is initiated in Mode 0 by the condi- tion RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = Multiprocessor Communications Modes 2 and 3 have a special provision for multi- processor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a Stop Bit. The port can be pro- grammed such that when the Stop Bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting Bit SM2 in SCON. A way to use this feature in multi-proces- sor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is '1' in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupt- ed by a data byte. An ad-dress byte, however, will interrupt all slaves, so that each slave can exam- ine the received byte and see if it is being ad- dressed. The addressed slave will clear its SM2 Bit and prepare to receive the data bytes that will be coming. The slaves that weren’t being ad- dressed leave their SM2s set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the Stop Bit. In a Mode 1 reception, if SM2 = 1, the Receive Inter- rupt will not be activated unless a valid Stop Bit is received.

Figure 27. Serial Port Mode 0, Block Diagram Table 43. Serial Port Control Register (SCON)

Table 44. Description of the SCON Bits

UPSD3212C, UPSD3212CV Baud Rates. The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = fOSC / 12 The baud rate in Mode 2 depends on the value of Bit SMOD = 0 (which is the value on reset), the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. Mode 2 Baud Rate = (2 SMOD / 64) x fOSC In the uPSD321X Devices, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate. Using Timer 1 to Generate Baud Rates.When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows (see Table 45, page 62): Mode 1,3 Baud Rate = SMOD / 32) x (Timer 1 overflow rate) The Timer 1 Interrupt should be disabled in this application. The Timer itself can be configured for either “timer” or “counter” operation, and in any of its 3 running modes. In the most typical applica- tions, it is configured for “timer” operation, in the Auto-reload Mode (high nibble of TMOD = 0010B). In that case the baud rate is given by the formula: Mode 1,3 Baud Rate = SMOD / 32) x (fOSC / (12 x [256 – (TH1)])) One can achieve very low baud rates with Timer 1 by leaving the Timer 1 Interrupt enabled, and con- figuring the Timer to run as a 16-bit timer (high nib- ble of TMOD = 0001B), and using the Timer 1 Interrupt to do a 16-bit software reload. Figure 22 lists various commonly used baud rates and how they can be obtained from Timer 1. Using Timer/Counter 2 to Generate Baud Rates. In the uPSD321X Devices, Timer 2 select- ed as the baud rate generator by setting TCLK and/or RCLK (see Figure 22, page 53 Timer/ Counter 2 Control Register (T2CON)). Note: The baud rate for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer into its Baud Rate Generator Mode. The RCLK and TCLK Bits in the T2CON register configure UART 1. The RCLK1 and TCLK1 Bits in the PCON register configure UART 2. The Baud Rate Generator Mode is similar to the Auto-reload Mode, in that a roll over in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. Now, the baud rates in Modes 1 and 3 are deter- mined at Timer 2’s overflow rate as follows: Mode 1,3 Baud Rate = Timer 2 Overflow Rate / 16 The timer can be configured for either “timer” or “counter” operation. In the most typical applica- tions, it is configured for “timer” operation (C/T2 = 0). “Timer” operation is a little different for Timer 2 when it’s being used as a baud rate generator. Normally, as a timer it would increment every ma- chine cycle (thus at the 1/6 the CPU clock frequen- cy). In the case, the baud rate is given by the formula: Mode 1,3 Baud Rate = f OSC / (32 x [65536 - (RCAP2H, RCAP2L)] where (RCAP2H, RCAP2L) is the content of RC2H and RC2L taken as a 16-bit unsigned inte- ger. Timer 2 also be used as the Baud Rate Generating Mode. This mode is valid only if RCLK + TCLK = 1 in T2CON or in PCON. Note: A roll-over in TH2 does not set TF2, and will not generate an interrupt. Therefore, the Timer in- terrupt does not have to be disabled when Timer 2 is in the Baud Rate Generator Mode. Note: If EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt, if de- sired. It should be noted that when Timer 2 is running (TR2 = 1) in “timer” function in the Baud Rate Gen- erator Mode, one should not try to READ or WRITE TH2 or TL2. Under these conditions the timer is being incremented every state time, and the results of a READ or WRITE may not be accu- rate. The RC registers may be read, but should not be written to, because a WRITE might overlap a reload and cause WRITE and/or reload errors. Turn the timer off (clear TR2) before accessing the Timer 2 or RC registers, in this case.

Table 45. Timer 1-Generated Commonly Used Baud Rates the TX Control block to commence a transmission. transmit shift are shifted to the right one position.

UPSD3212C, UPSD3212CV More About Modes 2 and 3.Eleven bits are transmitted (through TxD), or received (through RxD): a Start Bit (0), 8 data bits (LSB first), a pro- grammable 9th data bit, and a Stop Bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of '0' or '1.' On receive, the data bit goes into RB8 in SCON. The baud rate is programma- ble to either 1/16 or 1/32 the CPU clock frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1. Figure 31, page 66 and Figure 33, page 67 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The “WRITE to SBUF” signal also loads TB8 into the 9th bit po- sition of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next roll-over in the divide-by- 16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “WRITE to SBUF” signal.) The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that (see Figure 32, page 66 and Figure 34, page 67). The first shift clocks a '1' (the Stop Bit) into the 9th bit position of the shift register. There-after, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the out-put position of the shift register, then the Stop Bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then de- activate SEND and set TI. This occurs at the 11th divide-by 16 rollover after “WRITE to SUBF.” Reception is initiated by a detected 1-to-0 transi- tion at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been es- tablished. When a transition is detected, the di- vide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of R-D. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not '0,' the receive circuits are reset and the unit goes back to looking for an- other 1-to-0 transition. If the Start Bit proves valid, it is shifted into the input shift register, and recep- tion of the rest of the frame will proceed. As data bits come in from the right, '1s' shift out to the left. When the Start Bit arrives at the left-most position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following con- ditions are met at the time the final shift pulse is generated: 1. RI = 0, and 2. Either SM2 = 0, or the received 9th data bit = 1 If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input.

Table 46. ADC SFR Memory Map Table 47. Description of the ACON Bits Table 48. ADC Clock Input

UPSD3212C, UPSD3212CV PULSE WIDTH MODULATION (PWM) The PWM block has the following features: ■ Four-channel, 8-bit PWM unit with 16-bit prescaler ■ One-channel, 8-bit unit with programmable frequency and pulse width ■ PWM Output with programmable polarity 4-channel PWM Unit (PWM 0-3) The 8-bit counter of a PWM counts module 256 (i.e., from 0 to 255, inclusive). The value held in the 8-bit counter is compared to the contents of the Special Function Register (PWM 0-3) of the corre- sponding PWM. The polarity of the PWM outputs is programmable and selected by the PWML Bit in PWMCON register. Provided the contents of a PWM 0-3 register is greater than the counter val- ue, the corresponding PWM output is set HIGH (with PWML = 0). When the contents of this regis- ter is less than or equal to the counter value, the corresponding PWM output is set LOW (with PWML = 0). The pulse-width-ratio is therefore de- fined by the contents of the corresponding Special Function Register (PWM 0-3) of a PWM. By load- ing the corresponding Special Function Register (PWM 0-3) with either 00H or FFH, the PWM out- put can be retained at a constant HIGH or LOW level respectively (with PWML = 0). For each PWM unit, there is a 16-bit Prescaler that are used to divide the main system clock to form the input clock for the corresponding PWM unit. This prescaler is used to define the desired repeti- tion rate for the PWM unit. SFR registers B1h - B2h are used to hold the 16-bit divisor values. The repetition frequency of the PWM output is giv- en by: fPWM 8 = (fOSC / prescaler0) / (2 x 256) And the input clock frequency to the PWM counters is = fOSC / 2 / (prescaler data value + 1) See the I/O PORTS (MCU Module), page 44 for more information on how to configure the Port 4 pin as PWM output.

Figure 36. Four-Channel 8-bit PWM Block Diagram

Table 49. PWM SFR Memory Map

Figure 37. Programmable PWM 4 Channel Block Diagram

enable/disable and polarity of the PWM 4 channel. Figure 38. PWM 4 With Programmable Pulse Width and Frequency

control arbitration are all controlled by hardware. handling and operates in 4 modes. used as a vector to various service routines. – S2DAT: data shift register. recognition is performed by On-Chip H/W. Figure 39. Block Diagram of the I

Table 50. Serial Control Register (S2CON) Table 51. Description of the S2CON Bits Table 52. Selection of the Serial Clock Frequency SCL in Master Mode repeated START condition when this bit is set. STOP Flag. With this bit set while in Master Mode a STOP condition is generated. set, STOP condition in Master Mode is generated after 1 cycle interrupt period. 3 ADDR This bit is set when address byte was received. Must be cleared by software.

• Own slave address is received
• A data byte is received while the device is programmed to be a Master Receiver
• A data byte is received while the device is a selected Slave Receiver. When this bit is reset, no acknowledge is returned. SIO release SDA line as high during the acknowledge clock pulse. 1C R 1 These two bits along with the CR2 Bit determine the serial clock frequency when SIO is in the Master Mode.0C R 0 CR2 CR1 CR0 f OSC Divisor Bit Rate (kHz) at fOSC 12MHz 24MHz 36MHz 40MHz 0 0 0 16 375 750 X X 0 0 1 24 250 500 750 833 0 1 0 30 200 400 600 666 0 1 1 60 100 200 300 333 1 0 0 120 50 100 150 166 1 0 1 240 25 50 75 83 1 1 0 480 12.5 25 37.5 41 1 1 1 960 6.25 12.5 18.75 20

interface are given Table 54.

1. Own slave address has been received during
2. The general call address has been received
3. A data byte has been received or transmitted in
4. A data byte has been received or transmitted as
5. A stop condition is received as selected slave

Table 53. Serial Status Register (S2STA) Table 54. Description of the S2STA Bits Note: 1. Interrupt Flag Bit (INTR, S2STA Bit 5) is cleared by Hardware as reading S2STA register.

1. I2C Interrupt Flag (INTR) can occur in below case.

Table 55. Data Shift Register (S2DAT)

7 GC General Call Flag

4 TX_MODE Transmission Mode Flag.

when programmed as a slave receive/transmitter. Table 56. Address Register (S2ADR) Note: SLA6 to SLA0: Own slave address. Table 57. Start /Stop Hold Time Detection Register (S2SETUP) Table 58. System Cock of 40MHz Table 59. System Clock Setup Examples

UPSD3212C, UPSD3212CV PSD MODULE ■ The PSD Module provides configurable Program and Data memories to the 8032 CPU core (MCU). In addition, it has its own set of I/O ports and a PLD with 16 macrocells for general logic implementation. ■ Ports A,B,C, and D are general purpose programmable I/O ports that have a port architecture which is different from the I/O ports in the MCU Module. ■ The PSD Module communicates with the MCU Module through the internal address, data bus (A0-A15, D0-D7) and control signals (RD, WR, PSEN , ALE, RESET). The user defines the Decoding PLD in the PSDsoft Development Tool and can map the resources in the PSD Module to any program or data address space. Figure 40 shows the functional blocks in the PSD Module. Functional Overview ■ 512Kbit Flash memory. This is the main Flash memory. It is divided into 4 sectors (16KBytes each) that can be accessed with user-specified addresses. ■ Secondary 128Kbit Flash boot memory. It is divided into 2 sectors (8KBytes each) that can be accessed with user-specified addresses. This secondary memory brings the ability to execute code and update the main Flash concurrently. ■ 16Kbit SRAM. The SRAM’s contents can be protected from a power failure by connecting an external battery. ■ CPLD with 16 Output Micro Cells (OMCs) and up to 20 Input Micro Cells (IMCs). The CPLD may be used to efficiently implement a variety of logic functions for internal and external control. Examples include state machines, loadable shift registers, and loadable counters. ■ Decode PLD (DPLD) that decodes address for selection of memory blocks in the PSD Module. ■ Configurable I/O ports (Port A,B,C and D) that can be used for the following functions: – MCU I/Os –P L D I / O s – Latched MCU address output – Special function I/Os. – I/O ports may be configured as open drain outputs. ■ Built-in JTAG compliant serial port allows full- chip, In-System Programmability (ISP). With it, you can program a blank device or reprogram a device in the factory or the field. ■ Internal page register that can be used to expand the 8032 MCU Module address space by a factor of 256. ■ Internal programmable Power Management Unit (PMU) that supports a low-power mode called Power-down Mode. The PMU can automatically detect a lack of the 8032 CPU core activity and put the PSD Module into Power-down Mode. ■ Erase/WRITE cycles: – Flash memory - 100,000 minimum – PLD - 1,000 minimum – Data Retention: 15 year minimum (for Main Flash memory, Boot, PLD and Configuration bits)

Figure 40. PSD MODULE Block Diagram

8 SECTORS

2 EXT CS TO PORT D

20 INPUT MACROCELLS

2 SECTORS

16 OUTPUT MACROCELLS

8032 Bus

tional blocks of the PSD MODULE. Table 60. Methods of Programming Different Functional Blocks of the PSD MODULE

1. PSDsoft is available from our web site (the ad-

or other distribution channels. our web site for the current list. Figure 41. PSDsoft Express Development Tool atorial and registered logic in CPLD.

Table 61. Register Address Offset Note: 1. Other registers that are not part of the I/O ports. and/or Data space on an individual basis.

UPSD3212C, UPSD3212CV PSD MODULE DETAILED OPERATION As shown in Figure 15, the PSD MODULE con- sists of five major types of functional blocks: ■ Memory Block ■ PLD Blocks ■ I/O Ports ■ Power Management Unit (PMU) ■ JTAG Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. MEMORY BLOCKS The PSD MODULE has the following memory blocks: ■ Primary Flash memory ■ Secondary Flash memory ■ SRAM The Memory Select signals for these blocks origi- nate from the Decode PLD (DPLD) and are user- defined in PSDsoft Express. Primary Flash Memory and Secondary Flash memory Description The primary Flash memory is divided into 4 sec- tors (16KBytes each). The secondary Flash mem- ory is divided into 2 sectors (8KBytes each). Each sector of either memory block can be separately protected from Program and Erase cycles. Flash memory may be erased on a sector-by-sec- tor basis. Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading. During a Program or Erase cycle in Flash memory, the status can be output on Ready/Busy (PC3). This pin is set up using PSDsoft Express Configu- ration. Memory Block Select Signals The DPLD generates the Select signals for all the internal memory blocks (see the section entitled “PLDs,” page 97). Each of the eight sectors of the primary Flash memory has a Select signal (FS0- FS3) which can contain up to three product terms. Each of the 2 sectors of the secondary Flash memory has a Select signal (CSBOOT0- CSBOOT1) which can contain up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped in Pro- gram or Data space. Ready/Busy (PC3).This signal can be used to output the Ready/Busy status of the Flash memo- ry. The output on Ready/Busy (PC3) is a 0 (Busy) when Flash memory is being written to, or when Flash memory is being erased. The output is a 1 (Ready) when no WRITE or Erase cycle is in progress. Memory Operation. The primary Flash memory and secondary Flash memory are addressed through the MCU Bus. The MCU can access these memories in one of two ways: – The MCU can execute a typical bus WRITE or READ operation. – The MCU can execute a specific Flash memory instruction that consists of several WRITE and READ operations. This involves writing specific data patterns to special addresses within the Flash memory to invoke an embedded algo- rithm. These instructions are summarized in Ta- ble 62. Typically, the MCU can read Flash memory using READ operations, just as it would read a ROM de- vice. However, Flash memory can only be altered using specific Erase and Program instructions. For example, the MCU cannot write a single byte di- rectly to Flash memory as it would write a byte to RAM. To program a byte into Flash memory, the MCU must execute a Program instruction, then test the status of the Program cycle. This status test is achieved by a READ operation or polling Ready/Busy (PC3).

UPSD3212C, UPSD3212CV Instructions An instruction consists of a sequence of specific operations. Each received byte is sequentially de- coded by the PSD MODULE and not executed as a standard WRITE operation. The instruction is ex- ecuted when the correct number of bytes are prop- erly received and the time between two consecutive bytes is shorter than the time-out pe- riod. Some instructions are structured to include READ operations after the initial WRITE opera- tions. The instruction must be followed exactly. Any in- valid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory resets the device logic into READ Mode (Flash memory is read like a ROM device). The Flash memory supports the instructions sum- marized in Table 62: Flash memory: ■ Erase memory by chip or sector ■ Suspend or resume sector erase ■ Program a Byte ■ RESET to READ Mode ■ Read Sector Protection Status These instructions are detailed in Table 62. For ef- ficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. The coded cycles consist of writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cy- cle. Address signals A15-A12 are Don’t Care dur- ing the instruction WRITE cycles. However, the appropriate Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1) must be selected. The primary and secondary Flash memories have the same instruction set. The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memo- ry is selected if any one of Sector Select (FS0- FS3) is High, and the secondary Flash memory is selected if any one of Sector Select (CSBOOT0- CSBOOT1) is High.

Table 62. Instructions

1. All values are in hexadecimal:

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of WRITE Strobe (WR, CNTL0). PA is an even address for PSD in Word Programming Mode. erased, or verified, must be Active (High).

1. Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1) signals are active High, and are defined in PSDsoft Express.
2. Only address Bits A11-A0 are used in instruction decoding.
3. No Unlock or instruction cycles are required when the device is in the READ Mode
4. The RESET Instruction is required to return to the READ Mode after reading the Sector Protection Status, or if the Error Flag Bit
5. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs.
6. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
7. The system may perform READ and Program cycles in non-erasing sectors, read the Sector Protection Status when in the Suspend

Sector Erase Mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.

1. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase Mode.
2. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is

Status of the primary Flash memory.

UPSD3212C, UPSD3212CV Power-down Instruction and Power-up Mode Power-up Mode. The PSD MODULE internal logic is reset upon Power-up to the READ Mode. Sector Select (FS0-FS3 and CSBOOT0- CSBOOT1) must be held Low, and WRITE Strobe (WR , CNTL0) High, during Power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of WRITE Strobe (WR , CNTL0). Any WRITE cycle initiation is locked when VCC is below VLKO . READ Under typical conditions, the MCU may read the primary Flash memory or the secondary Flash memory using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to obtain status information about a Program or Erase cycle that is currently in progress. Lastly, the MCU may use instructions to read special data from these memory blocks. The following sections describe these READ functions. READ Memory Contents. Primary Flash memo- ry and secondary Flash memory are placed in the READ Mode after Power-up, chip reset, or a Reset Flash instruction (see Table 62, page 86). The MCU can read the memory contents of the pri- mary Flash memory or the secondary Flash mem- ory by using READ operations any time the READ operation is not part of an instruction. READ Memory Sector Protection Status.The primary Flash memory Sector Protection Status is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ opera- tion (see Table 62). During the READ operation, address Bits A6, A1, and A0 must be '0,' '1,' and '0,' respectively, while Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1) designates the Flash memory sector whose protection has to be veri- fied. The READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (primary Flash memory or secondary Flash mem- ory) can also be read by the MCU accessing the Flash Protection registers in PSD I/O space. See the section entitled “Flash Memory Sector Pro- tect,” page 92, for register definitions. Reading the Erase/Program Status Bits.The Flash memory provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 63, page 88. The status bits can be read as many times as needed. For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See the section entitled “Programming Flash Memory,” page 89, for de- tails. Data Polling Flag (DQ7).When erasing or pro- gramming in Flash memory, the Data Polling Flag Bit (DQ7) outputs the complement of the bit being entered for programming/writing on the DQ7 Bit. Once the Program instruction or the WRITE oper- ation is completed, the true logic value is read on the Data Polling Flag Bit (DQ7) (in a READ opera- tion). – Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). It must be performed at the address being pro- grammed or at an address within the Flash memory sector being erased. – During an Erase cycle, the Data Polling Flag Bit (DQ7) outputs a '0.' After completion of the cy- cle, the Data Polling Flag Bit (DQ7) outputs the last bit programmed (it is a '1' after erasing). – If the byte to be programmed is in a protected Flash memory sector, the instruction is ignored. – If all the Flash memory sectors to be erased are protected, the Data Polling Flag Bit (DQ7) is re- set to '0' for about 100µs, and then returns to the previous addressed byte. No erasure is per- formed.

to read any byte of the memory. accessible for a new READ or WRITE operation. the previous addressed byte. condition while attempting to program a byte. grammed byte belongs must no longer be used. Other Flash memory sectors may still be used. Table 63. Status Bit

1. DQ7-DQ0 represent the Data Bus bits, D7-D0.
2. FS0-FS3 and CSBOOT0-CSBOOT1 are active High.

ed. Figure 43 shows the Data Toggle algorithm. erased (not erased is logic '0'). byte that was intended to be written. Flag Bit (DQ6) and the Error Flag Bit (DQ5). Figure 43. Data Toggle Flowchart

does this before erasing to 0FFh. Flash memory does not accept any instructions. Table 62. Additional Flash Sector Erase codes progress, and reset the device to READ Mode. gramming Flash Memory,” page 89. cle, terminates the time out period. that was being erased outputs invalid data. erase cycle may be resumed with this instruction.

JTAG Port or a Device Programmer. operation results in a READ of the protected data. Flash memory Program or Erase cycle. of the Reset Flash instruction having been issued. Table 64. Sector Protection/Security Bit Definition – Flash Protection Register Sec<i>_Prot 1 = Primary Flash memory or secondary Flash memory Sector <i> is write-protected. Sec<i>_Prot 0 = Primary Flash memory or secondary Flash memory Sector <i> is not write-protected. Table 65. Sector Protection/Security Bit Definition – Secondary Flash Protection Register Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write-protected. Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write-protected. Security_Bit 0 = Security Bit in device has not been set; 1 = Security Bit in device has been set.

VM Register that resides in the CSIOP space. Table 66. VM Register

Table 67. DPLD and CPLD Inputs Note: 1. These inputs are not available in the 52-pin package. code PLD (DPLD), and the Complex PLD (CPLD). tion entitled “Complex PLD (CPLD),” page 100. Figure 48 shows the configuration of the PLDs. memory, registers, and I/O ports. The AND Array is used to form product terms. These product terms are specified using PSDsoft. put signals are shown in Table 67. block MCU control signals from entering the PLDs.

Figure 48. PLD Diagram

20 INPUT MACROCELL

16 OUTPUT

2 PORT D INPUTS

Figure 49. DPLD Logic Array

1. Inputs from the MCU module

4 PRIMARY FLASH

(ECS1-ECS2), routed to Port D. D do not consume any Output Macrocells (OMC). standard PLD macrocell architectures. Figure 50. Macrocell and I/O Port

input can use up to two product terms. Table 68. Output Macrocell Port and Data Bit Assignments Note: 1. McellAB0-McellAB7 can only be assigned to Port B in the 52-pin package.

1. Port PC0, PC1, PC5 and PC6 are assigned to JTAG pins, and are not available as macrocell outputs

terms and may borrow up to six more. Express performs this expansion as needed. Figure 51. CPLD Output Macrocell

(Mask Macrocell AB) with the value 0Fh. routed as an input to the AND Array. by the MCU through the internal data bus. one product term and 7-4 by another. Figure 52. Input Macrocell

■ Individual Port functionality. that pin is no longer available for other purposes. and B only) and PSDsoft Express Configuration. all connected to the Port Data Buffer (PDB). Figure 53. General I/O Port Architecture

UPSD3212C, UPSD3212CV The Port pin’s tri-state output driver enable is con- trolled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CPLD output in the PSDsoft, then the Direction Register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the MCU. The Port Data Buffer (PDB) feedback path allows the MCU to check the contents of the registers. Ports A, B, and C have embedded Input Macro- cells (IMC). The Input Macrocells (IMC) can be configured as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by Address Strobe (ALE) or a product term from the PLD AND Array. The outputs from the Input Macrocells (IMC) drive the PLD input bus and can be read by the MCU. See the section entitled “In- put Macrocell,” page 103. Port Operating Modes The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft, some by the MCU writing to the Control Registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft must be pro- grammed into the device and cannot be changed unless the device is reprogrammed. The modes that can be changed by the MCU can be done so dynamically at run-time. The PLD I/O, Data Port, Address Input, and Peripheral I/O Modes are the only modes that must be defined before program- ming the device. All other modes can be changed by the MCU at run-time. See Application Note AN1171 for more detail. Table 69 summarizes which modes are available on each port. Table 72 shows how and where the different modes are configured. Each of the port operating modes are described in the following sections. MCU I/O Mode In the MCU I/O Mode, the MCU uses the I/O Ports block to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD MODULE are mapped into the MCU address space. The ad- dresses of the ports are listed in Table 61. A port pin can be put into MCU I/O Mode by writing a '0' to the corresponding bit in the Control Regis- ter. The MCU I/O direction may be changed by writing to the corresponding bit in the Direction Register, or by the output enable product term. See the section entitled “Peripheral I/O Mode,” page 105. When the pin is configured as an out- put, the content of the Data Out Register drives the pin. When configured as an input, the MCU can read the port input through the Data In buffer. See Figure 53, page 104. Ports C and D do not have Control Registers, and are in MCU I/O Mode by default. They can be used for PLD I/O if equations are written for them in PS- Dabel. PLD I/O Mode The PLD I/O Mode uses a port as an input to the CPLD’s Input Macrocells (IMC), and/or as an out- put from the CPLD’s Output Macrocells (OMC). The output can be tri-stated with a control signal. This output enable control signal can be defined by a product term from the PLD, or by resetting the corresponding bit in the Direction Register to '0.' The corresponding bit in the Direction Register must not be set to '1' if the pin is defined for a PLD input signal in PSDsoft. The PLD I/O Mode is specified in PSDsoft by declaring the port pins, and then writing an equation assigning the PLD I/ O to a port. Address Out Mode Address Out Mode can be used to drive latched MCU addresses on to the port pins. These port pins can, in turn, drive external devices. Either the output enable or the corresponding bits of both the Direction Register and Control Register must be set to a '1' for pins to use Address Out Mode. This must be done by the MCU at run-time. See Table 71 for the address output pin assignments on Ports A and B for various MCUs. Peripheral I/O Mode Peripheral I/O Mode can be used to interface with external peripherals. In this mode, all of Port A serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O Mode is enabled by set- ting Bit 7 of the VM Register to a '1.' Figure 54 shows how Port A acts as a bi-directional buffer for the MCU data bus if Peripheral I/O Mode is en- abled. An equation for PSEL0 and/or PSEL1 must be written in PSDsoft. The buffer is tri-stated when PSEL0 or PSEL1 is low (not active). The PSEN signal should be “ANDed” in the PSEL equations to disable the buffer when PSEL resides in the data space. JTAG In-System Programming (ISP) Port C is JTAG compliant, and can be used for In- System Programming (ISP). For more information on the JTAG Port, see the section entitled “PRO- GRAMMING IN-CIRCUIT USING THE JTAG SE- RIAL INTERFACE,” page 118.

Figure 54. Peripheral I/O Mode Table 69. Port Operating Modes Note: 1. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins.

1. Port A is not available in the 52-pin package.
2. On pins PC2, PC3, PC4 and PC7 only.

Table 70. Port Operating Mode Settings

1. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product

term (.oe) from the CPLD AND Array. Table 71. I/O Port Latched Address Output Assignments

each bit in the register controls its respective pin. each register in Table 72 is 00h. and B have an associated Control Register. fault mode for all port pins is input. Register has sole control of a given pin’s direction. should be used for pins configured as Open Drain. '1.' The default pin drive is CMOS. ister is set to '1.' The default rate is slow slew. pins the slew rate can be set for. Table 72. Port Configuration Registers (PCR) Note: 1. See Table 76 for Drive Register Bit definition. Table 73. Port Pin Direction Control, Output Table 74. Port Pin Direction Control, Output Table 75. Port Direction Assignment Example

0 Input

1 Output

put is read through the Data In buffer. also be read back by the MCU. tion entitled “PLDs,” page 97. (IMC) can be used to latch or store external inputs. MCU. See the section entitled “PLDs,” page 97. and the pin is in input mode. Table 76. Drive Register Pin Assignment Note: 1. NA = Not Applicable. Table 77. Port Data Registers

McellBC0 can be connected to Port B or Port C. ■ CPLD Input – Via the Input Macrocells (IMC). address output as per Table 71. Figure 55. Port A and Port B Structure

can be connected to Port B or Port C. therefore no Control Register is required. Figure 56. Port C Structure

52-pin package). See Figure 57 and Figure 58. are used to configure pins PD2 and PD1. Figure 57. Port D Structure

term that can be configured active High or Low. Figure 58. Port D External Chip Select Signals

does not block CLKIN (PD1) from the APD Unit. Mode effects on PSD MODULE ports. that are independent of the Power-down Mode. setting bits in PMMR0 and PMMR2. Figure 60. Enable Power-down Flow Chart Table 78. Power-down Mode’s Effect on Ports

by the Turbo Bit (Bit 3) in PMMR0 (see Table 79). at a composite frequency of less than 15MHz. 5MHz from the maximum rated clock frequency. duce PLD AC power consumption. Voltage Standby (VSTBY , PC2) as a power source. the clock should be disabled to save AC power. trol signals should be disabled to save AC power. by setting Bits 2, 3, 4, 5, and 6 to a '1' in PMMR2. Table 79. Power Management Mode Registers PMMR0 Bit 0 X 0 Not used, and should be set to zero. 0 = off Automatic Power-down (APD) is disabled. 1 = on Automatic Power-down (APD) is enabled. Bit 2 X 0 Not used, and should be set to zero. 1 = offPLD Turbo Mode is off, saving power. 1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power. 0 = on CLKIN (PD1) input to the PLD macrocells is connected. 1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero.

Table 80. Power Management Mode Registers PMMR2 Note: The bits of this register are cleared to zero following Power-up. Subsequent RESET pulses do not clear the registers. Table 81. APD Counter Operation Bit 0 X 0 Not used, and should be set to zero. Bit 1 X 0 Not used, and should be set to zero. 0 = on WR input to the PLD AND Array is connected. 1 = off WR input to PLD AND Array is disconnected, saving power. 0 = on RD input to the PLD AND Array is connected. 1 = off RD input to PLD AND Array is disconnected, saving power. 0 = on PSEN input to the PLD AND Array is connected. 1 = off PSEN input to PLD AND Array is disconnected, saving power. 0 = on ALE input to the PLD AND Array is connected. 1 = off ALE input to PLD AND Array is disconnected, saving power. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero.

0 X Not Counting

1 Pulsing Not Counting

and sets the Flash memory into operating mode. automatically when VCC is below VLKO . termined by the PLD equations. Figure 61. Reset (RESET Table 82. Status During Power-on RESET, Warm RESET and Power-down Mode Note: 1. The SR_cod and PeriphMode Bits in the VM Register are always cleared to '0' on Power-on RESET or Warm RESET.

TDO) are dedicated pins on Port C (see Table 83). used to speed up Program and Erase cycles. the basic JTAG signals TMS, TCK, TDI, and TDO. Table 83. JTAG Port Signals ten to the secondary Flash memory. Chip Erase command is allowed. set in PSDsoft Express Configuration.

Table 84. PSD MODULE Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off) O pins being disconnected and IOUT = 0 mA.

Table 85. Absolute Maximum Ratings

Table 86. Operating Conditions (5V Devices) Table 87. Operating Conditions (3V Devices)

Table 88. AC Symbols for Timing Figure 64. Switching Waveforms – Key

Table 89. DC Characteristics (5V Devices)

UPSD3212C, UPSD3212CV Note: 1. IPD (Power-down Mode) is measured with: XTAL1=V SS ; XTAL2=not connected; RESET=V CC ; Port 0 =VCC ; all other pins are disconnected. PLD not in Turbo Mode. 2. ICC_CPU (active mode) is measured with: XTAL1 driven with tCLCH , tCHCL = 5ns, VIL = VSS +0.5V, VIH = Vcc – 0.5V, XTAL2 = not connected; RESET=V SS ; Port 0=VCC ; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately 1mA). 3. ICC_CPU (Idle Mode) is measured with: XTAL1 driven with tCLCH , tCHCL = 5ns, VIL = VSS +0.5V, VIH = VCC – 0.5V, XTAL2 = not connected; Port 0 = VCC ; RESET =V CC ; all other pins are disconnected. 4. See Figure 62 for the PLD current calculation. 5. I/O current = 0 mA, all I/O pins are disconnected. ISTBY SRAM (PSD) Standby Current (VSTBY input) VCC = 0V 0.5 1 µA IIDLE SRAM (PSD) Idle Current (VSTBY input) VCC > VSTBY –0.1 0.1 µA IRST Reset Pin Pull-up Current (RESET ) VIN = VSS –10 –55 µA IFR XTAL Feedback Resistor Current (XTAL1) XTAL1 = VCC XTAL2 = VSS –20 –50 µA ILI Input Leakage Current VSS < VIN < VCC –1 1 µA ILO Output Leakage Current 0.45 < VOUT < VCC –10 10 µA IPD (1) Power-down Mode VCC = 5.5V LVD logic disabled 250 µA LVD logic enabled 380 µA ICC_CPU (2,3,5) Active (12MHz) VCC = 5V 20 30 mA Idle (12MHz) 8 10 mA Active (24MHz) VCC = 5V 30 38 mA Idle (24MHz) 15 20 mA Active (40MHz) VCC = 5V 40 62 mA Idle (40MHz) 20 30 mA ICC_PSD (DC)(5) Operating Supply Current PLD Only PLD_TURBO = Off, f = 0MHz(4) 0 µA/PT(5) PLD_TURBO = On, f = 0MHz 400 700 µA/PT Flash memory During Flash memory WRITE/Erase Only 15 30 mA Read only, f = 0MHz 0 0 mA SRAM f = 0MHz 0 0 mA ICC_PSD (AC)(5) PLD AC Base Note 4 Flash memory AC Adder 2.5 3.5 mA/ MHz SRAM AC Adder 1.5 3.0 mA/ MHz Symbol Parameter Test Condition (in addition to those in Table 86, page 122) Min. Typ. Max. Unit

Table 90. DC Characteristics (3V Devices)

UPSD3212C, UPSD3212CV Note: 1. IPD (Power-down Mode) is measured with: XTAL1=V SS ; XTAL2=not connected; RESET=V CC ; Port 0 =VCC ; all other pins are disconnected. PLD not in Turbo mode. 2. ICC_CPU (active mode) is measured with: XTAL1 driven with tCLCH , tCHCL = 5ns, VIL = VSS +0.5V, VIH = Vcc – 0.5V, XTAL2 = not connected; RESET=V SS ; Port 0=VCC ; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately 1mA). 3. ICC_CPU (Idle Mode) is measured with: XTAL1 driven with tCLCH , tCHCL = 5ns, VIL = VSS +0.5V, VIH = VCC – 0.5V, XTAL2 = not connected; Port 0 = VCC ; RESET =V CC ; all other pins are disconnected. 4. See Figure 62 for the PLD current calculation. 5. I/O current = 0 mA, all I/O pins are disconnected. ITL Logic 1-to-0 Transition Current (Ports 1,2,3,4) VIN = 3.5V (2.5V for Port 4[pin 2])–25 –250 µA ISTBY SRAM (PSD) Standby Current (VSTBY input) VCC = 0V 0.5 1 µA IIDLE SRAM (PSD) Idle Current (VSTBY input) VCC > VSTBY –0.1 0.1 µA IRST Reset Pin Pull-up Current (RESET ) VIN = VSS –10 –55 µA IFR XTAL Feedback Resistor Current (XTAL1) XTAL1 = VCC XTAL2 = VSS –20 –50 µA ILI Input Leakage Current VSS < VIN < VCC –1 1 µA ILO Output Leakage Current 0.45 < VOUT < VCC –10 10 µA IPD (1) Power-down Mode VCC = 3.6V LVD logic disabled 110 µA LVD logic enabled 180 µA ICC_CPU (2,3,5) Active (12MHz) VCC = 3.6V 81 0 m A Idle (12MHz) 4 5 mA Active (24MHz) VCC = 3.6V 15 20 mA Idle (24MHz) 8 10 mA ICC_PSD (DC)(5) Operating Supply Current PLD Only PLD_TURBO = Off, f = 0MHz(4) 0 µA/PT(5) PLD_TURBO = On, f = 0MHz 200 400 µA/PT Flash memory During Flash memory WRITE/Erase Only 10 25 mA Read only, f = 0MHz 0 0 mA SRAM f = 0MHz 0 0 mA ICC_PSD (AC)(5) PLD AC Base Note 4 Flash memory AC Adder 1.5 2.0 mA/MHz SRAM AC Adder 0.8 1.5 mA/MHz Symbol Parameter Test Condition (in addition to those in Table 87, page 122) Min. Typ. Max. Unit

Figure 65. External Program Memory READ Cycle Table 91. External Program Memory AC Characteristics (with the 5V MCU Module)

1. Interfacing the uPSD321X Devices to devices with float times up to 20ns is permissible. This limited bus contention does not cause

any damage to Port 0 drivers.

Table 92. External Program Memory AC Characteristics (with the 3V MCU Module)

1. Interfacing the uPSD321X Devices to devices with float times up to 35ns is permissible. This limited bus contention does not cause

any damage to Port 0 drivers. Table 93. External Clock Drive (with the 5V MCU Module) Table 94. External Clock Drive (with the 3V MCU Module)

Table 95. External Data Memory AC Characteristics (with the 5V MCU Module)

Table 96. External Data Memory AC Characteristics (with the 3V MCU Module) Table 97. A/D Analog Specification CA IN Overall Accuracy ±2 l.s.b. N NLE Non-Linearity Error ±2 l.s.b. N DNLE Differential Non-Linearity Error ±2 l.s.b. N ZOE Zero-Offset Error ±2 l.s.b. N FSE Full Scale Error ±2 l.s.b.

Figure 68. Input to Output Disable / Enable Table 98. CPLD Combinatorial Timing (5V Devices)

1. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR , PSEN and ALE to CPLD combinatorial

Table 99. CPLD Combinatorial Timing (3V Devices)

1. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR , PSEN and ALE to CPLD combinatorial

Figure 69. Synchronous Clock Mode Timing – PLD Table 100. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.

1. CLKIN (PD1) tCLCL = tCH + tCL .

Table 101. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.

1. CLKIN (PD1) tCLCL = tCH + tCL .

Table 103. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)

Figure 72. Input Macrocell Timing (product term clock) Table 104. Input Macrocell Timing (5V Devices) Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX . Table 105. Input Macrocell Timing (3V Devices) Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX .

Table 106. Program, WRITE and Erase Times (5V Devices) Note: 1. Programmed to all zero before erase.

1. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

Table 107. Program, WRITE and Erase Times (3V Devices) Note: 1. Programmed to all zero before erase.

1. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

Figure 73. Peripheral I/O READ Timing Table 108. Port A Peripheral Data Mode READ Timing (5V Devices) Note: 1. Any input used to select Port A Data Peripheral Mode.

1. Data is already stable on Port A.

Table 109. Port A Peripheral Data Mode READ Timing (3V Devices) Note: 1. Any input used to select Port A Data Peripheral Mode.

1. Data is already stable on Port A.

Figure 74. Peripheral I/O WRITE Timing Table 110. Port A Peripheral Data Mode WRITE Timing (5V Devices) Note: 1. Data stable on Port 0 pins to data on Port A. Table 111. Port A Peripheral Data Mode WRITE Timing (3V Devices) Note: 1. Data stable on Port 0 pins to data on Port A.

Figure 75. Reset (RESET) Timing Table 112. Reset (RESET) Timing (5V Devices) Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. Table 113. Reset (RESET) Timing (3V Devices) Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. Table 114. VSTBYON Definitions Timing (5V Devices) Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms. Table 115. VSTBYON Timing (3V Devices) Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.

Figure 76. ISC Timing Table 116. ISC Timing (5V Devices) Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.

1. For Program or Erase PLD only.

Figure 83. TQFP52 – 52-lead Plastic Quad Flatpack Package Outline Note: Drawing is not to scale.

Table 119. TQFP52 – 52-lead Plastic Quad Flatpack Package Mechanical Data

Figure 84. TQFP80 – 80-lead Plastic Quad Flatpack Package Outline Note: Drawing is not to scale.

Table 120. TQFP80 – 80-lead Plastic Quad Flatpack Package Mechanical Data

Table 121. Ordering Information Scheme please contact your nearest ST Sales Office.

UPSD3212C, UPSD3212CV

REVISION HISTORY

Table 122. Document Revision History

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