UPG506B NEC | Alldatasheet

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Technical content

FEATURES

  • WIDE OPERATING FREQUENCY RANGE: f = 8 to 14 GHz (TA = 25°C)
  • LOW PHASE NOISE
  • GUARANTEED OPERATING TEMPERATURE RANGE (TA = -25°C to +75°C) INPUT POWER vs. INPUT FREQUENCY

14 GHz DIVIDE-BY-8

Input Frequency, f (GHz) Input Power, PIN (dBm) -10 2468 1 0 1 2 1 4 1 6 1 8 TA=-25°C to +75°C TA=+25°C Recommended Operating Region TA = -25°C TA = +25°C TA = +75°C VDD = 3.8V VSS1 =0V VSS2 =-2.2VDESCRIPTION The UPG506B is a GaAs divide-by-8 prescaler capable of operating up to 14 GHz. It is designed for use in frequency synthesizers of microwave communication systems and measurement equipment. The UPG506B is a dynamic fre- quency divider and employs BFL (Buffered FET Logic) cir- cuits. The UPG506B is available in a hermetic 8-lead ceramic flat package. PART NUMBER UPG506B PACKAGE OUTLINE BF08 SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN TYP MAX IDD Supply Current mA 70 105 140 ISS1 Sink Current1 ISS1 = IDD - ISS2 mA 35 ISS2 Sink Current1 mA 44 70 96 fIN(U) Upper Limit of Input Frequency at PIN = +6 dBm GHz 14 fIN(L) Lower Limit of Input Frequency at PIN = +6 dBm GHz 8 PIN Input Power at f = 9 to 13 GHz dBm 2.0 10.0 POUT Output Power at fIN = 14 GHz dBm 0 2.0 R TH(CH-C) Thermal Resistance (Channel to Case) °C/W 10.0 ELECTRICAL CHARACTERISTICS (TA = 25°C, VDD = +3.8 V, VSS1 = 0 V, VSS2 = -2.2 V) UPG506B Note: 1. Current is positive into the IDD pin and returns through the ISS1 and ISS2 pins. California Eastern Laboratories

SSB Phase Noise (dBc/Hz) ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C) SYMBOLS PARAMETERS UNITS RATINGS VDD - VSS1 Supply Voltage V 5 VSS2 - VSS1 Supply Current mA -5 PT Total Power Dissipation2 W 1.5 PIN Input Power Level dBm 13 TC CaseTemperature °C -65 to +125 TSTG Storage Temperature °C -65 to +175 Notes: 1. Operation in excess of any one of these conditions may result in permanent damage. 2. T C ≤ 125˚C. POWER DERATING CURVES Case Temperature, TC (°C) Total Power Dissipation, PT (W) TYPICAL PERFORMANCE CURVES (TA = 25°C) 10 100 1K 10K 100K 1M -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 Offset from Carrier (Hz) +75°C +25°C SSB PHASE NOISE vs. OFFSET FROM CARRIER fIN = 12.7 GHz 2.5 2.0 1.5 1.0 0.5 0 0 2 4 8 12 18 Input Frequency, f (GHz ) Output Power, POUT (dBm) TA = -25°C TA = +25°C TA = +75°C 10 14 16 PIN = +10dBm OUTPUT POWER vs. INPUT FREQUENCY 2.5 2.0 1.5 1.0 0.5 0 50 100 150 200 250 110 ELECTRICAL CHARACTERISTICS (TA = -25°C to +75°C, VDD = +3.8 V, VSS1 = 0 V, VSS2 = -2.2 V) PART NUMBER UPG506B PACKAGE OUTLINE BF08 SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN TYP MAX IDD Supply Current mA 105 ISS1 Sink Current1 ISS1 = IDD - ISS2 mA 35 ISS2 Sink Current1 mA 70 fIN(U) Upper Limit of Input Frequency at PIN = +6 dBm GHz 13.2 fIN(L) Lower Limit of Input Frequency at PIN = +6 dBm GHz 8.2 PIN Input Power at f = 9 to 13 GHz dBm 2.0 10.0 POUT Output Power at fIN = 14 GHz dBm -1.0 1.0 TCASE MAX = 125°C Note: 1. Current is positive into the IDD pin and returns through the ISS1 and ISS2 pins.

Notes: 1. Because of the high internal gain and gain compression of the UPG506B, the device is prone to self-oscillation in the absence of an RF input signal. This self-oscillation can be suppressed by either of the following means:

  • Add a shunt resistor to the RF input line. Typically a resistor value between 50 and 1000 ohms will suppress the self- oscillation (see the test circuit schematic).
  • Apply a negative voltage through a 1000 ohm resistor to the normally open VGG1 connection. Typically voltages between 0 and -9 volts will suppress the self-oscillation. Both of these approaches will reduce the input sensitivity of the device (by as much as 3 dB for a 50 ohm shunt resistor), but otherwise have no effect on the reliability or electrical characteristics of the device. * For VSS1, the bias voltage of -6.0 should be applied through a 2.2 V Zener Diode (RD2.2FB or IN3394). * VSS1 should be connected to GND through a 2.2 V Zener Diode (RD2.2FB or IN3394). VDD = 3.8 V VSS1 = 0 V (GND) VSS2 = –2.2 V VDD = +6.0 V VSS2 = 0 V (GND) C: 1000 - 5000 pF Chip Capacitor CONFIGURATION 2 Single Positive Bias Supply CONFIGURATION 3 Single Negative Bias Supply C: 1000 - 5000 pF Chip Capacitor VDD = 0 V (GND) VSS2 = –6 V C: 1000 - 5000 pF Chip Capacitor CONFIGURATION 1

2 Bias Supply

C See Note 1 OPEN OPEN OPEN IN Zo = 50 Ω 10 µF C10 µF VSS2 (-6 V) OUT Zo = 50 Ω 5 IN

6 VGG1

7 VGG2

8 VSS2

2.2 V C C -6 V* C See Note 1 OPEN OPEN OPEN IN Zo = 50 Ω GND (0 V) VSS2 10 µF C 10 µF VDD (+6 V) OUT Zo = 50 Ω 5 IN 2.2 V C C C See Note 1 OPEN OPEN OPEN IN Zo = 50 Ω VSS2 (-2.2 V) 10 µF C C 10 µF VDD (3.8 V) VSS1 (0 V) GND OUT Zo = 50 Ω 5 IN C

OUTLINE DIMENSIONS (Units in mm) 7.0±0.5 2.6 4.4±0.2 10.4±0.5

1.7 MAX

1.27 ±0.1 1.27 ±0.1 1.27 ±0.1 8 7 6 5 1 2 3 4 0.4 5.0±0.2 0.2+0.05 -0.02 LEAD CONNECTIONS 1. OUTPUT 2. VSS1 3. NC* 4. VDD * No Connection UPG506B PACKAGE OUTLINE BFO8 5. INPUT 6. VGG1 7. VGG2 8. VSS2 UPG506B EXCLUSIVE NORTH AMERICAN AGENT FOR RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS CALIFORNIA EASTERN LABORATORIES • Headquarters • 4590 Patrick Henry Drive • Santa Clara, CA 95054-1817 • (408) 988-3500 • Telex 34-6393 • FAX (408) 988-0279 24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) • Internet: http://WWW.CEL.COM PRINTED IN USA ON RECYCLED PAPER -4/97DATA SUBJECT TO CHANGE WITHOUT NOTICE