UPG503B NEC | Alldatasheet

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Technical content

9 GHz DIVIDE-BY-4

FEATURES

  • WIDE OPERATING FREQUENCY RANGE: fIN = 3.5 to 9.0 GHz (TA = 25°C)
  • DIVISION RATIO OF 4
  • GUARANTEED OPERATING TEMPERATURE RANGE: -25°C to +75°C INPUT POWER vs. INPUT FREQUENCY ELECTRICAL CHARACTERISTICS 1 (TA = 25°C, VDD = 3.8 V, VSS1 = 0 V, VSS2 = -2.2 V) UPG503B Input Power, PIN (dBm) Input Frequency, f (GHz) TA = -25˚C TA = +25˚C TA = +75˚C TA = -25˚C to +75˚C VDD = 3.8V VSS1 = 0V VSS2 = - 2.2 V (VGG1,2 OPEN) 0 1 2 3 4 5 6 7 8 9 10 +10 -10 Recommended Operating Region

DESCRIPTION

The UPG503B is a GaAs divide-by-4 prescaler that is capable of operating up to 9 GHz. It is designed to be used in the frequency synthesizers of microwave communication sys- tems and measurement equipment. The UPG503B is a dynamic divider. It employs buffered FET logic (BFL). The UPG503B is available in a hermetic 8-lead ceramic flat package. PART NUMBER UPG503B PACKAGE OUTLINE BF08 SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN TYP MAX IDD Supply Current mA 40 80 130 ISS1 Sink Current2 ISS1 = IDD - ISS2 mA 27 ISS2 Sink Current2 mA 21 53 93 fIN(U) Upper Limit of Input Frequency, PIN = +9 to +10 dBm GHz 8.6 9.0 fIN(L) Lower Limit of Input Frequency, PIN = +9 to +10 dBm GHz 3.5 3.7 PIN Input Power, fIN = 3.7 to 8.6 GHz dBm 9.0 10.0 fIN = 5.0 to 7.4 GHz dBm 3.0 10.0 POUT Output Power, fIN = 8.6 GHz, PIN = +10 dBm dBm 0 3 fIN = 3.7 GHz, PIN = +10 dBm dBm 0 3 R TH Thermal Resistance, Channel to Case °C/W 10 Note: 1.Device may exhibit low frequency spur typically below 150 Hz and -45 dBm. 2. Current is positive into the I DD pin and returns through the ISS1 and ISS2 pins. California Eastern Laboratories

SYMBOLS PARAMETERS UNITS RATINGS VDD-VSS1 Supply Voltage V 5.0 VSS2 -VSS1 Supply Voltage V -5.0 PIN Input Power dBm 13 PT Total Power Dissipation2 W 1.5 TSTG Storage Temperature °C -65 to +175 TC Case Temperature °C -65 to +125 Notes: 1. Operation in excess of any one of these conditions may result in permanent damage. 2. T C ≤ 125°C 2.5 2.0 1.5 1.0 0.5 0 50 100 150 200 250 110 POWER DERATING CURVE Total Power Dissipation, PT (W) TCASE MAX = 125°C OUTPUT POWER vs. INPUT FREQUENCY 10 100 1K 10K 100K Offset from Carrier (Hz) SSB Phase Noise (dBc/Hz) -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 01 2 4 5 6 Input Frequency, fIN (GHz) Output Power, POUT (dBm) +10 -10 89 1 0 VDD = 3.8V VSS1 =0V VSS2 =-2.2V (VGG1,2 OPEN) TA = -25°C TA = +25°C TA = +75°C SSB PHASE NOISE VS. OFFSET FROM CARRIER fIN = 6.82 GHz, TA = 25°C TYPICAL PERFORMANCE CURVES (TA = 25°) Case Temperature, TC (°C) PART NUMBER UPG503B PACKAGE OUTLINE BF08 SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN TYP MAX IDD Supply Current mA 80 ISS1 Sink Current1 ISS1 = IDD - ISS2 mA 27 ISS2 Sink Current1 mA 53 fIN(U) Upper Limit of Input Frequency, PIN = +9 to +10 dBm GHz 8.0 fIN(L) Lower Limit of Input Frequency, PIN = +9 to +10 dBm GHz 4.0 PIN Input Power, fIN = 4.0 to 8.0 GHz dBm 9.0 10.0 fIN = 5.0 to 7.0 GHz dBm 4.0 10.0 POUT Output Power fIN = 8.0 GHz, PIN = +10 dBm dBm -1.0 2.0 fIN = 4.0 GHz, PIN = +10 dBm dBm -1.0 2.0 ELECTRICAL CHARACTERISTICS TA = 25°C to +75°C, VDD = 3.8 V, VSS1 = 0 V, VSS2 = -2.2 V) Note: 1. Current is positive into the IDD pin and returns through the ISS1 and ISS2 pins. ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C)

  • VSS1 should be connected to GND through a 2.2 V Zener Diode (RD2.2FB or IN3394). VDD = 3.8 V VSS1 = 0 V (GND) VSS2 = –2.2 V VDD = +6.0 V VSS2 = 0 V (GND) C: 1000 - 5000 pF Chip Capacitor CONFIGURATION 2 Single Positive Bias Supply CONFIGURATION 3 Single Negative Bias Supply C: 1000 - 5000 pF Chip Capacitor VDD = 0 V (GND) VSS2 = –6 V C: 1000 - 5000 pF Chip Capacitor CONFIGURATION 1

2 Bias Supply

  • For VSS1, the bias voltage of -6.0 should be applied through a 2.2 V Zener Diode (RD2.2FB or IN3394). POWER SUPPLY CONFIGURATIONS (VGG1 and VGG2 are normally open) Notes: 1. Because of the high internal gain and gain compression of the UPG503B, the device is prone to self-oscillation in the absence of an RF input signal. This self-oscillation can be suppressed by either of the following means:
  • Add a shunt resistor to the RF input line. Typically a resistor value between 50 and 1000 ohms will suppress the self- oscillation (see the test circuit schematic).
  • Apply a negative voltage through a 1000 ohm resistor to the normally open VGG1 connection. Typically voltages between 0 and -9 volts will suppress the self-oscillation. Both of these approaches will reduce the input sensitivity of the device (by as much as 3 dB for a 50 ohm shunt resistor), but otherwise have no effect on the reliability or electrical characteristics of the device. C See Note 1 OPEN OPEN OPEN IN Zo = 50 Ω 10 µF C10 µF VSS2 (-6 V) OUT Zo = 50 Ω 5 IN

6 VGG1

7 VGG2

8 VSS2

2.2 V C C -6 V* C See Note 1 OPEN OPEN OPEN IN Zo = 50 Ω GND (0 V) VSS2 10 µF C 10 µF VDD (+6 V) OUT Zo = 50 Ω 5 IN 2.2 V C C C See Note 1 OPEN OPEN OPEN IN Zo = 50 Ω VSS2 (-2.2 V) 10 µF C C 10 µF VDD (3.8 V) VSS1 (0 V) GND OUT Zo = 50 Ω 5 IN C

7.0±0.5 2.6 4.4±0.2 10.4±0.5

1.7 MAX

1.27 ±0.1 1.27 ±0.1 1.27 ±0.1 8 7 6 5 1 2 3 4 0.4 5.0±0.2 0.2+0.05 -0.02 1. OUTPUT 2. VSS1 3. NC* 4. V DD 5. INPUT 6. V GG1 7. VGG2 8. VSS2 OUTLINE DIMENSIONS (Units in mm) UPG503B PACKAGE OUTLINE BF08 * No Connection LEAD CONNECTIONS: EXCLUSIVE NORTH AMERICAN AGENT FOR RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS CALIFORNIA EASTERN LABORATORIES • Headquarters • 4590 Patrick Henry Drive • Santa Clara, CA 95054-1817 • (408) 988-3500 • Telex 34-6393 • FAX (408) 988-0279 24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) • Internet: http://WWW.CEL.COM PRINTED IN USA ON RECYCLED PAPER -4/97DATA SUBJECT TO CHANGE WITHOUT NOTICE