UPD160062

UPD160062 NEC | Alldatasheet

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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. 2002 MOS INTEGRATED CIRCUIT µ PD160062 420-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALE) Document No. S16449EJ1V0DS00 (1st edition) Date Published July 2003 NS CP(K) Printed in Japan DATA SHEET

DESCRIPTION

The µ PD160062 is a source driver for TFT-L CDs capable of dealing with displays wi th 64-gray scale. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels ), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as V SS2 +0.1 V to VDD2 –0.1 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this s ource driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respec tively output gray scale voltages of differing polarity. Assuring a clock frequency of 45 MHz when driving at 2.3 V, th is driver is applicable to SXGA+ standard TFT-LCD panels.

FEATURES

 CMOS level input (2.3 to 3.6 V)  420 outputs  Input of 6 bits (gray scale data) by 6 dots  Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC)  Logic power supply voltage (V DD1) : 2.3 to 3.6 V  Driver power supply voltage (VDD2) : 8.0 to 9.0 V  High-speed data transfer: fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.3 V)  Output dynamic range VSS2 +0.1 V to VDD2 –0.1 V  Apply for dot-line inversion, n-line inversion and column line inversion  Output voltage polarity inversion function (POL)  Input data inversion function (capable of controlling by each input port) (POL21, POL22)  Current consumption control function (LPC, HPC, Bcont)  Slim chip

ORDERING INFORMATION

µ PD160062N-××× TCP (TAB package) Remark The TCP’s external shape is customized. To order the required shape, pleas e contact one of our sales representatives.

Data Sheet S16449EJ1V0DS 2 µ PD160062 1. BLOCK DIAGRAM STHL VDD1 VSS1 VDD2 VSS2 S2S1 V0 to V9 POL D00 to D05 C1 C2 C69 C70 STB CLK 70-bit bidirectional shift register Data register Latch Level shifter D/A converter Voltage follower output R,/L STHR D10 to D15 D20 to D25 S3 S420 POL21, POL22 D30 to D35 D40 to D45 D50 to D55 Bcont HPC LPC Remark /xxx indicates active low signal. 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 S2 S419 6-bit D/A converter S420 POL Multi- plexer

Data Sheet S16449EJ1V0DS 3 µ PD160062 3. PIN CONFIGURATION (µ PD160062N-xxx: TCP) (Copper Foil Surface, Face-up) S420 S419 STHL S418 D55 S417 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 VDD1 R,/L VDD2 VSS2 Bcont HPC VSS1 LPC CLK STB POL POL21 POL22 D D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 S4 D02 S3 D01 S2 D00 S1 STHR Copper Foil Surface Remark This figure does not specify the TCP package.

Data Sheet S16449EJ1V0DS 4 µ PD160062 4. PIN FUNCTIONS (1/2) Pin Symbol Pin Name I/O Description S1 to S420 Driver Output The D/A converted 64-gray-scale analog voltage is output. D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 Display data Input The display data is input with a widt h of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). DX0: LSB, DX5: MSB R,/L Shift direction control Input The shift direction control pin of shift register. The shift directions of the shift registers are as follows. R,/L = H (right shift) : STHR input, S1 → S420, STHL output R,/L = L (left shift) : STHL input, S420 → S1, STHR output STHR Right shift start pulse I/O STHL Left shift start pulse I/O These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. R,/L = H (right shift) : STHR input, STHL output R,/L = L (left shift) : STHL input, STHR output A H level should be input as the pulse of one cycle of the clock signal. If the start pulse input is more than 2 CLK, the first 1 CLK of the H level input is valid. CLK Shift clock Input Refers to the shift register’s shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 70th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. If 72 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. STB Latch Input The contents of the data register ar e transferred to the latch circuit at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL Polarity input Input POL = L: The S 2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to V9 as the reference supply. POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to V4 as the reference supply. S2n−1 indicates the odd output and S2n indicates the even output. Input of the POL signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge. POL21, POL22 Data inversion Input Data inversion can invert when display data is loaded. POL21: Invert/not invert of display data D00 to D05, D10 to D15, D20 to D25 POL22: Invert/not invert of display data D30 to D35, D40 to D45, D50 to D55 POL21, POL22 = H: Data inversion loads display data after inverting it. POL21, POL22 = L: Data inversion does not invert input data. LPC Low power control Input HPC High power control Input Controls the write function of the driver section by digitally controlling the bypass current of the output amplifier. Refer to 9. CURRENT CONSUMPTION CONTROL FUNCTION for details. This pin is pulled up to the VDD1 power supply inside the IC. Bcont Bias control Input This pin can be used to finely control the bias current inside the output amplifier. Refer to 9. CURRENT CONSUMPTION CONTROL FUNCTION for details. When this fine-control function is not required, leave this pin open.

Data Sheet S16449EJ1V0DS 5 µ PD160062 (2/2) Pin Symbol Pin Name I/O Description V0 to V9 γ -corrected power supplies − Input the γ -corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. V DD2 −0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 V DD2 0.5 V DD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 +0.1 V VDD1 Logic power supply − 2.3 to 3.6 V VDD2 Driver power supply − 8.0 to 9.0 V VSS1 Logic ground − Grounding VSS2 Driver ground − Grounding Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down. 2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 µF is also recommended between the γ -corrected power supply terminals (V0, V1, V2, ···, V9) and VSS2.

Data Sheet S16449EJ1V0DS 6 µ PD160062 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The µ PD160062 incorporates a 6-bit D/A converter whose odd out put pins and even output pins output respectively gray scale voltages of differing polarity with respect to th e LCD’s counter electrode (common electrode) voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ -compensated voltages to V 0’ to V63’ and V0” to V63” is almost equivalent. For the 2 sets of five γ -compensated power supplies, V 0 to V 4 and V 5 to V 9, respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the γ -compensated power supplies V1 to V3 and V6 to V8. Figure 5−1 shows the relationship between the driving volt ages such as liquid-crystal driving voltages VDD2 and VSS2, common electrode potential V COM, and γ -corrected voltages V 0 to V 9 and the input data. Be s u r e t o m a i n t a i n t h e voltage relationships of VDD2 −0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 +0.1 V Figures 5−2 shows γ -corrected power supply voltage and ladder resistors ratio and figure 5−3 shows the relationship between the input data and the output voltage. Figure 5−1. Relationship between Input Data and γ -corrected Power Supplies VSS2 00 10 20 30 3F VDD2 0.1 V 0.1 V Input data (HEX)

0.5 VDD2

Data Sheet S16449EJ1V0DS 7 µ PD160062 Figure 5−2. γ -corrected Voltages and Ladder Resistors Ratio V17’’ V16’’ V15’’ V1’’ V2’’ V0’’ V61’’ V60’’ V49’’ V48’’ V47’’ r60 r59 r49 r48 r47 r46 r61 r17 r16 r15 r14 V62’’ r62 V63’’V5 V47’ V48’ V49’ V61’ V62’ V63’ V2’ V3’ V15’ V16’ V17’ r14 r15 r16 r17 r46 r47 r48 r49 r60 r61 r62 V1’ V0’ rn Ratio 1 Ratio 2 Value (Ω) r0 8.00 0.0505 544 r1 7.50 0.0473 510 r2 7.00 0.0442 476 r3 6.50 0.0410 442 r4 6.00 0.0379 408 r5 5.50 0.0347 374 r6 5.50 0.0347 374 r7 5.00 0.0315 340 r8 5.00 0.0315 340 r9 4.00 0.0252 272 r10 4.00 0.0252 272 r11 3.50 0.0221 238 r12 3.50 0.0221 238 r13 3.50 0.0221 238 r14 3.00 0.0189 204 r15 3.00 0.0189 204 r16 3.00 0.0189 204 r17 2.50 0.0158 170 r18 2.50 0.0158 170 r19 2.50 0.0158 170 r20 2.00 0.0126 136 r21 2.00 0.0126 136 r22 2.00 0.0126 136 r23 1.50 0.0095 102 r24 1.50 0.0095 102 r25 1.50 0.0095 102 r26 1.50 0.0095 102 r27 1.00 0.0063 68 r28 1.00 0.0063 68 r29 1.00 0.0063 68 r30 1.00 0.0063 68 r31 1.00 0.0063 68 r32 1.00 0.0063 68 r33 1.00 0.0063 68 r34 1.00 0.0063 68 r35 1.00 0.0063 68 r36 1.00 0.0063 68 r37 1.00 0.0063 68 r38 1.00 0.0063 68 r39 1.00 0.0063 68 r40 1.00 0.0063 68 r41 1.00 0.0063 68 r42 1.00 0.0063 68 r43 1.00 0.0063 68 r44 1.00 0.0063 68 r45 1.00 0.0063 68 r46 1.00 0.0063 68 r47 1.00 0.0063 68 r48 1.00 0.0063 68 r49 1.00 0.0063 68 r50 1.00 0.0063 68 r51 1.00 0.0063 68 r52 1.00 0.0063 68 r53 1.50 0.0095 102 r54 1.50 0.0095 102 r55 1.50 0.0095 102 r56 2.00 0.0126 136 r57 2.00 0.0126 136 r58 2.50 0.0158 170 r59 2.50 0.0158 170 r60 3.00 0.0189 204 r61 5.00 0.0315 340 r62 8.00 0.0505 544 10778 Total resistance Minimum resistance value Remark The resistance ratio1 is a relative ratio in the case of setting the minimum resistance value to 1. The resistance ratio2 is a relative ratio in the case of setting the total resistance to 1. Caution There is no connection between V4 and V5 terminal in the chip.

Data Sheet S16449EJ1V0DS 8 µ PD160062 Figure 5−3. Relationship between Input Data and Output Voltage (POL21, POL22 = L) (Output Voltage 1) VDD2 −0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 (Output Voltage 2) 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 +0.1 V Input Data 00H V 0' V0 V0'' V9 01H V 1' V1+(V0-V1)× 4930 / 5474 V 1'' V9+(V8-V9)× 544 / 5474 02H V 2' V1+(V0-V1)× 4420 / 5474 V 2'' V9+(V8-V9)× 1054 / 5474 03H V 3' V1+(V0-V1)× 3944 / 5474 V 3'' V9+(V8-V9)× 1530 / 5474 04H V 4' V1+(V0-V1)× 3502 / 5474 V 4'' V9+(V8-V9)× 1972 / 5474 05H V 5' V1+(V0-V1)× 3094 / 5474 V 5'' V9+(V8-V9)× 2380 / 5474 06H V 6' V1+(V0-V1)× 2720 / 5474 V 6'' V9+(V8-V9)× 2754 / 5474 07H V 7' V1+(V0-V1)× 2346 / 5474 V 7'' V9+(V8-V9)× 3128 / 5474 08H V 8' V1+(V0-V1)× 2006 / 5474 V 8'' V9+(V8-V9)× 3468 / 5474 09H V 9' V1+(V0-V1)× 1666 / 5474 V 9'' V9+(V8-V9)× 3808 / 5474 0AH V 10' V1+(V0-V1)× 1394 / 5474 V 10'' V9+(V8-V9)× 4080 / 5474 0BH V 11' V1+(V0-V1)× 1122 / 5474 V 11'' V9+(V8-V9)× 4352 / 5474 0CH V 12' V1+(V0-V1)× 884 / 5474 V 12'' V9+(V8-V9)× 4590 / 5474 0DH V 13' V1+(V0-V1)× 646 / 5474 V 13'' V9+(V8-V9)× 4828 / 5474 0EH V 14' V1+(V0-V1)× 408 / 5474 V 14'' V9+(V8-V9)× 5066 / 5474 0FH V 15' V1+(V0-V1)× 204 / 5474 V 15'' V9+(V8-V9)× 5270 / 5474 10H V 16' V1 V16'' V8 11H V 17' V2+(V1-V2)× 1666 / 1870 V 17'' V8+(V7-V8)× 204 / 1870 12H V 18' V2+(V1-V2)× 1496 / 1870 V 18'' V8+(V7-V8)× 374 / 1870 13H V 19' V2+(V1-V2)× 1326 / 1870 V 19'' V8+(V7-V8)× 544 / 1870 14H V 20' V2+(V1-V2)× 1156 / 1870 V 20'' V8+(V7-V8)× 714 / 1870 15H V 21' V2+(V1-V2)× 1020 / 1870 V 21'' V8+(V7-V8)× 850 / 1870 16H V 22' V2+(V1-V2)× 884 / 1870 V 22'' V8+(V7-V8)× 986 / 1870 17H V 23' V2+(V1-V2)× 748 / 1870 V 23'' V8+(V7-V8)× 1122 / 1870 18H V 24' V2+(V1-V2)× 646 / 1870 V 24'' V8+(V7-V8)× 1224 / 1870 19H V 25' V2+(V1-V2)× 544 / 1870 V 25'' V8+(V7-V8)× 1326 / 1870 1AH V 26' V2+(V1-V2)× 442 / 1870 V 26'' V8+(V7-V8)× 1428 / 1870 1BH V 27' V2+(V1-V2)× 340 / 1870 V 27'' V8+(V7-V8)× 1530 / 1870 1CH V 28' V2+(V1-V2)× 272 / 1870 V 28'' V8+(V7-V8)× 1598 / 1870 1DH V 29' V2+(V1-V2)× 204 / 1870 V 29'' V8+(V7-V8)× 1666 / 1870 1EH V 30' V2+(V1-V2)× 136 / 1870 V 30'' V8+(V7-V8)× 1734 / 1870 1FH V 31' V2+(V1-V2)×6 8 / 1870 V 31'' V8+(V7-V8)× 1802 / 1870 20H V 32' V2 V32'' V7 21H V 33' V3+(V2-V3)× 1020 / 1088 V 33'' V7+(V6-V7)× 68 / 1088 22H V 34' V3+(V2-V3)× 952 / 1088 V 34'' V7+(V6-V7)× 136 / 1088 23H V 35' V3+(V2-V3)× 884 / 1088 V 35'' V7+(V6-V7)× 204 / 1088 24H V 36' V3+(V2-V3)× 816 / 1088 V 36'' V7+(V6-V7)× 272 / 1088 25H V 37' V3+(V2-V3)× 748 / 1088 V 37'' V7+(V6-V7)× 340 / 1088 26H V 38' V3+(V2-V3)× 680 / 1088 V 38'' V7+(V6-V7)× 408 / 1088 27H V 39' V3+(V2-V3)× 612 / 1088 V 39'' V7+(V6-V7)× 476 / 1088 28H V 40' V3+(V2-V3)× 544 / 1088 V 40'' V7+(V6-V7)× 544 / 1088 29H V 41' V3+(V2-V3)× 476 / 1088 V 41'' V7+(V6-V7)× 612 / 1088 2AH V 42' V3+(V2-V3)× 408 / 1088 V 42'' V7+(V6-V7)× 680 / 1088 2BH V 43' V3+(V2-V3)× 340 / 1088 V 43'' V7+(V6-V7)× 748 / 1088 2CH V 44' V3+(V2-V3)× 272 / 1088 V 44'' V7+(V6-V7)× 816 / 1088 2DH V 45' V3+(V2-V3)× 204 / 1088 V 45'' V7+(V6-V7)× 884 / 1088 2EH V 46' V3+(V2-V3)× 136 / 1088 V 46'' V7+(V6-V7)× 952 / 1088 2FH V 47' V3+(V2-V3)×6 8 / 1088 V 47'' V7+(V6-V7)× 1020 / 1088 30H V 48' V3 V48'' V6 31H V 49' V4+(V3-V4)× 2278 / 2346 V 49'' V6+(V5-V6)× 68 / 2346 32H V 50' V4+(V3-V4)× 2210 / 2346 V 50'' V6+(V5-V6)× 136 / 2346 33H V 51' V4+(V3-V4)× 2142 / 2346 V 51'' V6+(V5-V6)× 204 / 2346 34H V 52' V4+(V3-V4)× 2074 / 2346 V 52'' V6+(V5-V6)× 272 / 2346 35H V 53' V4+(V3-V4)× 2006 / 2346 V 53'' V6+(V5-V6)× 340 / 2346 36H V 54' V4+(V3-V4)× 1904 / 2346 V 54'' V6+(V5-V6)× 442 / 2346 37H V 55' V4+(V3-V4)× 1802 / 2346 V 55'' V6+(V5-V6)× 544 / 2346 38H V 56' V4+(V3-V4)× 1700 / 2346 V 56'' V6+(V5-V6)× 646 / 2346 39H V 57' V4+(V3-V4)× 1564 / 2346 V 57'' V6+(V5-V6)× 782 / 2346 3AH V 58' V4+(V3-V4)× 1428 / 2346 V 58'' V6+(V5-V6)× 918 / 2346 3BH V 59' V4+(V3-V4)× 1258 / 2346 V 59'' V6+(V5-V6)× 1088 / 2346 3CH V 60' V4+(V3-V4)× 1088 / 2346 V 60'' V6+(V5-V6)× 1258 / 2346 3DH V 61' V4+(V3-V4)× 884 / 2346 V 61'' V6+(V5-V6)× 1462 / 2346 3EH V 62' V4+(V3-V4)× 544 / 2346 V 62'' V6+(V5-V6)× 1802 / 2346 3FH V 63' V4 V63'' V5 Output Voltage 1 Out put Voltage 2

Data Sheet S16449EJ1V0DS 9 µ PD160062 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format: 6 bits × 2 RGBs (6 dots) Input width: 36 bits (2-pixel data) (1) R,/L = H (right shift) Output S 1 S 2 S 3 S 4 xxx S419 S 420 Data D 00 to D05 D 10 to D15 D 20 to D25 D 30 to D35 xxx D40 to D45 D 50 to D55 (2) R,/L = L (left shift) Output S 1 S 2 S 3 S 4 xxx S419 S 420 Data D 00 to D05 D 10 to D15 D 20 to D25 D 30 to D35 xxx D40 to D45 D 50 to D55 POL S2n−1 Note S 2n Note L V 0 to V4 V 5 to V9 H V 5 to V9 V 0 to V4 Note S2n−1 (odd output), S2n (even output) 7. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM The output voltage is written to the LCD panel synchronized with the STB falling edge. Selected voltage V0 to V4 Hi-Z STB POL S2n S2n-1 Hi-Z Hi-Z Selected voltage V5 to V9 Selected voltage V0 to V4 Selected voltage V0 to V4 Selected voltage V5 to V9 Selected voltage V5 to V9 Remark Hi-Z: High impedance

Data Sheet S16449EJ1V0DS 11 µ PD160062 9. CURRENT CONSUMPTION CONTROL FUNCTION The µ PD160062 has a power control function which can switch the bias current of the output amplifier between four levels and a bias control function (Bcont) which can be used to finely control the bias current. < Power control function (LPC, HPC) > The bias current of the output amplifier can be switched between four levels using LPC (Low Power Control) pins and HPC (High Power Control) pins (show in below table). Power Mode LPC HPC High L L Middle H or open L Normal L H or open Low H or open H or open Following graph shows the relationship between each power modes and bias current. High Middle Normal Low 6.00 8.007.00 9.00 VDD2 IDD2 Remark This relationship is founded on results of simulation and don’t assuring a characteristics of this product.

Data Sheet S16449EJ1V0DS 12 µ PD160062 < Bias Current Control Function (Bcont) > It is possible to fine-control the current consumption by using the bias current control function (Bcont pin). When using this function, connect this pin to the stabilized ground potential (VSS2) via an external resistor (REXT). When not using this function, leave this pin open. Figure 9−1. Bias Current Control Function (Bcont) PD160062 Bcont HPC REXT H/L VSS2 LPC H/L µ Refer to the table below for the percentage of current regulation when using the bias current control function. Table 9−1. Current Consumption Regulation Percentage Compared to Normal Mode (VDD1 = 3.3 V, VDD2 = 8.7 V) Current Consumption Regulation Percentage (%) REXT (kΩ) LPC = L LPC = H/open ∞ (Open) 100 65 50 110 70 20 115 80 10 120 85 Remark The above current consumption regulation percentages are founded on results of simulation and don’t assuring a characteristics of this product. Caution Because the power and bias-current control functions control the bias current in the output amplifier and regulate the over-all current consumption of the driver IC, when this occurs, the characteristics of the output amplifier will simultaneously change. Therefore, when using these functions, be sure to sufficiently evaluate the picture quality.

Data Sheet S16449EJ1V0DS 13 µ PD160062 10. ELECTRICAL SPECIFICATIONS Parameter Symbol Rating Unit Logic Part Supply Voltage V DD1 −0.5 to +4.0 V Driver Part Supply Voltage V DD2 −0.5 to +10.0 V Logic Part Input Voltage V I1 −0.5 to VDD1 +0.5 V Driver Part Input Voltage V I2 −0.5 to VDD2 +0.5 V Logic Part Output Voltage V O1 −0.5 to VDD1 +0.5 V Driver Part Output Voltage V O2 −0.5 to VDD2 +0.5 V Operating Ambient Temperature T A −10 to +75 °C Storage Temperature T stg −55 to +125 °C Caution Product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any parameter/ That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = −10 to +75°C, VSS1 = VSS2 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Logic Part Supply Voltage V DD1 2.3 3.6 V Driver Part Supply Voltage V DD2 8.0 8.5 9.0 V High-Level Input Voltage V IH 0.7 V DD1 V DD1 V Low-Level Input Voltage V IL 0 0.3 V DD1 V V0 to V4 0.5 V DD2 VDD2 −0.1 V γ -corrected Voltage V5 to V9 V SS2 +0.1 0.5 V DD2 V Driver Part Output Voltage V O V SS2 +0.1 VDD2 −0.1 V Maximum Clock Frequency f CLK VDD1 = 2.3 V 45 MHz

Data Sheet S16449EJ1V0DS 14 µ PD160062 unless otherwise specified, power mode = normal, Bcont = open.) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input Leak Current I IL ±1.0 µA High-Level Output Voltage V OH STHR (STHL), I OH = 0 mA VDD1 −0.1 V Low-Level Output Voltage V OL STHR (STHL), I OL = 0 mA 0.1 V γ -corrected Resistance Rγ V DD2 = 8.5 V, V0 to V4 = V5 to V9 = 4.0 V 5.4 10.8 21.6 kΩ IVOH VX = 7.0 V, VOUT = 6.5 V Note −30 µA Driver Output Current IVOL VX = 1.0 V, VOUT = 1.5 V Note 30 µA Output Voltage Deviation ∆VO ±7 ±20 mV Output swing difference deviation ∆VP–P TA = 25°C, VDD1 = 3.3 V, VDD2 = 8.5 V, VOUT = 2.0 V, 4.25 V, 6.5 V ±2 ±15 mV Logic Part Dynamic Current Consumption IDD1 V DD1 1.0 6.5 mA Driver Part Dynamic Current Consumption IDD2 V DD2, with no load 3.0 6.5 mA Note VX refers to the output voltage of analog output pins S 1 to S 420. VOUT refers to the voltage applied to analog output pins S1 to S420. Cautions 1. fSTB = 64 kHz, fCLK = 40 MHz 2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 3. Refers to the current consumption per driver when cascades are connected under the assumption of SXGA+ single-sided mounting (10 units). Switching Characteristics (TA = −10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.0 to 9.0 V, VSS1 = VSS2 = 0 V, unless otherwise specified, power mode = normal, Bcont = open.) Parameter Symbol Conditions MIN. TYP. MAX. Unit Start Pulse Delay Time t PLH1 C L = 10 pF 10 20 ns tPLH2 2.5 5 µs tPLH3 5 8 µs tPHL2 2.5 5 µs Driver Output Delay Time tPHL3 CL = 75 pF, RL = 5 kΩ 5 8 µs CI1 STHR (STHL) excluded, TA = 25°C 10 pF Input Capacitance CI2 STHR (STHL), T A = 25°C 10 pF

Data Sheet S16449EJ1V0DS 15 µ PD160062 Timing Requirement (TA = −10 to +75°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns) Parameter Symbol Conditions MIN. TYP. MAX. Unit Clock Pulse Width PW CLK 22 ns Clock Pulse High Period PW CLK(H) 4 ns Clock Pulse Low Period PW CLK(L) 4 ns Data Setup Time t SETUP1 4 ns Data Hold Time t HOLD1 0 ns Start Pulse Setup Time t SETUP2 4 ns Start Pulse Hold Time t HOLD2 0 ns POL21, POL22 Setup Time t SETUP3 4 ns POL21, POL22 Hold Time t HOLD3 0 ns STB Pulse Width PW STB 2 CLK Last Data Timing t LDT 2 CLK CLK-STB Time t CLK-STB CLK ↑ → STB ↑ 6 ns STB-CLK Time t STB-CLK STB ↑ → CLK ↑ 9 ns Time Between STB and Start Pulse t STB-STH STB ↑ → STHR(STHL) ↑ 2 CLK POL-STB Time t POL-STB POL ↑ or ↓ → STB ↑ –5 ns STB-POL Time t STB-POL STB ↓ → POL ↓ or ↑ 6 ns Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.

Data Sheet S16449EJ1V0DS 16 µ PD160062 Switching characteristics waveform (R,/L = H) Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. PWCLK(L) CLK POL (VX) Sn STB Dn0 to Dn5 STHR STHL PWCLK(H) tr tSETUP2 INVALID D1 to D6 tHOLD2 37 0 7 1 7 2 513 514 tf VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 PWCLK tCLK-STB tSTB-CLK tSTB-STHtSETUP1 90% 10% tHOLD1 tPLH1 tPOL-STB tSTB-POL tPLH3 tPLH2 tPHL2 tPHL3 Hi-Z Target voltage ±0.1 VDD2 6-bit accuracy tLDT PWSTB D7 to D12 D1 to D6 D7 to D12 D409 to D414 D415 to D420 D421 to D426 D3067 to D3072 INVALID INVALID VDD1 VSS1 tSETUP3 tHOLD3 POL21, POL22 (1st Dr.) (1st Dr.) INVALID

Data Sheet S16449EJ1V0DS 17 µ PD160062 11. RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for soldering conditions of the µ PD160062. For more details, refer to the Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html). Please consult with our sales offices in case other solderin g process is used, or in case the soldering is done under different conditions. µ PD160062N-×××: TCP (TAB package) Mounting Condition Mounting Method Condition Soldering Heating tool 300 to 350°C, heating for 2 to 3 seconds, pressure 100g (per solder) Thermocompression ACF (Adhesive Conductive Film) Temporary bonding 70 to 100°C, pressure 3 to 8 kg/cm , time 3 to 5 seconds. Real bonding 165 to 180°C, pressure 25 to 45 kg/cm , time 30 to 40 seconds. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.) Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more packaging methods at a time.

Data Sheet S16449EJ1V0DS 18 µ PD160062 NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.