Driver IC

UPD160061N

NEC

384-OUTPUT TFT-LCD SOURCE DRIVER

Manufacturer: NEC

Document: 18 Pages / 230Kb

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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. 2002 MOS INTEGRATED CIRCUIT µPD160061 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES) DATA SHEET Document No. S15843EJ3V0DS00 (3rd edition) Date Published June 2004 NS CP (K) Printed in Japan The mark ★ shows major revised points.

DESCRIPTION

The µPD160061 is a source driver for TFT-LCD’s capable of dealing with displays with 64-gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by -2 external power modul es. Because the output dynamic range is as large as V SS2 + 0.2 V to V DD2 – 0.2 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driv er is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polar ity. Assuring a maximum clock frequency of 65 MHz when driving at 2.7 V, this driver is applicable to XGA-standard TFT-LCD panels and SXGA TFT-LCD panels.

FEATURES

CMOS level input (2.3 to 3.6 V)
384 outputs
Input of 6 bits (gray-scale data) by 6 dots
Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC)
Logic power supply voltage (VDD1): 2.3 to 3.6 V
Driver power supply voltage (VDD2): 7.5 to 9.5 V
High-speed data transfer: fCLK = 65 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.7 V) 40 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.3 V)
Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V
Apply for dot-line inversion, n-line inversion and column line inversion
Output voltage polarity inversion function (POL)
Input data inversion function (capable of controlling by each input port) (POL21, POL22)
Apply for heavy load, light load
Semi slim-chip shaped

ORDERING INFORMATION

µPD160061N-xxx TCP (TAB package) µPD160061NL-xxx COF (COF package) Remark The TCP’s/COF’s external shape are customized. To order the required shape, so pl ease contact one of our sales representatives.

Data Sheet S15843EJ3V0DS 2 µPD160061 1. BLOCK DIAGRAM 64-bit bidirectional shift register Data register Latch Level shifter D/A converter Voltage follower output D00 D05 STHR STHL R,/L CLK VDD1 VSS1 POL V0 to V9 VDD2 VSS2 S2 S3 S384 STB D10 D15 D20 D25 POL21 to to to to to to D30 D35 D40 D45 D50 D55 POL22 SRC LPC HPC Remark /xxx indicates active low signal. 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER 6-bit D/A converterMulti- Plexer POL S1 S2 S383 S384

Data Sheet S15843EJ3V0DS 3 µPD160061 3. PIN CONFIGURATION (Copper foil surface) (µPD160061N-xxx: TCP (TAB package): Face-up/ µPD160061NL-xxx: COF (COF package): Face-down) S384 S383 STHL S382 D55 S381 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 VDD1 LPC R,/L VDD2 VSS2 HPC VSS1 SRC CLK STB POL POL21 POL22 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 S4 D02 S3 D01 S2 D00 S1 STHR IC Pad Surface Remark This figure does not specify the TCP or COF package.

Data Sheet S15843EJ3V0DS 4 µPD160061 4. PIN FUNCTIONS (1/2) Pin Symbol Pin Name I/O Description S1 to S384 Driver output Output The D/A conver ted 64-gray-scale analog voltage is output. D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 Display data input Input The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). D X0: LSB, DX5: MSB R,/L Shift direction control Input These refer to the start pulse I/O pi ns when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. R,/L = H (right shift): STHR input, S1→S384, STHL output R,/L = L (left shift): STHL input, S384→S1, STHR output STHR Right shift start pulse input/output I/O STHL Left shift start pulse input/output These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. When right shift: STHR input, STHL output When left shift: STHL input, STHR output A high level should be input as the pulse of one cycle of the clock signal. If the start pulse input is more than 2CLK, the first 1CLK of the high-level input is valid. CLK Shift clock input Input Refers to the shift register’s sh ift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 64th after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. If 66th clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. STB Latch input Input The contents of the data register are tr ansferred to the latch circuit at the rising edge. And, at the falling edge of the STB, the gray scale voltage is supplied to the driver. When STB = H period, driver output level is Hi-Z (High impedance). It is necessary to ensure input of one pulse per horizontal period. POL Polarity input Input POL = L: The S 2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to V9 as the reference supply. POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to V4 as the reference supply. S2n-1 indicates the odd output, and S2n indicates the even output. Input of the POL signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge. POL21, POL22 Data inversion input Input Data inversi on can invert when display data is loaded. POL21: D 00 to D05, D10 to D15, D20 to D25, data inversion can invert display data POL22: D30 to D35, D40 to D45, D50 to D55, data inversion can invert display data POL21, POL22 = H: Data inversion loads display data after inverting it. POL21, POL22 = L: Data inversion does not invert input data. LPC, HPC Bias current control input Input Please refer to panel loads and driver power supply voltage (V DD2), when set up these pins. Refer to 10. BIAS CURRENT CONTROL BY LPC AND HPC. LPC pin is pulled down to the VSS1 inside the IC, HPC pin is pulled up to the VDD1 inside the IC.

Data Sheet S15843EJ3V0DS 5 µPD160061 (2/2) Pin Symbol Pin Name I/O Description SRC High driving time control Input This pin is set up to high drive time of the output amplifier. Please decide the pin setting refer to panel loads and one horizontal period. SRC pin is pulled up to the VDD1 inside the IC. SRC = H or open: High drive time 64 CLK (Normally period mode) SRC = L: High drive time 128 CLK (Long time mode) Refer to 9. SRC AND HIGH DRIVE TIME. V0 to V9 γ -corrected power supplies − Input the γ -corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. V DD2 − 0.2 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 VDD2 − 0.3 V ≥ > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.2 V VDD1 Logic power supply − 2.3 to 3.6 V VDD2 Driver power supply − 7.5 to 9.5 V VSS1 Logic ground − Grounding VSS2 Driver ground − Grounding Cautions 1. The power start sequence must be V DD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down. 2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between V DD1 to VSS1 and VDD2 to VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 µF is also recommended between the γ -corrected power

Data Sheet S15843EJ3V0DS 6 µPD160061 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The µPD160061 incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD’s counter electrode voltage. T he D/A converter consists of ladder resistors and switches. The ladder resistors (r0 to r62) ar e designed so that the ratio of LCD panel γ-compensated voltages to V0’ to V63’ and V0” to V63” is almost equivalent, resistor ratio is shown in Figure 5−2. For the 2 sets of five γ-compensated power supplies, V0 to V4 and V5 to V9, respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine-gray scale voltage precision is not necessary, there is no need to connec t a voltage follower circuit to the γ- compensated power supplies V1 to V3 and V6 to V8. Figure 5–1 shows the relationship between the driving voltages such as liquid-crystal driving voltages V DD2 and V SS2, common electrode potential V COM, and γ -corrected voltages V0 to V9 and the input data. Be su re to maintain the voltage relationships of below. VDD2 – 0.2 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 0.5 VDD2 – 0.3 V ≥ V5 > V6 > V7 > V8 > V9 > VSS2 + 0.2 V Figures 5–2 indicates γ -corrected voltages and ladder resistors ratio. Fi gures 5–3 indicates the relationship between the input data and output voltage. Figure 5–1. Relationship between Input Data and γ -corrected Power Supplies 0.2 V 0.2 V 00 10 20 3F Input data (HEX.) 0.3 V

0.5 VDD2 Split interval

Data Sheet S15843EJ3V0DS 7 µPD160061 Figure 5–2. γ -corrected Voltages and Ladder Resistors Ratio Cautions 1. There is no connection between V 4 and V5 terminal in the IC. 2. The resistance ratio is a relative ratio in the case of setting the resistance minimum value to 1. V17’’ V16’’ V15’’ V1’’ V2’’ V0’’ V61’’ V60’’ V49’’ V48’’ V47’’ r60 r59 r49 r48 r47 r46 r61 r17 r16 r15 r14 V62’’ r62 V63’’V5 V47’ V48’ V49’ V61’ V62’ V63’ V2’ V3’ V15’ V16’ V17’ r14 r15 r16 r17 r46 r47 r48 r49 r60 r61 r62 V1’ V0’ rn Ratio Value (TYP.) r0 8.5 800 r1 7.5 750 r2 7.0 700 r3 6.5 650 r4 6.0 600 r5 5.5 550 r6 5.5 550 r7 5.0 500 r8 5.0 500 r9 4.0 400 r10 4.0 400 r11 3.5 350 r12 3.5 350 r13 3.5 350 r14 3.0 300 r15 3.0 300 r16 3.0 300 r17 2.5 250 r18 2.5 250 r19 2.5 250 r20 2.0 200 r21 2.0 200 r22 2.0 200 r23 1.5 150 r24 1.5 150 r25 1.5 150 r26 1.5 150 r27 1.0 100 r28 1.0 100 r29 1.0 100 r30 1.0 100 r31 1.0 100 r32 1.0 100 r33 1.0 100 r34 1.0 100 r35 1.0 100 r36 1.0 100 r37 1.0 100 r38 1.0 100 r39 1.0 100 r40 1.0 100 r41 1.0 100 r42 1.0 100 r43 1.0 100 r44 1.0 100 r45 1.0 100 r46 1.0 100 r47 1.0 100 r48 1.0 100 r49 1.0 100 r50 1.0 100 r51 1.0 100 r52 1.0 100 r53 1.5 150 r54 1.5 150 r55 1.5 150 r56 2.0 200 r57 2.0 200 r58 2.5 250 r59 2.5 250 r60 3.0 300 r61 5.0 500 r62 8.0 800

Data Sheet S15843EJ3V0DS 8 µPD160061 Figure 5–3. Relationship between Input Data and Output Voltage (POL21, POL22 = L) Output Voltage 1: VDD2 – 0.2 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 Output Voltage 2: 0.5 VDD2 – 0.3 V ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.2 V Input Data 00H V 0' V0 V0'' V9 01H V 1' V1+(V0-V1)× 7250 / 8050 V 1'' V9+(V8-V9)× 800 / 8050 02H V 2' V1+(V0-V1)× 6500 / 8050 V 2'' V9+(V8-V9)× 1550 / 8050 03H V 3' V1+(V0-V1)× 5800 / 8050 V 3'' V9+(V8-V9)× 2250 / 8050 04H V 4' V1+(V0-V1)× 5150 / 8050 V 4'' V9+(V8-V9)× 2900 / 8050 05H V 5' V1+(V0-V1)× 4550 / 8050 V 5'' V9+(V8-V9)× 3500 / 8050 06H V 6' V1+(V0-V1)× 4000 / 8050 V 6'' V9+(V8-V9)× 4050 / 8050 07H V 7' V1+(V0-V1)× 3450 / 8050 V 7'' V9+(V8-V9)× 4600 / 8050 08H V 8' V1+(V0-V1)× 2950 / 8050 V 8'' V9+(V8-V9)× 5100 / 8050 09H V 9' V1+(V0-V1)× 2450 / 8050 V 9'' V9+(V8-V9)× 5600 / 8050 0AH V 10' V1+(V0-V1)× 2050 / 8050 V 10'' V9+(V8-V9)× 6000 / 8050 0BH V 11' V1+(V0-V1)× 1650 / 8050 V 11'' V9+(V8-V9)× 6400 / 8050 0CH V 12' V1+(V0-V1)× 1300 / 8050 V 12'' V9+(V8-V9)× 6750 / 8050 0DH V 13' V1+(V0-V1)× 950 / 8050 V 13'' V9+(V8-V9)× 7100 / 8050 0EH V 14' V1+(V0-V1)× 600 / 8050 V 14'' V9+(V8-V9)× 7450 / 8050 0FH V 15' V1+(V0-V1)× 300 / 8050 V 15'' V9+(V8-V9)× 7750 / 8050 10H V 16' V1 V16'' V8 11H V 17' V2+(V1-V2)× 2450 / 2750 V 17'' V8+(V7-V8)× 300 / 2750 12H V 18' V2+(V1-V2)× 2200 / 2750 V 18'' V8+(V7-V8)× 550 / 2750 13H V 19' V2+(V1-V2)× 1950 / 2750 V 19'' V8+(V7-V8)× 800 / 2750 14H V 20' V2+(V1-V2)× 1700 / 2750 V 20'' V8+(V7-V8)× 1050 / 2750 15H V 21' V2+(V1-V2)× 1500 / 2750 V 21'' V8+(V7-V8)× 1250 / 2750 16H V 22' V2+(V1-V2)× 1300 / 2750 V 22'' V8+(V7-V8)× 1450 / 2750 17H V 23' V2+(V1-V2)× 1100 / 2750 V 23'' V8+(V7-V8)× 1650 / 2750 18H V 24' V2+(V1-V2)× 950 / 2750 V 24'' V8+(V7-V8)× 1800 / 2750 19H V 25' V2+(V1-V2)× 800 / 2750 V 25'' V8+(V7-V8)× 1950 / 2750 1AH V 26' V2+(V1-V2)× 650 / 2750 V 26'' V8+(V7-V8)× 2100 / 2750 1BH V 27' V2+(V1-V2)× 500 / 2750 V 27'' V8+(V7-V8)× 2250 / 2750 1CH V 28' V2+(V1-V2)× 400 / 2750 V 28'' V8+(V7-V8)× 2350 / 2750 1DH V 29' V2+(V1-V2)× 300 / 2750 V 29'' V8+(V7-V8)× 2450 / 2750 1EH V 30' V2+(V1-V2)× 200 / 2750 V 30'' V8+(V7-V8)× 2550 / 2750 1FH V 31' V2+(V1-V2)× 100 / 2750 V 31'' V8+(V7-V8)× 2650 / 2750 20H V 32' V2 V32'' V7 21H V 33' V3+(V2-V3)× 1500 / 1600 V 33'' V7+(V6-V7)× 100 / 1600 22H V 34' V3+(V2-V3)× 1400 / 1600 V 34'' V7+(V6-V7)× 200 / 1600 23H V 35' V3+(V2-V3)× 1300 / 1600 V 35'' V7+(V6-V7)× 300 / 1600 24H V 36' V3+(V2-V3)× 1200 / 1600 V 36'' V7+(V6-V7)× 400 / 1600 25H V 37' V3+(V2-V3)× 1100 / 1600 V 37'' V7+(V6-V7)× 500 / 1600 26H V 38' V3+(V2-V3)× 1000 / 1600 V 38'' V7+(V6-V7)× 600 / 1600 27H V 39' V3+(V2-V3)× 900 / 1600 V 39'' V7+(V6-V7)× 700 / 1600 28H V 40' V3+(V2-V3)× 800 / 1600 V 40'' V7+(V6-V7)× 800 / 1600 29H V 41' V3+(V2-V3)× 700 / 1600 V 41'' V7+(V6-V7)× 900 / 1600 2AH V 42' V3+(V2-V3)× 600 / 1600 V 42'' V7+(V6-V7)× 1000 / 1600 2BH V 43' V3+(V2-V3)× 500 / 1600 V 43'' V7+(V6-V7)× 1100 / 1600 2CH V 44' V3+(V2-V3)× 400 / 1600 V 44'' V7+(V6-V7)× 1200 / 1600 2DH V 45' V3+(V2-V3)× 300 / 1600 V 45'' V7+(V6-V7)× 1300 / 1600 2EH V 46' V3+(V2-V3)× 200 / 1600 V 46'' V7+(V6-V7)× 1400 / 1600 2FH V 47' V3+(V2-V3)× 100 / 1600 V 47'' V7+(V6-V7)× 1500 / 1600 30H V 48' V3 V48'' V6 31H V 49' V4+(V3-V4)× 3350 / 3450 V 49'' V6+(V5-V6)× 100 / 3450 32H V 50' V4+(V3-V4)× 3250 / 3450 V 50'' V6+(V5-V6)× 200 / 3450 33H V 51' V4+(V3-V4)× 3150 / 3450 V 51'' V6+(V5-V6)× 300 / 3450 34H V 52' V4+(V3-V4)× 3050 / 3450 V 52'' V6+(V5-V6)× 400 / 3450 35H V 53' V4+(V3-V4)× 2950 / 3450 V 53'' V6+(V5-V6)× 500 / 3450 36H V 54' V4+(V3-V4)× 2800 / 3450 V 54'' V6+(V5-V6)× 650 / 3450 37H V 55' V4+(V3-V4)× 2650 / 3450 V 55'' V6+(V5-V6)× 800 / 3450 38H V 56' V4+(V3-V4)× 2500 / 3450 V 56'' V6+(V5-V6)× 950 / 3450 39H V 57' V4+(V3-V4)× 2300 / 3450 V 57'' V6+(V5-V6)× 1150 / 3450 3AH V 58' V4+(V3-V4)× 2100 / 3450 V 58'' V6+(V5-V6)× 1350 / 3450 3BH V 59' V4+(V3-V4)× 1850 / 3450 V 59'' V6+(V5-V6)× 1600 / 3450 3CH V 60' V4+(V3-V4)× 1600 / 3450 V 60'' V6+(V5-V6)× 1850 / 3450 3DH V 61' V4+(V3-V4)× 1300 / 3450 V 61'' V6+(V5-V6)× 2150 / 3450 3EH V62' V4+(V3-V4)× 800 / 3450 V62'' V6+(V5-V6)× 2650 / 3450 3FH V63' V4 V63'' V5 Output Voltage 1 Out put Voltage 2

Data Sheet S15843EJ3V0DS 9 µPD160061 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format : 6 bits x 2 RGBs (6 dots) Input width : 36 bits (2-pixel data) (1) R,/L = H (Right shift) Output S 1 S 2 S 3 S 4 ... S383 S 384 Data D 00 to D05 D 10 to D15 D 20 to D25 D 30 to D35 ... D40 to D45 D 50 to D55 (2) R,/L = L (Left shift) Output S 1 S 2 S 3 S 4 ... S383 S 384 Data D 00 to D05 D 10 to D15 D 20 to D25 D 30 to D35 ... D40 to D45 D 50 to D55 POL S2n–1 Note S 2n Note L V 0 to V4 V 5 to V9 H V 5 to V9 V 0 to V4 Note S 2n–1 (Odd output), S2n (Even output)

Data Sheet S15843EJ3V0DS 11 µPD160061 8. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM When the STB is high level, all output s became Hi-Z and the gray-scale voltage is output to the LCD in synchronization with the falling edge of STB. Therefore, high drive time of the output amplifier as below is determined by the CLK number of the required SRC pin setting. Be sure to avoid using such as extremely changing the CLK frequency (ex. CLK stop). Hi-Z STB Inside bias current POL Vx (odd output) Vx (even output) Hi-Z Hi-Z V5 - V9 V0 - V4 V0 - V4 V0 - V4 V5 - V9 V5 - V9 High drive time High drive time High drive time 9. SRC AND HIGH DRIVE TIME The µPD160061 can control high drive time of the output amplifier by SRC pin logic (refer to below figure). SRC = H or open (high drive time: standard mode): High drive time (PWhp) of the output amplifier is in 64 CLK period from falling edge of the STB. SRC = L (high drive time: long-term mode): High drive time (PWhp) of the output amp lifier is in 128 CLK period from falling edge of the STB. STB CLK Inside bias current PWhp We recommend a thorough simulation of the output amplifier in advance when set the SRC pin.

Data Sheet S15843EJ3V0DS 12 µPD160061 10. BIAS CURRENT CONTROL BY LPC AND HPC The µPD160061 can control the bias current of the output amplifier in high drive period and low drive period. Bias Current LPC HPC Panel Load High H L Heavy Middle L or open L Normal L or open H or open Low H H or open Light We recommend a thorough simulation of the output amplifier in advance, when set the LPC and HPC pins. Refer to the table below for the example of the combination of setting level and panel load, with driver part supply voltage. Example of Condition LPC HPC SRC L or open L Example 1 Load: R L = 5 kΩ, CL = 75 pF Driver part supply voltage: VDD2 = 7.5 V Bias current mode: Middle H or open L or open H or open Example 2 Load: R L = 5 kΩ, CL = 75 pF Driver part supply voltage: VDD2 = 9.0 V Bias current mode: Normal H or open H L Example 3 Load: R L = 40 kΩ, CL = 80 pF Driver part supply voltage: VDD2 = 9.0 V Bias current mode: High L

Data Sheet S15843EJ3V0DS 13 µPD160061 11. ELECTRICAL SPECIFICATIONS Parameter Symbol Rating Unit Logic Part Supply Voltage V DD1 –0.5 to +4.0 V Driver Part Supply Voltage V DD2 –0.5 to +10.0 V Logic Part Input Voltage V I1 –0.5 to V DD1 + 0.5 V Driver Part Input Voltage V I2 –0.5 to V DD2 + 0.5 V Logic Part Output Voltage V O1 –0.5 to V DD1 + 0.5 V Driver Part Output Voltage V O2 –0.5 to V DD2 + 0.5 V Operating Ambient Temperature T A –10 to +75 °C Storage Temperature T stg –55 to +125 °C Caution Product quality may suffer if the absolute m aximum rating is exceeded ev en momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Logic Part Supply Voltage V DD1 2.3 3.6 V Driver Part Supply Voltage V DD2 7.5 8.5 9.5 V High-Level Input Voltage V IH 0.7 V DD1 V DD1 V Low-Level Input Voltage V IL 0 0.3 V DD1 V γ -Corrected Voltage V 0 to V4 7.5 V ≤ VDD1 ≤ 9.5 V 0.5 V DD2 V DD2 – 0.2 V 8.5 V ≤ VDD1 ≤ 9.5 V 0.2 0.5 V DD2 V Driver Part Output Voltage V O 0.2 V DD2 – 0.2 V 2.3 V ≤ VDD1 < 2.7 V 40 MHz Clock Frequency f CLK 2.7 V ≤ VDD1 ≤ 3.6 V 65 MHz

Data Sheet S15843EJ3V0DS 14 µPD160061 Parameter Symbol Condition MIN. TYP. MAX. Unit Input Leak Current I IL Except LPC, HPC, SRC ±1.0 µA LPC, HPC, SRC ±150 µA High-Level Output Voltage V OH STHR (STHL), I OH = 0 mA V DD1 – 0.1 V Low-Level Output Voltage V OL STHR (STHL), I OL = 0 mA 0.1 V IVOH V DD2 = 8.0 V, VX = 7.0 V, VOUT = 6.5 V Note1 – 20 µA Driver Output Current IVOL V DD2 = 8.0 V, VX = 1.0 V, VOUT = 1.5 V Note1 20 µA Output Voltage Deviation ∆VO ±10 ±20 mV Output Swing Difference Deviation ∆VP–P TA = 25°C, VDD1 = 3.3 V, VDD2 = 8.5 V, VOUT = 2.0 V, 4.25 V, 6.5 V ±3 ±15 mV Logic Part Dynamic Current Consumption Note2, 3, 4 IDD1 V DD1 4 12 mA Driver Part Dynamic Current Consumption Note2, 4 IDD22 V DD2, with no load 3.5 8 mA Notes 1. V X refers to the output vo ltage of analog output pins S 1 to S384. V OUT refers to the voltage applied to analog output pins S1 to S384. 2. Specified at fSTB = 65 kHz and fCLK = 54 MHz. 3. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 4. Refers to the current consum ption per driver when cascades are connected under the a ssumption of XGA single-sided mounting (8 units). Switching Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 7.5 to 9.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit CL = 15 pF, 2.3 V ≤ VDD1 < 2.7 V 20 ns Start Pulse Delay Time t PLH1 CL = 10 pF, 2.7 V ≤ VDD1 ≤ 3.6 V 10.5 ns CL = 10 pF, 2.3 V ≤ VDD1 < 2.7 V 20 ns t PLH1 CL = 10 pF, 2.7 V ≤ VDD1 ≤ 3.6 V 10.5 ns tPLH2 5 µs tPLH3 8 µs tPHL2 5 µs Driver Output Delay Time tPHL3 CL = 75 pF, RL = 5 kΩ, LPC = L or open, HPC = H or open, SRC = H or open 8 µs CI1 Logic input of exclude STHR (STHL), TA = 25°C 10 pF Input Capacitance CI2 STHR (STHL), T A = 25°C 5 pF <Measurement condition> RLn = 1 kΩ, CLn = 15 pF GND Output The measurement point CL1 CL2 CL3 CL4 CL5 RL1 RL2 RL3 RL4 RL5

Data Sheet S15843EJ3V0DS 15 µPD160061 Timing Requirements (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns) Parameter Symbol Condition MIN. TYP. MAX. Unit 2.3 V ≤ VDD1 < 2.7 V 25 ns Clock Pulse Width PW CLK 2.7 V ≤ VDD1 ≤ 3.6 V 15 ns 2.3 V ≤ VDD1 < 2.7 V 6 ns Clock Pulse High Period PW CLK(H) 2.7 V ≤ VDD1 ≤ 3.6 V 4 ns 2.3 V ≤ VDD1 < 2.7 V 6 ns Clock Pulse Low Period PW CLK(L) 2.7 V ≤ VDD1 ≤ 3.6 V 4 ns Data Setup Time t SETUP1 4 ns Data Hold Time t HOLD1 0 ns Start Pulse Setup Time t SETUP2 4 ns Start Pulse Hold Time t HOLD2 0 ns POL21, POL22 Setup Time t SETUP3 4 ns POL21, POL22 Hold Time t HOLD3 0 ns STB Pulse Width PW STB 2 CLK Last Data Timing t LDT 2 CLK STB-CLK Time t STB -CLK STB ↑→ CLK ↑ 9 ns Time Between STB and Start Pulse t STB-STH STB ↑ → STHR(STHL) ↑ 2 CLK POL-STB Time t POL-STB POL ↑ or ↓ → STB ↑ –5 ns STB-POL Time t STB-POL STB ↓ → POL ↓ or ↑ 6 ns Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.

Data Sheet S15843EJ3V0DS 16 µPD160061 SWITCHING CHARACTERISTICS WAVEFORM (R,/L = H) Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. PW CLK(L) CLK POL Sn(V STB D to D STHR STHL PW CLK(H) tr tSETUP2 INVALID D 1to D tHOLD21 tf V DD1 V SS1 V DD1 V SS1 V DD1 V SS1 V DD1 V SS1 V DD1 V SS1 V DD1 V SS1 PW CLK tSTB-CLK tSTB-STH tSETUP1 90% 10% tHOLD1 tPLH1 tPOL-STB tSTB-POL tPLH3 tPLH2 tPHL2tPHL3 Hi-Z Target Voltage: 10% tLDT PW STB D 7to D D 1to D D 7to D D 373 to D 378 D 379 to D 384 D 385 to D 390 LastData INVALID INVALID V DD1 V SS1 tSETUP3 tHOLD3 POL21,POL22(1st Dr.) (1st Dr.) INVALID Target Voltage: 2%+−

Data Sheet S15843EJ3V0DS 17 µPD160061 12. RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for mounting conditions of the µPD160061. For more details, refer to the Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html). Please consult with our sales offices in case other m ounting process is used, or in case the mounting is done under different conditions. µ PD160061N - ×××: TCP (TAB package) Mounting Condition Mounting Method Condition Soldering Heating tool 300 to 350°C, heating for 2 to 3 seconds, pressure 100 g (per solder) Thermocompression ACF (Adhesive Conductive Film) Temporary bonding 70 to 100°C, pressure 3 to 8 kg/cm , time 3 to 5 seconds. Real bonding 165 to 180°C, pressure 25 to 45 kg/cm , time 30 to 40 seconds. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.) Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time.

Data Sheet S15843EJ3V0DS 18 µPD160061 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V IL (MAX) and V IH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V IL (MAX) and VIH (MIN). HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. NOTES FOR CMOS DEVICES

Product Information

UPD160061N specifications and overview.

Summary

384-OUTPUT TFT-LCD SOURCE DRIVER

Description

384-OUTPUT TFT-LCD SOURCE DRIVER

Source title UPD160061N Datasheet(PDF) - NEC

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