UPD160040A

UPD160040A NEC | Alldatasheet

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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. 2001 MOS INTEGRATED CIRCUIT µµµµPD160040A 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES) DATA SHEET Document No. S15918EJ1V0DS00 (1st edition) Date Published June 2003 NS CP (K) Printed in Japan The mark # shows major revised points.

DESCRIPTION

The µPD160040A is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scales. Data input is based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216 colors by output of 256 values γ -corrected by an internal D/A converter and 8-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.2 V to VDD2 – 0.2 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity.

FEATURES

• CMOS level input
• 384 outputs
• Input of 8 bits (gray scale data) by 6 dots
• Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter
• Logic power supply voltage (VDD1 ): 2.5 to 3.6 V
• Driver power supply voltage (VDD2 ): 12.5 to 15.5 V (switchable, VSEL )
• High-speed data transfer: fCLK = 55 MHz MAX. (internal data transfer speed when operating at 3.0 V ≤ VDD1 ≤ 3.6 V) = 40 MHz MAX. (internal data transfer speed when operating at 2.5 V ≤ VDD1 < 3.0 V)
• Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output voltage polarity inversion function (POL)
• Output inversion function (POL21, POL 22)
• Output reset control is possible (MODE)
• Slew-rate control is possible (SRC)
• Output resistance control is possible (ORC)
• Single bank arrangement is possible (Loaded with slim TCP)

ORDERING INFORMATION

µPD160040AN-xxx TCP (TAB package) Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our sales representatives.

µµµµPD160040A 1. BLOCK DIAGRAM 64-bit bidirectional shift register C 1 C2 C 63 C64 Data register Latch D/A converter Voltage follower output S1 S2 S3 S384 V0-V15 POL D 00-D07 D 10-D17 D 20-D27 STHR R,/L CLK STB MODE STHL V DD1 VSS1 D 30-D37 D 40-D47 D50-D57 POL21 POL22 Level shifter VSS2 VDD2 SRC ORC VSEL TEST Input Remark /xxx indicates active low signal. 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 S2 S383 S384 8-bit D/A converter Multi- plexer POL

Data Sheet S15918EJ1V0DS 3 µµµµPD160040A 3. PIN CONFIGURATION (µµµµPD160040AN-xxx: TCP) (Copper Foil Surface, Face-up) S384 S383 STHL S382 D 57 D 56 D 51 D 50 D 47 D 46 D 41 D 40 D 37 D 36 D 31 D 30 SRC ORC VSEL VDD1 R,/L V 15 V 14 V 13 V 12 V 11 V 10 VDD2 VSS2 VSS1 MODE TEST CLK STB POL POL22 POL21 D 27 D 26 D 21 D 20 D 17 D 16 D 11 D 10 D 07 D 06 D 01 S 3 D 00 S 2 STHR S 1 C opper Foil Surface Remark This figure does not specify the TCP package.

µµµµPD160040A 4. PIN FUNCTIONS (1/2) Pin Symbol Pin Name I/O Description S1 to S384 Driver Output The D/A converted 256-gray-scale analog voltage is output. D 00 to D07 Port 1 display data Input The display data is input with a width of 48 bits, viz., the gray scale data D 10 to D17 (8 bits) by 6 dots (2 pixels). D 20 to D27 D X0: LSB, DX7: MSB D 30 to D37 Port 2 display data Input D 40 to D47 D 50 to D57 R,/L Shift direction control Input The shift direction control pin of shift register. The shift directions of the shift registers are as follows. R,/L = H (right shift): STHR input → S 1→ S384→ STHL output R,/L = L (left shift) : STHL input → S384→ S1→ STHR output STHR Right shift start pulse I/O STHL Left shift start pulse I/O These are the start pulse input/output pins when connected in cascade. Loading of display data starts when a high level is read at the rising edge of CLK. At the rising edge of the 64th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. For right shift, STHR is input and STHL is output. For left shift, STHL is input and STHR is output. CLK Shift clock Input The shift clock input pin of shift register. The display data is loaded into the data register at the rising edge. When 66 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. STB Latch Input The contents of the data register are transferred to the latch circuit at the rising edge. In addition, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. SRC Slew-rate control Input SRC = H: High-slew-rate mode (large current consumption) SRC = L: Low-slew-rate mode (small current consumption) SRC is pulled up to the V DD1 in the IC. ORC Output resistance control Input ORC = H: Low output resistance mode ORC = L: High output resistance mode ORC is pulled up to the V DD1 in the IC. POL Polarity Input POL = L: The S 2n−1 output uses V0-V7 as the reference supply. The S2n output uses V8-V15 as the reference supply. POL = H: The S2n−1 output uses V8-V15 as the reference supply. The S2n output uses V0-V7 as the reference supply. S2n−1 indicates the odd output and S2n indicates the even output. Input of the POL signal is allowed the setup time (tPOL –STB ) with respect to STB ’s rising edge. When it switches such as POL = H→ L or L→ H, all output pins are output reset during STB = H. When it does not switch, all output pins become Hi-Z (High impedance) during STB = H. Refer to 7. RELATIONSHIP BETWEEN MODE, STB, SRC, ORC, POL AND OUTPUT WAVEFORM for details.

Data Sheet S15918EJ1V0DS 5 µµµµPD160040A (2/2) Pin Symbol Pin Name I/O Description MODE Output reset control Input MODE = H or open: Output reset MODE = L: No output reset MODE is pulled up to the V DD1 in the IC. POL21, POL22 Data inversion Input Select of inversion or no inversion for input data. POL21: Data inversion or no inversion of Port1. POL22: Data inversion or no inversion of Port2 POL21, POL22 = H: Data are inverted in the IC. POL21, POL22 = L: Data are not inverted in the IC. VSEL Driver voltage select Input The driver voltage can be switched by controlling the stationary bias current of the output amplifier via VSEL . VSEL = H: VDD2 = 12.5 to (14.0 V) (Large bias current) VSEL = L or open: VDD2 = (14.0 V) to 15.5 V (Small bias current) LPC is pulled down to the VSS1 in the IC. V0-V15 γ -corrected power supplies − Input the γ -corrected power supplies from outside by using operational amplifier. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. Make sure to maintain the following relationships. V TEST Test I Normally, set the TEST pin to high level or leave open. This pin is pulled up to VDD1 in the IC. VDD1 Logic power supply − 2.5 to 3.6 V VDD2 Driver power supply − 12.5 to 15.5 V VSS1 Logic ground − Grounding VSS2 Driver ground − Grounding Cautions 1. The power start sequence must be VDD1 , logic input, and VDD2 & V0-V15 in that order. Reverse this sequence to shut down. 2. To stabilize the supply voltage, please be sure to insert a 0.47 µµµµF bypass capacitor between VDD1 -VSS1 and V DD2 -VSS2 . Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.1 µµµµF is also advised between the γγγγ-corrected

µµµµPD160040A 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The µPD160040A incorporates a 8-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD’s counter electrode voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors (r0 to r253) are designed so that the ratio of LCD panel ( γ -compensated voltages to V0’-V255’ and V0”-V255” is almost equivalent as shown in Figure 5−2. For the 2 sets of eight γ -compensated power supplies, V0-V7 and V8-V15, respectively, input gray scale voltages of the same polarity with respect to the 0.5 VDD2 . Figure 5−1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 , VSS2 and 0.5 VDD2 , and γ -corrected voltages V0-V15 and the input data. Be sure to maintain the voltage relationships below. VDD2 –0.2 V ≥ V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 ≥ 0.5 VDD2 +0.5 V 0.5 VDD2 –0.5 V ≥ V8 > V9 > V10 > V11 > V12 > V13 > V14 > V15 ≥ 0.5 VSS2 +0.2 V Also, V6-V7 and V8-V9 are left open in the IC. Be sure to input the gray scale level power supply at a constant level to the all pins, as V0-V15. Figures 5−2 shows γ-Corrected Voltages and Ladder Resistors Ratio and figure 5−3 shows the relation ship between the input data and the output voltage (POL21, POL22 = L). Figure 5−−−−1. Relationship between Input Data and γ γ γ γ -corrected Power Supplies V DD2 0.2 V

0.2 V V SS2

Input data (HEX) 01 20 C0 V10 V11 V12 V13 V14 V15 0.5 V 0.5 V

0.5 VDD2

Data Sheet S15918EJ1V0DS 7 µµµµPD160040A Figure 5−−−−2. γγγγ-Corrected Voltages and Ladder Resistors Ratio V243’’ V244’’ V245’’ V254’’ V255’’ V3’’ V4’’ V31’’ V32’’ V33’’ V5’’ r29 r30 r31 r32 V10 r241 r242 r243 r244 V14 V2’’ V15 V1’’V9 V0’’V8 V33’ V32’ V31’ V3’ V2’ V1’ V253’ V245’ V244’ V243’ r251 r244 r243 r242 r241 r252 r32 r31 r30 r29 V4’ V0’V7 V254’ r253 r252 r253 V255’ rn Ratio 1 Ratio 2 Value rn Ratio 1 Ratio 2 Value rn Ratio 1 Ratio 2 Value rn Ratio 1 Ratio 2 Value Remark The resistance ratio1 is a relative ratio in the case of setting the minimum resistance value to 1. The resistance ratio2 is a relative ratio in the case of setting the total resistance to 1.

µµµµPD160040A Figure 5−−−−3. Relationship between Input Data and Output Voltage (POL21, POL22 = L) (1/2) (Output voltage1) VDD2 – 0.2 V ≥≥≥≥ V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 ≥≥≥≥ 0.5 VDD2 + 0.5 V Data Data Data Data 00H V0' V7 40H V64' V4 80H V128' V3 C0H V192' V2 Output voltage1 Output voltage1 Output voltage1 Output voltage1

Data Sheet S15918EJ1V0DS 9 µµµµPD160040A Figure 5−−−−3. Relationship between Input Data and Output Voltage (POL21, POL22 = L) (2/2) (Output voltage2) 0.5 VDD2 − − − − 0.5 V ≥≥≥≥ V8 > V9 > V10 > V11 > V12 > V13 > V14 > V15 ≥≥≥≥ 0.5 VSS2 +0.2 V Data Data Data Data 00H V0" V8 40H V64" V11 80H V128" V12 C0H V192" V13 Output voltage2 Output voltage2 Output voltage2 Output voltage2

Data Sheet S15918EJ1V0DS10 µµµµPD160040A 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format: 8 bits x 2 RGBs (6 dots) Input width: 48 bits (2-pixel data) (1) R,/L = H (Right shift) Output S 1 S2 S3 S4 … S383 S384 Data D 00 to D07 D 10 to D17 D 20 to D27 D 30 to D37 … D 40 to D47 D 50 to D57 (2) R,/L = L (Left shift) Output S 1 S2 S3 S4 … S383 S384 Data D 00 to D07 D 10 to D17 D 20 to D27 D 30 to D37 … D 40 to D47 D 50 to D57 POL S2n–1 Note S2n Note LV 0-V7 V8-V15 HV 8-V15 V0-V7 Note S2n–1 (Odd output), S2n (Even output), n = 1, 2, ..., 192.

Data Sheet S15918EJ1V0DS 11 µµµµPD160040A 7. RELATIONSHIP BETWEEN MODE, STB, SRC, ORC, POL AND OUTPUT WAVEFORM When MODE = H or open and STB is high level, all outputs are reset (shorted) and the gray-scale voltage is output to LCD in synchronization with the falling edge of STB. When MODE = L and STB is high level, all outputs became Hi-Z and the gray-scale voltage is output to the LCD in synchronization with the falling edge of STB. Also, setting the SRC pin to high level allows the bias current value of the output amplifier to rise temporarily, and setting the ORC pin to high level allows the output resistance value of the amplifier to lower temporarily. For the timing and the processing of STB, SRC, or ORC during a high-level period, We recommend a thorough evaluation of the LCD panel specifications in advance. (1) MODE = H or open STB POL S2n–1 S2n ResetResetReset SRC ORC Low-slew-rate period High output resistance period Voltage selected form V0 to V7 Voltage selected form V0 to V7 Voltage selected form V8 to V15 Voltage selected form V0 to V7 Voltage selected form V8 to V15 High-slew-rate period Voltage selected form V8 to V15 Low output resistance period

Data Sheet S15918EJ1V0DS12 µµµµPD160040A (2) MODE = L STB POL S2n–1 S2n Hi-ZHi-ZHi-Z SRC ORC Low-slew-rate period High-slew-rate period High output resistance period Low output resistance period Voltage selected form V0 to V7 Voltage selected form V8 to V15 Voltage selected form V0 to V7 Voltage selected form V8 to V15 Voltage selected form V0 to V7 Voltage selected form V8 to V15

Data Sheet S15918EJ1V0DS 13 µµµµPD160040A 8. ELECTRICAL SPECIFICATIONS Parameter Symbol Ratings Unit Logic part supply voltage V DD1 –0.5 to +4.0 V Driver part supply voltage V DD2 –0.5 to +17.0 V Logic part input voltage V I1 –0.5 to VDD1 + 0.5 V Driver part input voltage V I2 –0.5 to VDD2 + 0.5 V Logic part output voltage V O1 –0.5 to VDD1 + 0.5 V Driver part output voltage V O2 –0.5 to VDD2 + 0.5 V Operating ambient temperature TA –10 to +75 °C Storage temperature T stg –55 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (T A = –10 to +75°C, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Logic part supply voltage V DD1 2.5 3.6 V VSEL = H 12.5 13.0 (14.0) VDriver part supply voltage V DD2 VSEL = L or open (14.0) 15.0 15.5 V High-level input voltage V IH 0.7 VDD1 VDD1 V Low-level input voltage V IL 0 0.3 V DD1 V γ -corrected voltage V 0-V7 0.5 VDD2 + 0.5 V DD2 − 0.2 V V8-V15 0.2 0.5 V DD2 − 0.5 V Driver part output voltage V O 0.2 V DD2 − 0.2 V Clock frequency f CLK 3.0 V ≤ VDD1 ≤ 3.6 V 55 MHz 2.5 V ≤ VDD1 < 3.0 V 40 MHz Remark The value enclosed in parentheses is a reference value.

Data Sheet S15918EJ1V0DS14 µµµµPD160040A Parameter Symbol Condition MIN. TYP. MAX. Unit Input leakage current I IL ±1.0 µA High-level output voltage V OH STHR (STHL), IOH = 0 mA V DD1 − 0.1 V Low-level output voltage V OL STHR (STHL), IOL = 0 mA 0.1 V γ -corrected power supply static Iγ VDD2 = 15.0 V, V 0, V8 pins 340 681 1020 µA current consumption V 0-V7 = V8-V15 = 7.0 V V 7, V15 pins −1020 −681 −340 µA Driver output current I VOH VX = 12 V, VOUT = 11 V Note1 −0.40 mA IVOL VX = 1 V, VOUT = 2 V Note1 0.65 mA Output voltage deviation ∆VO TA = 25°C, VSS2 +1.0 V to VDD2 − 1.0 V ±10 ±20 mV ∆VP-P1 VOUT = 7.0 to 8.0 V Note1 ±5 ±10 mV ∆VP-P2 VOUT = 4.0 to 11.0 V Note1 ±7 ±15 mV Output swing voltage difference deviation ∆VP-P3 VDD1 = 3.3 V, VDD2 = 15.0 V, TA = 25°C VOUT = 1.0 to 14.0 V Note1 ±10 ±20 mV Logic part dynamic current consumption IDD1 VDD1 Notes 2,3 1.3 12 mA Driver part dynamic current consumption IDD2 VDD2 , with no load Notes 3,4 12 30 mA Notes 1. VX refers to the output voltage of analog output pins S1 to S384. VOUT refers to the voltage applied to analog output pins S1 to S384 2. fSTB = 64 kHz, fCLK = 54 MHz 3. The TYP. values refer to an all black or all white input pattern. The MAX. Value refers to the measured values in the dot checkerboard input pattern. 4. Refers to the current consumption per driver when cascades are connected under the assumption of SXGA single-sided mounting (10 units). Switching Characteristics (TA = −−−−10 to +75°°°°C, VDD1 = 2.5 to 3.6 V, VDD2 = 12.5 to 15.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Start pulse delay time t PLH1 C L = 15 pF, 3.0 V ≤ VDD1 ≤ 3.6 V 17 ns C L = 15 pF, 2.5 V ≤ VDD1 < 3.0 V 24 ns Driver output delay time tPLH2 Note C L = 100 pF, RL = 10 kΩ 5 µs tPLH3 Note 10 µs tPHL2 Note 5 µs tPHL3 Note 10 µs Input capacitance C I1 logic input, except STHR (STHL), TA = 25°C 51 0 p F C I2 STHR (STHL), TA = 25°C1 0 1 5 p F Note tPLH2 , tPHL2 refer to the arrival time from falling edge of STB to target voltage ±10% tPLH3 , tPHL3 refer to the arrival time from falling edge of STB to target voltage ±0.02 V (condition: VO = 3.0 V ↔ 12.0 V) <Test Condition> Output C L1 C L2 C L3 R L3R L2 R L5 R Ln = 2 kΩ C Ln = 20 pF C L4 R L4 C L5 R L1 Measurement point GND

Data Sheet S15918EJ1V0DS 15 µµµµPD160040A Timing Requirements (TA = −−−−10 to +75°C, VDD1 = 2.5 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns) Parameter Symbol Condition MIN. TYP. MAX. Unit Clock pulse width PW CLK 3.0 V ≤ VDD1 ≤ 3.6 V 18 ns 2.5 V ≤ VDD1 < 3.0 V 25 ns Clock pulse high period PW CLK (H) 3.0 V ≤ VDD1 ≤ 3.6 V 4 ns 2.5 V ≤ VDD1 < 3.0 V 6 ns Clock pulse low period PW CLK (L) 4n s Data setup time t SETUP1 0n s Data hold time t HOLD1 4n s Start pulse setup time t SETUP2 0n s Start pulse hold time t HOLD2 4n s POL21, POL22 setup time t SETUP3 0n s POL21, POL22 hold time t HOLD3 4n s STB pulse width PW STB 1.0 µs Last data timing t LDT 2C L K CLK-STB time t CLK-STB CLK ↑→ STB↑ 4n s STB-CLK time t STB-CLK STB ↑→ CLK↑ 4n s Time between STB and start pulse tSTB-STH STB ↑→ STHR (STHL) ↑ 2C L K POL-STB time t POL-STB POL ↑ or ↓→ STB ↑ 4n s STB-POL time t STB-POL STB ↓→ POL ↓ or ↑ 4n s STB-SRC time t STB-SRC STB ↑ → SRC ↑ 0n s STB-ORC time t STB-ORC STB ↓→ ORC ↑ 0n s Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1 , VIL = 0.3 VDD1 .

Data Sheet S15918EJ1V0DS16 µµµµPD160040A Switching Characteristic Waveform (1) R,/L= H, MODE = H or open Unless otherwise specified, VIH, VIL are defined to be VIH = 0.7 VDD1 , VIL = 0.3 VDD1 (Numbers clock and display data are example when in SXGA). PW CLK(L) CLK POL Sn (Vx) STB D n0 to D n7 STHR (1st Dr.) STHL (1st Dr.) PW CLK(H) tr tSETUP2 Invalid D 1 to D 6 tHOLD2 36 4 6 5 6 6 641 642 tf VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 PW CLK tCLK-STB tSTB-CLK tSTB-STHtSETUP1 90 % 10 % tHOLD1 tPLH1 tPOL-STB tSTB-POL tPLH3 tPLH2 tPHL2 tPHL3 tLDT PW STB D 7 to D 12 D 1 to D 6 D 7 to D 12D 373 to D 378 D 385 to D 390 D 3835 to D 3840 Invalid Invalid VDD1 VSS1 Invalid POL21, POL22 D 379 to D 384 tHOLD3tSETUP3 SRC, ORC VDD1 VSS1 tSTB-SRC tSTB-ORC

Data Sheet S15918EJ1V0DS 17 µµµµPD160040A (2) R,/L= H, MODE = L Unless otherwise specified, VIH, VIL are defined to be VIH = 0.7 VDD1 , VIL = 0.3 VDD1 (Numbers clock and display data are example when in SXGA). PW CLK(L) CLK POL STB D n0 to D n7 STHR (1st Dr.) STHL (1st Dr.) PW CLK(H) tr tSETUP2 Invalid D 1 to D 6 tHOLD2 36 4 6 5 6 6 641 642 tf VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 PW CLK tCLK-STB tSTB-CLK tSTB-STHtSETUP1 90 % 10 % tHOLD1 tPLH1 tPOL-STB tSTB-POL tPLH3 tPLH2 tPHL2 tPHL3 Hi-Z tLDT PW STB D 7 to D 12 D 1 to D 6 D 7 to D 12D 373 to D 378 D 385 to D 390 D 3835 to D 3840 Invalid Invalid VDD1 VSS1 InvalidPOL21, POL22 D 379 to D 384 tHOLD3tSETUP3 SRC, ORC VDD1 VSS1 tSTB-SRC tSTB-ORC Sn (Vx)

Data Sheet S15918EJ1V0DS18 µµµµPD160040A 9. RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for mounting conditions of the µPD160040A. For more details, refer to the [Semiconductor Device Mount Manual] (http://www.n ecel.com/pkg/en/mount/index.html) Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. µPD160040AN- xxx: TCP (TAB Package) Mounting Condition Mounting Method Condition Thermocompression Soldering Heating tool 300 to 350 °C, heating for 2 to 3 sec, pressure 100g (per solder). ACF (Adhesive Conductive Film) Temporary bonding 70 to 100°C, pressure 3 to 8 kg/cm 2, time 3 to 5 sec. Real bonding 165 to 180°C pressure 25 to 45 kg/cm2, time 30 to 40 sec. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.) Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time.

Data Sheet S15918EJ1V0DS 19 µµµµPD160040A NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.