UPD121A10 RENESAS | Alldatasheet
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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. 2007 MOS INTEGRATED CIRCUIT μ PD121A10 2-POWER SUPPLY INPUT METHOD 1.0 V/2.0 A REGULATOR DATA SHEET Document No. G18843EJ1V0DS00 (1st edition) Date Published July 2007 NS Printed in Japan
DESCRIPTION
μ PD121A10 is the CMOS regulator which can output 2.0 A current. This regulator is suitable for power supply for 1.0 V ASIC core, for example our companies’ CB-90 (90 nm process LSI) etc. The dropout voltage is made small (0.7 V MAX. (IO = 1.0 A) by dividing bias voltage (V DD) from input voltage (V IN). Therefore this product can output under the
FEATURES
- Output Current: 2.0 A
- Output Voltage: 0.95 to 1.15 V
- Bias Voltage: 4.0 to 5.5 V
- Reference Voltage Tolerance: VREF ± 10 mV (TJ = 25°C)
- Low Dropout Voltage: VDIF = 0.7 V MAX. (IO = 1.0 A)
- On-chip over-current protection circuit
- On-chip thermal shut down circuit
APPLICATIONS
This regulator is suitable for low power supply voltage IC, for example core of CB-90 (90 nm process LSI) etc. BLOCK DIAGRAM VDD INPUT OUTPUT SENSE GND Reference voltage Constant current Over-current protection Thermal shut down Error amp. Buffer Triming PIN CONFIGURATION (Marking Side) 5-PIN TO-252 (5-PIN MP-3ZK) 12345 Note No.3 pin is cut and can not be connected to substrate. No.6 is Fin and common to GND pin. 1. INPUT 2. VDD (ON/OFF) 3. GND Note 4. SENSE 5. OUTPUT 6. GND (Fin)
Data Sheet G18843EJ1V0DS 2 μ PD121A10
ORDERING INFORMATION
Part Number Package Reference Voltage Output Voltage Marking μ PD121A10T1F 5-PIN TO-252 (5-PIN MP-3ZK) 0.6 V 0.95 to 1.15 V 121A10 Remark Since it is the tape-packaged product, “-E1” or “-E2” is added to the end of its product name. Part Number Note Package Package Type μ PD121A10T1F-E1-AT 5-PIN TO-252 (5-PIN MP-3ZK) • 16 mm wide embossed taping
- Pin 1 on draw-out side
- 2,500 pcs/reel μ PD121A10T1F-E2-AT 5-PIN TO-252 (5-PIN MP-3ZK) • 16 mm wide embossed taping
- Pin 1 at take-up side
- 2,500 pcs/reel Note Pb-free (This product does not contain Pb in the external electrode and other parts.) ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise specified) Parameter Symbol Rating Unit Input Voltage VIN −0.3 to +6.0 V Bias Voltage VDD −0.3 to +6.0 V Internal Power Dissipation (TC = 25°C) Note PT 10 W Operating Ambient Temperature TA −20 to +85 °C Operating Junction Temperature TJ −20 to +150 °C Storage Temperature Tstg −55 to +150 °C Thermal Resistance (junction to ambient) R th(J-A) 125 °C/W Thermal Resistance (junction to case) R th(J-C) 12.5 °C/W Note Internally limited. When the operati ng junction temperature rises above 150° C, the internal circuit shuts down the output voltage. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum rating s are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. TYPICAL CONNECTION PD121A10 GND GND INPUT OUTPUT SENSE OUTPUTINPUT CIN COUT VDD μ
Data Sheet G18843EJ1V0DS 3 μ PD121A10 CIN : 0.1 μ F or higher. Be sure to connect CIN to prevent parasitic oscillation. Set this value according to the length of the line between the regulator and the INPUT pin. Use of a film capacitor or other capacitor with first-rate voltage and temperature characteristics is recommended. If using a laminated ceramic capacitor, it is necessary to ensure that CIN is 0.1 μ F or higher for the voltage and temperature range to be used. COUT : 10 μ F or higher. Be sure to connect COUT to prevent oscillation and improve excessive load regulation. Place CIN and COUT as close as possible to the IC pins (within 1 to 2 cm). Use the capacitor whose capacitance value is 10 μ F or more under use conditions. D1 : If the OUTPUT pin has a higher voltage than the INPUT pin, connect a diode. D2 : If the OUTPUT pin has a lower voltage than the GND pin, connect a Schottky barrier diode. R1, R2: The total amount of R1 and R2 is sure to below 200 kΩ (100 kΩ TYP .). VOUT = (1 + R1/R2) VREF Note Note When VOUT = 1 V: R1 = 40 kΩ, R2 = 60 kΩ Caution1. Make sure that no external voltage is applied to the OUTPUT pin. 2. VDD pins (Bias voltage) must be supplied in a separate power supply from that of INPUT pins (Input voltage). RECOMMENDED OPERATING CONDITIONS Parameter Symbol MIN. TYP. MAX. Unit Input Voltage (VO = 1.0 V) VIN 1.62 Note 2.0 2.65 V Output Voltage VO 0.95 1.0 1.15 V Bias Voltage VDD 4.0 5.0 5.5 V Output Current IO 0 2.0 A Operating Ambient Temperature TA − 20 + 85 °C Operating Junction Temperature TJ − 20 + 125 °C Note It needs 1.7 V ≤ VIN ≤ 2.65 V to output IO = 2.0 A. Caution1. Power on V IN first, and then V DD on start-up. When the power is turned off, turn off V DD first. Note that the voltage of VDD must not be kept 3.0 V or less. 2. If absolute maximum rating is not exceeded, you can used this product above the recommended operating range. However, since a margin with absolute maximum rating decreases, please use this product after sufficient evaluation.
Data Sheet G18843EJ1V0DS 4 μ PD121A10
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions MIN. TYP. MAX. Unit VREF1 − 0.59 0.6 0.61 V Reference Voltage (SENSE pin) Line Regulation REGIN 1.7 V ≤ VIN ≤ 2.65 V − 1 15 mV Load Regulation REGL 0 A ≤ IO ≤ 2.0 A − 1 15 mV IBIAS1 I O = 0 A − 125 500 μ A Quiescent Current IBIAS2 I O = 2.0 A − 300 1000 μ A ΔIBIAS1 4.0 V ≤ VDD ≤ 5.5 V, IO = 0 A − 12 300 μ A Quiescent Current Change ΔIBIAS2 0 A ≤ IO ≤ 2.0 A − 100 500 μ A Output Noise Voltage Vn 10 Hz ≤ f ≤ 100 kHz − 230 − μ Vr.m.s. Ripple Rejection R • R f = 1 kHz, 1.8 V ≤ VIN ≤ 2.2 V − 56 − dB Dropout Voltage VDIF I O = 1.0 A − 0.17 0.7 V Short Circuit Current IOshort V O = 0 V − 3.0 − A Peak Output Current IOpeak 4.0 V ≤ VDD ≤ 5.5 V 2.0 − − A Temperature Coefficient of Output Voltage ΔVO/ΔT I O = 0 A, 0°C ≤ TJ ≤ 125°C − 0.14 − mV/°C ON-state Voltage (VDD) VDD(ON) − 4.0 − − V OFF-state Voltage (VDD) VDD(OFF) − − − 0.5 V IBIAS(ON1) I O = 0 A − IBIAS1 − μ A ON-state Bias Pin (VDD Pin) Current IBIAS(ON2) I O = 2.0 A − IBIAS2 − μ A OFF-state Bias Pin (VDD Pin) Current Note IBIAS(OFF) I O = 0 A, VDD = 0 V − − 1 μ A Note Standby Current Remark Values in parentheses are product design values, and are thus provided as reference values.
Data Sheet G18843EJ1V0DS 5 μ PD121A10 TYPICAL CHARACTERISTICS PD vs. TA Δ VREF vs.TJ PD - Power Dissipation - W 50 85 100 150 1.0 With infinite heatsink Without heatsink TA - Operating Ambient Temperature - °C Δ VREF - Reference Voltage Temperature Change - mV 10.0 5.0 -5.0 -10.0 -20 0 25 50 75 100 125 VIN = 2.0 V VDD = 5.0 V IO = 1.0 A TJ - Operating Junction Temperature - °C VO vs. VDD IBIAS vs. VDD VO - Output Voltage - V 0.2 0.4 0.6 0.8 1.0 1.2 TJ = 25°C VIN = 2.0 V IO = 0 A 0.1 A 1.0 A VDD - Bias Voltage - V IBIAS - Quiescent Current - μ A 100 150 200 TJ = 25°C VIN = 2.0 V IO = 0 A 0.1 A 1.0 A VDD - Bias Voltage - V VDIF vs. TJ R • R vs. f VDIF - Dropout Voltage - V -20 0 25 50 75 100 125 VDD = 5.0 V IO = 1.0 A 0.3 0.25 0.2 0.15 0.1 0.05 TJ - Operating Junction Temperature - °C R • R - Ripple Rejection - dB TJ = 25°C VIN = 1.8 to 2.2 V VDD = 5.0 V CIN = 0.1 μ F COUT = 10 μ F IO = 0 A 1.0 A 2.0 A f - Frequency - Hz 10 100 1 k 10 k 100 k
Data Sheet G18843EJ1V0DS 6 μ PD121A10 VDD(ON) vs. TJ VDD(OFF) vs. TJ VDD(ON) - ON-state Voltage - V 4.0 3.0 2.0 1.0 -20 0 25 50 75 100 125 VIN = 2.0 V TJ - Operating Junction Temperature - °C VDD(OFF) - OFF-state Voltage - V -20 0 25 50 75 100 125 1.5 1.0 0.5 VIN = 2.0 V TJ - Operating Junction Temperature - °C VO vs. IO VO - Output Voltage - V TJ = 25°C VIN = 2.0 V VDD = 5.0 V 1.25 1.0 0.75 0.50 0.25 IO - Output Current - A
Data Sheet G18843EJ1V0DS 7 μ PD121A10 PACKAGE DRAWING (Unit: mm) 5-PIN TO-252 (MP-3ZK) E A D 12 34 5 H e E1 L1 ITEM DIMENSIONS D E H A b e 6.10 4.4TYP(4.0MIN) 4.4TYP(4.3MIN) ±0.20 6.50 ±0.20 9.8TYP(10.3MAX) 0 to 0.25 2.30± 0.10 0.60± 0.10 0.50± 0.10 0.50± 0.10 1.52± 0.12 5.0 (UNIT:mm) 0.508 1.14 1.0 0.80 L c 2006 b GAUGE PLANE SEATING PLANE NOTE 1. No Plating area Lc P5T1F-114-1
Data Sheet G18843EJ1V0DS 8 μ PD121A10 RECOMMENDED MOUNTING CONDITIONS The μ PD121A10 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than th ose recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) μ PD121A10T1F-AT Note: 5-PIN TO-252 (5-PIN MP-3ZK) Process Conditions Symbol Infrared reflow Package peak temperature: 260°C, Time: 60 seconds MAX. (at 220°C or higher), Count: Three times, Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. IR60-00-3 Partial Heating Method Pin temperature: 350 °C or below, Heat time: 3 seconds or less (per each side of the device). P350 Note Pb-free (This product does not contain Pb in the external electrode and other parts.) Caution Apply only one kind of soldering condition to a device, except for "partial heating method", or the device will be damaged by heat stress. REFERENCE DOCUMENTS USER’S MANUAL USAGE OF THREE TERMINAL REGULATORS Document No.G12702E INFORMATION VOLTAGE REGULATOR OF SMD Document No.G11872E SEMICONDUCTOR DEVICE MOUNT MANUAL http:// www.necel.com/pkg/en/mount/index.html
Data Sheet G18843EJ1V0DS 9 μ PD121A10 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V IL (MAX) and V IH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V IL (MAX) and VIH (MIN). HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. NOTES FOR CMOS DEVICES
μ PD121A10 The information in this document is current as of July, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customer- designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) M8E 02. 11-1 (1) (2) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "Standard": "Special": "Specific":