UPB8282 NEC | Alldatasheet

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: E C . uPB8282/83 NEC Electronics Inc. 8-BIT LATCHES Description Pin Configurations The yPB8262 and »PB8283 are &-bit latches with three- state output buffers. The zPB8282 is non-inverting and ood prec tech BP veo the yPB8283 inverts the input data. These devices are od pros a2 19410 ad hoo ods 1h 60, ideal for demultiplexing the address/data buses on va Foo; pads 17100 the 8085A/8086 microprocessors. The ¢PB8282/83 are od Boo, oudds 8 fo0, fabricated using NEC's Schottky bipolar process. ond boo. =o ce Es fhe. ow eT ee) S12 Features on fo =o] 13 005 oq foo, =e fo 12 fi, CO Support «PB8080, 8085A, 8048, 8086 family ono | fsre — cnocfr0 upste systems soma (i Transparent during active strobe C Fully paraliel &-bit data register and buffer Pin Functions C High output drive capability (82 mA) for driving = _ the system data bus OE (Output Enable) O Three-state outputs This active low input control signal enables the con- ‘i 5 1 tents of the data latches onto the data output pins Ordering Information (Bo-B7). When OE goes high, the output buffers Part ‘Output Drive become high impedance. Number Package Type Capenitty uPBB2B20 20-pin plastic DIP 32 mA STB (Strobe) ¥PBB283C 20-pin plastic DIP 32 mA This input control pulse strobes data at input Ag-A7 into the data latches. Data is latched at STB's high Pin Identification to low transition. When active high, STB admits in- to Symboy_ CC _Funetion 2

18 DloDlz Oata in Dig-Di7 (Data In)

—_— —____ When data that satisfies the STB strobe setup time jo GND Ground requirements is input to these pins, it Is latched into uN STB Strobe the data latches. 1249 (uPBB282) D07-D0o Data out (uPB8283) 007-000 1D0p-DO7 (uPB8282) (Data Out) 0 Vee Power supply DOo-DO7 (.PB8283) When OE is active (low), it outputs data to the DOp-DO; pins. When OE is inactive high, DO9-DO; are high impedance. Enabling or disabling the output buf- fers will not cause negative-going transients to appear on the data output bus. GND (Ground) This is the ground. Vcc (Power Supply) This is the +5 V power supply. 8417

a _ 8283 7) ia 1 a an ] =| OB G+ ts} ++ 1 fF 1 1 F | lem a r= _—a ) al rey ie) aL 2) ~ ----— ny my ----- aN Ke) —_ red es) = e) ra) ----- ny lan —---— zy ) ae 2) ee) iL ee) on <a las 7 oo ZY Keo} al S) () = 1) Tem ----- ry Hy ----- my One e) Ok ee) | ~ ----- rm ~ oo ~ Os S GH Om a = ran al _—— ma GH He onny S) LN AN £\\ LN | ™ AS TaN os ey e) i) ©) _ sore Functional Description DC Characteristics ‘The /PB8282/83 are 8-bit latches with three-state out-_ TA= 0°C 10 *70°C:Voo = +8 V 10% put buffers. Data on the inputs is latched into the data Uitts Tost latches on a high-to-low transition of the STB fine. —_ parameter Symbol Min Max Unit Conditions When STB is high, the latches appear transparent. input damp Ve TV ga cb mA The OE input enables the latched data to be transfer- —_vottage red to the output pins. When OE is high, the outputs ower suppy ige”SC*C~CSs mA are put in the three-state condition. OE will not cause current transients to appear on the data outputs. Forward input 02 mA Vpe0dsV current Absolute Maximum Ratings Reverse input i SOA V5 Ta = 25°C current Operating temperature OC to +70°C Output low voltage Vou 0.45 Vly = 32 mA Storage temperature -85°C to +150°C ome high Vou 2.4 Vo oy = -5 ma ‘il eutput and supply voltages 0510470 ee UN pS PEE Aiinput voltages SS”S~*~*~S*S*S~S to yt current _Ioge £50 uA Vor = 0.45 10 5.25 V $$ _ipntiow'vorage vy 08 V Veco = 50Vi) Comment: Exposing the device to stresses above those listed inj nee ye Absolute Maximum Ratings could cause permanent damage. The !®Put high voltage Vin 2.0 WV Veg = S.OV(1) device is not meant to be operated under conditions outside the ‘Input capacitance Cy 12 pF Vaiss = 2.5 Vy limits described in the operational sections of this specification. Voc = 5V. Ta = 25°C, Exposure to absolute maximum rating conditions for extended F = 1 MHz periods may affect device reliability. Ne (1) Output loading Io, = 32 mA, lo = —5 mA, CL = 300 pF 8-118

AC Characteristics Load Circuits Ta = 0°C to +70°C; Veg = 5V + 10% lo, = 32 MA, lon = —5 mA, Cy = 300 pF 1sv ‘sv 2uev mits Parameter Symbol“ Wax Unit ne wa ara Input to output delay tivov. out ‘out out inverting 5 2 ns —Non-inverting 5 90 ns Te [" ” Ter STB to output delay tsHov = + - inverting 0 40 hs State 10 Vou State 10 Vou Switching —Non-inverting 10 45 ns Se oeseeen Output disable time tenoz 5 22 ns Output enable time teov 10 30 as. Input to STB setup time tiysi 0 ns Input to STB hold time tux 25 ns STB high time tsHsL. 15, ns Input, output rise time tiui tOLOH 20 ns Input, output fall time tints towoe 12 ns AC Test Points oa 04s AC Testing: Inputs are driven at 24 V fora logle 1 and 045 V for ‘ Togle 0 timing measuremanta are made at 15,V for Both 1 logic and 0. 2.010684 Timing Waveform a ae “ me | 8 | ° |_| sist wow tenor te.ov- Tore aT Tav tsnov—e « “Note: Output may be momentary Invalid following the high going into STB transition soon 6-119