UPB6100

UPB6100 NEC | Alldatasheet

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z "Tao AAR NY NE C ELECTRONICS INC 72 ya | by27S25 OO08L10 1 Tr T-42-11-05 NEC . uPB6100 (TTL-2) SERIES NEC Electronics Inc. BIPOLAR TTL GATE ARRAYS C Revision 1 March 1985 Description Configuration Data The ¢PB6100 series features three high-speed, low- HPB6IO1 uPB6102 «=» PBB103. power, TTL-compatible gate arrays using advanced Number of cells (Note 1) 256 598 918 bipolar technology. The wPB6101, wPB6102, and a roWSX 26rOWSX S4TOWSX UPB6103 have 256, 598 and 918 internal cells, respec- _Configuration ‘Bcolumes 23 columes 27 columns voor All devices are available in a variety of package “Number of input buffers. —~=~O@2~S~S*~<CSs:C“‘*‘S*# ; Number of output buff 30 52 64 Gate arrays are intended for customers seeking cost Pail oli effective alternatives. By using gate arrays, customers Note: 1. A cell consists of two transistors and four resistors as : me shown in figure 2. can reduce component count and board size so that they can be more competitive in the markets they Absolute Maximum Ratings serve. NEC’s gate array program allows a customized Ta = +25°C IC to be developed quickly and at a small fraction of the Power supply voltage, Voc +7.0V cost of a full custom development program. input voltage, V, ~05t0470V NEC’s comprehensive CAD support system and master “QutputvoltagVo.SOCOCSC< 2; 7 ; " (put voltage, Vo slice system significantly reduce the time and expense Open-collector 0.5 to 47.0V normally associated with semicustom devices. Normal Except open-collector 0.5 to +5.5V turn-around time, after logic validation, is only 8 to 10 Storage temperature, Tsra 65 to 150°C weeks. Advanced CAD tools such as logic simulation, Comment: Exposing the device to stresses above those listed in automatic placement and routing, delay simulation, solute Maximum Ratings could cause permanent damage. The - and test program generation ensure accurate error- device is not meant to be operated outside the Recommended C free designs of all NEC gate arrays. Operating Conditions below. Exposure to absolute maximum rating conditions for extended periods may affect device reliability, Features Recommended Operating Conditions O High speed — 2.5 ns/gate Parameter ‘Symbol Value 5 Low power — 1.4 mW/gate Power supply voltage Vec 5.0V40.5V Quick turn-around time — 8 - 10 weeks Doeratingtemoeratue Ina EB*G : Operating t e T Oto +85°C O Fully supported by advanced CAD een eee torr — Logic simulation 'H” level output current lou —1000 wA max — Automatic placement and routing “L" level output current low 12 mA max — Test program generation — Delay simutation AC Characteristics D Direct access to CAD simulation Voc = 5.0 V: Ta = 425°C — Customers can use the local network through a their own terminal to an NEC design center ——_—— Test for logic simulation Parameter Symbol Min Typ Max Unit Conditions O Four types of output buffers available Delay time, try, §=201.3«19 «27 ~~sons Fan-out=3; — Totem-pole - gate try 19 27 38 ns L=3mm — Open-collector Delay time, tex. 13 19 27 ns Fan-out=3; — Three-state input buffer tPLH 16 23 32 -ns L=3mm — Bidirectional Delay time, tex. 33 47 66 ns C.=15 pF; O Wide choice of DIP, flat, and PGA (pin-grid-array) output buffer try 38 54 76 ns RL, =5009 packages to suit unique applications ya

NE C ELECTRONICS INC 72 DEP 427525 OO0aLL1 3 | T=42-11-05- : uPB6100 (TTL-2) SERIES NEC DC Characteristics Power Dissipation Data . ) Ta = 0 to +85°C Block Power Limits Test Parameter Type Dissipation —_Unit Parameter Symbol Min Typ Max Unit Conditions Internal gate F010 14 mW Input clamp Vig 15 v Voc = 4.5 V; Input buffer M001 19 mW Note 18 MA Sutput butter (totem-pole) B01 24 mW High-level = 7 -( output voltage Voy. 25 34 v Veo = ASM Output buffer (open-collector) B002 24 mW (totem pole) ‘OH Output buffer (three-state) B003 25 mW High-level Veo = 45 V; Output buffer (bidirectional) B004 44 mW output voltage Voy 22 33 Vv ey Dntout butter (bidi; onan (three-state) Io = —3.3. mA Output buffer (bidir, open-coll) B007 44 mW Low-level : Voc = 4.5 V; output voltage VOL 03°05 Vo ih t2mA Chip Layout High-level ha 20 yA Voc = 5.5 V; The arrays are divided into three basic areas. The I/O input current W=27V buffers are placed uniformly on the periphery of each High-level Voc =55V: device so that there is an equal number on each die maximum limax 100 WA Ve 70V edge. At each signal pad location, the pin function can input current be one of several possible !/O configurations, vent i 100 uh Woo ss. The area between the cells and the bonding pads Arr contains all the peripheral circuitry needed to convert High-level t \\ 100 pa Voo=45¥; external I/O levels to internal logic levels. Power and input current oH Vo =55V ground distribution is also handled by the peripheral (open collector) circuit Short-circuit : ultry. . ; ; oy output current \\ 100 25 mA Voc =5.5V; The center of the die contains rows of continuous ) (except open ‘08 Vo=0V gates separated by horizontal routing channels. The ~ collector) density of the array is a factor of the total cell count Off-state Vee =55V: (row x column). output current Igz_- -20 20 uA Vee o4V/27V (three-state) Figure 1. Chip Layout of Bipolar Gate Array Off-state Veo = 5.5 V: output current — Igz_- —100 40 uA Woe 04 V/27V dresioy ee | (a ======== == TO Input threshold Hy 1]

4 Sin

(hysteresis iil put) [I] —=-=-===-— TI] con . Input threshold Region voltage = (hysteresis Vin- 055 08 085 V Veg=5.0V input) fegton Vin : " Hysteresis minus 0.4 0.65 V Vec=5.0V th— [| = Region £2-0000604

8 FOI1 — 3-Input AND 2 23

Figure 3. Output Loading Condition C054 4-Wide 3-Input AND-OR Inverter 4 28 Figure 4. Output Loading Condition B007 Output Buffer (Bidirectional) (Open-collector) — 4.4

a NE C ELECTRONICS INC 72 vel b427525 0008113 ? T-42+11-05 y»PB6100 (TTL-2) SERIES NEC Figure §. Example of a Logic Drawing : i) aor > HOLpS Not (Moot) Hoty (Foi) HOt yicS10] enh taoz (>to [som a Not De p> two > onot I zzzi oi [| os}tio2 al (Moos) ry zzzi xs 1HO4, teSio) ee zz21 198 Bs e802 (>t Bo Net HOt icet0} Meee a eT Not Ho2 NOS._6-, poy* o<] H03_- 7 Bott aot (680) NOL Hoty (cSt0) an oF zzz HO2f Not HOMIES) Not_ oop es Hots ceo) LO zzz1 108 B Hoe ) paoz [>Het a ne D: —— M2175 oze* ae zzz 3.0000678,

| (__v-a9-11.)8 NE C ELECTRONICS INC 72 DEP b4¥e27525 0008114 4 D T=42-11-05 NE Cc . yPB6100 (TTL-2) SERIES a C Figure 6. Example of a Timing Chart ‘Time Chert pPBGIOIC {1 — 100] 0 20 40 60 80 100 ee aA RA RADA DARA DARRARARAAARRAR LAER wot «OT

103 A SE

105 ———— a 108 ———— 107 ———— a a ES + 77 108 eee ee ne ee rel z A i] i) oe 12 a es er <n s 4 sl ns eee OOOO ee} 03 ST?

004 Fe Ses = es = a * Sn > = Se = A = SO - E

018 SS =

020 ——— oat SE sl bd SS a a 2-0000688 5 .

/ NE C ELECTRONICS INC 72 ve bye7Se5 0008115 0 | T-42-11-05 ; uPB6100 (TTL-2) SERIES NEC EY Gate Array Development Process : ) Figure 7 is a flowchart showing supporting data, development steps, and customer/NEC interface options. Customer/NEC Interface Options Development Steps i Pp NEC’s computer and communications environment Design Rule Checking. Once the circuit interconnect allows gate array designers toselecttheinterfacemost data is complete, the first step of the logic validation suitable to their needs. process is the design rule check. Parameters such as Standard Data. For the simplest interface, the customer cell usage, power dissipation and fan-out loading are provides a circuit diagram and test patterns. The “etermined and checked. remainder of the development process is NEC’s Unit Simulation [Static Logic Simulation]. Here, any responsibility. coding errors and data conversion errors are eliminated. Macro Converted Data. The customer provides a Delay Time Simulation. Before automatic placement circuit diagram based on the macros in the Block _and routing, delay time simulation gives an accurate Library plus test pattern data. estimate of the expected circuit delays. File Generated Data. The customer provides a netlist | Automatic Placement and Routing. NEC's advanced pi and test pattern file in NEC compatible format. The _ software allows up to 95-percent cell utilization without netlist is a text file describing circuit interconnections. _ resorting to manual routing. Data may be sent to NEC on magnetic tape ora floppy —_ Final Delay Time Simulation. Here, wire lengths are disk or transmitted via telephone. The formats and taken into account. Results of this step provide the Procedures for handing these mee beng fullyspecified — customer with an accurate circuit analysis. es . Y PPFOP 9 . Production. If the above steps are completed suc- Graphic PC Generated Data. Using the PC9800 cessfully, design enters actual production followed by \\ workstation, a customer can easily generate the —490-percent wafer testing. ) necessary netlist and test pattern file. The PC9800 ae workstation supports schematic capture and limited Packaging. Successtully tested wafers are divided into design rule checking. individual chips, which are then die-bonded onto the . customer-specified package. Chips are then wire- Workstation Generated Data. For this interface, the bonded and sealed. The dc parameters and logic customer performs logic simulation using either — functions of each chip are checked in the final test. workstations by Valid Systems, Mentor Graphics, Daisy . Systems and others, or the TEGAS-5™ software on a Prototype Evaluation. Ten engineering samples are , main frame computer. NEC does the final compatibility delivered to the customer for the system function test. check. (Separate manuals describe the various work- If customer evaluation is satisfactory, the development station interfaces.) abate finished. NEC is ready to begin mass PG Mask Tape Interface. A separate manual will be P . issued when this interface becomes available. TEGAS-S5 is the trademark of Calma Company.

N E C ELECTRONICS INC 72 ve b427525 OOO8lLb 2 VO rnin > NEC vPB6100 (TTL-2) SERIES. a C Figure 7. Flowchart for Gate Array Development [Support | Development Steps Customer Data to NEC : Circuit Diagram Test Patiern {Circuit Data} (Timing Data} Block o> Library [ lO] [aera | Block Library for Graphic Logic File Pattern File Data Key-In Generation Generation BARRIER or Program Graphic pc generated data OK Circuit Diagram ‘Automatic Circuit] LODAC . Drawing [Option] Program C [Unit Detay Simutation | Program OK Delay Time Simulation NELSIM Before Routing Program ——_— 4. — — 4 ea ee ee Workstation or simulator : generated data (interface <Eiect> software available] OK MASTER 2 Automatic Program Placement and Routing Final Delay Test Program Time Simulation} | Generation ATPRG <> Program OK i ] PG mask tape generated data . — using NEC CAD tools ( Sentry Test Tape = {Option} OK 83-0011098

NE C ELECTRONICS INC ?e ve b4y27525 OOO8L1? 4 | T-42-11-05 : uPB6100 (TTL-2) SERIES NEC Operating Characteristics ») Output Voltage vs Input Voltage [Vcc = 5.0 V] Output Voltage vs Input Voltage [TA = +25°C] CET TTT) ber Lt} | fest | | : = — a ee ee ee ee ee

1 P, 1

° | ° ——— 0 Os 10 15 20 25 3.0 ° Os 10 Ws 2.0 25 30 Input Voltage [Vj] Input Voltage [V] Output Voltage vs High Level Output Current [Vcc = 5.0 V] Output Voltage vs High-Level Output Current [Ta = +25°C] 5 5 0 aN ee 2 NS B. ‘ Ee IN EIN Se SO 1 . F IN ae NG ee ee NN o SS 3 ° N 3 ° 25 80 78 ° 25 50 75 High-Level Output Current (mA) High-Level Output Current [mA] Output Voltage vs Low-Level Output Current [Vcc = 5.0 V) Output Voltage vs Low-Level Output Current [Ta = +25°C] 075 0.75 = 050 PF } | = oso | fi = na Ss 5 023| © 0.25 — AE - ®) | | ° ° 0 20 w ° o 10 20 30 Low-Level Output Current (mA] Low-Level Output Current (mA) .

NE C ELECTRONICS INC ?2 Pe | 6427525 OO08118 b Toor T-42-11-05 \\ NEC ; vPB6100 (TTL-2) SERIES ( Operating Characteristics (cont) . Input Current vs Low-Level Input Voltage [Ta = +25°C] Input Current vs Low-Level Input Voltage [Vcc = 5.0 V] 20 20 See) SAS © yhoo =v =| —~ oS) PRS Ze | S\\ a | —~\\\\ Os ec Do | to. rh Li tT ti} fF | |) | 0 05 10 ah 20 25 o 05 1.0. 1S 2.0 25 Low-Level Input Voltage [V} Low-Level Input Voltage [V] Delay Time vs Ambient Temperature Delay Time vs Load Capacitance Output Buffer [Totem-Pole] Output Buffer [Totem-Pole] 2s 25 Re » | | > > — Eu - i | Le | i Ee — i -_

0 Moot F000» S10 Bot Ps Mooi F000 «= cs10—Ba0t

5 & o o 8 0 2 50 Ly es oO 50 100 150 Ambient Temperature [°C] Load Capacitance (pF Delay Time vs Load Capacitance Delay Time vs Load Resistance Output Buffer [Open Collector) Output Buffer [Open Collector] 100 100 F a a Zee i C e 2 moot F000 ‘CS10 8002 2 ‘moot O00 cs10 8002

0 H 0 H

° 50 100 150 200 250 o 05 10 1S 20 25 Load Capacitance [pF] Load Resistance [kQ]

dpuactaneem naan tsmnapenenasens inne ES —_—_— ONE C ELECTRONICS INC 72 Depp b4ue7ses 0008119 8 i tazi-05 uPB6100 (TTL-2) SERIES NEC Packaging Information Package Marking ») The uPB6100 (TTL-2) gate arrays are available in a wide variety of packages to accommodate unique Example of PGA Package applications. Package Pin Counts Company | over Part Package Pins Maric nN. TT “ain Number Minimum Maximum NEC JAPAN uPB6101 16 44 HPB6102 20 72 woster_| IBIBO IR: | Strout BBIO 7 2 cose 77} (BIG) 1/0;2iRi_ | [gfo]7]——ne (814:3/5{P/1 Package Availability oP 16-Pin Plastic . 1BPin Plastic > Lot Number Pechage lames 20-Pin Plastic ° -e . 24-Pin Plastic . ° e Example of Plastic Package . 28-Pin Plastic ° . . SS ‘Company Lot 40-Pin Plastic e . . Origin = Mark ‘Number _, 48-Pin Plastic ° ° YS ) Shrink DIP we 64-Pin Plastic . NEC 8220K1 Flat 44-Pin Plastic . . B610x C 011 52-Pin Plastic ° aaa 64-Pin Plastic . 2 we aw rs rer “Name 72-Pin Ceramic . ° 83-000101