UPB409C NEC | Alldatasheet

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N: KE Cc »PB409C/D, .PB429C/D PT

16384 BIT BIPOLAR TTL

PROGRAMMABLE READ ONLY MEMORY Description The uPB409C, uPB409D, PB429C and uPB429D are high speed, electrically programmable, fully decoded 16384 bit TTL read only memories. On-chip address decoding, three chip select inputs and open-collector/three-state outputs allow easy expansion of memory capacity. The .PB409C, yPB409D, uPB429C and uPB290 are fabricated with logic level zero (low); logic level one (high) can be electrically programmed into the selected bit locations. The same address inputs are used for both programming and reading. Features © 2048 WORDS x8 BITS organization (Fully decoded) @ TTL Interface © Fast read access time : 45 ns MAX, (uPB409-3, uPB429-3) @ Medium power consumption _: 500 mW TYP. @ Three chip select inputs for memory expansion © Open-Collector outputs (PB409C, ,PB409D) / Three-state outputs {uPa429¢, wPB420D) © Cerdip 24-Lead Dual In-Line Package (uPB409D, 429D) @ Plastic 24-Lead Dual In-Line Package (uPB409C, 429C) @ Fast Programming time 7 200 ys/bit TYP. @ Replaceable with : Signetics’ 82S190/191, Harris’ HM76160/76171 and equivalent devices (as a ROM) f Connection Diagram sey se (Top View) Yee wo Hcy oe Pin names AQ-A10 : Address Inputs 01-08 : Data Outputs CS1, CS2, CS : Chip Select Inputs Voc : Power Supply (+5V) GND : Ground 527

uPB409C/D, .PB429C/D NE Cc lett ihc Operation First we define an internal Chip Select logic by three Chip Select inputs: CS'=CS1 +CS2-CS3 That is, CS’ is a logical zero (low) if and only if CS1=0 and CS2=CS3=1, While CS" is a logical one (high) in all the other cases. 1. Programming A logic one can be permanently programmed into a selected bit location by using special equipment (programmer). First, the desired word is selected by the eleven address inputs in TTL levels. The three Chip Select inputs must be set so that CS’ isa logical one. Secondly, a train of high current programming pulses is applied to the desired output. After the sensed voltage indicates that the selected bitisin the logic one state, an additional pulse train is applied, then is stopped. 2. Reading To read the memory, The three Chip Select inputs must be set so that CS’ is a logical zero. The outputs then correspond to the data programmed in the selected words. When the three Chip Select inputs are set so that CS' becomes a logical one, all the outputs will be high (floating). Logic Diagram Bo |

4 MULTIPLEXER O01

= BUFFER | ID Te see eit |: | MULTIPLEXER ourpur 00: (128 « 128) surren |_| . MEMORY CELLS Ton i ARRAY tT Tt i | oureut ° MULTIPLEXER tones Co 7 | Icon oureut 50, ADDRESS. cup Ao Ar Az Ag Aa As Ag Ar Aa Ag Ato Ti C283 528

NEC p»PB409C/D, .PB429C/D ABSOLUTE MAXIMUM RATINGS ‘Supply Voltage Vee 05 10 47.0 v Input Voltage vi 05 10 485 v Output Voltage vo 05 10485 v Output Current lo 50 mA Operating Temperature Topt -25 10 475 *c Storage Temperature Cerdip Package Tstg 65 to +150 °c Plastic Package Tstg 55 to +125 °c D.C. CHARACTERISTICS (Vcc = 4.5 to 5.5 V, Ta = 0 to+75 °C) CHARACTERISTIC [svmeot [Min [TvP. [MAX.] UNIT TEST CONDITIONS Outpattow Volto” | Vou [oas | v| lort6mA Voc=a5Vv Output Leakage Current lorrt [| 40 [wa | Vo=5.5V Vcc=5.5 V Output Leakage Current =lorF2 [| 40 [wa | Vo-oav Vec=55V Input Clamp Voltage “vie [| TF-18mA Vec=45V Power Supply Current tec | 100 | ‘All inputs GroundedVcc =55 V| + [Tostout Han Vorage vow f24 | |v | to-24ma_vocwa5V ~ Note: Applicable to #PBA20C and wPB429D. CAPACITANCE (Vcc =5 V, f= 1 MHz, Ta = 25 °c) CHARACTERISTIC | SYMBOL | MIN. | MAX.| UNIT | TEST CONDITIONS Input Capacitance CIN | | 8 T oF | VIN=25V ‘Output Capacitance Cout jo | pF | VouT=25V A.C. CHARACTERISTICS (Vcc = 4.5 to 5.5 V, Ta = 0 to +75 °C) Guanacrenistic Jevmeou===:emmeAsaarss ERE Rass nef ee ay BOUT an, ax | ma. [ wa, MIN [wax [ min, [ wa cupsacaccos tine sacs | | oof |e] [ao [|e || Note 1. Output Lood: See Fig. 1 Note 2, Input Wavetorm: 0.0.V for low level and 3.0 V for high level y cc tess than 10 ns for both rise ana fal iene. Note 3. Measurement References: 1.5 V for both inputs and outputs Note 4. Cin Fig. 1 includes jig and probe stray capacitances, son a : 0; our) cy + 90pF 600 i Re h Fig. 529

uPB409C/D, .PB429C/D NE' Cc Programming It is imperative that this specification be rigorously observed in order to Specification correctly program the uPB409C, yPB409D, yPB429C and uPB429D. NEC will not accept responsibility for any device found to be defective if it were not programmed according to this specification. Programming Pulse ‘Amplitude 200 #5 % mA Clamp Voltage 28 +0 % 2% v Ramp Rate (Both in Rise and in Fall) 70 MAX. Vins Pulse Width 7.5 25% us| 18 point/150 2 toad Duty Cycle 70% MIN. Sense Current ‘Amplitude 2020.5 mA Clamp Voltage 28.40% -2% v Ramp Rate 70 MAX. Vins | 18V point/160 9 toad, Sense Current Interruption before and after address change TOMIN. us Programming Voc sorsx-o% [ovo to Maximum Sensed Voltage* Delay from trailing edge of programming : ; Pulse before sensing output voltage 0.7 MIN. lad * A biti judged to be programmed when two succeive sense readings 10 us apart with no intervening programming puke, pass the limit. When this condition has been mat, four additional pulses re applied and the pulse tain, than the wenee current is terminated. Fig, 2 Typical Output Voltage Waveform. Acciona a8 et eran mA regain 100 ma Pit 20 ma Soar ator) Se ro Vw FN 20 ak Song ate #2 eno 158 100 seman 10 Sse 530

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