UPB419C NEC | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 5

Technical content

Ni EK Cc »PB419C/D aN

16384 BIT BIPOLAR TTL

PROGRAMMABLE READ ONLY MEMORY Description The uPB419C and uPB419D are high speed, electrically programmable, fully decoded 16384 bit TTL read only memories. On-chip address decoding, two chip select inputs and three-state outputs allow easy expansion of memory capacity. The uPB419C and uPB4190 are fabricated with logic level zero (low); logic level one (high) can be electrically programmed into the selected bit locations. The same address inputs are used for both programming and reading. Features @ 2048 WORDS x8 BITS organization (Fully decoded) @ TTL Interface @ Fast read access time : 50 ns MAX. (uPB419-2) @ Medium power consumption : 500 mW TYP. @ Two chip select inputs for memory expansion @ Three-state outputs © Cerdip 24-Lead Dual In-Line Package (uPB419D) @ Plastic 24-Lead Dual In-Line Package (yPB419C) @ Fast Programming time £200 ps/bit TYP. @ Replaceable with : Intel’s 2716 and equivalent devices {as a ROM) Connection Diagram sa) st (Top View) vec Ae A NC TS AI GH OO O% Oo toa as es 6 7 gp 9 RAMEN SND OO oO HD «Sir uso Pin names Ag-AtO : Address Inputs 04 = 08 : Data Outputs CS1, CS2 : Chip Select Inputs NC : No Connection Voc : Power Supply (+5V) GND =: Ground 521

Operation 1. Programming A logic one can be permanently programmed into a selected bit location by using special equipment (programmer). First, the desired word is selected by the eleven address inputs in TTL levels. Either or both of the two Chip Select inputs CS1 and CS2 should be at a logical one. Secondly, a train of high current programming pulses is applied to the desired output. After the sensed voltage indicates that the selected bit is in the logic one state, an additional pulse train is applied, then is stopped. 2. Reading To read the memory, Both of the two Chip Select inputs must be held at a logical zero. The outputs then correspond to the data programmed in the ‘selected words. When either or both of the two Chip Select inputs are at a logical one, all the outputs will be floating. Logic Diagram a =e oo = surren vesosorn Poo, MEMORY CELLS surren | : ARRAY Tu uU go : rit f ouTPUT PLEXe! 00; Lene | H— | Icom yiTicene oureur | | . curren setcer Ao Ar A2 Ag Aa As Ag Ar As Ag Alo cs $22

‘Supply Voltage Vee 0510 47.0 v Input Voltage vi 05 10455 v Output Voltage vo -05 10 485. v Output Current lo 50 mA Operating Temperature Topt =25 to +76 °c Storage Temperature Cerdip Package Tst9 65 10 +150 °c Plastic Package Tstg 85 to +125, °c D.C. CHARACTERISTICS (Vcc = 4.5 to 5.5 V, Ta = 0 to +75 °C) CHARACTERISTIC svmaou [MIN. [TvP, [Max.[UNIT| TEST CONDITIONS a Input High Current Im [| 40 Wesevvec=s8V Input Low Current =r | [o25 [ma [ viroav Vvec=55V Output Leakage Current torer |_| | 40 | wa | Vo=55v Vec=5.5V Output Leakage Current [tore2 | |_| 40 | wa | Voroav Vvec=55V [ou Cons votaw | we] [pe |v | ientema—_vecas | Power Supply Current [tcc |_| 100 | 160 | ma | Ail inputs Grounded¥cc=55 CAPACITANCE (Vcc = 5 V, f = 1 MHz, Ta = 25°C) CHARACTERISTIC syMBOL| MIN. | MAX. TEST CONDITIONS. Output Capacitance Cour | | 10 Vout = 25V A.C. CHARACTERISTICS (Vcc = 4.5 to 5.5 V, Ta = 0 to +75 °C) HARACTERISTIC Meo | MeSt180-2 wear) CHARAG ie MIN, [MAX, | MIN. [MAX. | MIN, Aldres AcconTine | aa |) | | Chip Select Access Time tacs [40 | | | vs | Note 1, Output Lood: See Fig. 1. Note 2. Input Wavetorm: 0.0 V for low level and 3.0 V for high level, tess than 10 m8 for both rise an fall times. Vee Note 3. Measurement References: 1.5 V for both inputs and outputs. Note 4. Cin Fig. 1 includes jig and probe stray capacitances, a3 08 0; (oun i 6009 uF 00 oF 2 Fig.1 523

»PB419C/D NE Cc Programming It is imperative that this specification be rigorously observed in order to Specification correctly program the uPB419C and uPB419D. NEC will not accept responsibility for any device found to be defective if it were not programmed according to this specification. re Programming Pulse Amplitude 200 5 % mA Clamp Voltage 28 +0 % —2% v Ramp Rate (Both in Rise and in Fall) 70 MAX. Vins Pulse Width 7.5 25% us 15 V point/150 2 load. Duty Cycle 70 % MIN. ‘Sense Current Amplitude 20 +0.5 mA ‘Clamp Voltage 2840 % -2% v Ramp Rate 70 MAX. Vius 15 V point/150 2 toad. ‘Sense Current Interruption before and after address change TOMIN: us Maximum Sensed Voltage” [iewememerse™ | oer | vy | Delay from trailing edge of programming | Rittdavestonsatcee™™ | orm | we | | * A Dit is judged to be programmed when two successive sense readings 10 ms apart with no intervening programming pulse, pas the limit. Wen this condition has been met, (our aditionsl pulses ae applied and the pulse train, then the sense current is teminated. Fig. 2 Typical Output Voltage Waveform. ‘Adina Puen 200 mA Progam ue 100 ma Point 20 mA Sorin totoreP) "10 vw 1 20 mA Sang ar eno 750 7 min 0 (Outbr Votuge Sensing 524

Le Aig gigi linn’