UPB1005K NEC | Alldatasheet
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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. BIPOLAR ANALOG + DIGITAL INTEGRATED CIRCUIT µµµµPB1005K REFERENCE FREQUENCY 16.368 MHz, 2ND IF FREQUENCY 4.092 MHz RF/IF FREQUENCY DOWN-CONVERTER + PLL FREQUENCY SYNTHESIZER IC FOR GPS RECEIVER Document No. P14016EJ1V0DS00 (1st edition) Date Published November 1999 N CP(K) Printed in Japan PRELIMINARY DATA SHEET © 1999
DESCRIPTION
The µPB1005K is a silicon monolithic integrated circuit for GPS receiver. This IC is designed as double conversion RF block integrated RF/IF down-converter + PLL frequency synthesizer on 1 chip. The µPB1005K features 36-pin plastic QFN, fixed prescaler and supply voltage. The 36-pin plastic QFN package is suitable for high density surface mounting. The fixed division internal prescaler is needless to input serial counter data. Supply voltage is 3 V. Thus, the µPB1005K can make RF block fewer components and lower power consumption. This IC is manufactured using NEC’s 20 GHz fT NESAT TM III silicon bipolar process. This process uses direct silicon nitride passivation film and gold electrodes. These materials can protect the chip surface from pollution and prevent corrosion/migration. Thus, this IC realizes excellent performance, uniformity and reliability.
FEATURES
- Double conversion : f REFin = 16.368 MHz, f2ndIFout = 4.092 MHz
- Integrated RF block : RF/IF frequency down-converter + PLL frequency synthesizer
- High-density surface mountable : 36-pin plastic QFN (6.0 × 6.0 × 0.95 mm)
- Needless to input counter data : fixed division internal prescaler
- VCO side division : ÷ 200 (÷ 25, ÷ 8 serial prescaler)
- Reference division : ÷ 2
- Supply voltage : V CC = 2.7 to 3.3 V
- Low current consumption : I CC = 45.0 mA TYP.@VCC = 3.0 V
- Gain adjustable externally : Gain control voltage pin (control voltage up vs. gain down) APPLICATION
- Consumer use GPS receiver of reference frequency 16.368 MHz, 2nd IF frequency 4.092 MHz
ORDERING INFORMATION
Part Number Package Supplying Form µPB1005K-E1 36-pin plastic QFN Embossed tape 12 mm wide. Pin 1 is in pull-out direction. Qty 2.5 kp/reel. Remark To order evaluation samples, please contact your local NEC sales office. (Part number for sample order: µPB1005K) Caution Electro-static sensitive device
Preliminary Data Sheet P14016EJ1V0DS002 µµµµPB1005K PIN CONNECTION AND INTERNAL BLOCK DIAGRAM 123456789 IF-MIXout RF-MIXout IF-MIXin N.C. REFin N.C. LOout PD-Vout1 PD-Vout2 N.C. GND (divider block) GND (Phase detector) VCC (divider block) N.C. VGC (IF-MIX) GND (IF-MIX) VCC (IF-MIX) VCC (RF-MIX) RF-MIXin (2ndIF-AMP) VCC (2ndIF-AMP) VCC (reference block) 2ndIFin12ndIFin2 2ndIFout N.C. REFout 2ndIFbypass N.C. PD-Vout3 1stLO-OSC1 1stLO-OSC2 GND GND (RF-MIXin) VCC (1stLO-OSC) VCC (phase detector) GND (1stLO-OSC) PD ÷25 26 25 24 23 22 21 20 19
Preliminary Data Sheet P14016EJ1V0DS00 3 µµµµPB1005K PRODUCT LINE-UP (TA = +25 °°°°C, VCC = 3.0 V) Type Part Number Functions (Frequency unit: MHz) VCC (V) ICC (mA) CG (dB) Package Status µPC2756T 6-pin minimold µPC2756TB RF down-converter with osc. Tr2.7 to 3.3 6.0 14 6-pin super minimold General Purpose Wideband Separate IC µPC2753GR IF down-converter with gain control amplifier 2.7 to 3.3 6.5 60 to 79 20-pin plastic SSOP (225 mil) Available µPB1003GS RF/IF down-converter + PLL synthesizer REF = 18.414 1stIF = 28.644/2ndIF = 1.023 2.7 to 3.3 37.5 72 to 92 µPB1004GS 2.7 to 3.3 37.5 72 to 92 Discontinued µPB1005GS 30-pin plastic SSOP (300 mil) Clock Frequency Specific 1 chip IC µPB1005K RF/IF down-converter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 2.7 to 3.3 45.0 72 to 92 36-pin plastic QFN Available Notice Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail. To know the associated products, please refer to their latest data sheets. SYSTEM APPLICATION EXAMPLE GPS receiver RF block diagram
1575.42 MHz
µ PC2749TBe.g. 1540f0 RF-MIX RF-MIXout 60f0 BPF IF-MIXin IF-MIX 40f0 LPF VGC IF-MIXout 2ndlFin1 2ndlFin22ndlFbypass 2ndlF-Amp 16f0 4f0 16f0
4.092 MHz
16.368 MHz
- f0 = 1.023 MHz in the diagram.
- PB1005K is in .µ 64f0 Caution This diagram schematically shows only the µµµµPB1005K’s internal functions on the system. This diagram does not present the actual application circuits.
Preliminary Data Sheet P14016EJ1V0DS004 µµµµPB1005K ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions Rating Unit Supply Voltage V CC TA = +25 °C3 . 6 V Total Circuit Current I CC TA = +25 °C 120 mA Power Dissipation P D Mounted on double-sided copper clad 50 × 50 × 1.6 mm epoxy glass PWB (TA = +85 °C) 430 mW Operating Ambient Temperature T A −40 to +85 °C Storage Temperature T stg −55 to +150 °C RECOMMENDED OPERATING RANGE Parameter Symbol MIN. TYP. MAX. Unit Supply Voltage V CC 2.7 3.0 3.3 V Operating Ambient Temperature T A −40 +25 +85 °C RF Input Frequency f RFin 1575.42 MHz 1st LO Oscillating Frequency f 1stLOin 1616.80 1636.80 1656.80 MHz 1st IF Input Frequency f 1stIFin 61.38 MHz 2nd LO Input Frequency f 2ndLOin 65.472 MHz 2nd IF Input/output Frequency f2ndIFin f2ndIFout 4.092 MHz Reference Input/output Frequency fREFin fREFout 16.368 MHz LO Output Frequency f LOout 8.184 MHz
Preliminary Data Sheet P14016EJ1V0DS00 5 µµµµPB1005K ELECTRICAL CHARACTERISTICS (Unless otherwise specified TA = +25 °°°°C, VCC = 3.0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Total Circuit Current I CC total I CC 1 + ICC 2 + ICC 3 + ICC 4 32.0 45.0 60.0 mA RF Down-converter Block (fRFin = 1575.42 MHz, f1stLOin = 1636.80 MHz, PLOin = −10 dBm, ZS = ZL = 50 Ω ) Circuit Current 1 I CC 1 No Signals 6.0 10.0 14.0 mA RF Conversion Gain CG RF PRFin = −40 dBm 12.5 15.5 18.5 dB RF-SSB Noise Figure NF RF PRFin = −40 dBm 7.0 10.0 13.0 dB Maximum IF Output P O(sat)RF PRFin = −10 dBm −5.5 −2.5 +0.5 dBm IF Down-converter Block (f1stIFIn = 61.38 MHz, f2ndLOIn = 65.472 MHz, ZS = 50 Ω , ZL = 2 kΩ ) Circuit Current 2 I CC 2 No Signals 3.4 5.3 7.2 mA IF Conversion Voltage Gain CG(GV)IF at Maximum Gain, P1stIFin = −50 dBm 38 41 44 dB IF-SSB Noise Figure NF IF at Maximum Gain, P1stIFin = −50 dBm 8.5 11.5 14.5 dB Maximum 2ndIF Output P O(sat)IF at Maximum Gain, P1stIFin = −20 dBm −9.5 −6.5 −3.5 dBm Gain Control Voltage V GC Voltage at Maximum Gain CGIF 1.0 V Gain Control Range D GC P1stIFin = −50 dBm 20 dB 2nd IF Amplifier (f2ndIF = 4.092 MHz, ZS = 50 Ω , ZL = 2 kΩ ) Circuit Current 3 I CC 3 No Signals 1.55 2.40 3.25 mA Voltage Gain G V P2ndIFin = −60 dBm 37 40 43 dB Output Power P 2ndIFout P2ndIFin = −30 dBm −14.5 −11.5 −8.5 dBm PLL Synthesizer Block Circuit Current 4 I CC 4 PLL All Block Operating 18.5 28.5 38.5 mA Phase Comparing Frequency fPD PLL Loop 8.0 8.184 8.4 MHz Reference Input Minimum Level VREFin ZL = 10 kΩ //20 pF Note 200 mV P-P Loop Filter Output Level (H) VLP(H) 2.8 V Loop Filter Output Level (L) VLP(L) 0.4 V Reference Output Swing V REFout ZL = 10 kΩ //2 pF Note 1.0 VP-P Note Impedance of measurement equipment
Preliminary Data Sheet P14016EJ1V0DS006 µµµµPB1005K STANDARD CHARACTERISTICS (Unless otherwise specified TA = +25 °°°°C, VCC = 3.0 V) Parameter Symbol Conditions Reference Unit RF Down-converter Block (P1stLOin = −10 dBm, ZS = ZL = 50 Ω ) LO Leakage to IF Pin LO if f1stLOin = 1 636.80 MHz −30 dBm LO Leakage to RF Pin LO rf f1stLOin = 1 636.80 MHz −30 dBm Input 3rd Order Intercept Point IIP3RF f RFin1 = 1 600 MHz, fRFin2 = 1605 MHz f1stLOin = 1 660 MHz −13 dBm IF Down-converter Block (1st LO oscillating, ZS = 50 Ω , ZL = 2 kΩ ) LO Leakage to 2nd IF LO 2ndif f2ndLOin = 65.472 MHz −20 dBm LO Leakage to 1st IF LO 1stif f2ndLOin = 65.472 MHz −40 dBm Input 3rd Order Intercept Point IIP3IF f 1stIFin1 = 61.38 MHz, f1stIFIn2 = 61.48 MHz f2ndLOin = 65.472 MHz −34 dBm VCO Block Phase Noise C/N PLL Loop, Δ1kHz of VCO wave −78 dBc/Hz
Preliminary Data Sheet P14016EJ1V0DS00 7 µµµµPB1005K PIN EXPLANATION Pin No. Pin Name Applied Voltage (V) Pin Voltage (V) Function and Application Internal Equivalent Circuit 35 RX-MIXout 1.68 Output pin of RF mixer. 1st IF filter must be inserted between pin 33 & 35. 36 V CC (RF-MIX) 2.7 to 3.3 Supply voltage pin of RF mixer block. This pin must be decoupled with capacitor (example: 1 000 pF). 1R F - M I X i n 1.20 Input pin of RF mixer. 1 575.42 MHz band pass filter can be inserted between pin 1 and external LNA. 2 GND (RF-MIX) 0 Ground pin RF mixer. 1stLO -OSC 3V CC (1stLO-OSC) 2.7 to 3.3 Supply voltage pin of differential amplifier for 1st LO oscillator circuit. 41 s t L O - O S C 1 1.88 51 s t L O - O S C 2 1.88 Pin 4 & 5 are each base pin of differential amplifier for 1st LO oscillator. These pins should be equipped with LC and varactor to oscillate on 1 636.80 MHz as VCO. 6G N D (1stLO-OSC) 0 Ground pin of differential amplifier for 1st LO oscillator circuit. 4 5 RF-MIX or Prescaler input VCC 7V CC (phase detector) 2.7 to 3.3 Supply voltage pin of phase detector and active loop filter. 8N . C . Non connection
9 PD-Vout3 Pull-up
10 PD-Vout2 Output in
11 PD-Vout1 Pull-up
Pins of active loop filter for tuning voltage output. The active transistors configured with darlington pair are built on chip. Pin 11 should be pulled down with external resistor. Pin 9 to 10 should be equipped with external RC in order to adjust dumping factor and cutoff frequency. This tuning voltage output must be connected to varactor diode of 1st LO-OSC.
12 GND (phase
detector) 0 Ground pin of phase detector + active loop filter. PD
Preliminary Data Sheet P14016EJ1V0DS008 µµµµPB1005K Pin No. Pin Name Applied Voltage (V) Pin Voltage (V) Function and Application Internal Equivalent Circuit
13 V CC
(divider block) 2.7 to 3.3 Supply voltage pin of prescalers. 14 LOout 2.08 Monitor pin of comparison frequency at phase detector.
15 GND
(divider block) 0 Ground pin of prescalers + LOout amplifier 1st LO OSC ÷25 ÷8 IF MIX PD PD Ref. 17 REFin 1.96 Input pin of reference frequency. This pin should be equipped with external 16.368 MHz oscillator (example: TCXO). 18 N.C. Non connection
19 V CC
(reference block) 2.7 to 3.3 Supply voltage pin of input/output amplifiers in reference block. 20 REFout 1.65 Output pin of reference frequency. The frequency from pin 17 can be took out as 1 V P-P swing. PD 22 2ndIFout 1.56 Output pin of 2nd IF amplifier. This pin output 4.092 MHz clipped sinewave. This pin should be equipped with external inverter to adjust level to next stage on user’s system.
23 V CC
(2ndIF-AMP) 2.7 to 3.3 Supply voltage pin of 2nd IF amplifier. 24 2ndIF bypass 2.30 Bypass pin of 2nd IF amplifier input 1. This pin should be grounded through capacitor. 25 2ndIFin2 2.35 Pin of 2nd IF amplifier input 2. This pin should be grounded through capacitor. 26 2ndIFin1 2.35 Pin of 2nd IF amplifier input 1. 2nd IF filter can be inserted between pin 26 & 28.
27 GND
(2ndIF-AMP) 0 Ground pin of 2nd IF amplifier.
Preliminary Data Sheet P14016EJ1V0DS00 9 µµµµPB1005K Pin No. Pin Name Applied Voltage (V) Pin Voltage (V) Function and Application Internal Equivalent Circuit 28 IF-MIXout 1.15 Output pin from IF mixer. IF mixer output signal goes through gain control amplifier before this emitter follower output port. 29 N.C. Non connection 30 V GC (IF-MIX) 0 to 3.3 Gain control voltage pin of IF mixer output amplifier. This voltage performs forward control GC up → Gain down). 31 V CC (IF-MIX) 2.7 to 3.3 Supply voltage pin of IF mixer, gain control amplifier and emitter follower transistor. 32 N.C. Non connection 33 IF-MIXin 2.00 Input pin of IF mixer. 34 GND (IF-MIX) 0 Ground pin of IF mixer. 2nd LO Caution Ground pattern on the board must be formed as wide as possible to minimize ground impedance.
Preliminary Data Sheet P14016EJ1V0DS0010 µµµµPB1005K TEST CIRCUIT PD 123456789 Signal Generator Signal Generator Signal Generator Signal Generator 26 25 24 23 22 21 20 19 C6 C7 Spectrum Analyzer Spectrum Analyzer Spectrum Analyzer Osillo- scope Osillo- scope R2L C9 C10 C11 C12 C13 C14C15C16C18 C17 C19C20 V-Di 50 Ω 50 Ω 50 Ω 50 Ω VCC C3VCC VCC VCC VCC VCC C23VCC C22 C21R6 To get maximum gain. Apply 1.0V MAX. ÷25 Spectrum Analyzer : measure frequency Oscilloscope : measure output voltage swing Component List Form Symbol Value C1 to C5, C8, C11 to C15, C17, C18, C22 1 000 pF C6, C7 24 pF (UJ) C9 1800 pF C10 33 nF C19 10 000 pF C23 1 µF C16, C20 0.1 µF Chip capacitor C21 0.01 µF R1, R2 4.7 k Ω R3 6.2 k Ω R4 1.2 k Ω Chip resistor R5, R6 1.95 k Ω Varactor Diode V-Di 1SV285 Chip Inductor L 3.9 nH
Preliminary Data Sheet P14016EJ1V0DS00 11 µµµµPB1005K PACKAGE DIMENSIONS
36 PIN PLASTIC QFN (UNIT: mm)
6.2±0.2 6.0±0.2 6.2±0.2 6.2±0.2 6.0±0.2 6.0±0.2 6.2±0.2 6.0±0.24–C0.5 Pin36 Pin1 1.0MAX 0.22±0.05 0.6±0.1 0.5±0.025 Bottom View
Preliminary Data Sheet P14016EJ1V0DS0012 µµµµPB1005K NOTE ON CORRECT USE (1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent abnormal oscillation). (3) Keep the track length of the ground pins as short as possible. (4) Connect a bypass capacitor (example: 1 000 pF) to the V CC pin. (5) Frequency signal input/output pins must be each coupled with external capacitor for DC cut. RECOMMENDED SOLDERING CONDITIONS This product should be soldered under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Soldering Method Soldering Conditions Recommended Condition Symbol Infrared Reflow Package peak temperature: 235 °C or below Time: 30 seconds or less (at 210 °C) Count: 2, Exposure limit Note : None IR35-00-2 Partial Heating Pin temperature: 300 °C Time: 3 seconds or less (per side of device) Exposure limit Note : None Note After opening the dry pack, keep it in a place below 25 °C and 65 % RH for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E).
Preliminary Data Sheet P14016EJ1V0DS00 13 µµµµPB1005K [MEMO]
Preliminary Data Sheet P14016EJ1V0DS0014 µµµµPB1005K [MEMO]
Preliminary Data Sheet P14016EJ1V0DS00 15 µµµµPB1005K [MEMO]
µµµµPB1005K ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES NESAT (NEC Silicon Advanced Technology) is a trademark of NEC Corporation.
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