UPA2502TM

UPA2502 NEC | Alldatasheet

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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. MOS FIELD EFFECT TRANSISTOR µ PA2502 N-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING DATA SHEET Document No. G16681EJ1V0DS00 (1st edition) Date Published September 2004 NS CP(K) Printed in Japan 2004

DESCRIPTION

The µ PA2502, which has a heat spreader, is N-channel MOS Field Effect Transistor designed for DC/DC converter and power management applications of notebook computers.

FEATURES

• µ PA2502 has a thin surface mount package with a heat spreader. The land size is same as 8-pin TSSOP.
• Low on-state resistance R DS(on)1 = 12.0 mΩ MAX. (VGS = 10.0 V, ID = 7.0 A) R DS(on)2 = 18.0 mΩ MAX. (VGS = 4.5 V, ID = 7.0 A)
• Low Ciss: 760 pF TYP. (VDS = 10.0 V, VGS = 0 V)

ORDERING INFORMATION

µ PA2502TM 8PIN HWSON ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) V DSS 30.0 V Gate to Source Voltage (VDS = 0 V) V GSS ±20.0 V Drain Current (DC) Note1 ID(DC) ±13.0 A Drain Current (pulse) Note2 ID(pulse) ±52.0 A Total Power Dissipation Note1 PT 2.7 W Channel Temperature T ch 150 °C Storage Temperature T stg −55 to +150 °C Single Avalanche Current Note3 IAS 13.0 A Single Avalanche Energy Note3 EAS 16.9 mJ Notes 1. Mounted on FR-4 board of 25 cm 2 x 1.6 mm, PW ≤ 10 sec 2. PW ≤ 10 µs, Duty Cycle ≤ 1% 3. Starting Tch = 25°C, VDD = 15.0 V, RG = 25 Ω, VGS = 20.0 → 0 V Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. PACKAGE DRAWING (Unit: mm) 0.65 TYP. 3 ±0.1 3.15 ±0.15 6.4 ±0.1 5.8 ±0.1 0.25 −0.05 0.10 M +0.1 0.10 S 0 −0 +0.05 0.17 ±0.05 0.8 MAX. 2.2 ±0.2 1, 2, 3 : Source 4 : Gate 5, 6, 7, 8: Drain EQUIVALENT CIRCUIT Source Body Diode Gate Protection Diode Gate Drain

Data Sheet G16681EJ1V0DS 2 µ PA2502 ELECTRICAL CHARACTERISTICS (TA = 25°C) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current I DSS V DS = 30.0 V, VGS = 0 V 1.0 µA Gate Leakage Current I GSS V GS = ±20.0 V, VDS = 0 V ±10.0 µA Gate Cut-off Voltage V GS(off) V DS = 10.0 V, ID = 1.0 mA 1.50 2.50 V Forward Transfer Admittance Note | yfs | V DS = 10.0 V, ID = 7.0 A 5 S Drain to Source On-state Resistance Note RDS(on)1 V GS = 10.0 V, ID = 7.0 A 9.3 12.0 m Ω R DS(on)2 V GS = 4.5 V, ID = 7.0 A 13.1 18.0 m Ω Input Capacitance C iss V DS = 10.0 V 760 pF Output Capacitance C oss V GS = 0 V 300 pF Reverse Transfer Capacitance C rss f = 1.0 MHz 100 pF Turn-on Delay Time t d(on) V DD = 15.0 V, ID = 7.0 A 14 ns Rise Time t r V GS = 10.0 V 3 ns Turn-off Delay Time t d(off) R G = 10 Ω 32 ns Fall Time t f 4 ns Total Gate Charge Q G V DD = 15.0 V 8.5 nC Gate to Source Charge Q GS V GS = 5.0 V 2.8 nC Gate to Drain Charge Q GD I D = 13.0 A 3.5 nC Body Diode Forward Voltage Note VF(S-D) I F = 13.0 A, VGS = 0 V 0.84 V Reverse Recovery Time t rr I F = 13.0 A, VGS = 0 V 27 ns Reverse Recovery Charge Q rr di/dt = 100 A/ µs 24 nC Note Pulsed: PW ≤ 350 µs, Duty Cycle ≤ 2% TEST CIRCUIT 3 GATE CHARGE VGS = 20 → 0 V PG. RG = 25 Ω 50 Ω D.U.T. L VDD TEST CIRCUIT 1 AVALANCHE CAPABILITY PG. D.U.T. RL VDD TEST CIRCUIT 2 SWITCHING TIME RG PG. IG = 2 mA 50 Ω D.U.T. RL VDD ID VDD IAS VDS BVDSS Starting Tch VGS τ = 1 s Duty Cycle ≤ 1% τ VGS Wave Form VDS Wave Form VGS VDS 10%0 90% 90% 90% VGS VDS ton toff td(on) tr td(off) tf 10% 10% µ

Data Sheet G16681EJ1V0DS 3 µ PA2502 TYPICAL CHARACTERISTICS (TA = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE dT - Percentage of Rated Power - % 100 120 0 25 50 75 100 125 150 175 TA - Ambient Temperature - °C P T - Total Power Dissipation - W 0.5 1.5 2.5 0 25 50 75 100 125 150 175 Mounted on FR-4 board of 25 cm2 x 1.6 mm, PW ≤ 10 sec TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA I D - Drain Current - A 0.01 0.1 100 1000 0.1 1 10 100 30 ms 10 ms ID(pulse) PW = 1 ms RDS(on) Limited (at VGS = 10 V) 10 s Single pulse Mounted on FR-4 board of 25 cm2 x 1.6 mm ID(DC) VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH r th(ch-A) - Transient Thermal Resistance - °C/W 0.1 100 1000 Single pulse Mounted on FR-4 board of 25 cm2 x 1.6 mm PW - Pulse Width - s 1 m 10 m 100 m 1 10 100 1000

Data Sheet G16681EJ1V0DS 4 µ PA2502 DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS I D - Drain Current - A 0 0.2 0.4 0.6 0.8 1 Pulsed VGS = 10.0 V 4.5 V VDS - Drain to Source Voltage - V I D - Drain Current - A 0.001 0.01 0.1 100 12345 VDS = 10.0 V Pulsed TA = 125°C 75°C 25°C −25°C V GS - Gate to Source Voltage - V GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT V GS(off) - Gate Cut-off Voltage - V 0.8 1.2 1.6 2.0 2.4 -50 0 50 100 150 VDS = 10.0 V ID = 1.0 mA Tch - Channel Temperature - °C | y fs | - Forward Transfer Admittance - S 0.01 0.1 100 0.01 0.1 1 10 100 VDS = 10.0 V Pulsed TA = −25°C 25°C 75°C 125°C ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE RDS(on) - Drain to Source On-state Resistance - mΩ 0.1 1 10 100 Pulsed 10.0 V VGS = 4.5 V ID - Drain Current - A RDS(on) - Drain to Source On-state Resistance - mΩ 0 4 8 12 16 20 ID = 7.0 A Pulsed VGS - Gate to Source Voltage - V

Data Sheet G16681EJ1V0DS 5 µ PA2502 DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE RDS(on) - Drain to Source On-state Resistance - mΩ -50 0 50 100 150 ID = 7.0 A Pulsed VGS = 4.5 V 10.0 V Tch - Channel Temperature - °C C iss, Coss, Crss - Capacitance - pF 100 1000 10000 0.1 1 10 100 VGS = 0 V f = 1.0 MHz Ciss Coss Crss VDS - Drain to Source Voltage - V SWITCHING CHARACTERISTICS DYNAMIC INPUT CHARACTERISTICS t d(on), tr, td(off), tf - Switching Time - ns 100 1000 0.1 1 10 100 VDD = 15.0 V VGS = 10.0 V RG = 10 Ω td(off) td(on) tf tr ID - Drain Current - A V DS - Drain to Source Voltage - V 048 1 2 VDD = 6.0 V 15.0 V 24.0 V ID = 13.0 A Q G - Gate Charge - nC SOURCE TO DRAIN DIODE FORWARD VOLTAGE SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD I F - Diode Forward Current - A 0.01 0.1 100 0.4 0.6 0.8 1 1.2 VGS = 0 V Pulsed VF(S-D) - Source to Drain Voltage - V I AS - Single Avalanche Current - A 0.1 100 0.01 0.1 1 10 IAS = 13.0 A EAS = 16.9 mJ VDD = 15.0 V RG = 25 Ω VGS = 20.0 → 0 V Starting Tch = 25°C L - Inductive Load - mH

Data Sheet G16681EJ1V0DS 6 µ PA2502 EXAMPLE OF THE LAND PATTERN Please optimize the land pattern in consideration of dens ity, appearance of solder fillet s, common difference, etc in an actual design. l1 l2 e1: 0.65 b2: 0.35 b3: 2.7 l1: 1.3 l2: 3.7 l3: 7.1 (Unit: mm)

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