UPA1560 NEC | Alldatasheet

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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. © 1999 COMPOUND FIELD EFFECT POWER TRANSISTOR µ µ µ µ PA1560 N-CHANNEL POWER MOS FET ARRAY SWITCHING INDUSTRIAL USE DATA SHEET Document No. G14283EJ1V0DS00 (1st edition) Date Published April 1999 NS CP(K) Printed in Japan

DESCRIPTION

The µPA1560 is N-Channel Power MOS FET Array that built in 4 circuits designed for solenoid, motor and lamp driver.

FEATURES

  • Full mold package with 4 circuits
  • 4 V driving is possible
  • Low on-state resistance R DS(on)1 = 165 mΩ MAX. (VGS = 10 V, ID = 1.5 A) R DS(on)2 = 200 mΩ MAX. (VGS = 4 V, ID = 1.5 A)
  • Low input capacitance C iss = 600 pF TYP.

ORDERING INFORMATION

µ PA1560H 10-pin SIP ABSOLUTE MAXIMUM RATINGS (T A = 25°C) Drain to Source Voltage (VGS = 0 V) V DSS 120 V Gate to Source Voltage (VDS = 0 V) V GSS(AC) ±20 V Gate to Source Voltage (VDS = 0 V) V GSS(DC) + 20, –10 V Drain Current (DC) I D(DC) ±3.0 A Drain Current (pulse) Note1 ID(pulse) ±12 A Total Power Dissipation (TC = 25°C) P T1 28 W Total Power Dissipation (TA = 25°C) P T2 3.7 W Channel Temperature T ch 150 °C Storage Temperature T stg –55 to + 150 °C Single Avalanche Current Note2 IAS 3.0 A Single Avalanche Energy Note2 EAS 0.9 mJ Notes 1.PW ≤ 10 µs, Duty Cycle ≤ 1 % 2. Starting Tch = 25 °C, VDD = 60 V, RG = 25 Ω , VGS = 20 V → 0 V Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. PACKAGE DRAWING (Unit : mm) 26.8 MAX. 4.0 2.5 1.4 123456789 1 0 0.6±0.1 2.54 1.4 10 MIN. 0.5±0.1 EQUIVALENT CIRCUIT 2468 11 0 579 ELECTRODE CONNECTION 2, 4, 6, 8 3, 5, 7, 9 1, 10 : Gate : Drain : Source

Data Sheet G14283EJ1V0DS002 µ µ µ µ PA1560 ELECTRICAL CHARACTERISTICS (T A = 25 °C) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Drain to Source On-state Resistance R DS(on)1 VGS = 10 V, ID = 1.5 A 130 165 m Ω R DS(on)2 VGS = 4.0 V, ID = 1.5 A 145 200 m Ω Gate to Source Cut-off Voltage V GS(off) VDS = 10 V, ID = 1.0 mA 1.0 1.8 2.5 V Forward Transfer Admittance | y fs |V DS = 10 V, ID = 1.5 A 2 4.5 S Drain Leakage Current I DSS VDS = 120 V, VGS = 0 V 10 µA Gate to Source Leakage Current I GSS VGS = ±20 V, VDS = 0 V ±10 µA Input Capacitance C iss VDS = 10 V 600 pF Output Capacitance C oss VGS = 0 V 160 pF Reverse Transfer Capacitance C rss f = 1.0 MHz 70 pF Turn-on Delay Time t d(on) ID = 1.5 A 35 ns Rise Time t r VGS(on) = 10 V 80 ns Turn-off Delay Time t d(off) VDD = 60 V 700 ns Fall Time t f R L = 30 Ω 250 ns Total Gate Charge Q G ID = 3.0 A 28 nC Gate to Source Charge Q GS VDD = 96 V 2.5 nC Gate to Drain Charge Q GD VGS = 10 V 9 nC Body Diode Forward Voltage V F(S-D) IF = 3.0 A, VGS = 0 V 0.9 V Reverse Recovery Time t rr 160 ns Reverse Recovery Charge Q rr IF = 3.0 A, VGS = 0 V di/dt = 50 A/ µs 280 nC TEST CIRCUIT 1 AVALANCHE CAPABILITY R G = 25 Ω 50 Ω PG L VDD VGS = 20 → 0 V BV DSSIAS ID VDS Starting Tch VDD D.U.T. TEST CIRCUIT 3 GATE CHARGE PG. 50 Ω D.U.T. R L VDD IG = 2 mA 90 %VGS(on) 90 % td(off) t f 10 % ID toff TEST CIRCUIT 2 SWITCHING TIME PG. R G VGS D.U.T. R L VDD τ = 1 sµ Duty Cycle ≤ 1 % VGS Wave Form ID Wave Form VGS 10 % 10 %0 ID 90 % td(on) trτ R G = 10 Ω ton

Data Sheet G14283EJ1V0DS00 3 µ µ µ µ PA1560 [MEMO]

µ µ µ µ PA1560

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