UPA101 NEC | Alldatasheet

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© 1995, 1999 DATA SHEET COMPOUND TRANSISTOR µPA101

FEATURES

  • BUILT-IN ULTRAHIGH FREQUENCY MULTIPLIER: (Each Transistor has fT 9 GHz)
  • OUTSTANDING h FE LINEARITY
  • TWO PACKAGE OPTIONS: µPA101B: Superior thermal dissipation due to studded 14-pin ceramic package µPA101G: Reduced circuit size due to 8-pin plastic SOP package for surface mounting DESCRIPTION AND APPLICATIONS This Si bipolar transistor array contains six bipolar transistors which have fT 9 GHz. Applications include a multiplier, double balanced mixer, phase detector, or AGC circuit. The two package options offer a choice of excellent heat dissipation or 35 % size reduction.

ORDERING INFORMATION

µPA101B-E1 14-pin ceramic package µPA101G-E1 8-pin plastic SOP (225 mil) ABSOLUTE MAXIMUM RATINGS (T A = +25 °C) SYMBOLS PARAMETERS UNITS RATINGS VCBO * Collector to Base Voltage V 15 VCEO * Collector to Emitter Voltage V 6 VEBO * Emitter to Base Voltage V 2.5 IC * Collector Current mA 40 PT Power Dissipation µPA101B mW 650 µPA101G mW 250 TJ Junction Temperature µPA101B °C 200 µPA101G °C 125 TSTG Storage Temperature µPA101B °C –55 to +200 µPA101G °C –55 to +125 * Absolute maximum ratings for each transistor. HIGH FREQUENCY NPN TRANSISTOR ARRAY Caution electro-static sensitive devices The mark shows major revised points. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. P10706EJ2V0DS00 (2nd edition) Date Published October 1999 N CP(K) Printed in Japan

µPA101

2 Data Sheet P10706EJ2V0DS00

PACKAGE DIMENSIONS (UNIT: mm) µPA101B

14 PIN CERAMIC PACKAGE

µPA101G See connection diagram for description of leads.

8 PIN PLASTIC SOP (225 mil)

NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. 1 4 M detail of lead end 5.2± 0.2 1.49 0.85 MAX. 1.27 0.12 1.57± 0.2 0.1± 0.1 6.5± 0.3 0.6± 0.2 1.1± 0.2 0.10 4.4± 0.15 +7° −3° 0.17 +0.08 −0.07 0.42 +0.08 −0.07 φ 0.8 TOP VIEW 0.35 1.27 6.2 5.0 MAX. 4.5 MIN. 0.08 2.3 MIN. 1.6φ 2. 7 MAX.SIDE VIEW BOTTOM VIEW 1.8 3.0

µPA101 3Data Sheet P10706EJ2V0DS00 ELECTRICAL CHARACTERISTICS (Unless otherwise specified TA = +25 ˚C µPA101B, µPA101G common) SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN. TYP. MAX. ICBO Collector Cut-off Current at VCB = 5 V, IE = 0 (Q1 thru Q6) µA 1.0 IEBO Emitter Cut-off Current at VEB = 1 V, IC = 0 (Q5 and Q6) µA 1.0 hFE Direct Current Amplification, VCE = 3 V, IC = 1 mA (Q5 and Q6) 40 100 250 hFE1 /hFE2 Direct Current Amplification Ratio, VCE = 3 V, IC = 1 mA, (Q5 and Q6) 0.9 1.0 1.1 C EB Emitter to Base Capacitance at VEB = 0, f = 1 MHz pF 1.4 2.8 fT Gain Bandwidth Product* at VCE = 3 V, IC = 10 mA GHz 9 * Measured by installing a single transistor in a Micro-X package: the value shown is a reference value. CONNECTION DIAGRAM (Top View) µPA101B µPA101G NC NC NC NC NCSUB * 14 13 12 11 10 9 8 1234567 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 * Substrate should be connected to the lowest voltage point to prevent latch-up. TEST CIRCUIT SCHEMATIC* (For Electrical Characteristics Measurements excluding fT) Q 1 Q 2 Q 3 Q 4 Q 5 8 9 13 14 1 2 6 7 VBE IB Q 6 IC V8-2 VCE * See performance characteristics for voltage. Q 1 Q 2 Q 5 Q 3 Q 4 Q 6 8765 1234

µPA101

4 Data Sheet P10706EJ2V0DS00

TYPICAL PERFORMANCE CHARACTERISTICS (TA = +25 °C) 0012345 Input Voltage, V IN (V) IB = 20 Aµ 100 COLLECTOR CURRENT vs. PIN 8 TO PIN 2 OR 6 VOLTAGE 0.4 Collector current, IC (mA) Base to Emitter Voltage, VBE (V) COLLECTOR CURRENT vs. BASE TO EMITTER VOLTAGE Collector current, IC (mA) 0.1 0.2 0.5 VCE = 3 V 1000 0.5 1 2 Collector Current, IC (mA ) DC CURRENT GAIN vs. COLLECTOR CURRENT 4 1 Gain Bandwidth, fT (GHz) Collector Current, IC (mA ) GAIN BANDWIDTH PRODUCT vs. COLLECTOR CURRENT DC Current Gain, (hFE ) 200 500 100 51 0 2 0 5 0 VCE = 3 V 502 5 10 20 VCE = 5 V 3 V 1 V

µPA101 5Data Sheet P10706EJ2V0DS00 NOTES ON CORRECT USE (1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as wide as possible to minimize ground impedance (to prevent undesired operation). (3) Design circuits connected Subpin to the lowest voltage to prevent latch-up. (4) Design circuits as each pin voltage difference within 15 V maximum. RECOMMENDED SOLDERING CONDITIONS This product should be soldered in the following recommended conditions. Other soldering methods and conditions than the recommended conditions are to be consulted with our sales representatives. µPA101G Soldering process Soldering conditions Recommended condition symbol Infrared ray reflow Package peak temperature: 235 °C, Hour: within 30 s. (more than 210 °C), Time: 2 times, Limited days: no.Note Time: 2 times, Limited days: no.Note Wave soldering Soldering tub temperature: less than 260 °C, Hour: within 10 s. Time: 1 time, Limited days: no.Note Pin part heating Pin area temperature: less than 300 °C, Hour: within 3 s./pin Limited days: no.Note µPA101B Soldering process Soldering conditions Symbol Infrared ray reflow Peak package’s surface temperature: 230 °C or below, Reflow time: 10 seconds or below (210 °C or higher), Number of reflow process: 1, Exposure limit*: None Partial heating method Terminal temperature: 260 °C or below, Flow time: 10 seconds or below, Exposure limit*: None Note It is the storage days after opening a dry pack, the storage conditions are 25 °C, less than 65 % RH. Caution The combined use of soldering method is to be avoided (However, except the pin area heating method). For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E). IR35-00-2 VP15-00-2 WS60-00-1

µPA101

6 Data Sheet P10706EJ2V0DS00

[MEMO]

µPA101 7Data Sheet P10706EJ2V0DS00 [MEMO]

µPA101 NESAT (NEC Silicon Advanced Technology) is a trademark of NEC Corporation.

  • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
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  • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information.
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