UM82C94 ETC | Alldatasheet
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: UM82C94 CMOS Clock Generator & Driver - PIN CONFIGURATION ™ Generates the System Clock for CMOS or PUK LA 2 7s | NMOS Microprocessors. AENTIET 3S) — | «16 FE) X2 . ® Up to 25 MHz Operation. RDYI LJ 4 z 16 FF) ASYNC @ Uses a Parallel Mode Crystal Circuit or READY LIS 14 LJ EPI External Frequency Source. rovetje B 13F Fe @ Provides Ready Synchronization. AENZ—G7 | 12, ) ose m Generates System Reset Output from Schmitt cx{j8 — 116) Res Trigger Input. ‘ gnpC}s° . 100) Reser @ Capable of Clock Synchronization with Other . a Some] eoes [tee ® TTL Compatible Inputs/Outputs. ® 18-pin Package. | @ Single +5V Power Supply. RES | Normat | Reset : ® Reguried 2 Times the Frequency of the Desired | CLK Output Address Address fem | desea | essing - 2 Stage Read 1 Stage Read a UM8237A-5/AE-5 Programmable DMA Controller summa FEATURES PIN CONFIGURATION Enable/Disable Control of Individual oR ch S~a0b ar DMA Requests owo2. 39 [F) AG @ Four independent DMA Channels MENA = ’ an . . ne = independent Autoinitialization of all i x os - 36 fy EOP Channels READY C36 _.. $5 As @ Memory-to-memory Transfers HLDA C47 — s 34 A2 . ff Memory Block Initialization ey de a ® Address Increment or Decrement Ha [10 - § 31D Vop a High Performance: Transfers up to 1.6M csi. a 30 [] peo Bytes/Second with 5 MHz 8237A-5 ee BE ee _ @ Directly Expandable to any Number of pack2 ig ll 27 1) DB3 Channels DACK3 [J 16- 26 1) Das ® End of Process Input for Terminating DREOS Cj 16 © 25 FJ DACKO prea2 C17 > 24 [1] DACK1 Transfers oneo1 118 23 4] ves = Software DMA Requests preoo Ck19—- 22 1) pee ® Independent Polarity Control for DREQ Vgg 4 20 ' 23 087 and DACK Singnals @ Available in EXPRESS . — Standard Temperature Range