UM70C171

UM70C171 UMC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 15

Technical content

Features

™ Pixel Rates of 35 MHz = Composite Blank . ™ 266 x 18 Bit Color Palette ™ Single +6V Power Supply = 266K possible Colors = Low Power, High Performance CMOS Process . Color Palette ae = TTL Compatible Inputs ™ Three Internal 6-Bit DACs = Full A P Interf = Direct Drive (782) Video Cable ull Asynchronous uP Interfsce = RGB Analog Output ™ Available in 28 pin DIP and 44 PLCC packages

Description

The UM70C171 is a monolithic triple 6-bit video digital single or double terminated 752 loads to normal video to-analog converter with on-chip 266 x 18 Bit color levels at pixel rates of 35 MHz, The UM70C171 provides palette intended for graphics applications. The color a bidirectional microprocessor interface with TTL com- palette makes possible the display of 266 colors selected patible inputs. The UM70C171 is pin compatible with from a total of 266K possible colors through the internal the inmos IMS G171. 6-bit RGB video DACs, The DACs are capable of driving Pin Configurations Block Diagram 28-Pin DIP reo] 7B Vee Gneen C]2 27 [7] AS TIMING enue {3 26 [1 AS PcuK GENERATOR Nec Iner C]4 awa one Polis 2 o, PIXEL LATCH COLOR PALETTE ad 7¥MTOCI7t, f] Os Cle 21 O. Cfo 2of05 04-0 >| rstqo Eo _ micro. U processor 0 = a= a = wrenrace. KC 188i DATA Hie m0 Peuk Ct 16f-] STARR ma “| ‘Arent bac Bue GnoC]'4 1s.) AO peux 44-Pin PLCC ‘ace e 2 Boneennonam Ba 7 F) mad yan) seB ey Po - Py Pixel address inputs othe Bey Dg - Dy. Program data 1/0's : ore] 0 ae So + ASy Register select edu SB RED, GREEN, BLUE | Anaiog vdeo outputs «Cy 12 umeciL = ube, PCLK Pixel clock OC} ia safer pal Wate anabie ood ie zDt SLANE Video Blanking input WAC] 16 2F) IREF Reference current 39] 17 2 Vee #5 :volt supply input 18 19 20 21 22 23 24 25 2827 23 GND Ground ts 2 $32 9238 63° : 3-98

UNICORN MICROELECTRONICS 24E D M@® 9278786 0000318 4 ® T-52Q-33-43 UuUMcG . UM70C171 Pin Description : RED These signals are the analog outputs of the 6-bit DACs, These are GREEN the currents used for each of the guns in an RGB (Red, Green, BLUE Blue) video display, Each DAC is composed of 63 current sources, The output of each of these current sources is summed together according to the applied 6-bit binary value, IREF This is the Reference Current Input. The current forced out of this pin to ground determines the current sourced by each of the 63 current sources in each of the three 6-bit DACs. Each current source produces 1/30 of IREF when activated by the 6-bit digital input code, . These are the Pixel Address lines. This byte-wide information is latched and masked by the Pixel Mask Register. The resulting value is used as an address of a location in the Color Palette RAM, wake 13 PCLK The Pixel Clock signal is applied to this pin. The rising edge controls B= the latching of the Pixel Address and Blanking Inputs, It also con- an trols the progress of these values through the three stage pipeline Q- of the Color Palette and through the DACs to the outputs. sae ee ee ee This Is the power supply connection, and is connected to ground. This is the active Low READ bus control signal. When active, any information present on the Internal data bus is available on the Data I/O lines (Do-D7). BLANK This is an active Low signal that forces the DAC’s outputs to zero. When BLANK is asserted, a video monitor's screen becomes black and the DACs ignore any output values from the Color Palette, However, the Color Palette can still be updated through Dg-D7. 17-24 Tie} These are the bidirectional Data 1/O lines used by the host _micro- processor to WRITE information (using the active Low WR) into and READ information (using the active Low RD) from the UM70C171 internal registers (Pixel Address register, Color Value register, and Pixel Mask register). During the WRITE cycle, the rising edge of WR latches the data Into the selected register. The rising edge of RD determines the end of the READ cycle, With RD and WA equal to a logic HIGH, the Data I/O lines will no longer contain information from the selected register and will go into a tristate mode, WR This is the active Low WRITE signal, and controls the timing of the WRITE operations on the microprocessor interface Inputs, Do-D>. 26,27 RSo, RSy These are the Register Select lines which control the selection . of one of the three internal registers. These lines are sampled during the falling edges of the enable signals (RD or WA). (See Functional Description for more information regarding the internal registers.) 28 Vee This is the positive power supply pin. It is normally connected to +5V DC and bypassed with a 10uF tantalum capacitor, 3-99

INICORN MICROELECTRONICS 24E D MH 32747466 00003195 T mm . T-52-33-43 ume uMm70C171 eee Functional Description The Color Value register is an internal 18-bit wide re- t . gister used as a buffer between the microprocessor inter- : The UM70C171 forms the output stage for high resolution face and the color palette. It is accessed by setting RSo = raster scan RGB video systems, It contains a Color Palette 1 and RS, = 0. A color definition can be read from or . with 266 memory locations that are 18 bits wide. The written to this register by a sequence of three byte-wide color palette’s output is connected to thres high speed transfers to this register address, When a byte is written current output 6-bit video DACs. The devices use on- tq this register, only the least significant six bits (Do- board registers to easily interface with microprocessors, Ds) contain color information, When a byte Is read from Microprocessor Interface this register address, only the six least significant bits . contain information - the most significant two bits are The UM70C171 Microprocessor interface consists of set to zero, Refer to Figures 9-13, three internal registers; Pixel Address Register, Color . Value Register and Pixel Mask Register. These are in- After the write sequence Is completed, the Color Value dividually accessed by register select signals, RS and register’s contents are written to the specified color palette RS,. The following table defines which register Is selected address stored in the Pixel Address register. Finally, the by the logic states of RSp and RS,. Pixel Address register is automatically incremented, The color definitions can be read from the UM70C171 color palette. After setting RSo and RS, equal to 1, the " desired color palette address is stored in the Pixel Address ° ° Pixel Address (Write Made} register. The color definition (18-bits) in the desired color 1 1 Pixel Address (Read Mode) oe 1 0 Color Value palette location is then transferred to the Color Value 0 1 Pixel Mask register and the Pixel Address is auto-incremented, With successive read cycle, the color definitions pointed to by the incremented address is transferred to the Color The contents of the color palette can be accessed through Value register, Refer to Figure 12. the Color Value and Pixel Address ragistars. Attempting to update the color palette when BLANK All of the operations on the microprocessor interface is not asserted results in the data from, the Color Value can take place asynchronously to the pixel information register taking precedence over the UM70C171 bit mapping currently being processed by the Color Pelette, operation, The output of the three 6-bit DACs will be based on the color definition from the memory location The Pixel Address register is a byte-wide latch that receives specified by the Pixel Address register and not the address and latches address information applied to pins Po-P,, found on P9-P,. This conflict results in the DACs generat- It can be used in both Read and Write mode depending —_—ing unexpected output fevels. This can last as long as two on the logic state of RS and RS;,With RSp=RS,:=0 — PCLK periods, (register select = 0, 0), the Pixel Address register is In the write mode, Two events normally precede WRITING The Pixel Mask register is a byte-wide latch, By setting one or more new color definitions to the color palette, RSo = 0 and RS; = 1, the Pixel Mask register can be The first. is the specification of a color palette address, accessed by the microprocessor Interface, Do-D7. This Second, the Color Value register must be loaded with a register is used to mask selected bits of the Pixel Address color definition, The sequence of data transfer is (1) Values applied to the Pixel Address inputs (Po-P2). A the desired color palette address - this address is stored “1"" in any location in the Pixel Mask register leaves the in the Pixel Address register and (2) the color definitions: corresponding bit to zero. The operation of the Pixel RED, GREEN and lastly, BLUE, Refer to Figures 10 Mask register does not affect the address of the color and 11, definition when the microprocessor accesses the color palette, The masking operation makes it possible to alter When RS» = RS; = 1 (register select = 1, 1), the Pixel the ‘displayed colors without altering the contents of Address register is in the Read mode, Once again, two external video memory or the UM70C171 color palette. events take place and normally precede READING one or more color definitions in the cofor palette, The first Writing to the color palette action {is to specify an address within the color palette, A new color definition can be stored in the color palette The second is to load the Color Value register with the by first specifying the Initial address under write mode. contents of the location addressed in the color palette. This address is stored in the Pixel Address register (RSo = The color definition data transfer sequence is RED, RS, = 0). The initial address is followed by RED, GREEN GREEN and lastly, BLUE, Refer to Figures 9, 12, and and BLUE color definition data (RSO = 1, RS1 = 0), 13, These six-bit inputs are collected together in the Color 3~100

UNICORN MICROELECTRONICS 24E D M@ 9278788 0000320 b T-5A-33-43 @ume UM70C171 Value register for a total of 18 bits. This new color de- Video path finition is then transferred to the location pointed to The Video path consists of the Pixel Latch and Mask by the information stored in the Pixel Address register, {inputs Po-P7), color palette (266 18-bit wide RAM), As soon as this transfer is completed, the Pixel Address 18-bit wide bus, and an 18-bit wide latch on the inputs register {is auto-incremented, This allows consecutive of the three G-bit high-speed video DACs, The video path color palette locations to be updated without the micro- uses a three clock cycle (PCLK) pipeline for the Pixel Processor specifying each address, All that is necessary Address and BLANK inputs. These signals are latched Is to continue supplying the RED, GREEN and BLUE on the rising edge of PCLK. data for each consecutive address, Refer to Figures 10 and 11, Analog outputs The analog outputs are designed to drive single-terminated Reading fro lor palette a from the color palette 769. loads to a peak-white amplitude of 0,7V. To read a location in the color palette, an address is sent on the Data I/O lines (Do-D7) under Read mode and The reference current (IREF) for’this output is set to stored in the Pixel Address register (RSq = RS; = 1). The 4.44 mA, The analog outputs can also drive double-ter- color definitién contained in the specified location is minated 762 loads with REF set to 8.88 mA. then transferred to the Color Value register, Once again, the Pixel Address register is auto-incremented, The color The analog outputs can be set to zero by using BLANK definition can now be retrieved with three sequential input, This is an active Low signal that forces the analog os read operations (RS = 1, RS, = 0}, The first byte placed outputs to ground by placing all zeros on the DACs’ inputs, ane on the Data 1/0 lines contains the RED value. The next ‘The color definition selected by the Pixel Address is ig- Bee \\s GREEN and the final is BLUE, The two most signif- "ored. Each of the 63 current sources used In each of the ae: icant bits are set to zero In each case. In a manner similar. 6:bit_ DACs produces 1/30 IREF. Therefore, the mag- — to the write mode, consecutive color palette locations _—itude of peak white voltage is a function of the output can be ready by simply specifiying the beginning address _—_‘'0ading and is determined by: and reading color palette one or more times, Refer to Vv. = 21(I, IR Figures 9, 12 and 13. PEAK WHITE REF L V, =0V. If the Pixel address register is ever updated during a read BLACK LEVEL or write operation, the current data sequence Is terminated and a new read or write operation js initialized. AC Characteristics: T, = 0°C to +70°C, Voc = 6V + 10%, GND = OV [om | roomy To [ome | etn rGHBX [BLANK Hold Tine ee AIGHAV_| — Oiferontl utp Delay a a CS es 1SVWL Register Select Setup Time (Write Cycle) | 18 | | | ons | | Regier SdectSeup Reed Greil |_| [| | . 3-101

eee... ’ a - oe a ve a SR ee St a a ea JINICORN MICROELECTRONICS 24— D MH 92747466 0000321 46 mm UMG : ® . UM70C171 SO AC Characteristics (Continued) : Syne | rumen | Ta tWLSX Register Select Hold Tima(Writecycle) | 16 | S| os S| Output Tuna Delay a tWHWL1 Successive Write Interval ee ee tRHALt Successive READ Interval a ce tRHWLI1 RD followed by WRITE Interval ee ee tWHRL2 RD after Color Write [| 3 [ss tcHcH~—|—sNoteo ‘| tRHWL2 WR after Color Read ; 6 | | tcHcH ‘WHALS RO after Read Address Write [| 6 | | tcHcH [| escirieenabi Tanitton Tine ffs dd Note 1: This parameter is the allowed variation in the pixel clock frequency. It does not permit the pixel clock period to vary below the minimum value for pixel clock (tCHCH) period specified. Note 2: It is necessary that the color palette’s pixel address be a valid logic level with the appropriate setup and hold times at each rising edge of PCLK (this requirement includes blanking period). Note 3: A valid analog output is defined as the 60% point between successive values, This parameter is stable with time but can vary between different devices and may vary with different DC operating conditions, Note 4: This applies to different analog outputs on the same device. This is a design parameter, not 100% tested. Note 5: Measured at +200 mV from initial steady state output voltage. Note 6: This parameter allows synchronization between operations on the microprocessor Interface and the pixel stream being processed by the color palette. AC Test Conditions Pins 17 «24 60pF 3-102

8 ASHAY |

8 TTS LANK BLANK

: Figure 2, Timing Diagram Detailing Timing Specifications. Figure 3. Basic Write Cycle Timing Diagram.

EE _—_——ooooOOOOVOOeeeeeeeee .S.SSaSSS JNICORN MICROELECTRONICS 24E D M@@ 9278746 OOOO32b 7? © UMG uM70C171 Absolute Maximum Ratings * *Comments this device at these or any other conditions above those Applied Input Voltege ~O8V 10 +7.0V indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended periods may affect device re- liability. Electrical Characteristics: Tq = 0°C to 70°C, Voc BV # 10%, GND = OV [Simbel | ___ Parmeter Min [Moe Unk_[ Condon] P| ren iaiawain eee [ou [owertsiscone i of fm fd Icc Operating Supply Current (UM70C171) 160 mA PCLK = 35 MHz 160 mA PCLK = 50 MHz 1OUT=Max, Digital Outputs Unloaded VREF Reference Voltage at IREF Pin Veo-3 v Veg = 4.5V, IREF = 10 mA IOUT . Output Current Compliance (Pins 1-3) mA VOUT S1V IREF <10 mA Full Scale Error +5 ZL = 762 + 30 pF Note 7 IREF = 4.44 mA . ZL = 37,69430 pF {REF = 8,88 mA DAC-to DAC Mismatch Bal ZL = 769 + 30 pF Note 8 IREF = 4.44 mA Internal Linearity LSB ZL = 75Q + 30 pF Note 9 IREF = 4,44 mA 1ON Rise Time ZL = 7650. + 30 pF Note 10 IREF = 4.44 mA 3-107

UNICORN MICROELECTRONICS 24E D mm@ 9278788 0000327 7 a . UMG © . UM70C171 a TE DC Characteristics (Continued) ; : Full-Scale Setting Time (UM70C171) 28 ZL = 762. + 30 pF Note 11 IREF = 4.44 mA Glitch Energy pV-sec ZL = 762 + 30 pF Note 12 IREF = 4.44 mA COUTA | Analog Capacitance (Pins 1-3) [0 |r [BLANK Logic Low VoUuT- Blanking Output Voltage 40.5 Ls8 | BLANK=Logic Low BLANK ZL = 762 + 30 pF : IREF = 4.44 mA Unadjusted Output Offset Error 405 LsB | BLANK=Logic High| ZL = 760. + 30 pF IREF = 4.44 mA Clock Feedthrough (UM70C171) PCLK = 35 MHz Note 13 PCLK = 50 MHz ZL = 762 + 30 pF IREF = 4.44 mA ov. Note 8: The listed value is relative to the midpoint of the full-scale distribution of the internal three DACs. Note9: Zero and full-scale adjusted linearity error = [VOUT—VOFFSET—(D x VLSB)) / VLSB, VLSB = (VFULLSCALE —VOFFSET)/63] . Note 10: The rise time Is measured for 10% to 90% of the full scale transition. Note 11: The output signal's setting time Is measured from a 2% change’ at the transition’s initial value until it has settled to within 2% of the final value, Note 12: This vafue is determined using triangle approximation: glitch energy = (area of positive transient) — (area of neg- ative transient), Note 13: These values are referenced to full-scale output. is caused by series impedance in the ground path and the Power supply current transients drawn by the UM70C171. The differen- The UM70C171 may draw large transient currents from tial ground noise can be minimized by using large, low the power supply. To ensure proper operation, it is neces- inductance ground paths between the digital devices that sary to utilize standard high frequency board layout drive the UM70C171 and pin 14, Therefore, a ground techniques and power supply distribution. plane layout is recommended. The transient currents required by the UM70C171 dictate Analog Output-Line Driving that the AC impedance of the ground path must be Kept — The connection between the UM70C171 outputs and to a minimum, This Is accomplished by using the recom- the RGB inputs of the video monitor it is driving should mended decoupling capacitors, C1 and C2, as shown In bg viewed as a transmission line, Impedance changes along . Figure 14, These capacitors must have leads that are 2s this {Ine will result in the reflection of part of the video short as possible, High frequency decoupling is accomplish- signal back to the DACs’ outputs, These reflections may ed with a O.1uF chip capacitor, C1, A bead tantalum, ——resuit in a degradation in the picture quality displayed on between 104F to 47HF, should be used for C2, the monitor, To ensure good signal fidelity RF techniques Differential ground noise can be created when voltage Should be observed. Any traces connecting the UM70C171 difference appears between pin 14 and the ground of the © af onboard connector should form a transmission line of 762 impedance. However, the need to ensure 3-108

OO OOOO OO —— eV UNICORN MICROELECTRONICS 24E D mm@ 9278788 0000328 0 mm - : T-52.-33-43 , ume um70c171 that the connecting traces form a transmission line can mismatch occurs back to the DACs’ output, The signal be eliminated by placing the DACs’ output termination then reflects off the DAC’s output back toward the mon- resistor at the output connector Instead of the DACs’ itor. It arrives with a significant time delay following the output pin. The coaxial cable that connects the UM70C171 original signal and “ghosting” results. outputs to a video monitor should have a characteristic impedance of 759. Connectors on the coaxial line can (3) Double-termination of the OAC outputs allows each cause impedance change. Any connectors used with the end of the transmission IIne to be correctly matched. coaxial cable must match its characteristic impedance, This results in the least amount of reflection and the highest signal and display fidelity, This termination me- The UM70C171 DACs use switched current sources that thod also allows for the fastest rise time. The DAC ter- are summed together, thus generating the output current. mination’s RC time constant sets the outputs’ rise time. Each 6-bit DAC consists of 63 current sources, each of The greater the time constant, the slower the rise time. which has a magnitude of 1/30 (IREF). The digital input Therefore, the rise time will be minimized since the im- code determines the number of current sources that are pedance using this termination technique is less than active and contributing to the total output current. This that achieved with single termination. With double-ter- output current, in conjunction with a termination re- mination, it is necessary to increase IREF to 8.8 mA sistance connected between each DAC output and ground, to ensure a full-scale output voltage of 700 mV. sets the full-scale magnitude of the output voltage. There are four different methods of terminating the UM70C171 _{4 By placing @ buffer at the DAC’s output the UM70C171 7 DAC outputs: will be able to drive large capacitance loads such as long so lossy cables. The buffer requires a high Input impedance, & . (1) Single Termination at the DAC (752) a condition that is satisfied by the LM1201 and LM1203, Bs (2) Single Termination at the Destination (769) A760. oad Is placed at the buffer’s Input. sete! {3) Double Termination (37.62) The buffer’s low output impedance should be matched (4) Buffered Signal to the interconnecting cable with a series resistor. The . cable should then be terminated with the same resistance {1} Single termination at the source involves placing a at the monitor. single termination resistor at each DAC output of the UM70C171. No other terminating load is present. There- Analog Output-Protection fore, a high-input impedance monitor should be used, The AC load driven by the DACs’ outputs is the trans- Each of the UM70C171 pins has on-chip electrostatic misston line Impedance in parallel with the load resistor, ‘ischarge_damage (ESD) protection, However, proper The transmission line's impedance should match the im- Precautions for handling these parts are recommended pedance of the load resistor, Thus, the DACs’ output during manufacturing to reduce the possibility of ESD, has an initial signal amplitude that is half the DC value expected. This half-amplitude signal is 100% reflected Senerating IREF by the open circuit presented by the monitor input. This An active current source for IREF is recommended to restores the signal amplitude to the expected value, The ensure that the UM70C171 has predictable and stable reflections from the monitor propagate back towards output currents, There are numerous methods available the DAC outputs, The load resistor at each DAC output to generate the reference current. One of the simplest Presents a correctly terminated transmission line so no circuits is shown with the UM70C171 in Figure 14. As further reflections occur. This arrangement is relatively shown, this IREF generator will sink —4.44 mA (single tolerant to mismatches in the transmission line between termination) with R1 = 22,19 and R2 = 9312, the DAC and the monitor becausa no reflections occur at the DAC end of the transmission line, However, multi FOr applications that use double termination, R1 = 11 ple monitors should not be connected in parallel despite and R2 = 4649, The diode connected transistor, 21, each monitor's high input impedance, across Q2's base-emitter junction performs a first-order compensation for thermal variations, (2) Single-termination at the destination has the termina- . . . tlon impedance at the Input of the monitor acting as Figure 16 shows an alternative method of generating both the load resistor for the DAC and the termination ‘REF. The LM334 precision current source Is used in Impedance of the cable (transmission fine). if the connec- a temperature compensated configuration. The reference tion between the UM70C171 is correctly terminated there current is set by a single resistor, R1, Independent of will be no reflections, However, if there are any line im- Veg The current’s value is: pedance variations along the cable, reflections will occur and create “ghost images” on the display, This occurs IREF = 33.86 mV/At because there is a reflection from the point where the 3-109

ee ——EEOeeee INTCORN MICROELECTRONICS 24E D M@@ 9278788 0000329 2 mm . UMG : (43) . UM70C171 : Application Hints (Continued) : : . +5V 6] Po vee |28¢ + 6] P 0.18] 10uF 2 [0.1HF: 10uF 7] Pa Ter Te2 Toye s tt Pinal Address input { 51 5 lace [4 =—— tue is a 1= 22,19, R2= m Ps 14 Ne Ais For Inep = 8.8mA

6 G « -

72] Py ND __ R1= 119, R2= 4642, 17 | Dp UM70C171 = Pf at 18} 0; reik [3 19| 02 . I. | = = . 20] 03 RED To Monitor's RED Input Data Input/Output 4 2 52 762 ae 22} 0s . eer 23] 06 a ofa 24] 0: ~ foo 26 RS GREEN To Monitor's GREEN input vor 27} RS 762. ae : ¥ Control Signals 2 on & SEY 16} 8LANK — BLUE 43 To Monitor's BLUE Input Pixel Slanals UTUTULr 7 == 1/4 Watt Carbon Film Note: Bead-style tantalum capacitors should be used for the 10uF devices Thermally connect the NPN transistors together with a Wakefield 25V series Equalizing Link. Figure 14, Typical Connection Showing !REF Generator. Figure 16 shows an LM10 and a discrete transistor generat Decoupling IREF ing IREF, The LM’s onboard 200 mv voltage reference The UM70C171 uses DACs composed of switched current is used along with the roferance’s amplifier to sat the sources. Each current source Is based on a current mirror voltege on Fil to 200 mV, Ignoring the small amount that praduces (IREF)/30 when active, The total output of base oenen the Wserete transistor’s collector current current is determined by the number of active current (and therefore, IREF) is found to be: sources switched to the output and the magnitude of IREF = 200 mV/R1 IREF. For IREF = 4.44 mA, R1 is, to the nearest 1% value 44,29; The magnitude of the current flowing through the internal IREF = 8,88 mA gives an R1 of 22,1, The circuit shown current sources depends not only on IREF, but also in Figure 17 operates in the same fashion as the LM10 —N the voltage at pin 4 relative to Vcc. Therefore, voltage circuit in Figure 16, The LM611's on-board reference variations between Veg and the IREF input can result Produces a nominal 1.24V. The voltage divider connected —_ in variations In the DAC’s output current. These variations to the references output, pin 3, creates 200 mV that can be greatly attenuated by using a high frequency cap- is applied to At The current (IREF) through the dis- acitor in parallel with a larger electrolytic capacitor to crate transistor's collector is: couple the IREF input to Vgc. This allows the reference IREF = 200 mv/At current input to track both high and low frequency varia- tions in Veg. For IREF = 4.4 mA, R1 Is, to the nearest 1% value 44,22; IREF = 8,88 mA gives an R1 of 22,12, ° 3-110

Oe eEEEEEEEEEEEEEEEEE—EeEeEeEaE INICORN MICROELECTRONICS 24E D M@@ 97278788 0000330 5 a © UM70C171 Ee Application Hints (Continued) . i. . sir YOKE 3] cc} S4Pt 1 - zAPa = eo + Plxol Addross Input § “BPs trer A=—— AMET 1oMF oes [LMasa ter : ps GNOP*_1N457 tye] gyOt PCLK = Date Input/Out ra 3 reol To Monitor's RED Input ata Input/Output a 72 ry B05 + + _

8 Bg GREEN To Monitor's GREEN Input

271 AS 752. 762. Control Signats 2 35] 75 am G{WA.. siue}e+—¢ + To Monitor's BLUE Input Pixel Clock JUTLILTL 762-750 . 1 a 1/4 Watt Carbon Film Note: Bead-style tantalum capacitors should be used for the 10puF devices, dari az Figure 16, Double Termination with LM334 Current Source {REF Generator. a +8V * vec }-28 SCospr =e tyr SE 0.1m = = +, = O.4uF == 10uF 7 UM70C171 ine. | 4 mA : <a] Ns3904 eno} 4 910 = Rt 47k , 442 [a | Figure 16, IREF Generator using L110, - . +8V . vec}28 + f TDb.ipr =r 100r Tow S12Kk um7oct71 - ome "iour [a 3 er PL de bie one Ns3904 ty i <i ~ . eng!4 : + At 44.2 al 2k . r | 1 = Figure 17, REF Generator using LM611. . 3-111

eee... aa INITCORN MICROELECTRONICS 24E D m@®§ 9276786 0000331 0 . @ume T-52-33-43 UM70C171

Ordering information

a , ; 3-112