UM2364 UMC | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 3

Technical content

Features

  • 8192 x 8 Bit organization
  • Single +5 Volt Supply
  • Access Time - 200/300/450 ns (max.)
  • Totally static operation
  • Completely TT L compatible
  • 24 Pin JEDEC approved pinout General Description The UM2364 and UM2364A high performance Read Only Memories are organ ized 8192 words by 8 b its with access times from 200 ns to 450 ns. The ROMs are designed to be compatible with all microprocessor and similar applica­ tions where high performance, large bit storage and simple interfacing are important design considerations. Both ROMs conform to the JEDEC approved pinout for 24 pin 64K ROMs. The UM2364 offers the simplest operation (no power down.) Its programmable chip select allows two 64K ROMs to be OR-tied without external decoding. Pin Configuration A7 Vee A7 A6 As A6 A5 A9 As A4 A12 A4 A3 es A3 A2 AlO A2 Al All Al Ao Os Ao 01 07 01 02 06 02

03 Os 03

  • UM2364A - Automatic power down (CE)
  • UM2364 - non power down version - programmable chip select (CS)
  • Three state outputs for wire-OR expansion
  • EPROMs accepted as program data input
  • 2564 EPROM compatible The UM2364A offers an automatic power down feature. Power down is controlled by the Chip Enable (CE) input. When CE goes high, the device will automatically power down and remain in a low power standby mode as long as CE remains high. This unique feature provides system level power savings as much as 90%. Both the UM2364 and UM2364A are pin compatible with the 2564 EPROM thus eliminating the need to redesign printed circuit boards for volume mask programmed ROMs after prototyping with EPROMs. Block Diagram

65.536 BIT

(256 x 256) '-:-1>---0,

  • CHIP SELECT iCSI IS PROGRAMMABLE LOW ACTIVE, HIGH ACTIVE OR DONT CARE.

Absolute Maximum Ratings* Voltage on Any Pin with Respect to D.C. Characteristics (TA = o°c to + 70°C, Vee = +5V ± 10%) Symbol Parameter Min. VO H Output HIGH Level 2.4 VOL Output LOW Level V 1H Input HIGH Level 2.0 V 1L I nput LOW Level -0.5 III Input Leakage Current ILO Output Leakage Current lee Operating Supply Current IS8 Standby Supply Current los Output Short Circu it Current Capacitance (TA = 25°C, f = 1.0 MHz) Symbol Parameter CI I nput Capacitance Co Output Capacitance UM2364/UM2364A *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indi­ cated in the operational sections of this specification is not implied and exposure to absolute maximum rating condi­ tions for extended periods may affect device reliability. Typ. Max. Uni~s Conditions Vee V 10H = -1.0 mA 0.4 V 10L = 3.2 mA Vee V 0.8 V 10 /1A VIN = OV to Vee 10 /1A VOUT = OVto Vee 100 mA Note 1 12 mA Note 2 90 mA Note 3 Min. Max. Unit Conditions 5 pf V1N = OV 5 pf VOUT = OV Note: This parameter is periodically sampled and is not 100% tested. A. C. Characteristics (TA =00Cto+700C, Vee=+5V ±10%)(Note7) UM2364-2 UM2364·1 UM2364 Symbol Parameter UM2364A·2 UM2364A-1 UM2364A Unit Conditions tCYC Cycle Time 200 300 450 ns tAA Address Access Ti me 200 300 450 ns tOH Output Hold After Address Change 10 10 10 ns tACE Chip Enable Access Time 200 300 450 ns Note 4 tACS Chip Select Access Time 85 100 150 ns tLZ Ouput LOW Z Delay 10 10 10 ns Note 5 tHZ Output HIG HZ Delay 85 100 150 ns Note 6 tpu Power Up Time 0 0 0 ns Note 4 tPD Power Down Time 85 100 150 ns Note 4 Notes: 1. Measured with device selected and outputs unloaded. 2. Applies to "A" versions only and measured with CE = 2.0\\1 3. For a duration not to exceed one second. 4. Applies to "A" versions (power down) only. 5. Output low impedance delay (tLZ) is measured form CE going low or CS going active. 6. Output high impedance delay (tHZ) is measured from CE going high or CS going inactive. 7. A minimum 0.5 ms time delay is required after application of Vee (+5V) before proper device operation is achieved. 1-10

(l)UMC UM2364 / UM2364A Timing Diagrams Propagation Delay from Address (CE LOW or CS = Active) A~~~~~~ -----.... t 'AA ::::j, VAUD ADD""S D~0~ PREVIOUS DATA ~ VALID DATA Propagation Delay from Chip Enable, Chip Select (Address Valid) [4] CS VALID [5] [5] 50% '----tpD IS6 A.C. Testing Input, Output Waveform A.C. Testing Load Circuit 2AV 20V 20V > TEST POINTS < O.BV O.BV DOUT OAV INPUT OUTPUT ~::OU 775U 100pf (INCLUDING SCOPE AND JIG) AC TESTING: INPUTS ARE DRIVEN AT 2AV FOR A LOGIC "1" AND OAV FOR A LOGIC "a". TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC "1" AND O.BV FOR A LOGIC "0". INPUT PULSE RISE AND FALL TIMES ARE 5 ns. Programming Instructions All UMC Read Only Memories (ROM) utilize computer asided techniques to manufacture and test custom bit patterns. The customer's bit pattern and address informa­ tion can be supplied to UMC in a number of different ways. UMC can process customer inputs in EPROM, ROM, PROM, paper tape, and computer punched cards. Contact your UMC sales representative for complete details on each of the various data input formats. Programming instructions are listed at the end of the Memory Section. Figure 1. Package Availability

Ordering Information

UM2364-1 300 ns 100mA! UM2364-2 200 ns 100mA UM2364A 450 ns 100mA UM2364A-l 300 ns 100mA UM2364A-2 200 ns 100mA * Not Applicable. 1-11 Standby Package cU'rrent Type N.A.* Plastic N.A. Plastic N.A. Plastic 12mA Plastic 12mA Plastic 12mA Plastic