UM2120 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 18
Technical content
Datasheet sections
- 1 Hardware description and confi guration
- 2 Connection of two EVALSTGAP1 AS boards
- 3 Getting started
- 3.1 Using EVALSTGAP1AS in standalone mode
- 3.1.1 Check list
- 3.1.2 EVALSTGAP1AS board setup example
- 3.1.3 EVALSTGAP1AS board in standalone mode
- 3.1.4 EVALSTGAP1AS default parameters
- 3.2 Using EVALSTGAP1AS with STEVAL-PCC009V2 and STGAP1AS
- 3.2.1 Check list
- 3.2.2 Single EVALSTGAP1AS board setup exampl e
- 3.2.3 Connection to STEVAL-PCC009V2 interfac e board
- 3.2.4 Using two EVALSTGAP1AS boards in daisy chain configuration
- 4 Revision history
through a true galvanic isolation. order to exploit the ability of the STGAP1AS to handle very high power applications. available thanks to the driver's status registers that can be accessed through the SPI. Figure 1. EVALSTGAP1AS demonstration board
1 Hardware description and configuration
refer to Section 3.1: Using EVALSTGAP1AS in standalone mode on page 10. Table 1. STGAP1AS electrical specifications
- When UVLO is enabled this value is VH on_max.
- This value is limited by maxi mum gate-source voltage of Q1.
- When UVLO is enabled this value is VL on_max.
VDD Integrated 3.3 V voltage regulator input voltage vs.
- When JP6 = OPEN (VDD is not connected to VREG pin, refer to STGAP1AS DS).
- When JP6 = CLOSED (VDD is connected to VREG pin, refer to STGAP1AS DS).
- This value is limited by t he voltage rating of Q1 and D5.
Table 2. Connector descriptions J1 Board extension connector Used to connec t an optional slave EVALSTGAP1AS board. voltage VL to the gate driving side. J3 Control signals connector Used for control (logic inputs and fault signals interfacing). Used for the STGAP1AS SPI and diagnostic interfacing. STEVAL-PCC009V2 universal interface board. J6 Power supply connector Used to feed supply voltage VDD to the logic control side. C plate Load connection A plate hole for the load current input path (IGBT collector). E plate Load connection A plate hole for the load current output path (IGBT emitter).
Table 3. Jumper descriptions JP1, JP2 Configuration jumpers IN- and IN+ sharing in 2 -board configuration. JP3 Configuration jumper For SPI daisy chaining in 2-board configuration. JP6 Configuration jumper To connect VDD a nd Vreg when working with VDD = 3.3 V. JP7 Configuration jumper To bypass shunt resistors when SENSE is not used. Table 4. Jumper configurations for VDD power supply(1)
- Input signals logic leve ls shall be coherent with VDD voltage (3.3\\5 V).
Table 5. Jumper configurations for VL power supply Table 6. Jumper configurations for SPI and input signals settings Table 7. Jumper configurations for SENSE
- This configuration is preferred (but not mandator y) to avoid dissipating power on shunt resistors.
2 Connection of two EVALSTGAP1AS boards
through the daisy chain connection of the SPI bus. Figure 4. Relevant jumper and connector locations for 2-board configuration interleaved configuration of power switches Q1m and Q1s. shall be properly set (see Table 4). A setting of the JP4slave is not relevant. Table 8. Jumper configurations for SPI settings using two EVALSTGAP1AS boards
independently present on the J4master for interfacing with the µC and diagnostic purposes. driving both drivers with only two µC lines as shown in Figure 5. Figure 5. Half bridge configuration with hardware shoot-through protection JP1 and JP2 jumpers shall be properly set (see Table 9). Table 9. Jumper configurations for input signal settings
Figure 8. Half bridge with independent input signal configurations
3 Getting started
3.1 Using EVALSTGAP1AS in standalone mode
The STGAP1AS device can work also without SPI programming using the device default values.
3.1.1 Check list
EVALSTGAP1AS board Two power supplies (VDD and VH supply voltage) Power supply for negative gate driving voltage VL is optional PWM function generator
3.1.2 EVALSTGAP1AS board setup example
- VDD = 3.3 V or 5 V from external power supply (J6 connector) 2. VH from external power supply (J2 connector) 3. VL = GNDISO (JP5 closed) 4. PWM input signals can be applied to J3 connector (IN-, IN+) If you have only one PWM signal available: – To have gate output in phase with input command: PWM on IN+ and IN- = GND – To have gate output out of phase with input command: PWM on IN- and IN+ = VDD
3.1.3 EVALSTGAP1AS board in standalone mode
- Connect the power supply to the EVALSTGA P1AS VDD (J6 connector) and turn it on. The DIAG1 LED (DL2) on the EVALSTGAP1AS is turned on. The status of the DIAG2 depends on the voltage level forced on the IN- pin. 2. Connect the power supply to the EVALSTGAP1AS VH (J2 connector) and turn it on. 3. Set the SD pin low for at least 105 µs to clear the fault (J3 connector). 4. Set the SD pin to the 'High' logic level (which depends on VDD value): the DIAG1 LED (DL2) is switched off. 5. The device outputs will now follow the in put signals coming from IN+ and IN-.
3.1.4 EVALSTGAP1AS default parameters
IN-/DIAG2 configured as input Active Miller clamp enabled Desaturation detection enabled: VDESATth = 7 V and IDESAT = 250 µA VDD OVLO function enabled Thermal shutdown protection enabled The DIAG1 pin reports the following faults event: – DESAT events – VDD supply failures –M i s s i n g V H – Thermal shutdown – Register error R and L All others features are disabled
3.2 Using EVALSTGAP1AS wi th STEVAL-PCC009V2 and
STGAP1AS evaluation software Using the EVALSTGAP1AS board in connection with the 'STGAP1AS evaluation software' and the STEVAL-PCC009V2 interface board it is possible to evaluate the device functionalities and driving two EVALSTGAP1AS boards implementing independent, half bridge, or interleaved configuration of power switches. The software allows saving the device parameters configuration in a dedicated file that can be reloaded whenever it is necessary, for example after the board power-on. The 'Save' and 'Load' buttons on the bottom-left side of the STGAP1AS configuration panel (Figure 10) have these functions.
3.2.1 Check list
Microsoft® Windows® 7 or Windows® XP PC with a free USB port EVALSTGAP1AS board STEVAL-PCC009V2 interface board STGAP1AS evaluation software (the right version for your OS) Power supply PWM function generator 10-pin flat cable and USB - MiniUSB cable
3.2.2 Single EVALSTGAP1AS board setup example
- VDD = 3.3 V from the STEVAL-PCC009V2: closing JP4 and JP6 2. VH from external power supply (J2 connector) 3. VL = GNDISO (JP5 closed) 4. PWM input signals can be applied to the J3 connector (IN-, IN+)
If you have only one PWM signal available: – To have gate output in phase with input command: PWM on IN+ and IN- = GND – To have gate output out of phase with input command: PWM on IN- and IN+ = VDD
3.2.3 Connection to STEVAL-PCC009V2 interface board
The EVALSTGAP1AS shall be connected to the interface board and the following steps performed: 1. Connect the interface board to the PC through the USB cable: the red LED (POWER - D2) turns on 2. Connect the interface board 10-pin connector to the EVALSTGAP1AS J4 connector through the 10-pin flat cable The DIAG1 red LED (DL2) on the EVALSTGAP1AS turns-on 3. Connect the power supply to VH of the EVALSTGAP1AS (J2 connector) and turn it on 4. Start the EVALSTGAP1AS evaluation software 5. Click the icon 'Connect' on the top left side of the GUI window to establish a connection between the EVALSTGAP1AS and interface boards (see Figure 9) The DIAG1 LED (DL2) on the EVALSTGAP1AS is switched off 6. Press the 'Refresh' button and verify all fault lights are off. If OK jump to the next point, otherwise two options are available to clear the faults and make the device operative: a) Perform a double transition on SD (high => low => high) clicking on the SD button b) Perform a status reset clicking on the 'Reset' button and after set the SD button to 'High' 7. Set the SD button to 'High' 8. Connect IN- to GND and ap plying the PWM on IN+, the device outputs will follow the input signal In order to read the device status, use the 'Refresh' button to update the status indicators according to driver's status registers. To customize the device parameters and functions open the 'STGAP1AS configuration' panel pushing the relative toolbar icon (refer to Figure 9).
Figure 9. STGAP1AS evaluation software screenshot functionalities and set the device parameters.
Figure 10. STGAP1AS configuration panel the STGAP1AS configuration panel) as in the default settings.
3.2.4 Using two EVALSTGAP1AS boards in daisy chain configuration
Figure 11. How to drive two EVALSTGAP1AS boards with STGAP1AS evaluation software
Figure 12. How to set the same parameters in both devices
4 Revision history
Table 10. Document revision history 03-Nov-2016 1 Initial release.