UM1653 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 STM32 NAND driver blocks
- 1.1 STM32 USB peripheral
- 1.2 USB mass storage
- 1.3 FSMC
- 1.4 NAND architecture
- 1.5 NAND pin mapping
- 2 NAND driver firmware modules
- 2.1 Garbage collection
- 2.2 Wear leveling
- 2.3 ECC
- 2.3.1 Hamming code for NAND Flash
- 2.3.2 Error detection and correction
- 2.4 Bad block management
- 2.5 Look up table (LUT)
- 2.6 File system
- 2.7 NAND driver files
- 2.8 Supported NAND Flash
- 3 NAND evaluation board
- 3.1 Working with evaluation boards
- 3.1.1 Running in USB Mass Storage mode (STEVAL-CCM006/7/8V1)
- 3.1.2 Running in Standalone mode (STEVAL- CCM006/7/8V2)
- 3.2 Schematics
- 3.3 NAND evaluation board images
- 4 Revision history
STM32 Advanced NAND Flash Driver for SLC NAND Introduction The NAND driver library for STM32 is a generic library from which STM32 can access NAND with advanced features like garbage collection, wear leveling, bad block management, ECC checking etc. The NAND Flash driver supports dynamic NAND Flash detection based on the Device ID. The driver automatically detects the mounted SLC NAND Flash and works accordingly (described in more detail in Section 2.8). This solution runs on the STM32F1, STM32F2 & STM32F4 series of microcontrollers using the FSMC interface. The board can run in two modes: USB Mass Storage mode and Standalone mode. In USB Mass Storage mode, the NAND Flash works as USB mass storage media. In Standalone mode, the .bmp images stored in the ‘pics’ folder of the root directory are read using FatFS file system, and displayed on the onboard TFT LCD. Six evaluation boards are available for this SLC NAND FLASH Driver: STEVAL_CCM006V1: USB mass storage mode demo using STM32F103ZET6 STEVAL_CCM006V2: Standalone mode demo using STM32F103ZET6 STEVAL_CCM007V1: USB Mass Storage mode Demo using STM32F205ZET6 STEVAL_CCM007V2: Standalone mode Demo using STM32F205ZET6 STEVAL_CCM008V1: USB Mass Storage mode Demo using STM32F405ZGT6 STEVAL_CCM008V2: Standalone mode Demo using STM32F405ZGT6 NAND is a non-volatile Flash memory device where address lines are multiplexed with data input/output and commands input. The NAND driver library has the following features: 1. Supports both FAT file system and USB MSC device. 2. Supports SLC NAND with page size of 512 Bytes & 2 KBytes. 3. Garbage collection. 4. Wear leveling. 5. Bad block management. 6. ECC check. This document applies to the following microcontrollers: STM32L151xD, STM32L152xD, STM32L1562xD. STM32F405/415, STM32F407/417, STM32F427/437, STM32F429/439 lines. STM32F2 Series. STM32F103xC, STM32F103xD and STM32F103xE, STM32F103xF, STM32F103xG, STM32F101xC, STM32F101xD and STM32F101xE, STM32F101xF, STM32F101xG, STM32F100xC, STM32F100xD, STM32F100xE.
1 STM32 NAND driver blocks
both FAT file system and USB MSC device. Figure 1. Application architecture
1.1 STM32 USB peripheral
The STM32F embeds a USB peripheral that supports USB full-speed and high speed. The development of Endpoint and support suspend / resume are configured by software.
1.2 USB mass storage
cross reacts with the embedded system. defines that SCSI commands will be used with the protocol “bulk-only transport” (BOT). data transfer a CSW is returned with the remaining data length and the STATUS field. ZERO DATA: no data stage is needed so CSW block is sent immediately after CBW.
- Send the command block CBW.
- Return the status of the block CSW.
Figure 2. BOT protocol architecture
STM32 NAND driver blocks UM1653 Bulk-Only Transport State machine #define BOT_IDLE 0 //Idle state #define BOT_DATA_OUT 1 //Data Out state #define BOT_DATA_IN 2 //Data In state #define BOT_DATA_IN_LAST 3 //Last Data In Last #define BOT_CSW_Send 4 //Command Status Wrapper #define BOT_ERROR 5 //error state #define BOT_CBW_SIGNATURE 0x43425355 //1st 4 bytes of CBW pkt #define BOT_CSW_SIGNATURE 0x53425355 //1st 4 bytes of CSW pkt #define BOT_CBW_PACKET_LENGTH 31 #define CSW_DATA_LENGTH 13 CSW Status Definitions #define CSW_CMD_PASSED 0x00 #define CSW_CMD_FAILED 0x01 #define CSW_PHASE_ERROR 0x02 #define SEND_CSW_DISABLE 0 #define SEND_CSW_ENABLE 1 #define DIR_IN 0 #define DIR_OUT 1 #define BOTH_DIR 2
1.3 FSMC
The FSMC block is able to communicate with the synchronous and asynchronous memory. Its main purpose is to: Translate the AHB protocol transactions of external devices Respect the access time of external devices The FSMC provides a single access to an external device. The FSMC has four blocks: AHB Interface Controller NOR Flash / PSRAM Controller NAND Flash / PC Card Interface to external device The FSMC generates the appropriate signals to drive the NAND Flash memory. The FSMC controller consists of two blocks of code error correction hardware. They reduce the workload on the host processor when processing code error correction by the system software. These two blocks are identical and are respectively associated with banks 2 and 3. The ECC algorithm used in the FSMC can perform 1- and 2-bit error detection.
1.4 NAND architecture
input/output as well as with commands input. the pages in the block to logical 1. The small NAND Flash contains 528-byte pages (512 data area and 16 byte spare area). The page size for 2K NAND is 2112 (2048 data and 64 spare area). The page size for 4K NAND is 4224 (4096 data and 128 spare area). The page size for 8K NAND is 8448 (8192 data and 256 spare area). Figure 3. NAND block architecture Table 1. Spare area format for small NAND Flash Table 2. Spare area format for large NAND Flash
512 Physical page (unit)
STM32 NAND driver blocks UM1653 The Logical Index contains the logical address of the block. The Block Status returns the status of the block if it is valid or not. The Data Status informs if the page is valid or invalid. Wear Leveling Counter is the number of times the block has been erased. The ECC is the error correction code calculated for each page. NAND INTERFACE x8 or x16 bus width Multiplexed Address/ Data Pinout compatibility for all densities SUPPLY VOLTAGE 1.8V device: VCC = 1.65 to 1.95V 3.0V device: VCC = 2.7 to 3.6V PAGE SIZE x8 device: (512 + 16 spare) Bytes x16 device: (256 + 8 spare) Words x8 device: (2048 + 64 spare) Bytes x16 device: (1024 + 32 spare) Words
1.5 NAND pin mapping
I/O 8-15 Data Input/Outputs: for x16 devices. The I/O pins are used to input data, address, command and output data during read operation. I/O 0-7 Data Input/Outputs: Address Inputs, or Command Inputs for x8 and x16 devices. ALE Address Latch Enable: When active, an address can be written. CLE Command Latch Enable: This pin shou ld be LOW while writing commands to the command register. CE/ Chip Enable: The CE input enables the devi ce. Signal is active low. If the signal is inactive the device will be in standby. RE/ Read Enable: The RE input is the serial data out control. Signal is active low to out data. RB/ Ready/Busy (open-drain output) The RB output provides the status of the device operation. It is an open drain output, hence should be connected to a GPIO with pull-up. LOW: a program, erase or read operation is in process. HIGH: the process is complete. WE/ Write Enable: The WE input controls write operations to I/O port. Commands, data and address are latched on the rising edge of WE. WP/ Write Protect: Typically connected to Vc c, but may also be connected to a GPIO.
UM1653 NAND driver firmware modules
2 NAND driver firmware modules
The NAND driver library has the following modules: 1. Garbage collection 2. Wear leveling 3. Bad block management 4. ECC check 5. LUT 6. FAT file system
2.1 Garbage collection
The Garbage Collection software copies the valid data into a new (free) area and erases the original invalid data. Garbage Collection is performed when a virtual block is full or the number of free pages in the whole device is lower than a specified threshold value. The basic operations involved in Garbage Collection are the following: 1. The virtual blocks meeting the conditions are selected for erasure. 2. The valid physical pages are copied into a free area. 3. The selected physical blocks are erased. As virtual blocks can contain more than one physical block, the Garbage Collection may erase more than one physical block.
2.2 Wear leveling
Wear leveling is a technique to increase the lifetime of NAND Flash memory. The number of reliable write cycles in NAND Flash is 100,000 erase/write cycles. If some of the blocks are written repeatedly, wearing of these blocks will happen earlier than other blocks. To balance the erase cycles over all the blocks, a wear leveling technique is introduced. All new data is written to the empty blocks. The memory controller selects the new empty block based on the number of write / erase cycles it has experienced. After the new data is written, the controller updates the LUT to point to the position of the selected physical block. The block containing the old data is erased and the number of write/erase cycles increments.
Figure 4. Flow of wear leveling mechanism for STEVAL-CCM006V1
Figure 5. Flow of wear leveling mechanism for STEVAL-CCM007V1/ 008V1 Leveling Mechanism is implemented. address of the block in NAND Flash memory which comes out to be sequential.
NAND driver firmware modules UM1653 NAND_ADDRESS NAND_GetAddress (uint32_t Address) The above function translates a logical address into a physical one and stores it in a structure element of type NAND_ADDRESS. While writing to the NAND, the wear level algorithm should return the block to be written of which the erase count is least. To maintain the list of USED, FREE and BAD blocks an array is maintained: LUT[ ]. The previously fetched address for writing, and the free block obtained with least erase counts are swapped in LUT and updated, this ensures that the write takes place at the block with least erase count. uint16_t NAND_GetFreeBlock (void) The above function is called to get the free block for swap. The function returns the first free block it finds in the LUT[ ]. This implies that the LUT[ ] should have the free blocks arranged in the increasing order of erase count. The LUT[ ] is updated by the following function. uint16_t NAND_BuildLUT (uint8_t ZoneNbr) The above function arranges the bad block at the bottom of the array and the used and free blocks are located in the upper part of the array. uint16_t NAND_WearLeveling (void) The above function sorts the free blocks in the ascending order based on the wear level count. Now, the free block used for writing in the NAND would be the one with the least erase count.
2.3 ECC
Unlike NOR Flash memory that does not require error correction code, NAND memory needs to ensure data integrity. The disadvantage of the NAND configuration is that when a cell is read, the sense amplifier detects a signal much lower than for the NOR configuration because many transistors are in series. Therefore access to a cell is not straightforward and must necessarily go through all the cells in series which reduces precision and makes code error correction required. There are three error correction codes: The Hamming code can correct only one bit error. The Reed Solomon code can correct more errors. The BCH code can correct many errors and is more efficient than Reed Solomon.
2.3.1 Hamming code for NAND Flash
The Hamming code algorithm used by NAND Flash-based applications calculates two values of ECC for a data packet. Each bit in the values of ECC parity represents half of the bits of the data packet.
Figure 6. Example of decomposition of a data packet values of ECC. The results are concatenated to form the ECC values. ECC requires a value of n bits. calculated ECC differ from those programmed into the NAND Flash. allows the detection of two errors and the correction of only one bit. The erroneous bit position is identified by the position of the 1 in the "exclusive or" value. As the size of data packets increases, the Hamming algorithm becomes more efficient. partitions, the algorithm remains the same.
2.3.2 Error detection and correction
Figure 7. Flow chart for error detection and correction
2.4 Bad block management
present when the device is shipped, or may develop during the lifetime of the device. Figure 8. Flow chart for bad block management
2.5 Look up table (LUT)
block of NAND Flash to build the LUT.
2.6 File system
NAND Flash. This module should be ported to the selected file system. Table 3. File system interface functions disk_initialize Initialize disk drive. disk_read Interface function for a logical page read. disk_write Interface function for a logical page write. disk_status Interface function for testing if unit is ready. disk_ioctl Control device-dependent features.
Figure 9. Flow chart for File System
2.7 NAND driver files
Table 4. NAND_Init – NAND_OK: when the NAND is OK. – NAND_FAIL: when NAND fails to initialize. Table 5. NAND_Write Memory_Offset: Memory Offset. Writebuff: Pointer to the data to be written. Transfer_Length: Number of byte to write. – NAND_FAIL: when NAND fails to Write. Table 6. NAND_Read Behavior description Reads sectors. Memory_Offset: Memory Offset. Readbuff: Pointer to store the read data. Transfer_Length: Number of byte to read. – NAND_OK: when the NAND Read is successful. – NAND_FAIL: when NAND fails to Read.
Table 7. NAND_WriteECC Function name NAND_WriteECC. Behavior description Writes one sector & copy rest Block during ECC Correctable Error Case. Memory_Offset: Memory Offset. Writebuff: Pointer to the data to be written. Transfer_Length: Number of byte to write. Table 8. NAND_PostWriteECC Function name NAND_PostWriteECC. Behavior description Copies whole block after writing corrected page in ECC Correction. Output parameter Status of NAND Write. Table 9. NAND_CleanLUT Function name NAND_CleanLUT. Behavior description Rebuilds the Look Up Table. Input parameter ZoneNbr: Zone Number to Rebuild the Look Up Table. – NAND_OK: when the NAND Clean is successful. – NAND_FAIL: when NAND fails to clean look up table. Table 10. NAND_WearLeveling Function name NAND_WearLeveling. Behavior description Builds the Look Up Table According to the Wear Count. Input parameter ZoneNumber: Zone Number. – NAND_OK: when the NAND wear leveling is successful. – NAND_FAIL: when NAND fails to wear leveling.
Table 11. SBLK_NAND_WearLeveling Function name SBLK_NAND_WearLeveling. Behavior description Builds the Look Up Table According to the Wear Count. Input parameter ZoneNumber: Zone Number. – NAND_FAIL: when NAND fails to wear leveling. Table 12. LBLK_NAND_WearLeveling Function name LBLK_NAND_WearLeveling. Behavior description Builds the Look Up Table According to the Wear Count. Input parameter ZoneNumber: Zone Number. – NAND_FAIL: when NAND fails to wear leveling. Table 13. NAND_GetFreeBlock Function name NAND_GetFreeBlock. Behavior description Looks for a free Block for data exchange from Look Up Table. Output parameter Logical Block Number of free Block. Table 14. SBLK_NAND_ReadSpareArea Function name SBLK_NAND_ReadSpareArea. Behavior description Page Number in multiple of 512 Byte per Page. Input parameter address: Corresponding Page Number of Spare Area to be read. Output parameter SPARE AREA after reading. Table 15. LBLK_NAND_ReadSpareArea Function name LBLK_NAND_ReadSpareArea. Behavior description Page Number in multiple of 512 Byte per Page. Input parameter address: Corresponding Page Number of Spare Area to be read. Output parameter LBLK_ SPARE_AREA after reading.
Table 16. WriteSpareArea Function name WriteSpareArea. Behavior description Page Number in multiple of 512 Byte. Input parameter address: Corresponding Page Number of Spare Area to be read. buff: Pointer to the data to be written in SPARE AREA. – NAND_OK: when Write SPARE AREA is successful. – NAND_FAIL: when Write SPARE AREA fails to Write. Table 17. NAND_Copy Behavior description Copies pages from source to destination. Address_Src: Source Address. Address_Dest: Destination Address. PageToCopy: Number of Page to copy. – NAND_FAIL: when NAND fails to copy. Table 18. NAND_CopyBack Function name NAND_CopyBack. must have same page number). Address_Src: Source Address. Address_Dest: Destination Address. – NAND_FAIL: when NAND fails to copy.
Table 19. NAND_Format Behavior description Format the entire NAND Flash. – NAND_FAIL: when NAND fails to Format. Table 20. NAND_PostWrite Function name NAND_PostWrite. Behavior description NAND Post Write. – NAND_FAIL: when NAND fails to Post Write. Table 21. SBLK_NAND_PostWrite Function name SBLK_NAND_PostWrite. Behavior description Small Block NAND_PostWrite. Table 22. LBLK_NAND_PostWrite Function name LBLK_NAND_PostWrite. Behavior description Large Block NAND Post Write.
Table 23. NAND_GarbageCollection Function name NAND_GarbageCollection. Behavior description Erases Blocks ever y time the write operation is stopped. – NAND_FAIL: when NAND fails to Garbage collection. Table 24. NAND_UpdateWearLevelCounter Function name NAND_UpdateWearLevelCounter. Behavior description Increments the value of Wear Level counter after every erase. Input parameter Address: Logical Address. – NAND_FAIL: when NAND fails to Update Wear Level. Table 25. NAND_ConvertPhyAddress Function name NAND_ConvertPhyAddress. Behavior description Converts Memory Offset into Physical Address. Input parameter Address: Memory Offset in Multiple of 512B(0,512/512,1024/512...). Output parameter Physical Address. Table 26. NAND_BuildLUT Function name NAND_BuildLUT. Behavior description Builds the Look Up Table. Input parameter ZoneNbr: The Zone Number. – NAND_FAIL: when NAND fails to Build Look Up Table.
Table 27. SBLK_NAND_BuildLUT Function name SBLK_NAND_BuildLUT. Behavior description Builds the Look Up Table. Input parameter ZoneNbr: The Zone Number. – NAND_FAIL: when NAND fails to Build Look Up Table. Table 28. LBLK_NAND_BuildLUT Function name LBLK_NAND_BuildLUT. Behavior description Builds the Look Up Table. Input parameter ZoneNbr: The Zone Number. – NAND_FAIL: when NAND fails to Build Look Up Table. Table 29. GetParity Behavior description Calculate parity. Input parameter in_value: 16-bit value. Table 30. Swap Behavior description Swaps a 16-bit. Input parameter in: 16-bit value. Output parameter swapped value.
Table 31. WritePage Behavior description Writes a page & Corresponding SPARE AREA. Address: The address of the page to write. *buff: The buffer to write in. len: The Number of page to write. Table 32. SBLK_NAND_WritePage Function name SBLK_NAND_WritePage. Behavior description Writes page & Corresponding ECC in SPARE AREA in Small Block NAND. Address: The address of the page to write. *buff: The buffer to write in. len: The Number of page to write. Table 33. LBLK_NAND_WritePage Function name LBLK_NAND_WritePage. Address: The address of the page to write. *buff: The buffer to write in. len: The Number of page to write.
Table 34. ReadPage Behavior description Reads a page consideri ng Error correction code(1 bit per 512 Byte). Address: The address of the page to read. *buff: The buffer to read from. len: The number of page to read. Table 35. SBLK_NAND_ReadPage Function name SBLK_NAND_ReadPage. Address: The address of the page to read. *buff: The buffer to read from. len: The number of page to read. Table 36. LBLK_NAND_ReadPage Function name LBLK_NAND_ReadPage. Address: The address of the page to read. *buff: The buffer to read from. len: The number of page to read. Table 37. BitCount Behavior description Counts the number of 1's in 32 bit Number. Input parameter num: The number in which number of 1's to be counted. Output parameter The number of one in 32 bit number.
Table 38. FSMC_SelectNANDType Function name FSMC_SelectNANDType. may be SBLK_NAND or LBLK_NAND. Table 39. FSMC_NAND_NON_ONFI_Compliance Function name FSMC_NAND_NON_ONFI_Compliance. accordingly. NAND may be SBLK_NAND or LBLK_NAND. Table 40. FSMC_NAND_Init Function name FSMC_NAND_Init. function must be called before any write/read operation. Table 41. FSMC_NAND_ReadID Behavior description Reads NAND memory's Manufacturer and Device ID.
Table 42. FSMC_NAND_WriteSmallPage Function name FSMC_NAND_WriteSmallPage. Behavior description Writes one or several 512 Bytes Page size. pBuffer: pointer on the Buffer containing data to be written. Address: First page address. NumPageToWrite: Number of page to write. – NAND_VALID_ADDRESS: When the new address is valid. – NAND_INVALID_ADDRESS: When the new address is invalid. Table 43. FSMC_NAND_ReadSmallPage Function name FSMC_NAND_ReadSmallPage. Behavior description Sequential read from one or several 512 Bytes Page size. pBuffer: pointer on the Buffer to fill. Address: First page address. NumPageToRead: Number of page to read. – NAND_READY: when memory is ready for the next operation. – NAND_VALID_ADDRESS: When the new address is valid. – NAND_INVALID_ADDRESS: When the new address is invalid.
Table 44. FSMC_NAND_WriteSpareArea Function name FSMC_NAND_WriteSpareArea. Behavior description Writes spare area information for specified page addresses. pBuffer: pointer on the Buffer containing data to be written. Address: First page address. NumSpareAreaTowrite: Number of Spare Area to write. – NAND_VALID_ADDRESS: When the new address is valid. – NAND_INVALID_ADDRESS: When the new address is invalid. Table 45. FSMC_NAND_ReadSpareArea Function name FSMC_NAND_ReadSpareArea. Behavior description Reads the spare area info rmation from the specified page addresses. pBuffer: pointer on the Buffer to fill. Address: First page address. NumSpareAreaToRead: Number of Spare Area to read. – NAND_VALID_ADDRESS: When the new address is valid. – NAND_INVALID_ADDRESS: When the new address is invalid. Table 46. FSMC_NAND_EraseBlock Function name FSMC_NAND_EraseBlock. Behavior description Erases complete block from NAND FLASH. Input parameter Address: Any address into block to be erased. – NAND_READY: when memory is ready for the next operation.
Table 47. FSMC_NAND_Reset Function name FSMC_NAND_Reset. Behavior description Resets the NAND FLASH. Output parameter NAND_READY. Table 48. FSMC_NAND_GetStatus Function name FSMC_NAND_GetStatus. Behavior description Gets the NAND operation status. – NAND_READY: when memory is ready for the next operation. Table 49. FSMC_SBLK_NAND_CopyBack Function name FSMC_SBLK_NAND_CopyBack. Input parameter src: Source Address. – NAND_BUSY: when memory is busy. – NAND_READY: when memory is ready for the next operation. – NAND_ERROR: when the previous operation generates error.
Table 50. FSMC_LBLK_NAND_CopyBack Function name FSMC_LBLK_NAND_CopyBack. Input parameter src: Source Address. – NAND_BUSY: when memory is busy. – NAND_READY: when memory is ready for the next operation. – NAND_ERROR: when the previous operation generates error. Table 51. FSMC_NAND_ReadStatus Function name FSMC_NAND_ReadStatus. Behavior description Reads the NAND memory status using the Read status command. – NAND_BUSY: when memory is busy. – NAND_READY: when memory is ready for the next operation. – NAND_ERROR: when the previous operation generates Error. Table 52. FSMC_NAND_AddressIncrement Function name FSMC_NAND_AddressIncrement. Behavior description Increments the NAND memory address. Input parameter Address: address to increment. – NAND_VALID_ADDRESS: When the new address is valid address. – NAND_INVALID_ADDRESS: When the new address is invalid address. Table 53. FSMC_NAND_ONFI_Compliance Function name FSMC_NAND_ONFI_Compliance. Behavior description Selects the ONFI NAND Type & sets the Required Parameter accordingly. NAND may be SBLK_NAND or LBLK_NAND.
Table 54. FSMC_SBLK_NAND_SendAddress Function name FSMC_SBLK_NAND_SendAddress. Behavior description Sends the address for Small Block NAND. Input parameter Addr: NAND_ADRESS to be sent. Table 55. FSMC_LBLK_NAND_SendAddress Function name FSMC_LBLK_NAND_SendAddress. Behavior description Sends the row & column address for Large Block NAND. Input parameter row: Row Address.
2.8 Supported NAND Flash
Below is the list of supported NAND Flash in our firmware. change to hardware or firmware. Table 56. Supported NAND Flash
1 NAND128R3A 128 Mbits Y
2 NAND128W3A 128 Mbits Y
3 NAND256R3A 256 Mbits Y
4 NAND256W3A 256 Mbits Y
5 NAND512R3A 512 Mbits Y
6 NAND512W3A 512 Mbits Y
7 NAND01GR3A 1 Gbits Y
8 NAND01GW3A 1 Gbits Y
9 K9F5608U0A 256 MBits Y
1 NAND512R3B 512 Mbits N
2 NAND512W3B 512 Mbits N
3 NAND01GR3B 1 Gbits Y
4 NAND01GW3B 1 Gbits Y
5 NAND02GR3B 2 Gbits N
6 NAND02GW3B 2 Gbits N
7 NAND04GR3B 4 Gbits N
8 NAND04GW3B 4 Gbits N
9 NAND08GR3B 8 Gbits N
10 NAND08GW3B 8 Gbits N
11 H27U4G8F2DTR 1 Gbits Y
Table 57. NAND Flash driver file code size
3 NAND evaluation board
3.1 Working with evaluation boards
folder of root directory are displayed using the File System on the mounted TFT. components and sections on the board. Figure 10. Evaluation board: top side
Figure 11. Evaluation board: bottom side STEVAL-CCM008V1 and STEVAL-CCM008V2.
3.1.1 Running in USB Mass Stor age mode (STEVAL-CCM006/7/8V1)
board using proper firmware using available tool chain.
- Connect the mini-USB cable between a jumper on the PCB and the Host (PC)
- The device is detected as a USB mass stor age device in Device Manager of Host (PC).
- The device appears as a Removable Drive on the Host (PC).
- This drive can be used as Mass Storage Media.
3.1.2 Running in Standalone mode (STEVAL-CCM006/7/8V2)
- By default TFT is mounted on J6.
- Connect mini-USB cable between J4 on the PCB and the Host (PC).
- The bmp images stored in the "pics" folder of root directory are displayed on the TFT.
Figure 12. Demo running in Standalone mode
3.2 Schematics
Figure 13. Microcontroller schematic Figure 14. USB Full Speed schematic
0 Ohm0
0 Ohm
Figure 19. NAND Flash schematic
22 Ohm
3.3 NAND evaluation board images
Figure 22. Top side of PCB Figure 23. Bottom side of PCB
4 Revision history
Table 58. Document revision history 28-Nov-2013 1 Initial release.