UM12043

NXP Semiconductors

IMX91LP4EVK-11 Board User Manual Rev. 1.0 15 November 2024

Manufacturer: NXP Semiconductors

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Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 38

Technical content

Datasheet sections

1 IMX91LP4EVK-11 overview
1.1 Block diagram
1.2 Board kit contents
1.3 Board pictures
1.4 Board features
1.5 Connectors
1.6 User LEDs
1.7 Push buttons
1.8 DIP switches
2 Functional description
2.1 Processor
2.2 Power supply
2.2.1 Power monitoring
2.2.2 Power measurement board connector
2.3 Clocks
2.4 I2C interface
2.5 Boot mode and boot device configuration
2.6 Audio interface
2.7 LPDDR44 DRAM memory
2.8 SD card interface
2.11 QSPI NOR/NAND Flash
2.12 CAN interface
2.13 USB interface
2.14 Ethernet
2.14.1 LED and LDO configuration
2.15 EXPI
3 Debug support
3.1 USB debug interface
3.2 JTAG interface
4 PCB information
5 Acronyms and abbreviations
6 Related documentation
7 Revision history

IMX91LP4EVK-11 Board User Manual Rev. 1.0 — 15 November 2024 User manual Document information Information Content Keywords UM12043, i.MX91 applications processor, IMX91LP4EVK-11 board, 91LP4EVK-11SOM (SOM board), 91LP4EVK-11BB (Base board) Abstract The i.MX 91 evaluation kit (IMX91LP4EVK-11 board) is a hardware platform designed to display the commonly used features of the i.MX 91 applications processor in a small and low-cost package.

1 IMX91LP4EVK-11 overview

before investing a large amount of resources in more specific designs.

91LP4EVK-11SOM: referred to as the "SOM board" in this document.
91LP4EVK-11BB: referred to as the "Base board" in this document. This document includes system setup and configurations, and provides detailed information on the overall design and usage of the IMX91LP4EVK-11 board from a hardware system perspective.

1.1 Block diagram

Figure 1 shows the IMX91LP4EVK-11 block diagram.

16 GB HS400

1.2 Board kit contents

Table 1 lists the items included in the IMX91LP4EVK-11 board kit. Table 1. Board kit contents UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

1.3 Board pictures

Figure 2 shows the onboard connectors on the IMX91LP4EVK-11 board. Figure 2. IMX91LP4EVK-11 onboard connectors Figure 3 shows the onboard jumpers, switches, buttons, and LEDs available on the IMX91LP4EVK-11 board. UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

NXP Semiconductors UM12043 IMX91LP4EVK-11 Board User Manual

1.4 Board features

Table 2 lists the features of IMX91LP4EVK-11. Board feature Target processor feature used

Description

Applications

The i.MX 91 applications processor features an Arm Cortex-A55 core that can operate at speeds of up to 1.4 GHz. Note: For more details on the i.MX 91 processor, refer to the i.MX 91 Applications Processor Reference Manual and datasheet. See Section 6 "Related documentation" USB interface USB 2.0 high-speed host and device controller Two USB 2.0 Type C connectors DRAM memory DRAM controller and PHY 2 GB LPDDR4 (Micron MT53E1G16D1ZW-046 AAT:C) Mass storage uSDHC • 16 GB eMMC5.1 (SanDisk SDINBDA6-16G-I(3D TLC))

MicroSD card connector (SD3.0 supported) Boot configuration • Default boot mode is single boot from the eMMC device
The board supports three other boot devices listed below: – QSPI NOR Flash (M2-NOR-Flash) – QSPI NAND Flash (M2-NAND-Flash) – SD card (MicroSD connector) Ethernet interface Two Ethernet controllers • 10/100/1000 Mbit/s RGMII Ethernet supporting TSN connected with external PHY, RTL8211 through an RJ45 connector (J501)
10/100/1000 Mbit/s RGMII Ethernet connected with external PHY, RTL8211, through an RJ45 connector (J601) CAN interface CAN One high-speed CAN transceiver NXP TJA1057GT/3 (U1101) and a 4-pin CAN FD connector (J1101) Wi-Fi/Bluetooth interface USB, SDIO, I2S, UART, I2C, and GPIO
One M.2/NGFF Key E mini card 75-pin connector (J901) supporting SDIO, I2S, UART, I2C, and vendor-defined SPI interfaces
Murata Wi-Fi/Bluetooth module. It is based on NXP IW612/IW610 SoC, which supports dual-band (2.4 GHz /5 GHz) 1x1 Wi-Fi 6, Bluetooth 5.4, and IEEE 802.15.4 SAI/I2S • 3.5 mm audio jack for headset, microphone, headphone output support, J1201
Audio codec WM8962BECSN/R (U1201) can support 24-bit I2S data and 48 kHz sampling rate PDM • Four onboard PDM microphone support
3.5 mm audio jack for headset, microphone, headphone output support, J1301 Audio MQS MQS support Sensors I2C/I3C • LSM6DSOXTR (U1001) Inertial module—a 3D digital accelerometer and gyroscope ADC interface ADC Four-channel ADC support TAMPER Battery backed non-secure module (BBNSM) x2 Tamper function support

NXP Semiconductors UM12043 IMX91LP4EVK-11 Board User Manual Board feature Target processor feature used Debug interface • USB-to-UART/MPSSE ICs device, FT4232H

One USB 2.0 Type-C connector (J1401) of FT4232H provides four COM ports: – The first and second ports are reserved. – The third port is connected to UART1 for Cortex A55 system debugging. – The fourth port is connected to UART2 for general communication.
FT4232H is used for remote debug of JTAG, boot mode, ONOFF, SYS_nRST, and power measurement board communication EXPI 2x20 pin expansion interface J1001 for I2S, parallel display, parallel camera, UART, I2C, and GPIO expansion I2C connector I2C 8-pin dual-row pin header J1005 for I2C expansion I/O expanders • One I/O expander to provide remote I/O expansion for the target processor via the I2C-bus interface
One I/O expander to provide I/O expansion for FT4232H device for boot configuration, ONOFF, POR_B, and SYS_nRST Power supply • One USB 2.0 Type-C connector for power delivery only
PCA9451AHNY PMIC
Discrete DCDC/LDO Power monitoring Six quad-channel power monitors (PAC1934T-I/JQ) for power and energy monitoring (U902, U904, U907, U911, U912 on SOM board and U2014 on Base board) PCB • 91LP4EVK-11SOM: 2.4 inch × 2.9 inch, 6-layer
91LP4EVK-11BB: 5 inch × 7.45 inch, 8-layer Orderable part number IMX91LP4EVK-11

Table 2. IMX91LP4EVK-11 features...continued

1.5 Connectors

Table 3. 91LP4EVK-11BB connectors...continued Table 4 describes the connectors available on the 91LP4EVK-11SOM board. Table 4. 91LP4EVK-11SOM board connectors UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

1.6 User LEDs

reset, board faults. The information collected from LEDs can be used for debugging purposes. Figure 3 shows the LEDs available on the board. Table 5 describes the IMX91LP4EVK-11 LEDs. VDD_5V power supply is ON, and board is powered on.

D1403 ON – The UART data received from host computer. D1405 Green D1406 Orange UART2 • D1405 ON – The UART2 data transmitted to host computer.
D1406 ON – The UART2 data received from host computer. D1410 Red • ON: FT4232H IC power is ON
OFF: FT4232H IC power is OFF D1411 Orange • ON: FT4232H function is suspended
OFF: FT4232H function is running D1412 Red • ON: Local JTAG for debug
OFF: Remote JTAG for debug D1413 Green • ON: Remote JTAG for debug
OFF: Local JTAG for debug D1414 Orange • ON: WDOG_B trigger to PCA9451AHNY PMIC
OFF: Normal D1415 Orange System LED
ON: System Monitor is suspended
OFF: System Monitor is running

1.7 Push buttons

Figure 3 shows the push buttons available on the board. Table 6 describes the push buttons available on IMX91LP4EVK-11.

In the ON state: – If ON/OFF button is held longer than the debounce time, the power off interrupt is generated – If the button is held longer than defined max timeout, the state transits from ON to OFF, and send PMIC_ON_REQ signal to turn off the powers of PMIC.
In the OFF state: – If the ON/OFF button is held longer than the OFF-to-ON time, the state transits from OFF to ON, and send PMIC_ON_REQ signal to turn on the powers of PMIC SW1002 Reset button (RESET) The button is directly connected to the PMIC PCA9451AHNY. Holding the RESET button forces a reset of the PMIC power outputs except NVCC_SNVS_1V8 on the EVK board. The i.MX 91 applications processor is immediately turned off and reinitiates a boot cycle from the OFF state. SW1003, SW1004 User button The User buttons are kept for customized use cases.

1.8 DIP switches

SW1005 is used for RFU_BTN1 and RFU_BTN2 signals path selection. These signals are used as buttons (SW1003, SW1004) interrupts. By default, RFU_BTN1 and RFU_BTN2 signals connect with EXP_GPIO_IO23 and EXP_GPIO_IO24 from EXP GPIO connector (J1001).
SW1006 is used for ENET1_nINT and ENET2_nINT signals, which are used as Ethernet PHY interrupts. By default, the signals connect with EXP_BTN1 and EXP_BTN2 from I2C IO expander (U101).
SW1007 is used for USB_I2C_SDA and USB_I2C_SCL signals, which are USB-related peripherals configuration signals of the USB I2C bus. SW1007 connects these signals with GPIO_IO28 and GPIO_IO29 for I2C3 port by default. Value SW Signal name 4'b0101 4'b1010 RFU_BTN1 EXP_BTN1 EXP_GPIO_IO23 (default) SW1005 RFU_BTN2 EXP_BTN2 EXP_GPIO_IO24 (default) ENT1_nINT GPIO_IO28 EXP_BTN1 (default) SW1006 ENT2_nINT GPIO_IO29 EXP_BTN2 (default) USB_I2C_SDA GPIO_IO28 (default, used as I2 C3_SDA) I2C_SDA_BUF SW1007 USB_I2C_SCL GPIO_IO29 (default, used as I2 C3_SCL) I2C_SCL_BUF

Table 7. IMX91LP4EVK-11 DIP switches See Figure 3 for the DIP switch positions on the board. UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

2 Functional description

information about the processor, boot modes, storage devices, clocks, board interfaces, and debug support.

2.1 Processor

MIMX9131CVVXJAA. (U101). This part is qualified for Industrial applications (-40C to 105C).

Smart home
Building control
Contactless HMI
Commercial
Healthcare
Media IoT The processor provides a 16-bit LPDDR4 memory interface and other interfaces for connecting peripherals, such as WLAN, Bluetooth, USB2.0, uSDHC, Ethernet, CAN, ADC, and multi-sensors. For more detailed information about the processor, see the i.MX 91 data sheet and i.MX 91 Reference Manual at https://www.nxp.com/imx91.

2.2 Power supply

power delivery (PD) connector (J301). provided on the board. Table 8 describes the SW4 configuration. Table 8. Power switch (SW301) configuration

MP8759GD (U201) switches VBUS_IN supply to SYS_5V (5 V) power supply, which is the input power supply for PCA9451AHNY PMIC and other discrete devices on the board. Note: J201 connector is reserved for power input test. When the USB PD charger is not in use, user can provide 15 V power on J201 and short R202 to power up the system (For test purpose only). Figure 5 shows the IMX91LP4EVK-11 power supply block diagram. UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. User manual Rev. 1.0 — 15 November 2024 Document feedback

5 V/3 A

12 V/3 A

3.3 V/4 A

5 V/5 A

8 T7 - 400Load switch

2 DVS 1500VDD_SOC

Figure 5. IMX91LP4EVK-11 power tree Table 9 describes different power sources available on the board.

DCDC_5V
VSYS_5V
5 V at 8 A Supplies power to:
NX20P3483UK USB PD and Type-C switches (U305 and U402)
PMIC PCA9451AHNY
DC buck MP2147GD (U901)
Always-ON LDO for load switch (U905) U901 MP2147GD Monolithic Power Systems Inc. VEXT_3V3 3.3 V at 4 A Supplies power to M.2 / NGFF interface U701 PCA9451AHNY NXP Semiconductors BUCK2: LPD4/ x_VDDQ_0V6 0.6 V at 2 A Not used for i.MX 91, i.MX 91 only supports LPDDR4.

VDD_3V3
3.3 V at 3 A Supplies power to:
Board-to-board connector for 91LP4EVK-11SOM board (J803)
9
NVCC_GPIO, power supply for GPIO when it is in 3.3 V mode
VDD_USB_3P3 pin for USB PHY power
eMMC 5.1 device BUCK5:
VDD_1V8
1.8 V at 2 A Supplies power to:
Board-to-board connector for 91LP4EVK-11SOM (J801)
eMMC 5.1 device
VDD_ANA_1P8, analog core supply voltage
NVCC_WAKEUP, digital I/O supply BUCK6:
LPD4/x_ VDD2_1V1
1.1 V at 1.5 A Supplies power to:
VDD2_DDR, DDR PHY supply voltage LDO1: NVCC_ BBSM_ 1V8
1.8 V at 10 mA NVCC BBSM I/O supply LDO4: VDD_ ANA_0 P8
0.8 V at 200 mA Analog core supply voltage LDO5: NVCC_ SD2
1.8 V/3.3 V MicroSD card Switch: VSD2_3
3.3 V MicroSD card on base board U203 DML3006LFDS-7 (Load switch) Diodes Incorporated VDD_5V 5 V at 10 A • PDM/MQS/CAN interface
EXPI interface U1306 NCP161ASN180 T1G (Load switch) ON Semiconductor VMIC_1V8 1.8 V Supplies to four DMICs

Table 9. IMX91LP4EVK-11 power supply devices...continued

BUCK1 and BUCK3 are configured in dual phase mode.
The PCA9451AHNY BUCK1/3 dual phase default output voltage is 0.85 V.

2.2.1 Power monitoring

VDD_SOC_0V85
BB_VSYS_5V
S1_NVCC_BBSM_1V8 U904 PAC1934T-I/JQ 0x12 • LPD4/x_VDDQ_0V6
S1_VDD_SOC_0V85
NVCC_SD
S1_CPU_VDD2_DDR U907 PAC1934T-I/JQ 0x13 • LPD4/x_VDDQ_0V6
S1_CPU_VDDQ_DDR
LPD4/x_VDD2_1V1
BUCK1_LSW4_CPU_1V8 U911 PAC1934T-I/JQ 0x14 • S1_VSYS_5V
VDD_3V3
VDD_ANA_0V8 U912 PAC1934T-I/JQ 0x15 • VDD_1V8
VDD_ANA_1V8
VSD_3V3 On Base board U204 PAC1934T-I/JQ 0x16 • VEXT_3V3
DCDC_5V_OUT
VBUS_IN

Table 10. Power monitoring devices

2.2.2 Power measurement board connector

rails in different user cases. Refer to Table 11. Table 11 lists the J1404 connector pin definitions.

3 FT_SCL FT4232 I2C clock signal,

4 FT_IO_nINT FT4232 GPIO signal

5 FT_SDA FT4232 I2C data signal,

6 FT_IO_nRST FT4232 GPIO signal

7 FT_EECLK FT4232 EECLK signal,

8 Not connected Not connected

9 FT_EEDATA FT4232 EEDATA signal,

10 FT_EECS FT4232 EECS

Table 11. J1404 pin definitions...continued

2.3 Clocks

summarizes the specifications of each clock and the component that provides it. Table 12. IMX91LP4EVK-11 clocks

2.4 I2C interface

available on the IMX91LP4EVK-11 board. connection. Developers can use the port for specific application development. Table 13 explains the I2C header, J1005, pinout. Table 13. I2C header (J1005) pinout UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 13. I2C header (J1005) pinout...continued Table 14 describes the I2C devices and their I2C addresses (7-bit) on the Base board.

3.3 V IMU (I3C support)

Table 14. I2C devices on Base board Table 15 describes the I2C devices and their I2C addresses (7-bit) on SOM board. Table 15. I2C devices on SOM board UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 15. I2C devices on SOM board...continued

2.5 Boot mode and boot device configuration

Figure 6 shows the boot mode selection switch. Figure 6. Boot mode selection switch Table 16 describes the SW1301 values used in different boot modes. Table 16. Boot mode settings UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

NXP Semiconductors UM12043 IMX91LP4EVK-11 Board User Manual

2.6 Audio interface

The i.MX 91 processor's synchronous audio interface (SAI) supports an audio codec U1201 (WM8962BECSN/ R) on IMX91LP4EVK-11 board. The audio codec is used for encoding/decoding audio data and supports 24-bit I2S data and 48 kHz sampling rate. The audio codec is connected to a 3.5 mm 4-pole CTIA standard audio jack for audio input/output. The audio codec also allows connecting to a speaker via a 4-pin header (J1202) connector. The J1201 connector is The pulse density modulated (PDM) microphone interface of the processor provides PDM Medium Quality sound (MQS) support on the IMX91LP4EVK-11 board. By using MQS, a user can connect stereo speakers or microphone without using an additional DAC. The MQS allows I2S audio data from SAI to be converted to PWM signals that can drive external speaker directly. Its audio source comes from SAI-3 and its output is connected to pads through IOMUX. The TMUX1574RSVR (U1303) four-channel switch is configured through PDM/ MQS_SEL configuration signal from I/O expander (ADP5585ACPZ-00-R7, I2C Address 0x34) to output either PDM CLK/Data or MQS data. The J1301 audio jack is used for MQS output and two pairs of microphones (U1301/2 and U1304/5) are used for PDM interface. Figure 8 shows the audio interface on the board. Table 17 describes the audio codec, audio jacks, and PDM microphones used on the board. Part identifier Manufacturing part number J1201 and J1301 KJ366EYS 3.5 mm audio jacks for onboard audio codec and MQS analog input/output U1201 Cirrus Logic WM8962 BECSN/R Stereo audio codec. It receives analog audio from an input audio jack, encodes it as digital signals, decodes digital signals back to analog audio, and sends it to the output audio jack U1301, U1302, U1304, and U1305 SPK0641HT4H-1 Digital microphones with respective single-bit PDM output J1202 - 4-pin header for connecting speaker Table 17. Audio codec, audio jacks, and PDM microphones UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 8. Audio interface connections

2.7 LPDDR44 DRAM memory

to the i.MX 91 DRAM controller. resistor DRAM_ZQ used at i.MX 91 SoC side is 120 Ω 1% to GND. determined by the layout and other critical traces for the ease of routing.

2.8 SD card interface

support eMMC 5.1 devices. It is the default boot device of the board. Table 16 shows the boot settings. Table 18 describes the eMMC memory device that is supported by the uSDHC1 interface. Table 18. Supported eMMC device card, IEEE802.15.4 Radio, or 3G/4G cards. Table 19 describes the pinout of the M.2 mini card connector (J901). Table 19. M.2 mini card connector (J901) pinout UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

For further details about i.MX 91 interfaces, see i.MX 91 Reference Manual.

2.11 QSPI NOR/NAND Flash

rework step must be taken on 91LP4EVK-11BB (Base board). See Figure 9. Figure 9. Rework required on 91LP4EVK-11BB for using QSPI memory as boot device UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

NXP Semiconductors UM12043 IMX91LP4EVK-11 Board User Manual

2.12 CAN interface

The i.MX 91 processor supports a controller area network (CAN) module, which is a communication controller implementing the CAN protocol. The controller supports the CAN with flexible data rate (CAN FD) protocol and the CAN 2.0B protocol specification. The processor supports two CAN FD controllers. On the IMX91LP4EVK-11 board, one of the controllers is connected to the high-speed CAN transceiver TJA1057GT/3. The high-speed CAN transceiver drives CAN signals between the target processor and a 4-pin header connected to its physical two-wire CAN bus. The HS-CAN transceiver and header are described in Table 20. Part identifier Manufacturing part number (NXP Semiconductors) High-speed CAN transceiver. Provides an interface between a CAN protocol controller and the physical two-wire CAN bus. J1101 Not applicable 1x4 CAN header. It is connected to the CAN bus and allows external connection with the bus. Table 20. High-speed CAN transceiver and header Note: For details about the CAN Transceiver TJA1057, refer to the TJA1057 datasheet. Table 21 explains the pinout for CAN header, J1101.

1 VDD_5V 5 V power supply

2 CAN_H CAN transceiver high signal

3 CAN_L CAN transceiver low signal

4 GND Ground

Table 21. CAN header - pinout

2.13 USB interface

J401 USB2.0 Type- C Connects to full-speed USB host and device controller (USB 1) of target processor. It can operate as a device or host. The USBC_VBUS signal controls the VBUS drive for the USB port. J302 USB2.0 Type- C Connects to full-speed USB host and device controller (USB 2) of target processor. It can operate as a device or host. The USBC2_VBUS signal controls the VBUS drive for the USB port. The USB2_DP and USB2_DN signals from the USB2 controller of the target processor are connected to a 2:1 CBTL02043A multiplexer (U309). Depending upon the USB2_SEL configuration signal from PCAL6524HEAZ Table 22. USB ports UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

NXP Semiconductors UM12043 IMX91LP4EVK-11 Board User Manual Part identifier USB Port Type I/O expander (U101, I2C address: 0x22), the multiplexer directs USB data to either USB2 Type C port (J302) or to M.2 card connecter (J901) J301 USB 6 Type- C Power Delivery It is used for power only. It does not support USB data transfer. It is the only power supply port therefore it must always be supplied for system power. J1401 USB Type-C It is used for system debug purpose and supports the UART, remote debug, and power measurement functions. For detail, see the Section 3 "Debug support". Note: Remote debug and power measurement connectors are not populated on the IMX91LP4EVK-11 board. Table 22. USB ports...continued

2.14 Ethernet

processor supports Energy-Efficient Ethernet (EEE), Ethernet Audio Video Bridging (AVB), and IEEE 1588.

Uses RGMII for transmission/ reception
Uses 25 MHz crystal Y501 for clock source
Operating voltage: 1.8 V (default)
Uses ESD protection devices (PUSB3FR4) U502 and U503 J501 - RJ45 Ethernet connector for ENET1 U601 (ENET2) RTL8211FDI-VD-CG (Realtek Semiconductor) Ethernet transceiver that complies with 10Base-T, 100Base-TX, and 1000Base- T IEEE 802.3 standards.
Uses RGMII for transmission/ reception
Uses 25 MHz crystal Y601 for clock source
Operating voltage: 1.8 V (default)
Uses ESD protection devices (PUSB3FR4) U602 and U603 J601 - RJ45 Ethernet connector for ENET2

2.14.1 LED and LDO configuration

external combinations required for strapping and LED usage must be considered in order to avoid contention. high, then the corresponding LED outputs are configured as an active low driver. are needed, the components of the LED path (LED + 510 Ω) can be removed. Figure 10. LDO configuration

2.15 EXPI

the 8MIC-RPI-MX8, MX93AUD-HAT, and TM050RDH03-41. Table 24 lists the J1001 pin definitions.

1 VEXPI_3V3 2 VEXPI_5V

3 GPIO_IO02 4 VEXPI_5V

5 GPIO_IO03 6 GND

7 GPIO_IO04 8 GPIO_IO14

9 GND 10 GPIO_IO15

11 GPIO_IO17 12 GPIO_IO18

13 GPIO_IO27 14 GND

15 GPIO_IO22 16 GPIO_IO23

17 VEXPI_3V3 18 GPIO_IO24

19 GPIO_IO10 20 GND

21 GPIO_IO09 22 GPIO_IO25

23 GPIO_IO11 24 GPIO_IO08

25 GND 26 GPIO_IO07

27 GPIO_IO00 28 GPIO_IO01

29 GPIO_IO05 30 GND

31 GPIO_IO06 32 GPIO_IO12

33 GPIO_IO13 34 GND

35 GPIO_IO19 36 GPIO_IO16

37 GPIO_IO26 38 GPIO_IO20

39 GND 40 GPIO_IO21

Table 24. J1001 pin definitions...continued The GPIO pads have very flexible IOMUX options, can be used as many interfaces, see Table 25. IO02 gpio2.IO[2] i2c4.SDA isi.FRAME_VALID lcdif. IO03 gpio2.IO[3] i2c4.SCL isi.LINE_VALID lcdif. Table 25. GPIO pad IOMUX options UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

IO[10] spi3.SOUT isi.D[4] lcdif.D[6] tpm4. IO[11] spi3.SCK isi.D[5] lcdif.D[7] tpm5. Table 25. GPIO pad IOMUX options...continued UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

3 Debug support

3.1 USB debug interface

Putty, Tera Term, Xshell, or other terminal tools. Table 26 describes the required settings. Table 26. Terminal setting parameters The USB debug connector J1401 is shown in Figure 2.

3.2 JTAG interface

JTAG_TCK (TAP Clock)
JTAG_TMS (TAP Machine State)
JTAG_TDI (TAP Data In)
JTAG_TDO (TAP Data Out) The JTAG connector (J1405) is shown in Figure 2. UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. User manual Rev. 1.0 — 15 November 2024 Document feedback

4 PCB information

layer stack-up and the BB board uses 8-layer stack-up.

2 GND 1

3 Signal 1

4 Power 1

5 GND 1

Table 27. 91LP4EVK-11SOM Board stack up information

5 Power 1

6 Signal 1

7 GND 1

5 Acronyms and abbreviations

Table 29 lists and explains the acronyms and abbreviations used in this document. Table 29. Acronyms UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

6 Related documentation

IMX91IEC (Industrial datasheet)
IMX91CEC (Commercial datasheet) i.MX 91 Hardware Developer's Guide This document aims to help hardware engineers design and to test their i.MX 91 processor-based designs. It provides information about board layout recommendations and design checklists to ensure first-pass success and avoidance of board bring-up problems. UG10147

Table 30. Related documentation request access to these documents, contact your local field applications engineer (FAE) or sales representative. UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

7 Revision history

Table 31 summarizes the revisions to this document. Table 31. Document revision history UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

NXP Semiconductors UM12043 IMX91LP4EVK-11 Board User Manual Legal information Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at https://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this document expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. HTML publications — An HTML version, if available, of this document is provided as a courtesy. Definitive information is contained in the applicable document in PDF format. If there is a discrepancy between the HTML document and the PDF document, the PDF document has priority. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. NXP B.V. — NXP B.V. is not an operating company and it does not distribute or sell products. Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. User manual Rev. 1.0 — 15 November 2024 Document feedback

NXP Semiconductors UM12043 IMX91LP4EVK-11 Board User Manual AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK- PLUS, ULINKpro, μVision, Versatile — are trademarks and/or registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. Bluetooth — the Bluetooth wordmark and logos are registered trademarks owned by Bluetooth SIG, Inc. and any use of such marks by NXP Semiconductors is under license. I2C-bus — logo is a trademark of NXP B.V. UM12043 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. User manual Rev. 1.0 — 15 November 2024 Document feedback

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UM12043 specifications and overview.

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IMX91LP4EVK-11 Board User Manual Rev. 1.0 15 November 2024

Description

IMX91LP4EVK-11 Board User Manual Rev. 1.0 15 November 2024

Source title UM12043 Datasheet(PDF) - NXP Semiconductors

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