UM11650 NXP | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 14
Technical content
Datasheet sections
- 1 Introduction
- 2 Finding kit resources and information on
- 3 Getting ready
- 3.1 Kit contents
- 3.2 Additional hardware and software
- 4 Getting to know the hardware
- 4.1 KIT-TPLSNIFEVB features
- 4.2 Block diagram
- 4.3 Schematics
- 5 Configuring the hardware
- 5.1 Connecting to the TPL bus
- 5.1.1 Optional TPL bus loading
- 5.2 Power and data connections
- 5.2.1 Connecting to the logic analyzer
- 5.2.1.1 Interfacing with the Saleae Logic Analyzer
- 5.2.2 Powering the TPL sniffer
- 5.2.2.1 Power bank keep-alive function
- 6 Hardware specifications
- 7 References
- 8 Legal information
Rev. 1 — 4 August 2021 User manual Document information Information Content Keywords TPL, Transformer Physical Layer, decoder, TPL sniffer Abstract This document helps users understand how to use the KIT-TPLSNIFEVB to acquire TPL communications.
NXP Semiconductors UM11650 KIT-TPLSNIFEVB tool
Revision history
v.1 20210804 • Initial version User manual Rev. 1 — 4 August 2021
1 Introduction
(preferably a Saleae Logic Analyzer) and its software to help analyze any TPL signals. Figure 1. KIT-TPLSNIFEVB analyzer and its software which provides further analysis of such data. TPLSNIFEVB for additional details.
Figure 2. TPL sniffer toolchain
2 Finding kit resources and information on the NXP web site
referenced in this document. and receive input on just about any embedded design topic.
3 Getting ready
3.1 Kit contents
- Assembled and tested TPL sniffer dongle in anti-static bag
- A logic analyzer connection cable with 8-pin headers
- A TPL bus connection twisted cable with 2-pin headers User manual Rev. 1 — 4 August 2021
Figure 3. Kit contents
3.2 Additional hardware and software
Logic Analyzer) is required along with its software.
4 Getting to know the hardware
4.1 KIT-TPLSNIFEVB features
- Internal galvanic isolation between the TPL and rest of the circuits
- Connection to any point of the monitored TPL bus
- Minimal loading of the TPL line
- Logic analyzer connection, with a provided cable pin-to-pin compatible with the Saleae Logic 8 and Logic Pro 8/16 Analyzer series
- Powered through a USB connector by a 5.0 V source, typically a USB power bank or a USB cable connected to a computer
- Integrated keep-alive function to avoid power bank self shut-off User manual Rev. 1 — 4 August 2021
4.2 Block diagram
Figure 4. TPL sniffer block diagram
4.3 Schematics
5 Configuring the hardware
isolated from all other accessible points on the housing.
5.1 Connecting to the TPL bus
also for the system to be sniffed. Figure 5. In other cases, for example, when the TPL bus has
between the TPL_IN and TPL_OUT connectors, as long as the polarity is respected. : The two TPL interface connectors are named J1 and J2 in the schematic diagram. Figure 5. TPL bus connectors
5.1.1 Optional TPL bus loading
ratio T1 isolation transformer.
- The two jumpers JP1 and JP2 located on the bottom side, should be closed (with a drop of solder) in case a standard 150 Ω termination is desired.
- Additional component footprints are available on the top side of the PCB to accommodate different loads on the TPL bus interface. These are R13 (default DNP) and R14 and R15 (default 0 Ω). Note : If the board must be modified and then powered without housing, proceed with caution.
5.2 Power and data connections
- The GND banana plug: used to connect, if necessary, the GND of the TPL sniffer to another potential. It is labeled J5 in the schematics. In some cases of use, the whole system including, for example, the TPL sniffer, the power supply, the logic analyzer and the associated PC, could be an electrically floating block. This connector allows, if desired, the ground potential of the system (for example, the TPL sniffer and anything else that has its ground connected to the TPL sniffer ground) to be set to any other convenient potential, that is, the protective earth or the vehicle chassis ground (KL31).
- The data-out 8-pin connector: buffered SPI signals to be routed to the logic analyzer. It is labeled J3 in the schematics. See Section 5.2.1 "Connecting to the logic analyzer" for more details.
- The power-on LED indicator User manual Rev. 1 — 4 August 2021
- The USB Micro-B connector: to connect to a 5.0 V source. It is labeled J4 in the schematics.
Figure 6. Power and data connectors
5.2.1 Connecting to the logic analyzer
the logic analyzer, to transfer TPL messages converted to SPI format. therefore maintaining the logic and timing information.
- The cable used for the connection must have a characteristic impedance of 100 Ω. This is the impedance normally found on standard IDC ribbon cables.
- The logic analyzer side of the cable should only be loaded with high impedance terminations such as a High-Z input from an oscilloscope, for example, 15 pF || 1 MΩ, or 5 pF || 10 MΩ (better), or digital inputs from a logic analyzer (for example, 10 pF || 2 MΩ). Failure to follow these rules does not guarantee proper operation of the TPL sniffer, unless the cable length is considerably short (< 15 cm) so that reflections in the cable can be neglected. For signal integrity and EMI reduction, the data lines are interleaved with the ground potential with the pinout described in Table 1. The TPL sniffer data output lines and the TPL inputs are internally protected by ESD suppression devices. Nevertheless, standard electrostatic precautions should be taken when handling and using the TPL sniffer. The pin assignment for the data output connector is described in the following table: Pin Signal Description
1 INTB SPI interrupt signal
2 GND Ground
3 RXCLK SPI bus clock
4 GND Ground
5 RXDATA SPI bus data
Table 1. ANALYZER connector (J3) pin assignment
6 GND Ground
7 RXCSB SPI chip select
8 GND Ground
Table 1. ANALYZER connector (J3) pin assignment...continued Figure 7. ANALYZER connector pinout with the blue wires on top (NXP logo side) and the black wires on the bottom.
5.2.1.1 Interfacing with the Saleae Logic Analyzer
Figure 8. Saleae Logic Analyzer Saleae provides a software interface with its product to help decode the acquired signals. To learn more, visit the Saleae website. http://www.nxp.com/KIT-TPLSNIFEVB for more details.
5.2.2 Powering the TPL sniffer
or a USB cable connected to a computer.
5.2.2.1 Power bank keep-alive function
approximate). This simulates a load large enough to keep most power banks energized. with a power bank, consider trying another power bank model.
6 Hardware specifications
Table 2. Electrical characteristics
Table 3. Environmental characteristics Table 4. Mechanical characteristics
7 References
NXP Semiconductors UM11650 KIT-TPLSNIFEVB tool
8 Legal information
8.1 Definitions
Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information.
8.2 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.
Applications
— Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Evaluation products — This product is provided on an “as is” and “with all faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products.
8.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. User manual Rev. 1 — 4 August 2021
NXP Semiconductors UM11650 KIT-TPLSNIFEVB tool Tables Figures Fig. 1. KIT-TPLSNIFEVB . User manual Rev. 1 — 4 August 2021