UM11503 NXP | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 60
Technical content
Datasheet sections
- 1 Introduction
- 2 Finding kit resources and information on
- 2.1 Collaborate in the NXP community
- 3 Getting ready
- 3.1 Kit contents
- 3.2 Additional hardware
- 3.3 Windows PC workstation
- 3.4 Software
- 4 Getting to know the hardware
- 4.1 Kit overview
- 4.1.1 KITFS26AEEVM features
- 4.2 Kit featured components
- 4.2.1 FS26: Safety system basis chip with low
- 4.2.2 VBAT connectors
- 4.2.3 Power topology configuration
- 4.2.4 Output power supply connectors
- 4.2.5 Signal and program connectors
- 4.2.6 Indicators
- 4.2.7 Test points
- 4.2.8 VDDIO selection
- 4.2.9 Wake input switches
- 4.2.10 VDEBUG pin voltage control
- 4.2.11 VMONEXT monitoring
- 4.2.12 GPIO1 and GPIO2
- 4.3 Schematic, board layout and bill of
- 5 Installing and configuring software and
- 5.1 Flashing or updating the GUI firmware
- 5.1.1 Flashing Freedom board firmware for
- 5.1.2 Flashing Freedom board firmware from
- 5.2 Installing GUI software package
- 6 Configuring the hardware
- 7 FS26 NXP GUI
- 7.1 Framework
- 7.1.1 Framework settings
- 7.1.1.1 File
- 7.1.1.2 View
- 7.1.1.3 Export
- 7.2 Device manager
- 7.2.1 Device connection
- 7.2.2 Script shortcuts
- 7.3 Access
- 7.3.1 Register map
- 7.3.1.1 Register read only
- 7.3.1.2 Register read/write
- 7.3.1.3 Global read/write
- 7.3.2 INIT Safety
- 7.3.3 FS Config
- 7.3.4 Regulators
- 7.3.5 AMUX
- 7.4 Script editor
- 7.5 OTP Mirror
- 7.5.1 Read/write operation
- 7.5.2 Read/write all and write all operation
- 7.5.3 Mirror registers export option
- 7.5.4 OTP import to mirror registers
- 7.6 INT
- 7.6.1 Interrupt Configuration
- 7.6.2 Safety Diagnostics
- 7.7 Device programming
- 7.8 OTP tool
- 7.8.1 OTP tool application
- 7.8.2 OTP configuration sections
- 7.8.2.1 System Configuration
- 7.8.2.2 Regulators
- 7.8.2.3 System Safety Configuration
- 7.8.2.4 Voltage Monitoring
- 7.8.2.5 OTP ID
- 7.9 I/O pins
- 8 Using FS26 NXP GUI
- 8.1 Power up
- 8.2 Debug mode entry
- 8.3 Test mode entry
- 8.4 Emulate an OTP configuration
- 8.5 Program an OTP configuration
- 8.6 Go to INIT FS
- 8.7 Go to INIT FS in debug mode
- 8.8 Go to Normal mode
- 8.9 Low power mode
- 8.9.1 Go to standby
- 8.9.2 Go to LPOFF
- 9 Revision history
- 10 Legal information
Figure 1. KITFS26AEEVM design as well as attention to supply filtering, transient suppression, and I/O signal quality. NXP sales and technical support services. parameters, including Typical, must be validated for each customer application by customer’s technical experts. any other application in which the failure of the NXP product could create a situation where personal injury or death may occur. NXP was negligent regarding the design or manufacture of the part.
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board
1 Introduction
This document is the user guide for the KITFS26AEEVM evaluation board. This document is intended for the engineers involved in the evaluation, design, implementation, and validation of FS2600 Fail-safe system basis chip with multiple SMPS and LDO. The scope of this document is to provide the user with information to evaluate the FS2600 Fail-safe system basis chip with multiple SMPS and LDO. This document covers connecting the hardware, installing the software and tools, configuring the environment and using the kit. It is delivered with empty OTP content in order to leave the opportunity to the user to burn the OTP configuration. The board contains a superset device (PFS2630AMDA0AD), allowing tests on all the FS26 derivatives.
2 Finding kit resources and information on the NXP web site
NXP Semiconductors provides online resources for this evaluation board and its supported device(s) on http://www.nxp.com. The information page for KITFS26AEEVM evaluation board is at http://www.nxp.com/ KITFS26AEEVM. The information page provides overview information, documentation, software and tools, parametrics, ordering information and a Getting Started tab. The Getting Started tab provides quick-reference information applicable to using the KITFS26AEEVM evaluation board, including the downloadable assets referenced in this document.
2.1 Collaborate in the NXP community
The NXP community is for sharing ideas and tips, ask and answer technical questions, and receive input on just about any embedded design topic. The NXP community is at http://community.nxp.com.
3 Getting ready
Working with the KITFS26AEEVM requires the kit contents, additional hardware and a Windows PC workstation with installed software.
3.1 Kit contents
- Assembled and tested evaluation board and preprogrammed FRDM-KL25Z microcontroller board in an anti-static bag
- 3.0 ft USB-STD A to USB-B-mini cable
- Two connectors, terminal block plug, 2 pos., str. 3.81 mm
- Three connectors, terminal block plug, 3 pos., str. 3.81 mm
- Jumpers mounted on board
3.2 Additional hardware
In addition to the kit contents, the following hardware is necessary or beneficial when working with this kit. User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board
- Power supply with a range of 8.0 V to 40 V and a current limit set initially to 1.0 A
3.3 Windows PC workstation
This evaluation board requires a Windows PC workstation. Meeting these minimum specifications should produce great results when working with this evaluation board.
- USB-enabled computer with Windows 7 or Windows 10
3.4 Software
Installing software is necessary to work with this evaluation board.
- NXP GUI installation package
4 Getting to know the hardware
The KITFS26AEEVM provides flexibility to play with all the features of the device and make measurements on the main part of the application. The FRDM-KL25Z connected to the board, combined with the FS26 NXP GUI software allows full configuration and control of the FS26 SBC.
4.1 Kit overview
The FS26 family can be evaluated with this board as it is populated with a superset part. The FS26xx part soldered on the board can be fused one time or it is possible to test as many configurations as needed in Emulation mode. This board was designed to sustain up to 2.0 A total on VPRE. Layout is done using six- layer PCB stack up. Set initial current limitation of 1 A.
4.1.1 KITFS26AEEVM
features
- VBAT power supply connectors (Jack and Phoenix)
- VPRE output capability up to 2.0 A
- VBOOST in independent mode or in front-end topology to support battery cranking profiles
- VCORE up to 1.5 A peak
- LDO1 and LDO2 from 3.3 V or 5.0 V, up to 400 mA
- VTRK1 and VTRK2, from 3.3 V or 5.0 V, up to 125 mA
- VREF 1 % accuracy regulator for external ADC reference
- FS0B, FS1b external safety pins
- USB to SPI protocol for easy connection to software GUI
- LEDs that indicate signal or regulator status
- Manual or Automated OTP fuse programming
- Advance system monitoring via AMUX or external ADC
- Analog variable resistor to test external VMON
4.2 Kit featured components
identifies important components on the board. User manual Rev. 1 — 29 January 2021
- WAKE1 and WAKE2 inputs switches
- KL25Z Freedom headers (bottom)
- VDEBUG pin source selection (switch or MCU)
- VDEBUG pin voltage level switches
- VDDIO USB voltage level selection
- VMONEXT variable resistor
- Regulators output LED indicators
- Program burning voltage LED indicator
- Safety output LED indicators
Figure 2. Evaluation board featured component locations
4.2.1 FS26: Safety system basis chip with low power and fit for ASIL D
such as power train, chassis, safety and low-end gateway applications.
events from I/O, long duration timer or SPI communication. the latest on-demand latent fault monitoring.
- 40 V DC maximum input voltage
- Handles severe cranking operation (3.2 V battery) thanks to its BOOST controller
- Supports operating voltage range down to battery 6.0 V without BOOST
- Low-power Off mode with very low sleep current (50 µA typ)
- Low-power Standby mode, VPRE active
- LDO1 or LDO2 active selectable via OTP configuration (50 µA typ)
4.2.2 VBAT connectors
Table 1. VBAT Phoenix connector (J1) Table 2. VBAT three position connector (SW1)
Figure 3. VBAT connectors schematic
4.2.3 Power topology configuration
and Table 3. Default jumper configuration is boost in front-end topology. switching, and it is bypassed. See FS26 data sheet for more information. boost is supplied by the buck regulator VPRE.
0 SJ8
Figure 4. Schematic of boost external components for front end and back-end topologies
Figure 5. Boost configuration jumper section in the schematic Table 3. Jumper configuration for front end and back-end power topologies Figure 6 shows a simplified diagram of jumper configuration to associated device pins. Figure 6. Simplified diagram of jumper configuration for front-end and back-end topologies
4.2.4 Output power supply connectors
Figure 7. Power output Phoenix connectors Table 4. VCORE connector (J14) Table 5. VTRK1/VTRK2 connector (J15) Table 6. VPRE connector (J16) Table 7. VLDO1/VLDO2 connector (J17) Table 8. VREF connector (J18) Table 9. VBOOST connector (J19)
Table 9. VBOOST connector (J19)...continued
4.2.5 Signal and program connectors
program the device externally or to perform debug and diagnosis. Figure 8. Signal and debug headers connectors Table 10. Program connector (J11) Table 11. Signal connector (J23)
0.8 V externally
Table 11. Signal connector (J23)...continued
4.2.6 Indicators
by a low voltage MOSFET by the corresponding signal or regulator. avoid undesired losses and obtain more accurate current consumption measurements. Figure 9. Power and regulator LED indicators be disabled using switch SW5.
Figure 10. Safety output LED indicators
4.2.7 Test points
without a part number, as shown in Figure 11.
- Orange: test loop access to safety outputs and analog signals
- Red: test loop access for power supplies
- Black: test loop access to GND
- Blue: not a part; through hole small test points on board close to the signal aaa-039528 Debug Through hole test points TEST POINTS Ground Power GND GND VBAT VSUP VPI GND GND VDDIO VBST VBST_PG_OUT VBOOST GND GND VREF VLDO1 FS0B VCORE VLDO2 FS1B VPRE VTRK1 RSTB VTRK2 INTB AMUX VBST_FE_LS VBST_BE_LS VPRE_SW VCORE_SW VDEBUG VMONEXT_0.8V VBST_PG VBOS TP7 BH1 MTG1 TP44 TP11 TP34 TP25 TP32 BH3 MTG1 TP35 TP30 TP28 TP20 TP15 TP41 TP16 TP36 TP27 TP42 TP19 BH2 MTG1 TP22 TP18 TP5 TP14 TP26 TP10 BH4 MTG1 TP43 TP12 TP21 TP8 TP17 TP6 TP13 TP24 TP9 TP23
Figure 11. KITFS26AEEVM test points
4.2.8 VDDIO selection
J12 allows selection of the supply source, as shown in Table 12. Table 12. VDDIO connector (J12) Figure 12. VDDIO source selector headers
4.2.9 Wake input switches
Wake inputs can be exercised by switches SW2 for WAKE1_IN and SW3 for WAKE2_IN. These interrupts are supplied by the battery to VBAT signal. Figure 13. WAKE pins control switches
4.2.10 VDEBUG pin voltage control
The selection for manual (default) or automatic is done by J13. Table 13. Debug control selector (J13)
- VDEBUG < VDBG4TH (VDEBUG < 4.2 V): waive debug entry at power up or after low- power modes exit.
- VDEBUG > VDBG4TH (VDEBUG > 4.2 V): enter debug mode at power up or after low power modes exit.
- VDEBUG VDBG65TH (VDEBUG > 6.9 V): burning level for OTP programming. The power supply to generate the debug entry voltage threshold comes from KL25Z USB. This means that Freedom board and USB must be plugged in. Burning voltage for OTP is generated by an onboard boost IC that is also powered by FRDM-KL25Z. For manual mode, use SW6 to allow connection to 5.0 V power supply, and SW7 to connect to 8.0 V power supply; when VDBG65TH is reached a blue LED (D19) turns On. Table 14 shows the possible output voltage level to apply to VDebug pin depending on SW6 and SW7 positions. SW6 SW7 VDebug (J13-2) voltage level OFF OFF 0 V OFF ON 7.8 V ON OFF 4.5 V ON ON 7.8 V
Table 14. SW6 and SW7 VDebug output configuration
- At this step Debug mode is enabled and you can emulate an OTP configuration or
Figure 16. VDEBUG pin source selection schematic
4.2.11 VMONEXT monitoring
potentiometer. Default bridge resistor is 22.2 kΩ. Figure 17. VMONEXT voltage resistor bridge schematic
4.2.12 GPIO1 and GPIO2
- J23_5 for GPIO1 User manual Rev. 1 — 29 January 2021
- J23_7 for GPIO2 To exercise GPIO pins as inputs, R87 and R89 must be populated in order to apply voltage before RC filter. GPIO input supply can be applied through J23 header.
- GPIO1_IN can be accessed through J23_13; R87 must be populated.
- GPIO2_IN can be accessed through J23_15; R89 must be populated. aaa-039535 GND GND GND GND GND GND GPIO1_IN GPIO2_IN 0.01uF C80 0.01uF C82 5.1K R88 R87 5.1K DNP 0.022uF C79 0.022uF C81 GPIO13 GPIO26R89 5.1KDNP 5.1K R86 GPIO1 GPIO2
Figure 18. GPIO1 and GPIO2 schematics or pull-downs are not enabled by OTP, external PU/PD can be added through J23.
4.3 Schematic, board layout and bill of materials
board are available at http://www.nxp.com/KITFS26AEEVM.
5 Installing and configuring software and tools
5.1 Flashing or updating the GUI firmware
and Section 5.1.2 "Flashing Freedom board firmware from Windows 10".
5.1.1 Flashing Freedom board firmware for Windows 7
Steps 1 and 2 are not required if BOOTLOADER is already loaded in the Freedom board.
- Press the RST push-button and connect the USB cable into the SDA port on the
- A new “BOOTLOADER” device should appear on the left pane of the File explorer. 2. Drag and drop the file “MSD-DEBUG-FRDM-KL25Z_Pemicro_v118.SDA” into the BOOTLOADER drive. Note: Make sure to allow enough time for the firmware to be saved in the Bootloader. 3. Disconnect and reconnect the USB cable into the SDA port.
- This time without pressing the RST push-button, FRDM_KL25Z device should appear on the left pane of the File explorer. User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board 4. Locate the file “nxp-gui-fw-frdmkl25z-usb_hid-fs2630_vX.Y.bin” from the package and drag and drop the file into the FRDM_KL25Z device. Note: Make sure to allow enough time for the firmware to be saved. 5. Freedom board firmware is successfully loaded. Disconnect and reconnect the USB cable into the KL25Z USB port.
5.1.2 Flashing Freedom board firmware from Windows 10
- Disable the storage services: run the services, double-click on the storage service from the list and press STOP. Steps 2 and 3 are not required if BOOTLOADER is already loaded in the Freedom board. 2. Press the RST push-button and connect the USB cable into the SDA port on the Freedom board. a. A new “BOOTLOADER” device should appear on the left pane of the File explorer. 3. Drag and drop the file “MSD-DEBUG-FRDM-KL25Z_Pemicro_v118.SDA” into the BOOTLOADER drive. Note: Make sure to allow enough time for the firmware to be saved in the BOOTLOADER. 4. Disconnect and reconnect the USB cable into the SDA port.
- This time without pressing the RST push-button, FRDM_KL25Z device should appear on the left pane of the File explorer. 5. Locate the file “nxp-gui-fw-frdmkl25z-usb_hid-fs2630_vX.Y.bin” from the package and drag and drop the file into the FRDM_KL25Z device. Note: Make sure to allow enough time for the firmware to be saved. 6. Freedom board Firmware is successfully loaded. Disconnect and reconnect the USB cable into the KL25Z USB port. User manual Rev. 1 — 29 January 2021
5.2 Installing GUI software package
Double-click NXP_GUI_version-Setup.exe and follow the instructions. Figure 19. Application setup
6 Configuring the hardware
Figure 24. Typical initial configuration
- With SW1 in middle position, set DC power supply to 12 V and current limit to 1.0 A.
Phoenix connector(J1). Or connect 12 V power supply to VBAT Jack (J2). Table 15. VBAT Phoenix connector (J1) Table 16. VBAT three position connector (SW1)
- Connect the Windows PC USB port to the KL25Z USB side of the freedom board
included in the kit, using the provided USB 2.0 cable.
- Turn On SW6 to apply 5.0 V to the VDebug pin.
- Turn On the power supply.
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board Note: At this step, the product is in debug mode and all regulators are turned Off. The user can then power up with OTP configuration or configure the mirror registers before power up. Power up is effective as soon as SW6 is turned Off.
7 FS26 NXP GUI
Once the kit is ready and the NXP GUI is installed, launch the kit from the Windows search bar. Launching FS26_GUI application 1. When the NXP GUI is launched, the Kit Selection window is displayed. Check for the following settings and then select OK. 2. To avoid the kit selection window on every launch, select the box “Use this configuration and do not ask again”. The following window is displayed. User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board
7.1 Framework
Device manager: Start communication with device. Enter or exit test mode. Quick access to execute system scripts. Framework settings : Import or export files, configure framework. Window log: USB and Device communication events. USB and device status: Displays if USB or Device is connected or disconnected. Displays firmware and GUI version. Display current state of FS state machine; click Display to refresh. Tool access bar: Quick access to the FS26 evaluation tools and features. User manual Rev. 1 — 29 January 2021
7.1.1 Framework settings
The NXP GUI main menu has five GUI elements: File, View, Export, NXP, and Help.
7.1.1.1 File
when OTP tool tab is active.
- Load: Loads an existing configuration file previously exported from OTP tool to continue to modify it on the OTP tool. This file has a .cfg extension. It is identified as: FS26_ProgIDASILlevel_CONFIG.cfg. Example: FS26_A0D_CONFIG.cfg.
- Save : Saves the current configuration of the OTP tool as a .cfg file.
- Use default configuration: Loads default values into the OTP tool.
- Exit: Exits NXP GUI application
7.1.1.2 View
This main menu has options related to GUI display.
- Display
- Show
- Naming Conventions Display: It consists of Connection Tool Bar (enabled by default) option. To show or hide, go to View → Display, and then select Connection Tool Bar.
Figure 25. Display options Show: This option can be used to access various sections of the GUI.
register names as register's technical names throughout the OTP Tool.
7.1.1.3 Export
- OTP: Exports OTP configuration into OTP script file for programming.
- TBB: Exports OTP configuration into a TBB script file for emulation
- I-HEX: Exports to Intel Hex script file
- S-HEX: Exports to Simple Hex script file
Figure 29. Export options
7.2 Device manager
of the test mode; it also allows quick access to execute useful system scripts. Figure 30. Device manager
7.2.1 Device connection
to DISCONNECTED. Start button is enabled. Click Start to initiate communication with FS26 device.
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board When connected successfully, FS26 color changes to green and other buttons are enabled. USB status changes to CONNECTED. Apply test mode to send Main and Fail-safe Test mode entry keys. If test mode is entered correctly, button changes to “Exit test mode”. When test mode is entered, options requiring test mode are enabled, such as Mirrors and device programming. Click Polling to do a continuous check of test mode entry. If the device versioning bits are already programmed with an existing part number, the NXP GUI decodes and displays the assigned Device ID. The following example displays FS2633D.
7.2.2 Script shortcuts
To find a section with system script shortcuts, select the script and click execute. This does not warrant the entry or acknowledge of the device. Device must be in INIT FS state in most cases.
7.3 Access
7.3.1 Register map
The register access tab allows read/write to the FS26 Main and Fail-safe register maps and is divided into following sections: User manual Rev. 1 — 29 January 2021
- Functional: Main functional SPI registers (diagnostics, configuration, and controls)
- Safety: Safety SPI registers (diagnostics and configuration)
- Write_INIT_Safety: Safety registers that can be configured during INIT FS state (for example, WD configuration and WD window). There are three types of registers: read only (only read button), write only (only write button) or read/write (read and write buttons).
7.3.1.1 Register read only
displayed on label near READ button, and is displayed on the log window. Figure 31. Read only register To view the values of all the bits from a register after read operation, click Edit button. Bits are read with their corresponding values displayed as a pop-up window.
Figure 32. Register read with values and description
7.3.1.2 Register read/write
7.3.1.3 Global read/write
SELECT ALL option selects all the registers on the tab. Figure 33. Global read/write
7.3.2 INIT Safety
configuration, then modify it. Click the combo box controls to select configuration, then click Write. Read or Read All to get configuration; read values appear to the right of controls. Figure 34. INIT Safety
7.3.3 FS Config
This tab helps to configure safety features such as Watchdog and fault error counter. Click Read All to get current configuration.
Figure 35. FS Config
7.3.4 Regulators
Enable or disable FS26 regulators. Check enable or disable box, then click Write button. restart to 0. Write ‘0’ has no effect. VPRE can be only enabled or disabled in test mode.
Figure 36. Regulators
7.3.5 AMUX
The displayed values apply to the divider and temperature formulas.
Figure 37. AMUX To do a single read of all channels click Read. then start polling with Poll button. Click Poll again to stop measurements.
7.4 Script editor
OTP configuration as well with this tab. This tab can be accessed from Toolbar → SCRIPT or View → Show → Script Editor. Figure 38. Script editor available on the script commands section, or by loading a previously exported .txt file.
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board Click one type of command to access more options, until the command to build the sequence is found.
- Digital pins: Select the pin name, then pin value (High or Low). Command is automatically added to the script.
- Analog pins: Select the pin name, and then write the pin value. If the pin is read only, pin value is not enabled and it gets added to script editor automatically.
- Registers: Select the Operation (Read/Write). – Read: Select the register group then the register name. Register is added to script editor automatically. User manual Rev. 1 — 29 January 2021
- Write: Select the register group then the register name. Write value and click enter key. Value must be written in HEX. Press Enter key to add to the editor.
- Mode: Write command to exit or enter different device modes. – Test mode: Send Main and Fail-safe test mode entry keys – User mode: Exit test mode if device is in test mode.
- Generator: Select an existing script to add to the script editor. Some options may require to be in a specific mode or state. The script operations can be found at the bottom of the script editor window. This section is responsible for:
- Execution of script
- Script management: Create, Open, Save, Run
- Logging feature: Load, Save, Clear
Figure 39. Script editor options
View → Show → Script Editor → Help.
7.5 OTP Mirror
configuration can be imported or exported from this tab. Figure 40. OTP Mirror registers
7.5.1 Read/write operation
Figure 41. Read bit group To write to a bit group, modify the controls of each register, then click Write. Figure 42. Write bit group
7.5.2 Read/write all and write all operation
Read All reads the bits of each block from all mirror registers. Read values appear at the right of each register as well on the window log. Figure 43. Read All To write all OTP bit groups configuration, click Write All.
7.5.3 Mirror registers export option
Figure 44. Export option for reference
7.5.4 OTP import to mirror registers
and select the the.txt configuration file previously saved from this tab. Figure 45. OTP Import for reference
7.6 INT
Interrupt Editor window, click Menu → INT or View → Show → Interrupt Editor. It is separated in two tabs: Interrupt Configuration and Safety Diagnostic.
Figure 46. Interrupt Configuration tab
- Blue means Low or not activated
- Yellow means High or activated.
- To clear flags, click each check box from clear column or click Clear All.
- To mask the interruption, check the box of each interruption from mask column.
- Click Read on each box to read the current status or Read all to update the whole tab.
- Use Poll button to read each box periodically. Sense status can be read only.
7.6.1 Interrupt Configuration
over current of device. You can read, clear or mask an interruption. If an event occurs flag changes to red. When regulators are red or ‘1’ they are turned ON.
Figure 47. Interrupt Configuration
7.6.2 Safety Diagnostics
WD, SPI communication errors, FCCU pins, safety outputs, ABIST1 and ABIST2 status. Figure 48. Safety diagnostics tab register. 0 or blue after execution means fail.
7.7 Device programming
enable this window device must be in test mode.
Figure 49. Device programming this voltage, turn on SW7 (Apply 8.0 V to Vdebug). automatically if jumper J13 is on Automatic mode J13 3-2. reserved for NXP users only.
7.8 OTP tool
access OTP Tool from menu, go to View → Show/Hide → OTP Tool.
7.8.1 OTP tool application
- System Configuration
- Switching Regulators
- Regulators
- Voltage Monitoring
- System Safety Configuration
Figure 50. OTP tool configuration tabs for FS26
7.8.2 OTP configuration sections
7.8.2.1 System Configuration
Figure 51. System Configuration
7.8.2.2 Regulators
Figure 52. Regulators Tabs Figure 53. VBST configuration
7.8.2.3 System Safety Configuration
case of Fault or enable and disable Watchdog timer.
Figure 54. System Safety Configuration
7.8.2.4 Voltage Monitoring
- VMONPRE configuration
- VMONLDO1 configuration
- VMONCORE configuration
- VMONLDO2 configuration
- VMONEXT configuration
- VMONREF configuration Make sure that each VMON is assigned with the same voltage output value configured on Regulators tab, then select its fault OV/UV threshold and filtering time.
Figure 55. Voltage Monitoring
7.8.2.5 OTP ID
Displays OTP ID. Only NXP users can create a new OTP ID.
Figure 56. OTP ID
7.9 I/O pins
apply sequences to apply debug mode without moving any switches. Figure 57. I/O pins position 3-2. Select high or low to control the pins, default is low. removed, use VBAT_Ctrl instead of SW1 to turn the power supply on or off.
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board These pins are also accessible from script editor and be used to create script sequences.
8 Using FS26 NXP GUI
Once the NXP GUI (Section 5.2 "Installing GUI software package") is installed, follow these instructions for a quick power up, debug, programming, or entering the different operating modes of the FS26 SBC.
8.1 Power up
If the FS26 device contains an OTP configuration, connect a power supply to the VBAT Phoenix connector or the VBAT jack connector. See Section 4.2.2 "VBAT connectors". It is recommended to set the power supply to an initial value of 12 V and limit current to 1.0 A. Make sure the board has the correct jumper configuration. Every kit is delivered with a default configuration shown in the following figure. This configuration is enabled for a boost in front-end topology. User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board Verify that the KL25Z Freedom is plugged in, as well as the USB cable on KL25Z USB connector side. It is important that the USB cable is connected since in addition to enabling the communication with the NXP GUI, it provides voltages and references to some circuits on board as well as generates the VDDIO reference for the IC. Since all the previous statements are valid or considered, switch SW1 can be used to power on the board. If the OTP configuration has many safety features enabled, the device may restart or power Off after a few seconds. To prevent this, enter debug mode to waive some of those features. User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board
8.2 Debug mode entry
To modify any parameters or to communicate with the IC, enter debug mode. Refer to the power and connection statements from Section 8.1 "Power up". Once the kit is ready, follow the next steps: 1. Make sure the device is powered Off (SW1 middle position). 2. Turn On SW6 to apply 5.0 V to the VDebug pin. Make sure the jumper of J13 has the right configuration, default is Manual. See Section 4.2.10 "VDEBUG pin voltage control" for more details. 3. Power on VBAT, and the device enters debug mode, this allows access to the register map, to emulate or to program an OTP configuration on the NXP GUI. 4. To verify debug mode, use the NXP GUI Register map window to Read FS_STATES(0x17) or click on FS_STATES display from USB and device status bar. It is possible to start power up sequence and stay in debug mode. In order to start power up sequence, turn SW6 to put VDebug pin to 0 V.
8.3 Test mode entry
To enter test mode, the device must be in Debug mode. Test mode can be accessed by writing the appropriate key sequences. Access test mode from NXP GUI device manager or write the keys to the script editor. From Device Manager : Click Apply test mode to send the Main and Failsafe test mode entry keys. From Script Editor: Copy and paste the keys in the script editor: // Main Test mode entry SET_REG:FS26:M_TestMode:M_TM_ENTRY:0x0000 SET_REG:FS26:M_TestMode:M_TM_ENTRY:0xD5A7 User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board SET_REG:FS26:M_TestMode:M_TM_ENTRY:0xB8EE SET_REG:FS26:M_TestMode:M_TM_ENTRY:0x0F37 //Fail Safe Test mode entry SET_REG:FS26:FS_TestMode:FS_TM_ENTRY:0x0000 SET_REG:FS26:FS_TestMode:FS_TM_ENTRY:0xD5A7 SET_REG:FS26:FS_TestMode:FS_TM_ENTRY:0xB8EE SET_REG:FS26:FS_TestMode:FS_TM_ENTRY:0x0F37 GET_REG:FS26:FS_TestMode:FS_TM_STATUS1 Click Run Script.
8.4 Emulate an OTP configuration
Before starting, make sure that the power conditions from Section 8.1 "Power up" are valid. If not in debug mode: 1. Ensure the device is powered Off (SW1 middle position). User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board 2. Turn On the SW6 to apply ~4.5 V to the VDebug pin. Make sure that the jumper of J13 has the right configuration; default is Manual. See Section 4.2.2 "VBAT connectors" for more details. 3. Power On VBAT(SW1), and the device enters debug mode. If already in debug entry: 1. Open the NXP GUI, connect the device, and open the script editor. 2. Open the provided or created OTP configuration script (TBB) to load into the mirror registers. 3. Click Run Script. A TBB script contains usually Test mode entry keys; if it does not have it, see Section 8.3 "Test mode entry" to enter test mode. After running the script, read the mirror registers to verify the loaded OTP configuration in the OTP Mirrors tab. Turn the VDebug (SW6) switch to 0 V to start the power up sequence.
8.5 Program an OTP configuration
This section is intended to burn an OTP configuration permanently into the fuses. The device sectors can be programmed only one time. Make sure that sectors are available. You can program an OTP configuration from Device Programming tab or from the script editor. See Section 7.7 "Device programming". 1. If not in debug mode, see Section 8.2 "Debug mode entry". User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board 2. Turn SW7 On to apply ~8 V to the VDebug pin in order to reach the OTP burning threshold VDBG65TH. A blue LED (D19) indicates if this voltage is turned on Burning voltage LED indicator (D19): 3. Open the NXP GUI, connect the device, and go to the script editor. 4. Open the provided or created OTP configuration script to load on the mirror registers. Then click Run to run the script. User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board 5. Once the script has been sent, turn Off SW7, then SW6. 6. Device should power up with the burned OTP configuration or perform a POR on VBAT to verify the fused OTP configuration.
8.6 Go to INIT FS
From power up: 1. Put Debug pin to 5.0 V (SW6 On) to access debug entry. 2. Device powers up (SW1). 3. If the device does not have an OTP configuration emulate or program an OTP configuration. See Section 8.4 "Emulate an OTP configuration" for emulation or Section 8.5 "Program an OTP configuration" for programming. 4. Turn Off SW6 to continue the state machine and access INIT FS. You can verify current state from USB and device status bar, then click display to refresh.
8.7 Go to INIT FS in debug mode
From power up: 1. Put Debug pin to 5.0 V (SW6 On) to access debug entry. 2. Device power up (SW1) 3. If the device does not have an OTP configuration emulate or program an OTP configuration. See Section 8.4 "Emulate an OTP configuration" for emulation or Section 8.5 "Program an OTP configuration" for programming. 4. Turn Off SW6 to continue the state machine and access INIT FS. Verify current state from USB and device status bar, and click display to refresh.
8.8 Go to Normal mode
To enter Normal mode from GUI, you must be in debug mode and in INIT FS state. If simple Watchdog, use a script to release safety outputs FS0B and FS1B. If Watchdog challenger, sequence must be sent manually. 1. Once in INIT FS, Verify ABIST1 passes from Safety diagnostics tab. 2. Configure or verify Watchdog type from Mirrors tab. User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board 3. Use a script to release safety outputs; use script A for watchdog simple or script B for watchdog challenger. Script to release safety outputs is available in device manager scripts section, rr from script editor → Generator → Safety outputs release script and run. a. Sequence to enter normal mode with a Watchdog simple //INIT FS and simple WD enabled required //Open WD window SET_REG:FS26:Safety:FS_WDW_DURATION:0x008B SET_REG:FS26:Safety:FS_NOT_WDW_DURATION:0xF144 //Send 1 good wd refresh to close INIT window SET_REG:FS26:Safety:FS_WD_ANSWER:0x5AB2 //clean fault error counter SET_REG:FS26:Safety:FS_WD_ANSWER:0x5AB2 SET_REG:FS26:Safety:FS_WD_ANSWER:0x5AB2 SET_REG:FS26:Safety:FS_WD_ANSWER:0x5AB2 SET_REG:FS26:Safety:FS_WD_ANSWER:0x5AB2 SET_REG:FS26:Safety:FS_WD_ANSWER:0x5AB2 SET_REG:FS26:Safety:FS_WD_ANSWER:0x5AB2 //Exit dbg mode SET_REG:FS26:Safety:FS_STATES:0x4000 //release FS0B and FS1B SET_REG:FS26:Safety:FS_RELEASE_FS0B_FS1B:0xB2A5 b. Sequence to enter normal mode with a Watchdog Challenger //INIT FS and WD Challenger required //Open WD window SET_REG:FS26:Safety:FS_WDW_DURATION:0x008B SET_REG:FS26:Safety:FS_NOT_WDW_DURATION:0xF144 //Send 1 ZD refresh to close INIT window SET_REG:FS26:Safety:FS_WD_ANSWER:0xa54d //clean fault error counter SET_REG:FS26:Safety:FS_WD_ANSWER:0x4a9a SET_REG:FS26:Safety:FS_WD_ANSWER:0x9535 SET_REG:FS26:Safety:FS_WD_ANSWER:0x2a6a SET_REG:FS26:Safety:FS_WD_ANSWER:0x54d4 SET_REG:FS26:Safety:FS_WD_ANSWER:0xa9a9 SET_REG:FS26:Safety:FS_WD_ANSWER:0x5353 //Exit dbg mode SET_REG:FS26:Safety:FS_STATES:0x4000 //release FS0B and FS1B SET_REG:FS26:Safety:FS_RELEASE_FS0B_FS1B:0xA565 Release safety outputs without script To release safety outputs step by step, continue with these instructions: User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board 1. Configure WD window. Since it is not possible to send a WD refresh periodically, Open WD Window. From FS config tab, go to WD window box, select INFINITE window, and then click Write. Or from device manager select Open WD Window script, and then click execute. 2. Send one good WD refresh to move on the state machine. From FS Config tab, click WD challenger or WD simple one time. Or execute it from script editor or device manager. 3. Send the number selected good WD refresh to clean the Fault error counter. Example: default number is 6. Click six times on WD Challenger or WD simple button. Verify that the Fault error count is now 0 (FLT_ERR_CNT) in FS config tab. 4. Exit debug mode. Write 1 to exit debug mode bit in FS_STATES. Go to register map, then to safety tab. 5. Send “FS0b release” or “FS0b and FS1b release” command to move to normal mode. You can find these buttons in FS config tab. User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board 6. After these steps, device should move to Normal mode. To verify current state, click FS states display from USB and device status bar.
8.9 Low power mode
Once in INIT FS or Normal mode, select a way to exit the low power modes. Write 1 to the event or events that can wake the product from the low power modes.
8.9.1 Go to standby
Execute Go to Standby script from device manager. Or from Script editor → Generator, select Go to Standby script and run it. Device should go to standby mode. Only VPRE stays turn On and LDOs as configured.
8.9.2 Go to LPOFF
Once in INIT FS or Normal mode, execute Go to LPOFF script from device manager. Or from Script editor → Generator, select Go to LPOFF script and run it. Device should go to LPOFF mode. Only VPRE stays turned On. User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board
9 Revision history
v.1 20210129 Initial version
Revision history
User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board
10 Legal information
10.1 Definitions
Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information.
10.2 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
Applications
— Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Evaluation products — This product is provided on an “as is” and “with all faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products.
10.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. User manual Rev. 1 — 29 January 2021
NXP Semiconductors UM11503 KITFS26AEEVM evaluation board Tables Tab. 3. Jumper configuration for front end and Tab. 14. SW6 and SW7 VDebug output configuration . Figures Fig. 2. Evaluation board featured component Fig. 4. Schematic of boost external components for front end and back-end topologies . Fig. 5. Boost configuration jumper section in the Fig. 6. Simplified diagram of jumper configuration for front-end and back-end topologies .. Fig. 17. VMONEXT voltage resistor bridge schematic . User manual Rev. 1 — 29 January 2021