UM10601

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DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA UM10601 LPC800 User manual Rev. 1.0 — 7 November 2012 Preliminary user manual Document information Info Content Keywords ARM Cortex M0+, LPC800, USART, I2C, LPC810M021FN8, LPC811M001FDH16, LPC812M101FDH16, LPC812M101FD20, LPC812M101FDH20 Abstract LPC800 Preliminary user manual

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 2 of 313 Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors UM10601 LPC800 User manual

Revision history

1 20121107 Preliminary LPC800 user manual

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 3 of 313

1.1 Introduction

The LPC800 are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The UM10601 support up to 16 kB of flash memory and 4 kB of SRAM. The peripheral complement of the UM10601 includes a CRC engine, one I2C-bus interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up timer, and state-configurable timer, one comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O pins.

1.2 Features

• System: – ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz. – ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC). – Micro Trace Buffer – System tick timer
• Memory: – 16 kB on-chip flash programming memory. – 4 kB SRAM. – In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot loader software.
• Boot ROM API support: – UART drivers – I2C drivers – Power profiles – IAP/ISP
• Digital peripherals: – High-speed GPIO interface connected to the ARM Cortex-M0+ I/O port with up to 18 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. – Pin interrupt generation capability with boolean pattern-matching feature onup to eightselectable GPIO inputs. – Switch matrix for flexible configuration of each I/O pin function. – State Configurable Timer (SCT) with input and output functions (including capture and match) assigned to pins through the switch matrix. – Multiple-channel multi-rate timer for repetitive interrupt generation at up to four programmable, fixed rates. – Wake-up timer for self-timed wake-up from reduced power modes. UM10601 Chapter 1: LPC800 Introductory information Rev. 1.0 — 7 November 2012 Preliminary user manual

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• Analog peripherals: – Comparator with external voltage reference with pin functions assigned through the switch matrix. – Internal reference voltage.
• Serial interfaces: – Three UART interfaces with pin functions assigned through the switch matrix. – Two SPI controllers with pin functions assigned through the switch matrix. – One I2C-bus interface with open-drain full I2C spec fast Modeplus.
• Clock generation: – 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. – Crystal oscillator with an operating range of 1 MHz to 25 MHz. – Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz. – PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the external clock input (CLKIN), the system oscillator, or the internal RC oscillator.
• Power control: – Integrated PMU (Power Management Unit) to minimize power consumption. – Reduced power modes (Sleep, deep-sleep, power-down, deep power-down). – Power-On Reset (POR). – Brownout detect.
• Unique device serial number for identification.
• Single power supply.
• Available in a SO20 package, TSSOP20 package, TSSOP16, and DIP8 package.

1.3 Ordering information

Table 1. Ordering information Table 2. Ordering options

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1.4 Block diagram

Fig 1. LPC800 block diagram /g54/g53/g36/g48 /g20/g18/g21/g18/g23/g3/g78/g37 /g36/g53/g48 /g38/g50/g53/g55/g40/g59/g16/g48/g19/g14 /g55/g40/g54/g55/g18/g39/g40/g37/g56/g42 /g44/g49/g55/g40/g53/g41/g36/g38/g40 /g41/g47/g36/g54/g43 /g23/g18/g27/g18/g20/g25/g3/g78/g37 /g43/g44/g42/g43/g16/g54/g51/g40/g40/g39 /g42/g51/g44/g50 /g36/g43/g37/g3/g55/g50/g3/g36/g51/g37 /g37/g53/g44/g39/g42/g40/g3 /g38/g47/g50/g38/g46 /g42/g40/g49/g40/g53/g36/g55/g44/g50/g49/g15 /g51/g50/g58/g40/g53/g3/g38/g50/g49/g55/g53/g50/g47/g15 /g54/g60/g54/g55/g40/g48/g3 /g41/g56/g49/g38/g55/g44/g50/g49/g54 /g53/g40/g54/g40/g55/g15/g3/g38/g47/g46/g44/g49 /g70/g79/g82/g70/g78/g86/g3/g68/g81/g71/g3 /g70/g82/g81/g87/g85/g82/g79/g86 /g47/g51/g38/g27/g19/g19 /g68/g68/g68/g16/g19/g19/g24/g26/g23/g25 /g86/g79/g68/g89/g72 /g86/g79/g68/g89/g72 /g86/g79/g68/g89/g72 /g53/g50/g48 /g27/g3/g78/g37 /g86/g79/g68/g89/g72 /g38/g53/g38 /g86/g79/g68/g89/g72 /g51/g44/g49/g3/g44/g49/g55/g40/g53/g53/g56/g51/g55/g54/g18 /g51/g36/g55/g55/g40/g53/g49/g3/g48/g36/g55/g38/g43 /g36/g43/g37/g16/g47/g44/g55/g40/g3/g3/g37/g56/g54 /g44/g53/g38 /g58/g39/g50/g86/g70 /g37/g50/g39 /g51/g50/g53 /g54/g51/g44/g19 /g56/g54/g36/g53/g55/g19 /g54/g39/g36 /g54/g38/g47 /g38/g55/g44/g49/g66/g62/g22/g29/g19/g64 /g38/g55/g50/g56/g55/g66/g62/g22/g29/g19/g64 /g20/g27/g3/g91/g3 /g51/g44/g50/g19 /g20/g27/g3/g91/g3 /g58/g58/g39/g55 /g44/g50/g38/g50/g49 /g51/g48/g56 /g54/g40/g47/g41 /g58/g36/g46/g40/g16/g56/g51/g3/g55/g44/g48/g40/g53 /g48/g56/g47/g55/g44/g16/g53/g36/g55/g40/g3/g55/g44/g48/g40/g53 /g54/g51/g44/g20 /g44/g21/g38/g16/g37/g56/g54 /g54/g38/g55 /g54/g58/g44/g55/g38/g43 /g48/g36/g55/g53/g44/g59 /g38/g50/g48/g51/g36/g53/g36/g55/g50/g53 /g59/g55/g36/g47/g44/g49 /g59/g55/g36/g47/g50/g56/g55 /g36/g38/g48/g51/g66/g50 /g54/g60/g54/g38/g50/g49 /g53/g59/g39/g15/g3/g38/g55/g54 /g55/g59/g39/g15/g3/g53/g55/g54 /g36/g38/g48/g51/g66/g44/g20/g18/g21 /g57/g39/g39/g38/g48/g51 /g54/g38/g46/g15/g3/g54/g54/g40/g47 /g48/g44/g54/g50/g15/g3/g48/g50/g54/g44 /g54/g38/g46/g15/g3/g54/g54/g40/g47 /g48/g44/g54/g50/g15/g3/g48/g50/g54/g44/g36/g47/g58/g36/g60/g54/g16/g50/g49/g3/g51/g50/g58/g40/g53/g3/g39/g50/g48/g36/g44/g49 /g59/g55/g36/g47 /g54/g38/g47/g46 /g56/g54/g36/g53/g55/g20/g53/g59/g39/g15/g3/g38/g55/g54 /g55/g59/g39/g15/g3/g53/g55/g54 /g54/g38/g47/g46 /g56/g54/g36/g53/g55/g21/g53/g59/g39/g15/g3/g38/g55/g54 /g55/g59/g39/g15/g3/g53/g55/g54 /g54/g38/g47/g46 /g38/g47/g46/g50/g56/g55 /g54/g58/g38/g47/g46/g15/g3/g54/g58/g39

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1.5 General description

1.5.1 ARM Cortex-M0+ core configuration

The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO access at address 0xA000 0000. The core includes a single-cycle multiplier and a system tick timer (SysTick).

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2.1 How to read this chapter

The memory mapping is identical for all LPC800 parts. Different LPC800 parts support different flash memory sizes.

2.2 General description

The LPC800 incorporates several distinct memory regions. Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral is allocated 16 kB of space simplifying the address decoding. The registers incorporated into the ARM Cortex-M0+ core, such as NVIC, SysTick, and sleep mode control, are located on the private peripheral bus. The GPIO port and pin interrupt/pattern match registers are accessed by the ARM Cortex-M0+ single-cycle I/O enabled port (IOP). UM10601 Chapter 2: LPC800 Memory mapping Rev. 1.0 — 7 November 2012 Preliminary user manual

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2.2.1 Memory mapping

2.2.2 Micro Trace Buffer (MTB)

The LPC800 supports the ARM Cortex-M0+ Micro Trace Buffer. The private peripheral bus includes the ARM Cortex-M0+ peripherals such as the NVIC, SysTick, and the core control registers. Fig 2. LPC800 Memory mapping /g36/g51/g37/g3/g83/g72/g85/g76/g83/g75/g72/g85/g68/g79/g86 /g19/g91/g23/g19/g19/g19/g3/g23/g19/g19/g19 /g19/g91/g23/g19/g19/g19/g3/g27/g19/g19/g19 /g19/g91/g23/g19/g19/g19/g3/g38/g19/g19/g19 /g19/g91/g23/g19/g19/g20/g3/g19/g19/g19/g19 /g19/g91/g23/g19/g19/g20/g3/g27/g19/g19/g19 /g19/g91/g23/g19/g19/g21/g3/g19/g19/g19/g19 /g19/g91/g23/g19/g19/g21/g3/g27/g19/g19/g19 /g19/g91/g23/g19/g19/g22/g3/g27/g19/g19/g19 /g19/g91/g23/g19/g19/g22/g3/g38/g19/g19/g19 /g19/g91/g23/g19/g19/g23/g3/g19/g19/g19/g19 /g19/g91/g23/g19/g19/g23/g3/g23/g19/g19/g19 /g19/g91/g23/g19/g19/g23/g3/g27/g19/g19/g19 /g19/g91/g23/g19/g19/g23/g3/g38/g19/g19/g19 /g19/g91/g23/g19/g19/g24/g3/g19/g19/g19/g19 /g19/g91/g23/g19/g19/g24/g3/g27/g19/g19/g19 /g19/g91/g23/g19/g19/g24/g3/g38/g19/g19/g19 /g19/g91/g23/g19/g19/g25/g3/g19/g19/g19/g19 /g19/g91/g23/g19/g19/g25/g3/g23/g19/g19/g19 /g19/g91/g23/g19/g19/g27/g3/g19/g19/g19/g19 /g19/g91/g23/g19/g19/g21/g3/g23/g19/g19/g19 /g19/g91/g23/g19/g19/g20/g3/g38/g19/g19/g19 /g19/g91/g23/g19/g19/g20/g3/g23/g19/g19/g19 /g19/g91/g23/g19/g19/g19/g3/g19/g19/g19/g19/g58/g58/g39/g55 /g48/g53/g55 /g3/g86/g72/g79/g73/g3/g90/g68/g78/g72/g16/g88/g83/g3/g87/g76/g80/g72/g85 /g51/g48/g56 /g22/g20/g3/g16/g3/g21/g27/g3/g85/g72/g86/g72/g85/g89/g72/g71 /g68/g81/g68/g79/g82/g74/g3/g70/g82/g80/g83/g68/g85/g68/g87/g82/g85 /g19/g91/g23/g19/g19/g21/g3/g38/g19/g19/g19 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g19/g91/g23/g19/g19/g22/g3/g19/g19/g19/g19 /g19/g91/g23/g19/g19/g22/g3/g23/g19/g19/g19 /g19 /g20 /g21 /g22 /g23 /g24 /g25 /g26 /g27 /g28 /g20/g25 /g20/g24 /g20/g23 /g20/g26 /g20/g27 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g19/g91/g19/g19/g19/g19/g3/g19/g19/g19/g19/g19/g3/g42/g37 /g19/g17/g24/g3/g42/g37 /g23/g3/g42/g37 /g20/g3/g42/g37 /g19/g91/g20/g19/g19/g19/g3/g19/g19/g19/g19 /g19/g91/g20/g41/g41/g41/g3/g19/g19/g19/g19 /g19/g91/g20/g41/g41/g41/g3/g21/g19/g19/g19 /g19/g91/g21/g19/g19/g19/g3/g19/g19/g19/g19 /g19/g91/g24/g19/g19/g19/g3/g19/g19/g19/g19 /g19/g91/g24/g19/g19/g19/g3/g23/g19/g19/g19 /g19/g91/g41/g41/g41/g41/g3/g41/g41/g41/g41 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g19/g91/g23/g19/g19/g19/g3/g19/g19/g19/g19 /g19/g91/g23/g19/g19/g27/g3/g19/g19/g19/g19 /g36/g51/g37/g3/g83/g72/g85/g76/g83/g75/g72/g85/g68/g79/g86 /g19/g91/g24/g19/g19/g19/g3/g27/g19/g19/g19 /g19/g91/g36/g19/g19/g19/g3/g19/g19/g19/g19 /g19/g91/g36/g19/g19/g19/g3/g23/g19/g19/g19 /g38/g53/g38 /g54/g38/g55 /g42/g51/g44/g50 /g19/g91/g36/g19/g19/g19/g3/g27/g19/g19/g19 /g83/g76/g81/g3/g76/g81/g87/g72/g85/g85/g88/g83/g87/g86/g18/g83/g68/g87/g87/g72/g85/g81/g3/g80/g68/g87/g70/g75 /g19/g91/g20/g19/g19/g19/g3/g19/g23/g19/g19 /g20/g3/g78/g37/g3/g3/g54/g53/g36/g48/g3/g11/g47/g51/g38/g27/g20/g19/g12 /g19/g91/g20/g19/g19/g19/g3/g19/g27/g19/g19 /g21/g3/g78/g37/g3/g3/g54/g53/g36/g48/g3/g11/g47/g51/g38/g27/g20/g20/g12 /g19/g91/g20/g19/g19/g19/g3/g20/g19/g19/g19 /g23/g3/g78/g37/g3/g3/g54/g53/g36/g48/g3/g11/g47/g51/g38/g27/g20/g21/g12 /g19/g91/g20/g23/g19/g19/g3/g19/g19/g19/g19 /g19/g91/g20/g23/g19/g19/g3/g20/g19/g19/g19 /g23/g3/g78/g37/g3/g48/g55/g37 /g47/g51/g38/g27/g19/g19 /g19/g91/g19/g19/g19/g19/g3/g23/g19/g19/g19 /g19/g91/g19/g19/g19/g19/g3/g21/g19/g19/g19 /g19/g91/g19/g19/g19/g19/g3/g20/g19/g19/g19 /g20/g25/g3/g78/g37/g3/g82/g81/g16/g70/g75/g76/g83/g3/g73/g79/g68/g86/g75/g3/g11/g47/g51/g38/g27/g20/g21/g12 /g27/g3/g78/g37/g3/g82/g81/g16/g70/g75/g76/g83/g3/g73/g79/g68/g86/g75/g3/g11/g47/g51/g38/g27/g20/g20/g12 /g23/g3/g78/g37/g3/g82/g81/g16/g70/g75/g76/g83/g3/g73/g79/g68/g86/g75/g3/g11/g47/g51/g38/g27/g20/g19/g12 /g27/g3/g78/g37/g3/g69/g82/g82/g87/g3/g53/g50/g48 /g19/g91/g19/g19/g19/g19/g3/g19/g19/g19/g19 /g19/g91/g19/g19/g19/g19/g3/g19/g19/g38/g19 /g68/g70/g87/g76/g89/g72/g3/g76/g81/g87/g72/g85/g85/g88/g83/g87/g3/g89/g72/g70/g87/g82/g85/g86 /g68/g68/g68/g16/g19/g19/g24/g26/g23/g27 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g73/g79/g68/g86/g75/g3/g70/g82/g81/g87/g85/g82/g79/g79/g72/g85 /g54/g51/g44/g19 /g86/g90/g76/g87/g70/g75/g3/g80/g68/g87/g85/g76/g91 /g44/g50/g38/g50/g49 /g54/g60/g54/g38/g50/g49 /g19/g91/g23/g19/g19/g24/g3/g23/g19/g19/g19 /g20/g28 /g21/g21 /g21/g22 /g54/g51/g44/g20 /g56/g54/g36/g53/g55/g19 /g19/g91/g23/g19/g19/g25/g3/g27/g19/g19/g19/g56/g54/g36/g53/g55/g20 /g19/g91/g23/g19/g19/g25/g3/g38/g19/g19/g19 /g56/g54/g36/g53/g55/g21 /g19/g91/g23/g19/g19/g26/g3/g19/g19/g19/g19 /g21/g23 /g19/g91/g40/g19/g19/g19/g3/g19/g19/g19/g19 /g19/g91/g40/g19/g20/g19/g3/g19/g19/g19/g19 /g83/g85/g76/g89/g68/g87/g72/g3/g83/g72/g85/g76/g83/g75/g72/g85/g68/g79/g3/g69/g88/g86 /g44/g21/g38/g21/g19 /g21/g20 /g21/g24 /g21/g25 /g21/g26 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g85/g72/g86/g72/g85/g89/g72/g71 /g20/g19 /g20/g20 /g20/g21 /g20/g22

3.1 How to read this chapter

The NVIC is identical on all LPC800 parts.

3.2 Features

• Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0+.
• Tightly coupled interrupt controller provides low interrupt latency.
• Controls system exceptions and peripheral interrupts.
• The NVIC supports 32 vectored interrupts.
• Four programmable interrupt priority levels with hardware priority level masking.
• Software interrupt generation using the ARM exceptions SVCall and PendSV.
• Support for NMI.
• ARM Cortex M0+ Vector table offset register VTOR implemented.

3.3 General description

3.3.1 Interrupt sources

See Ref. 1 for a detailed description of the NVIC and the NVIC register description. Table 3. Connection of interrupt sources to the NVIC

0 SPI0_IRQ SPI0 interrupt See Table 192 “SPI Interrupt Enable read and Set register

1 SPI1_IRQ SPI1 interr upt Same as SPI0_IRQ

3 UART0_IRQ USART0 interrupt See Table 161 “USART Interrupt Enable read and set register

4 UART1_IRQ USART1 interrupt Same as UART0_IRQ

5 UART2_IRQ USART2 interrupt Same as UART0_IRQ

8 I2C0_IRQ I2C0 interrupt See Table 175 “

address 0x4005 000C) bit description”.

9 SCT_IRQ State configurable timer

10 MRT_IRQ Multi-rate timer in terrupt Global MRT interrupt.

11 CMP_IRQ Analog comparator interrupt COMPEDGE - ri sing, falling, or both edges can set the bit

12 WDT_IRQ Windowed watchdog timer

13 BOD_IRQ BOD interrupts BODINTVAL - BOD interrupt level

14 FLASH_IRQ Flash interrupt <tbd>

15 WKT_IRQ Self wake-up ti mer interrupt ALARMFLAG

24 PININT0_IRQ Pin interrupt 0 or pattern

25 PININT1_IRQ Pin interrupt 1 or pattern

26 PININT2_IRQ Pin interrupt 2 or pattern

27 PININT3_IRQ Pin interrupt 3 or pattern

28 PININT4_IRQ Pin interrupt 4 or pattern

29 PININT5_IRQ Pin interrupt 5 or pattern

30 PININT6_IRQ Pin interrupt 6 or pattern

31 PININT7_IRQ Pin interrupt 7 or pattern

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4.1 How to read this chapter

The system configuration block is identical for all LPC800 parts. USART2 and SPI1 are only available on parts LPC812M101FDH20 and LPC812M101FDH16 and the corresponding clocks, reset, and wake-up control bits are reserved for all other parts.

4.2 Features

• Clock control
• Reset control
• Pin interrupt set-up
• Configuration of reduced power modes
• Wake-up control
• BOD configuration

4.3 Basic configuration

Configure the SYSCON block as follows:

• The SYSCON uses the CKIN, CLKOUT, RESET, and XTALIN/OUT pins. Configure the pin functions through the switch matrix. See Section 4.4.
• No clock configuration is needed. The clock to the SYSCON block is always enabled. By default, the SYSCON block is clocked by the IRC.

4.3.1 Set up the PLL

The PLL creates a stable output clock at a higher frequency than the input clock. If you need a main clock with a frequency higher than the 12 MHz IRC clock, use the PLL to boost the input frequency. 1. Power up the system PLL in the PDRUNCFG register. Section 4.6.32 “Power configuration register” 2. Select the PLL input in the SYSPLLCLKSEL register. You have the following input options: – IRC: 12 MHz internal oscillator. – System oscillator: External crystal oscillator using the XTALIN/XTALOUT pins. – External clock input CLKIN. Select this pin through the switch matrix. Section 4.6.8 “System PLL clock source select register” 3. Update the PLL clock source<t bd> in the SYSPLLCKUEN register. Section 4.6.9 “System PLL clock source update register” 4. Configure the PLL M and N dividers. Section 4.6.3 “System PLL control register” UM10601 Chapter 4: LPC800 System configuration (SYSCON) Rev. 1.0 — 7 November 2012 Preliminary user manual

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4.3.2 Configure the main clock and system clock

The clock source for the registers and memories is derived from main clock. The main clock can be sourced from the IRC at a fixed clock frequency of 12 MHz or from the PLL. The divided main clock is called the system clock and clocks the core, the memories, and the peripherals (register interfaces and peripheral clocks). 1. Select the main clock . You have the following options: – IRC: 12 MHz internal oscillator (default). – PLL output: You must configure the PLL to use the PLL output. Section 4.6.10 “Main clock source select register” 2. Update the main clock source. Section 4.6.11 “Main clock source update enable register” 3. Select the divider value for the system cloc k. A divider value of 0 disables the system clock. Section 4.6.12 “System clock divider register” 4. Select the memories and peripherals that are operating in your application and therefore must have an active clock. The core is always clocked. Section 4.6.13 “System clock control register”

4.3.3 Set up the system oscillat or using XTALIN and XTALOUT

If you want to use the system oscillator with the LPC800, you need to assign the XTALIN and XTALOUT pins, which connect to the external crystal, through the fixed-pin function in the switch matrix. XTALIN and XTALOUT can only be assigned to pins PIO0_8 and PIO0_9. 1. In the IOCON block , remove the pull-up and pull-down resistors in the IOCON registers for pins PIO0_8 and PIO0_9. 2. In the switch matrix block, enable th e 1-bit functions for XTALIN and XTALOUT. 3. In the SYSOSCCTRL register, disable th e BYPASS bit and select the oscillator frequency range according to the desired oscillator output clock. Related registers: Table 62 “PIO0_8 register (PIO0_8, address 0x4004 4038) bit description” Table 61 “PIO0_9 register (PIO0_9, address 0x4004 4034) bit description” Table 105 “Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description” Table 10 “System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit description”

4.4 Pin description

The SYSCON inputs and outputs are assigned to external pins through the switch matrix. function to a pin on the LPC800 package.

4.5 General description

4.5.1 Clock generation

Table 4. SYSCON pin description

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4.5.2 Power control of analog components

The system control block controls the power to the analog components such as the oscillators and PLL, the BOD, and the analog comparator. For details, see the following registers: Section 4.6.30 “Deep-sleep mode configuration register” Section 4.6.3 “System PLL control register” Section 4.6.6 “Watchdog oscillator control register” Section 4.6.5 “System oscillator control register” Fig 3. LPC800 clock generation /g54/g60/g54/g55/g40/g48/g3/g3/g51/g47/g47 /g90/g68/g87/g70/g75/g71/g82/g74/g3/g82/g86/g70/g76/g79/g79/g68/g87/g82/g85 /g44/g53/g38/g3/g82/g86/g70/g76/g79/g79/g68/g87/g82/g85 /g44/g53/g38/g3/g82/g86/g70/g76/g79/g79/g68/g87/g82/g85 /g90/g68/g87/g70/g75/g71/g82/g74/g3/g82/g86/g70/g76/g79/g79/g68/g87/g82/g85 /g54/g60/g54/g55/g40/g48 /g50/g54/g38/g44/g47/g47/g36/g55/g50/g53 /g48/g36/g44/g49/g38/g47/g46/g54/g40/g47 /g11/g80/g68/g76/g81/g3/g70/g79/g82/g70/g78/g3/g86/g72/g79/g72/g70/g87/g12 /g54/g60/g54/g51/g47/g47/g38/g47/g46/g54/g40/g47 /g86/g92/g86/g87/g72/g80/g3/g51/g47/g47/g3/g70/g79/g82/g70/g78/g3/g86/g72/g79/g72/g70/g87 /g38/g47/g50/g38/g46/g3/g39/g44/g57/g44/g39/g40/g53 /g54/g60/g54/g36/g43/g37/g38/g47/g46/g39/g44/g57 /g36/g43/g37/g3/g70/g79/g82/g70/g78/g3/g19 /g11/g70/g82/g85/g72/g15/g3/g86/g92/g86/g87/g72/g80/g30/g3 /g68/g79/g90/g68/g92/g86/g16/g82/g81/g12 /g38/g47/g50/g38/g46/g3/g39/g44/g57/g44/g39/g40/g53 /g56/g36/g53/g55/g38/g47/g46/g39/g44/g57 /g56/g54/g36/g53/g55/g19 /g56/g54/g36/g53/g55/g20 /g56/g54/g36/g53/g55/g21 /g58/g58/g39/g55 /g44/g53/g38/g3/g82/g86/g70/g76/g79/g79/g68/g87/g82/g85/g58/g46/g55 /g79/g82/g90/g16/g83/g82/g90/g72/g85/g3/g82/g86/g70/g76/g79/g79/g68/g87/g82/g85/g58/g46/g55 /g90/g68/g87/g70/g75/g71/g82/g74/g3/g82/g86/g70/g76/g79/g79/g68/g87/g82/g85 /g44/g53/g38/g3/g82/g86/g70/g76/g79/g79/g68/g87/g82/g85 /g86/g92/g86/g87/g72/g80/g3/g82/g86/g70/g76/g79/g79/g68/g87/g82/g85/g38/g47/g50/g38/g46/g3/g39/g44/g57/g44/g39/g40/g53 /g38/g47/g46/g50/g56/g55/g39/g44/g57/g38/g47/g46/g50/g56/g55/g3/g83/g76/g81 /g38/g47/g46/g50/g56/g55/g54/g40/g47 /g11/g38/g47/g46/g50/g56/g55/g3/g70/g79/g82/g70/g78/g3/g86/g72/g79/g72/g70/g87/g12 /g80/g68/g76/g81/g3/g70/g79/g82/g70/g78 /g86/g92/g86/g87/g72/g80/g3/g70/g79/g82/g70/g78 /g54/g60/g54/g36/g43/g37/g38/g47/g46/g38/g55/g53/g47/g62/g20/g29/g20/g28/g64 /g11/g86/g92/g86/g87/g72/g80/g3/g70/g79/g82/g70/g78/g3/g72/g81/g68/g69/g79/g72/g12 /g80/g72/g80/g82/g85/g76/g72/g86 /g68/g81/g71/g3/g83/g72/g85/g76/g83/g75/g72/g85/g68/g79/g86/g15 /g83/g72/g85/g76/g83/g75/g72/g85/g68/g79/g3/g70/g79/g82/g70/g78/g86 /g20/g28 /g68/g68/g68/g16/g19/g19/g24/g26/g23/g28 /g44/g50/g38/g50/g49/g38/g47/g46/g39/g44/g57 /g38/g47/g50/g38/g46/g3/g39/g44/g57/g44/g39/g40/g53/g44/g50/g38/g50/g49/g3 /g74/g79/g76/g87/g70/g75/g3/g73/g76/g79/g87/g72/g85 /g26 /g59/g55/g36/g47/g44/g49 /g38/g47/g46/g44/g49 /g59/g55/g36/g47/g50/g56/g55 /g54/g60/g54/g38/g50/g49 /g51/g48/g56 /g41/g53/g36/g38/g55/g44/g50/g49/g36/g47/g3/g53/g36/g55/g40 /g42/g40/g49/g40/g53/g36/g55/g50/g53

4.5.3 Configuration of reduced power-modes

4.5.4 Reset and interrupt control

release individual peripheral resets. See Table 7. block (see Section 4.6.27 “Pin interrupt select registers”).

4.6 Register description

registers appear in the description of each function. Reset values describe the content of the registers after the boot loader has executed. All address offsets not shown in Table 5 are reserved and should not be written. Table 5. Register overview: System configuration (base address 0x4004 8000)

0 Table 34

Table 5. Register overview: System configuration (base address 0x4004 8000) …continued

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4.6.1 System memory remap register

The system memory remap register selects whether the exception vectors are read from boot ROM, flash, or SRAM. By default, the flash memory is mapped to address 0x0000 0000. When the MAP bits in the SYSMEMREMAP register are set to 0x0 or 0x1, the boot ROM or RAM respectively are mapped to the bottom 512 bytes of the memory map (addresses 0x0000 0000 to 0x0000 0200).

4.6.2 Peripheral reset control register

The PRESETCTRL register allows software to reset specific peripherals. A zero in any assigned bit in this register resets the specified peripheral. A 1 clears the reset and allows the peripheral to operate. PDSLEEPCFG R/W 0x230 Power-down states in deep-sleep mode 0xFFFF Table 35 PDAWAKECFG R/W 0x234 Power-down states for wake-up from deep-sleep 0xEDF0 Table 36 PDRUNCFG R/W 0x238 Power configuration register 0xEDF0 Table 37 DEVICE_ID R 0x3F4 Device ID part dependent Table 38 Table 6. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit

description

Bit Symbol Value Description Reset value 1:0 MAP System memory remap. Value 0x3 is reserved. 0x2 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 0x1 User RAM Mode. Interrupt ve ctors are re-mapped to Static RAM. 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. 31:2 - - Reserved - Table 7. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit Bit Symbol Value Description Reset value

0 SPI0_RST_N SPI0 reset control 1

0 Assert the SPI0 reset. 1 Clear the SPI0 reset.

1 SPI1_RST_N SPI1 reset control 1

0 Assert the SPI1 reset. 1 Clear the SPI1 reset.

2 UARTFRG_RST_N USART fractional baud rate generator

(UARTFRG) reset control 0 Assert the UARTFRG reset. 1 Clear the UARTFRG reset.

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4.6.3 System PLL control register

This register connects and enables the system PLL and configures the PLL multiplier and divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources. The input frequency is multiplied to a higher frequency and then divided down to provide the actual clock used by the CPU, peripherals, and memories. The PLL can produce a clock up to the maximum allowed for the CPU.

3 USART0_RST_N USART0 reset control 1

0 Assert the USART0 reset. 1 Clear the USART0 reset.

4 UART1_RST_N USART1 reset control 1

0 Assert the USART reset. 1 Clear the USART1 reset.

5 UART2_RST_N USART2 reset control 1

0 Assert the USART2 reset. 1 Clear the USART2 reset.

6 I2C_RST_N I2C reset control 1

0 Assert the I2C reset. 1 Clear the I2C reset.

7 MRT_RST_N Multi-rate timer (MRT) reset control 1

0 Assert the MRT reset. 1 Clear the MRT reset.

8 SCT_RST_N SCT reset control 1

0 Assert the SCT reset. 1 Clear the SCT reset.

9 WKT_RST_N Self wake-up timer (WKT) reset control 1

0 Assert the WKT reset. 1 Clear the WKT reset.

10 GPIO_RST_N GPIO and GPIO pin interrupt reset control 1

0 Assert the GPIO reset. 1 Clear the GPIO reset.

11 FLASH_RST_N Flash co ntroller reset control 1

0 Assert the flash controller reset. 1 Clear the flash controller reset.

12 ACMP_RST_N Analog comparator reset control 1

0 Assert the analog comparator reset. 1 Clear the analog comparator controller reset. 31:12 - - Reserved - Bit Symbol Value Description Reset value

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4.6.4 System PLL status register

This register is a Read-only register and supplies the PLL lock status (see <tbd>).

4.6.5 System oscillator control register

This register configures the frequency range for the system oscillator. Table 8. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description Table 9. System PLL status register (SYSPLLS TAT, address 0x4004 800C) bit description

0 LOCK PLL lock status 0

0 PLL not locked

1 PLL locked

Table 10. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit Bit Symbol Value Description Reset value

0 BYPASS Bypass system oscillator 0x0

0 Disabled. Oscillator is not bypassed. 1 Enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator.

1 FREQRANGE Determines frequency range for Low-power

oscillator. 0x0 0 1 - 20 MHz frequency range. 1 15 - 25 MHz frequency range 31:2 - - Reserved 0x00

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4.6.6 Watchdog oscillator control register

This register configures the watchdog oscillator. The oscillator consists of an analog and a digital part. The analog part contains the oscillator function and generates an analog clock (Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can be adjusted with the FREQSEL bits between 600 kHz and 4.6 MHz. With the digital part Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits. The output clock frequency of the watchdog oscillator can be calculated as wdt_osc_clk = Fclkana/(2  (1 + DIVSEL)) = 9.3 kHz to 2.3 MHz (nominal values). Remark: Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the listed frequency value. The watchdog oscillator is the clock source with the lowest power consumption. If accurate timing is required, use the IRC or system oscillator. Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL register before using the watchdog oscillator. Table 11. Watchdog oscillator control regi ster (WDTOSCCTRL, address 0x4004 8024) bit Bit Symbol Value Description Reset value 4:0 DIVSEL Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2  (1 + DIVSEL)) 00000: 2  (1 + DIVSEL) = 2 00001: 2  (1 + DIVSEL) = 4 to 11111: 2  (1 + DIVSEL) = 64 8:5 FREQSEL Select watchdog osc illator analog output frequency (Fclkana). 0x00 0x1 0.6 MHz 0x2 1.05 MHz 0x3 1.4 MHz 0x4 1.75 MHz 0x5 2.1 MHz 0x6 2.4 MHz 0x7 2.7 MHz 0x8 3.0 MHz 0x9 3.25 MHz 0xA 3.5 MHz 0xB 3.75 MHz 0xC 4.0 MHz 0xD 4.2 MHz 0xE 4.4 MHz 0xF 4.6 MHz 31:9 - - Reserved 0x00

4.6.7 System reset status register

The reset value given in Table 12 applies to the POR reset.

4.6.8 System PLL clock so urce select register

(see Section 4.6.9) must be toggled from LOW to HIGH for the update to take effect. Table 12. System reset status register (SYS RSTSTAT, address 0x4004 8030) bit description

0 POR POR reset status 0

0 No POR detected

1 POR detected. Writing a one clears this reset.

1 EXTRST Status of the external RESET

1 Reset detected. Writing a one clears this reset.

2 WDT Status of the Watchdog reset 0

0 No WDT reset detected

1 WDT reset detected. Writing a one clears this reset.

3 BOD Status of the Brown-out detect reset 0

0 No BOD reset detected

1 BOD reset detected. Writin g a one clears this reset.

4 SYSRST Status of the software system reset 0

0 No System reset detected

1 System reset detected. Writing a one clears this reset. Table 13. System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040) 0x3 CLKIN. External clock input.

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4.6.9 System PLL clock source update register

This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to. In order for the update to take effect, first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.

4.6.10 Main clock source select register

This register selects the main system clock, which can be the system PLL (sys_pllclkout), or the watchdog oscillator, or the IRC oscillator. The main system clock clocks the core, the peripherals, and the memories. Bit 0 of the MAINCLKUEN register (see Section 4.6.11) must be toggled from 0 to 1 for the update to take effect.

4.6.11 Main clock source update enable register

This register updates the clock source of the main clock with the new input clock after the MAINCLKSEL register has been written to. In order for the update to take effect, first write a zero to bit 0 of this register, then write a one. Table 14. System PLL clock source update enable register (SYSPLLCLKUEN, address

0 ENA Enable system PLL clock source update 0

0 No change

1 Update clock source

Table 15. Main clock source select regist er (MAINCLKSEL, address 0x4004 8070) bit Bit Symbol Value Description Reset value 1:0 SEL Clock source for main clock 0 0x0 IRC Oscillator 0x1 PLL input 0x2 Watchdog oscillator 0x3 PLL output 31:2 - - Reserved - Table 16. Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)

0 ENA Enable main clock source update 0

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4.6.12 System clock divider register

This register controls how the main clock is divided to provide the system clock to the core, memories, and the peripherals. The system clock can be shut down completely by setting the DIV field to zero.

4.6.13 System clock control register

The SYSAHBCLKCTRL register enables the clocks to individual system and peripheral blocks. The system clock (bit 0) provides the clock for the AHB, the APB bridge, the ARM Cortex-M0+, the SYSCON block, and the PMU. This clock cannot be disabled. Table 17. System clock divi der register (SYSAHBCLKDIV, address 0x4004 8078) bit Bit Symbol Description Reset value 7:0 DIV System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. 0x01 31:8 - Reserved - Table 18. System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit Bit Symbol Value Description Reset value

0 SYS Enables the clock for the AHB, the APB bridge, the

Cortex-M0+ core clocks, SYSCON, and the PMU. This bit is read only and always reads as 1.

0 Reserved

1 Enable

1 ROM Enables clock for ROM. 1

0 Disable

2 RAM Enables clock for SRAM. 1 3 FLASHREG Enables clock for flash register interface. 1 4 FLASH Enables clock for flash. 1 5 I2C Enables clock for I2C. 0

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6 GPIO Enables clock for GPIO port registers and GPIO pin

interrupt registers. 7 SWM Enables clock for switch matrix. 0 8 SCT Enables clock for state configurable timer. 0 9 WKT Enables clock for self wake-up timer. 0 10 MRT Enables clock for multi-rate timer. 11 SPI0 Enables clock for SPI0. 0 12 SPI1 Enables clock for SPI1. 13 CRC Enables clock for CRC. 0 14 UART0 Enables clock for USART0. 0 15 UART1 Enables clock for USART1. 0 16 UART2 Enables clock for USART2. 0 17 WWDT Enables clock for WWDT. 0 18 IOCON Enables clock for IOCON block. 0 …continued Bit Symbol Value Description Reset value

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4.6.14 USART clock divider register

This register configures the clock for the fractional baud rate generator and all USARTs. The UART clock can be disabled by setting the DIV field to zero (this is the default setting).

4.6.15 CLKOUT clock source select register

This register selects the signal visible on the CLKOUT pin. Any oscillator or the main clock can be selected. Bit 0 of the CLKOUTUEN register (see Section 4.6.16) must be toggled from 0 to 1 for the update to take effect.

4.6.16 CLKOUT clock source update enable register

This register updates the clock source of the CLKOUT pin with the new clock after the CLKOUTSEL register has been written to. In order for the update to take effect at the input of the CLKOUT pin, first write a zero to bit 0 of this register, then write a one. 19 ACMP Enables clock to analog comparator. 0 31:20 - - Reserved - …continued Bit Symbol Value Description Reset value Table 19. USART clock di vider register (UARTCLKDIV, address 0x4004 8094) bit description 7:0 DIV USART clock divider values. Table 20. CLKOUT clock source select regist er (CLKOUTSEL, address 0x4004 80E0) bit Bit Symbol Value Description Reset value 1:0 SEL CLKOUT clock source 0 0x0 IRC oscillator 0x1 Crystal oscillator (SYSOSC) 0x2 Watchdog oscillator 0x3 Main clock 31:2 - - Reserved 0

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4.6.17 CLKOUT clock divider register

This register determines the divider value for the signal on the CLKOUT pin.

4.6.18 USART fractional genera tor divider value register

All USART peripherals share a common clock U_PCLK, which can be adjusted by a fractional divider: U_PCLK = UARTCLKDIV/(1 + MULT/DIV). UARTCLKDIV is the USART clock configured in the UARTCLKDIV register. The fractional portion (1 + MULT/DIV) is determined by the two USART fractional divider registers in the SYSCON block: 1. The DIV value programmed in this register is the denominator of the divider used by the fractional rate generator to create the fractional component of U_PCLK. 2. The MULT value of the fractional di vider is programmed in the UARTFRGMULT register. See Table 24. Remark: To use of the fractional baud rate generator, you must write 0xFF to this register to yield a denominator value of 256. All other values are not supported. See also: Section 15.3.1 “Configure the USART clock and baud rate” Section 15.7.1 “Clocking and Baud rates” Table 21. CLKOUT clock source update enable register (CLKOUTUEN, address 0x4004

0 ENA Enable CLKOUT clock source update 0

Table 22. CLKOUT clock divider registers (CLKOUTDIV, address 0x4004 80E8) bit Bit Symbol Description Reset value 7:0 DIV CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255. 31:8 - Reserved -

4.6.19 USART fractional generato r multiplier value register

U_PCLK = UARTCLKDIV/(1 + MULT/DIV). UARTCLKDIV is the USART clock configured in the UARTCLKDIV register.

1. The DIV denominator of the fractiona l divider value is programmed in the
2. The MULT value programmed in this register is the numerator of the fractional divider

4.6.20 External trace buffer command register

Table 23. USART fractional generator divider value register (UARTFRGDIV, address 0x4004 Table 24. USART fractional generator multipli er value register (UARTFRGMULT, address Table 25. External trace buffer command register (EXTTRACECMD, address 0x4004 80FC)

0 START Trace start command <tbd> 0

1 STOP Trace stop command <tbd> 0

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4.6.21 POR captured PIO status register 0

The PIOPORCAP0 register captures the state of GPIO port 0 at power-on-reset. Each bit represents the reset state of one GPIO pin. This register is a read-only status register.

4.6.22 IOCON glitch filter cl ock divider registers 6 to 0

These registers individually configure the seven peripheral input clocks (IOCONFILTR_PCLK) to the IOCON programmable glitch filter. The clocks can be shut down by setting the DIV bits to 0x0.

4.6.23 BOD control register

The BOD control register selects four separate threshold values for sending a BOD interrupt to the NVIC and for forced reset. Reset and interrupt threshold values listed in Table 28 are typical values. Both the BOD interrupt and the BOD reset, depending on the value of bit BODRSTENA in this register, can wake-up the chip from Sleep, Deep-sleep, and Power-down modes. See <tbd>. Table 26. POR captured PIO status regist er 0 (PIOPORCAP0, address 0x4004 8100) bit Bit Symbol Description Reset value 17:0 PIOSTAT State of PIO0_17 through PI O0_0 at power-on reset Implementation dependent 31:18 - Reserved. - Table 27. IOCON glitch filter clock divider registers 6 to 0 (IOCONCLKDIV[6:0], address Bit Symbol Description Reset value 7:0 DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 31:8 - Reserved 0x00 Table 28. BOD control register (BODCTRL, address 0x4004 8150) bit description reset de-assertion threshold voltage is <tbd>. reset de-assertion threshold voltage is <tbd>. reset de-assertion threshold voltage is <tbd>. reset de-assertion threshold voltage is<tbd>.

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4.6.24 System tick count er calibration register

This register determines the value of the SYST_CALIB register.

4.6.25 IRQ late ncy register

The IRQLATENCY register is an eight-bit register which specifies the minimum number of cycles (0-255) permitted for the system to respond to an interrupt request. The intent of this register is to allow the user to select a trade-off between interrupt response time and determinism. Setting this parameter to a very low value (e.g. zero) will guarantee the best possible interrupt performance but will also introduce a significant degree of uncertainty and jitter. Requiring the system to always take a larger number of cycles (whether it needs it or not) will reduce the amount of uncertainty but may not necessarily eliminate it. Theoretically, the ARM Cortex-M0 core should always be able to service an interrupt request within 15 cycles. System factors external to the cpu, however, bus latencies, peripheral response times, etc. can increase the time required to complete a previous instruction before an interrupt can be serviced. Therefore, accurately specifying a minimum number of cycles that will ensure determinism will depend on the application. The default setting for this register is 0x010. 3:2 BODINTVAL BOD interrupt level 0 0x0 Level 0: The interrupt assertion threshold voltage is <tbd>; the interrupt de-assertion threshold voltage is <tbd> 0x1 Level 1: The interrupt assertion threshold voltage is <tbd>; the interrupt de-assertion threshold voltage is <tbd>. 0x2 Level 2: The interrupt assertion threshold voltage is <tbd>; the interrupt de-assertion threshold voltage is <tbd>. 0x3 Level 3: The interrupt assertion threshold voltage is <tbd>; the interrupt de-assertion threshold voltage is <tbd>.

4 BODRSTENA BOD reset enable 0

0 Disable reset function. 1 Enable reset function. 31:5 - - Reserved 0x00 Table 29. System tick timer ca libration register (SYSTCKCAL, address 0x4004 8154) bit Bit Symbol Description Reset value 25:0 CAL System tick timer calibration value 0 31:26 - Reserved -

4.6.26 NMI source selection register

numbers see <tbd>. For a description of the NMI functionality, see <tbd>. interrupt in the NVIC, as described in <tbd>.

4.6.27 Pin interrupt select registers

PINTSEL0 selects pin PIO0_5 for pin interrupt 0. description table in the data sheet. Remark: The GPIO port pin number serves to identify the pin to the PINTSEL register. Any digital function, including GPIO, can be assigned to this pin through the switch matrix. Table 30. IRQ latency register (IRQLATENCY, address 0x4004 8170) bit description Table 31. NMI source selection register (NMISRC, address 0x4004 8174) bit description

31 NMIEN Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source

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4.6.28 Start logic 0 pin wake-up enable register

The STARTERP0 register enables the selected pin interrupts for wake-up from deep-sleep mode and power-down modes. Remark: Also enable the corresponding interrupts in the NVIC. See Table 3 “Connection of interrupt sources to the NVIC”. Table 32. Pin interrupt select registers (PINT SEL[0:7], address 0x4004 8178 (PINTSEL0) to 5:0 INTPIN Pin number select for pin in terrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17). Table 33. Start logic 0 pin wake-up enable register 0 (STARTERP0, address 0x4004 8204) bit Bit Symbol Value Description Reset value

0 PINT0 GPIO pin in terrupt 0 wake-up 0

0 Disabled

1 Enabled

1 PINT1 GPIO pin in terrupt 1 wake-up 0

2 PINT2 GPIO pin in terrupt 2 wake-up 0

3 PINT3 GPIO pin in terrupt 3 wake-up 0

4 PINT4 GPIO pin in terrupt 4 wake-up 0

5 PINT5 GPIO pin in terrupt 5 wake-up 0

6 PINT6 GPIO pin in terrupt 6 wake-up 0

7 PINT7 GPIO pin in terrupt 7 wake-up 0

31:8 - Reserved -

4.6.29 Start logic 1 interrupt wake-up enable register

of interrupt sources to the NVIC”. Table 34. Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004

0 SPI0 SPI0 interrupt wake-up 0

1 SPI1 SPI1 interrupt wake-up 0

12 WWDT WWDT interrupt wake-up 0

13 BOD BOD interrupt wake-up 0

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4.6.30 Deep-sleep mode configuration register

The bits in this register (BOD_PD and WDTOSC_OD) can be programmed to control aspects of Deep-sleep and Power-down modes. The bits are loaded into corresponding bits of the PDRUNCFG register when Deep-sleep mode or Power-down mode is entered. Remark: Hardware forces the analog blocks to be powered down in Deep-sleep and Power-down modes. An exception are the exception of BOD and watchdog oscillator, which can be configured to remain running through this register. The WDTOSC_PD value written to the PDSLEEPCFG register is overwritten if the LOCK bit in the WWDT MOD register (see Table 142) is set. See Section 12.5.3 for details.

4.6.31 Wake-up confi guration register

This register controls the power configuration of the device when waking up from Deep-sleep or Power-down mode.

15 WKT Self wake-up time r interrupt wake-up 0

31:16 Reserved. - Table 35. Deep-sleep configuration regist er (PDSLEEPCFG, address 0x4004 8230) bit Bit Symbol Value Description Reset value 2:0 Reserved. 0b111

3 BOD_PD BOD power-down control for Deep-sleep and

0 Powered

1 Powered down

5:4 Reserved. 11

6 WDTOSC_PD Watchdog oscillator power-down control for

Deep-sleep and Power-down mode. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running. 15:7 - Reserved 0b111111111 31:7 - - Reserved 0

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4.6.32 Power configuration register

The PDRUNCFG register controls the power to the various analog blocks. This register can be written to at any time while the chip is running, and a write will take effect immediately with the exception of the power-down signal to the IRC. To avoid glitches when powering down the IRC, the IRC clock is automatically switched off at a clean point. Therefore, for the IRC a delay is possible before the power-down state takes effect. Table 36. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit Bit Symbol Value Description Reset value

0 IRCOUT_PD IRC oscillator out put wake-up configuration 0

1 IRC_PD IRC oscillator power-down wake-up configuration 0

2 FLASH_PD Flash wake-up configuration 0

3 BOD_PD BOD wake-up configuration 0

4 - Reserved. 1

5 SYSOSC_PD Crystal oscillator wake-up configuration 1

6 WDTOSC_PD Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running.

7 SYSPLL_PD System PLL wa ke-up configuration 1

11:8 - Reserved. Always write these bits as 0b1101 0b1101 14:12 - Reserved. Always write these bits as 0b110 0b110

15 ACMP Analog comparator wake-up configuration 1

31:16 - - Reserved 0

4.6.33 Device ID register

part. This register is also read by the ISP/IAP commands (see Table 229). Table 37. Power configuration register (PDRUNCF G, address 0x4004 8238) bit description

0 IRCOUT_PD IRC oscillator output power 0

1 IRC_PD IRC oscillator power down 0

2 FLASH_PD Flash power down 0

3 BOD_PD BOD power down 0

5 SYSOSC_PD Crystal oscillator power down 1

7 SYSPLL_PD System PLL power down 1

15 ACMP Analog comparator power down 1

4.7 Functional description

4.7.1 System PLL f unctional description

The LPC800 uses the system PLL to create the clocks for the core and peripherals. optionally two additional phases. The CCO frequency range is 156 MHz to 320 MHz. when the PLL has locked on to the input clock. Table 38. Device ID register (DEVICE_ID, address 0x4004 83F4) bit description

4.7.1.1 Lock detector

effectively prevents false lock indications, and thus ensures a glitch free lock signal.

4.7.1.2 Power-down control

operation and will make the lock signal high once it has regained lock on the input clock.

4.7.1.3 Divider ratio programming

4.7.1.3.1 Post divider

output clock with a 50% duty cycle.

4.7.1.3.2 Feedback divider

one, as specified in Table 8 .

4.7.1.3.3 Changing the divider values

4.7.1.4 Frequency selection

Table 39. PLL frequency parameters SYSPLLCLKSEL multiplexer (see Section 4.6.8). FCCO Frequency of the Current Controll ed Oscillator (CCO); 156 to 320 MHz.

4.7.1.4.1 Normal mode

1. Specify the input clock frequency Fclkin.
2. Calculate M to obtain the desired ou tput frequency Fclkout with M = Fclkout / Fclkin.
3. Find a value so that FCCO = 2  P  Fclkout.
4. Verify that all frequencies and divider va lues conform to the limits specified in Table 8.

system clock divider SYSAHBCLKDIV is set to one (see Table 17).

4.7.1.4.2 Power-down mode

the lock signal high once it has regained lock on the input clock. Table 40. PLL configuration examples

12 MHz 48 MHz 00011(binary) 4 01 (binary) 2 192 MHz

12 MHz 36 MHz 00010(binary) 3 10 (binary) 4 288 MHz

12 MHz 24 MHz 00001(binary) 2 10 (binary) 4 192 MHz

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5.1 How to read this chapter

The LPC800 provides an on-chip API in the boot ROM to optimize power consumption in active and sleep modes. See Table 247 “Power profile API calls”. Read this chapter to configure the reduced power modes Deep-sleep mode, Power-down mode, and Deep power-down mode.

5.2 Features

• Reduced power modes control
• Low-power oscillator control
• Four general purpose backup registers to retain data in Deep power-down mode

5.3 Basic configuration

The PMU is always on as long as VDD is present.

5.4 Pin description

The LPC800 has no configurable pins. In Deep power-down only the WAKEUP pin (pin PIO0_4) is functional. The WAKEUP function can be disabled in the DPDCTRL register to lower the power consumption even more. In this case enable the self wake-up timer to provide an internal wake-up signal. See Section 5.6.3 “Deep power-down control register”. Remark: When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in Deep power-down mode.

5.5 General description

Power on the LPC800 is controlled by the PMU, by the SYSCON block, and the ARM Cortex-M0+ core. The following reduced power modes are supported in order from highest to lowest power consumption: 1. Sleep mode: The sleep mode affects the ARM Cortex-M0 core only. Peripherals and memories are active. 2. Deep-sleep and power-down modes: The Deep-sleep and power-down modes affect the core and the entire system with memories and peripherals. UM10601 Chapter 5: LPC800 Reduced power modes and Power Management Unit (PMU) Rev. 1.0 — 7 November 2012 Preliminary user manual

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5.5.1 Wake-up process

If the part receives a wake-up signal in any of the reduced power modes, it wakes up to the active mode. See these links for related registers and wake-up instructions:

• To configure the system after wake-up: Table 36 “Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit description”.
• To use external interrupts for wake-up: Table 33 “Start logic 0 pin wake-up enable register 0 (STARTERP0, address 0x4004 8204) bit description” and Table 32 “Pin interrupt select registers (PINTSEL[0:7], address 0x4004 8178 (PINTSEL0) to 0x4004 8194 (PINTSEL7)) bit description”
• To enable external or internal signals to wake up the part from Deep-sleep or Power-down modes: Table 34 “Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit description”
• To configure the USART to wake up the part: Section 15.3.2 “Configure the USART for wake-up”
• For configuring the self wake-up timer: Section 14.5
• For a list of all wake-up sources: Table 41 “Wake-up sources for reduced power modes”

5.6 Register description

Table 41. Wake-up sources for reduced power modes Sleep Any interrupt Enable interrupt in NVIC. Pin interrupts Enable pin interrupts in NVIC and STARTERP0 registers. BOD interrupt • Enable interrupt in NVIC and STARTERP1 registers.

• Enable interrupt in BODCTRL register.
• BOD powered in PDSLEEPCFG register. BOD reset • Enable reset in BODCTRL register.
• BOD powered in PDSLEEPCFG register. WWDT interrupt • Enable interrupt in NVIC and STARTERP1 registers.
• WWDT running. Enable WWDT in WWDT MOD register and feed.
• Enable interrupt in WWDT MOD register.
• WDOsc powered in PDSLEEPCFG register. WWDT reset • WWDT running.
• Enable reset in WWDT MOD register.
• WDOsc powered in PDSLEEPCFG register. Self Wake-up Timer (WKT) time-out
• Enable interrupt in NVIC and STARTERP1 registers.
• Enable low-power oscillator in the GPREG4 register in the PCON block.
• Select low-power clock for WKT clock in the WKT CTRL register.
• Start the WKT by writing a time-out value to the WKT COUNT register. Interrupt from USART/SPI/I2C peripheral
• Enable interrupt in NVIC and STARTERP1 registers.
• Enable USART/I2C/SPI interrupts.
• Provide an external clock signal to the peripheral.
• Configure the USART in synchronous slave mode and I2C and SPI in slave mode. Deep power-down WAKEUP pin PIO0_4 Enable the WAKEUP fu nction in the GPREG4 register in the PMU. WKT time-out • Enable the low-power oscillator in the GPREG4 register in the PMU.
• Enable the low-power oscillator to keep running in Deep power-down mode in the GPREG4 register in the PMU.
• Select low-power clock for WKT clock in the WKT CTRL register.
• Start WKT by writing a time-out value to the WKT COUNT register.

Table 42. Register overview: PMU (base address 0x4002 0000)

5.6.1 Power control register

5.6.2 General purpose registers 0 to 3

power is still applied to the VDD pin but the chip has entered Deep power-down mode. the general purpose registers. Table 43. Power control register (PCON, address 0x4002 0000) bit description 0x0 Default. The part is in active or sleep mode. 0x1 ARM WFI will enter Deep-sleep mode. 0x2 ARM WFI will enter Power-down mode. Cortex-M0 core powered-down).

3 NODPD A 1 in this bit prevents entry to Deep power-down mode

SLEEPDEEP bit is set, and a WFI is executed.

8 SLEEPFLAG Sleep mode flag 0

1 Read: Sleep/Deep-sleep or Deep power-down mode

Write: Writing a 1 clears the SLEEPFLAG bit to 0.

11 DPDFLAG Deep power-down flag 0

0 Read: Deep power-down mode not entered. 1 Read: Deep power-down mode entered. Write: Clear the Deep power-down flag. Table 44. General purpose registers 0 to 3 (G PREG[0:3], address 0x4002 0004 (GPREG0) to

5.6.3 Deep power-down control register

register configures the functionality of the WAKEUP pin (pin PIO0_4).

2.2 V during Deep power-down, the hysteresis of the WAKEUP input pin has to be

wake-up function is not available. Table 45. Deep power down control register (D PDCTRL, address 0x4002 0014) bit description

0 WAKEUPHYS WAKEUP pin hysteresis enable 0

0 Disabled. Hysteresis for WAKEUP pin disabled. 1 Enabled. Hysteresis for WAKEUP pin enabled.

1 WAKEPAD_

wake-up timer is enabled and configured. Remark: Setting this bit is not necessary if Deep power-down mode is not used. 0 Enabled. The wake-up function is enabled on pin PIO0_4. 1 Disabled. Setting this bit disables the wake-up function on pin PIO0_4.

2 LPOSCEN Enable the low-power oscillator for use with the 10 kHz self wake-up timer

5.7 Functional description

5.7.1 Power management

mode provided that bit 12 in this register is set as well. up from Deep power-down mode. Table 45. Deep power down control register (D PDCTRL, address 0x4002 0014) bit description …continued Table 46. Peripheral configuration in reduced power modes

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5.7.2 Reduced power modes and WWDT lock features

The WWDT clock select lock feature influences the power consumption in any of the power modes because locking the WWDT clock source forces the selected WWDT clock source to be on independently of the Deep-sleep and Power-down mode software configuration through the PDSLEEPCFG register. For details see Section 12.5.3 “Using the WWDT lock features”. If the part uses Deep-sleep mode with the WWDT running, the watchdog oscillator is the preferred clock source as it minimizes power consumption. If the clock source is not locked, the watchdog oscillator must be powered by using the PDSLEEPCFG register. Alternatively, the IRC may be selected and locked in WWDT MOD register, which forces the IRC on during Deep-sleep mode. If the part uses Power-down mode with the WWDT running, the watchdog oscillator must be selected as the clock source. If the clock source is not locked, the watchdog oscillator must be powered by using the PDSLEEPCFG register. Do not lock the clock source with the IRC selected.

5.7.3 Active mode

In Active mode, the ARM Cortex-M0 core and memories are clocked by the system clock, and peripherals are clocked by the system clock or a dedicated peripheral clock. The chip is in Active mode after reset and the default power configuration is determined by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The power configuration can be changed during run time.

5.7.3.1 Power configuration in Active mode

Power consumption in Active mode is determined by the following configuration choices:

• The SYSAHBCLKCTRL register controls which memories and peripherals are running (Table 18).
• The power to various analog blocks (PLL, oscillators, the ADC, the BOD circuit, and the flash block) can be controlled at any time individually through the PDRUNCFG register (Table 37 “Power configuration register (PDRUNCFG, address 0x4004 8238) bit description”).
• The clock source for the system clock can be selected from the IRC (default), the system oscillator, or the watchdog oscillator (see Figure 3 and related registers).
• The system clock frequency can be selected by the SYSPLLCTRL (Table 8) and the SYSAHBCLKDIV register (Table 17).
• The USART and CLKOUT use individual peripheral clocks with their own clock dividers. The peripheral clocks can be shut down through the corresponding clock divider registers.

5.7.4 Sleep mode

In Sleep mode, the system clock to the ARM Cortex-M0+ core is stopped and execution of instructions is suspended until either a reset or an interrupt occurs.

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5.7.4.1 Power configuration in Sleep mode

Power consumption in Sleep mode is configured by the same settings as in Active mode:

• The clock remains running.
• The system clock frequency remains the same as in Active mode, but the processor is not clocked.
• Analog and digital peripherals are selected as in Active mode.

5.7.4.2 Programming Sleep mode

The following steps must be performed to enter Sleep mode: 1. The PD bits in the PCON register must be set to the default value 0x0. 2. The SLEEPDEEP bit in the ARM Cortex-M0+ SCR register must be set to zero. 3. Use the ARM Cortex-M0+ Wait-F or-Interrupt (WFI) instruction.

5.7.4.3 Wake-up from Sleep mode

Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns to its original power configuration defined by the contents of the PDRUNCFG and the SYSAHBCLKDIV registers. If a reset occurs, the microcontroller enters the default configuration in Active mode.

5.7.5 Deep-sleep mode

In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All analog blocks are powered down, except for the BOD circuit and the watchdog oscillator, which must be selected or deselected during Deep-sleep mode in the PDSLEEPCFG register. The main clock, and therefore all peripheral clocks, are disabled except for the clock to the watchdog timer if the watchdog oscillator is selected. The IRC is running, but its output is disabled. The flash is in stand-by mode. Deep-sleep mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself, memory systems and related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static.

5.7.5.1 Power configuration in Deep-sleep mode

Power consumption in Deep-sleep mode is determined by the Deep-sleep power configuration setting in the PDSLEEPCFG (Table 35) register:

• The watchdog oscillator can be left running in Deep-sleep mode if required for the WWDT.
• The BOD circuit can be left running in Deep-sleep mode if required by the application.

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5.7.5.2 Programming Deep-sleep mode

The following steps must be performed to enter Deep-sleep mode: 1. The PD bits in the PCON register must be set to 0x1 ( Table 43). 2. Select the power config uration in Deep-sleep mode in the PDSLEEPCFG (Table 35) register. 3. Select the power configuration after wake-up in the PDAWAKECFG ( Table 36) register. 4. If any of the available wake-up interrupts are needed for wake-up, enable the interrupts in the interrupt wake-up registers (Table 33, Table 34) and in the NVIC. 5. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register. 6. Use the ARM WFI instruction.

5.7.5.3 Wake-up from Deep-sleep mode

The microcontroller can wake up from Deep-sleep mode in the following ways:

• Signal on one of the eight pin interrupts selected in Table 32. Each pin interrupt must also be enabled in the STARTERP0 register (Table 33) and in the NVIC.
• BOD signal, if the BOD is enabled in the PDSLEEPCFG register: – BOD interrupt using the deep-sleep interrupt wake-up register 1 (Table 34). The BOD interrupt must be enabled in the NVIC. The BOD interrupt must be selected in the BODCTRL register. – Reset from the BOD circuit. In this case, the BOD circuit must be enabled in the PDSLEEPCFG register, and the BOD reset must be enabled in the BODCTRL register (Table 28).
• WWDT signal, if the watchdog oscillator is enabled in the PDSLEEPCFG register: – WWDT interrupt using the interrupt wake-up register 1 (Table 34). The WWDT interrupt must be enabled in the NVIC. The WWDT interrupt must be set in the WWDT MOD register. – Reset from the watchdog timer. The WWDT reset must be set in the WWDT MOD register. In this case, the watchdog oscillator must be running in Deep-sleep mode (see PDSLEEPCFG register), and the WDT must be enabled in the SYSAHBCLKCTRL register.
• Via any of the USART blocks. See Section 15.3.2 “Configure the USART for wake-up”.
• Via the I2C. See <tbd>.
• Via any of the SPI blocks. See <tbd>. Remark: If the watchdog oscillator is running in Deep-sleep mode, its frequency determines the wake-up time.

5.7.6 Power-down mode

In Power-down mode, the system clock to the processor is disabled as in Sleep mode. All analog blocks are powered down, except for the BOD circuit and the watchdog oscillator, which must be selected or deselected during Power-down mode in the PDSLEEPCFG

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 50 of 313 NXP Semiconductors UM10601 Chapter 5: LPC800 Reduced power modes and Power Management register. The main clock and therefore all peripheral clocks are disabled except for the clock to the watchdog timer if the watchdog oscillator is selected. The IRC itself and the flash are powered down, decreasing power consumption compared to Deep-sleep mode. Power-down mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself, memory systems and related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static. Wake-up times are longer compared to the Deep-sleep mode.

5.7.6.1 Power configuration in Power-down mode

Power consumption in Power-down mode can be configured by the power configuration setting in the PDSLEEPCFG (Table 35) register in the same way as for Deep-sleep mode (see Section 5.7.5.1):

• The watchdog oscillator can be left running in Power-down mode if required for the WWDT.
• The BOD circuit can be left running in Power-down mode if required by the application.

5.7.6.2 Programming Power-down mode

The following steps must be performed to enter Power-down mode: 1. The PD bits in the PCON register must be set to 0x2 ( Table 43). 2. Select the power configuration in Power-down mode in the PDSLEEPCFG (Table 35) register. 3. Select the power configuration after wake-up in the PDAWAKECFG ( Table 36) register. 4. If any of the available wake-up interrupts are used for wake-up, enable the interrupts in the interrupt wake-up registers (Table 33, Table 34) and in the NVIC. 5. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register. 6. Use the ARM WFI instruction.

5.7.6.3 Wake-up from Power-down mode

The microcontroller can wake up from Power-down mode in the same way as from Deep-sleep mode:

• Signal on one of the eight pin interrupts selected in Table 32. Each pin interrupt must also be enabled in the STARTERP0 register (Table 33) and in the NVIC.
• BOD signal, if the BOD is enabled in the PDSLEEPCFG register: – BOD interrupt using the interrupt wake-up register 1 (Table 34). The BOD interrupt must be enabled in the NVIC. The BOD interrupt must be selected in the BODCTRL register. – Reset from the BOD circuit. In this case, the BOD reset must be enabled in the BODCTRL register (Table 28).
• WWDT signal, if the watchdog oscillator is enabled in the PDSLEEPCFG register:

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 51 of 313 NXP Semiconductors UM10601 Chapter 5: LPC800 Reduced power modes and Power Management – WWDT interrupt using the interrupt wake-up register 1 (Table 34). The WWDT interrupt must be enabled in the NVIC. The WWDT interrupt must be set in the WWDT MOD register. – Reset from the watchdog timer. The WWDT reset must be set in the WWDT MOD register. – Via any of the USART blocks. See Section 15.3.2 “Configure the USART for wake-up”. – Via the I2C. See <tbd>. – Via any of the SPI blocks. See <tbd>.

5.7.7 Deep power-down mode

In Deep power-down mode, power and clocks are shut off to the entire chip with the exception of the WAKEUP pin and the self wake-up timer. During Deep power-down mode, the contents of the SRAM and registers are not retained except for a small amount of data which can be stored in the general purpose registers of the PMU block. All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin. Remark: Setting bit 3 in the PCON register (Table 43) prevents the part from entering Deep-power down mode.

5.7.7.1 Power configuration in Deep power-down mode

Deep power-down mode has no configuration options. All clocks, the core, and all peripherals are powered down. Only the WAKEUP pin and the self wake-up timer are powered.

5.7.7.2 Programming Deep power-down mode

The following steps must be performed to enter Deep power-down mode: 1. Pull the WAKEUP pin externally HIGH. 2. Ensure that bit 3 in the PCON register (Table 43) is cleared. 3. Write 0x3 to the PD bits in the PCON register (see Table 43). 4. Store data to be retained in the general purpose registers ( Section 5.6.2). 5. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register. 6. Use the ARM WFI instruction.

5.7.7.3 Wake-up from Deep power-down mode

Pulling the WAKEUP pin LOW wakes up the LPC800 from Deep power-down, and the part goes through the entire reset process. 1. On the WAKEUP pin, transition from HIGH to LOW. – The PMU will turn on the on-chip voltage regulator. When the core voltage reaches the power-on-reset (POR) trip point, a system reset will be triggered and the chip re-boots. – All registers except the GPREG0 to GPREG3 and PCON will be in their reset state.

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 52 of 313 NXP Semiconductors UM10601 Chapter 5: LPC800 Reduced power modes and Power Management 2. Once the chip has booted, read the deep power-down flag in the PCON register (Table 43) to verify that the reset was caused by a wake-up event from Deep power-down and was not a cold reset. 3. Clear the deep power-down flag in the PCON register ( Table 43). 4. (Optional) Read the stored data in the general purpose registers (Section 5.6.2). 5. Set up the PMU for the next Deep power-down cycle. Remark: The RESET pin has no functionality in Deep power-down mode. For using the self wake-up timer for waking up from Deep power-down mode, see Section 14.5.

6.1 How to read this chapter

on a specific package are reserved.

6.2 Features

• Pull-up/pull-down resistor
• Open-drain mode
• Hysteresis
• Digital glitch filter with programmable time constant
• Analog mode (for a subset of pins, see the LPC81xM data sheet) The true open-drain pins PIO0_10 and PIO0_11 can be configured for different I2C-bus speeds.

6.3 Basic configuration

the pins are configured, you can disable the IOCON clock to conserve power. Table 47. Pinout summary

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6.4 General description

6.4.1 Pin configuration

6.4.2 Pin function

The pin function is determined entirely through the switch matrix. By default one of the GPIO functions is assigned to each pin. The switch matrix can assign all functions from the movable function table to any pin in the IOCON block or enable a special function like an analog input on a specific pin. Related links: Table 94 “Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix)”

6.4.3 Pin mode

The MODE bit in the IOCON register allows enabling or disabling an on-chip pull-up resistor for each pin. By default all pull-up resistors are enabled except for the I2C-bus pins PIO0_10 and PIO0_11, which do not have a programmable pull-up resistor. Fig 5. Pin configuration /g51/g44/g49 /g57/g39/g39 /g57/g39/g39 /g40/g54/g39 /g57/g54/g54 /g40/g54/g39 /g86/g87/g85/g82/g81/g74 /g83/g88/g79/g79/g16/g88/g83 /g86/g87/g85/g82/g81/g74 /g83/g88/g79/g79/g16/g71/g82/g90/g81 /g57/g39/g39 /g90/g72/g68/g78 /g83/g88/g79/g79/g16/g88/g83 /g90/g72/g68/g78 /g83/g88/g79/g79/g16/g71/g82/g90/g81 /g82/g83/g72/g81/g16/g71/g85/g68/g76/g81/g3/g72/g81/g68/g69/g79/g72 /g82/g88/g87/g83/g88/g87/g3/g72/g81/g68/g69/g79/g72 /g85/g72/g83/g72/g68/g87/g72/g85/g3/g80/g82/g71/g72 /g72/g81/g68/g69/g79/g72 /g83/g88/g79/g79/g16/g88/g83/g3/g72/g81/g68/g69/g79/g72 /g83/g88/g79/g79/g16/g71/g82/g90/g81/g3/g72/g81/g68/g69/g79/g72 /g86/g72/g79/g72/g70/g87/g3/g71/g68/g87/g68 /g76/g81/g89/g72/g85/g87/g72/g85 /g71/g68/g87/g68/g3/g82/g88/g87/g83/g88/g87 /g71/g68/g87/g68/g3/g76/g81/g83/g88/g87 /g86/g72/g79/g72/g70/g87/g3/g74/g79/g76/g87/g70/g75 /g73/g76/g79/g87/g72/g85 /g68/g81/g68/g79/g82/g74/g3/g76/g81/g83/g88/g87 /g86/g72/g79/g72/g70/g87/g3/g68/g81/g68/g79/g82/g74/g3/g76/g81/g83/g88/g87 /g83/g76/g81/g3/g70/g82/g81/g73/g76/g74/g88/g85/g72/g71 /g68/g86/g3/g71/g76/g74/g76/g87/g68/g79/g3/g82/g88/g87/g83/g88/g87 /g71/g85/g76/g89/g72/g85 /g83/g76/g81/g3/g70/g82/g81/g73/g76/g74/g88/g85/g72/g71 /g68/g86/g3/g71/g76/g74/g76/g87/g68/g79/g3/g76/g81/g83/g88/g87 /g83/g76/g81/g3/g70/g82/g81/g73/g76/g74/g88/g85/g72/g71 /g68/g86/g3/g68/g81/g68/g79/g82/g74/g3/g76/g81/g83/g88/g87 /g51/g53/g50/g42/g53/g36/g48/g48/g36/g37/g47/g40 /g42/g47/g44/g55/g38/g43/g3/g41/g44/g47/g55/g40/g53

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 55 of 313 NXP Semiconductors UM10601 Chapter 6: LPC800 I/O configuration (IOCON) The repeater mode enables the pull-up resistor if the pin is high and enables the pull-down resistor if the pin is low. This causes the pin to retain its last known state if it is configured as an input and is not driven externally. Repeater mode may typically be used to prevent a pin from floating (and potentially using significant power if it floats to an indeterminate state) if it is temporarily not driven.

6.4.4 Open-drain mode

An open-drain mode can be enabled for all digital I/O pins. Except for pins PIO0_10 and PIO0_11, this mode is not a true open-drain mode. The input cannot be pulled up above VDD.

6.4.5 Analog mode

The switch matrix automatically configures the pin in analog mode whenever an analog input or output is selected as the pin’s function.

6.4.6 I 2C-bus mode

The I2C-bus pins PIO0_10 and PIO0_11 can be programmed to support a true open-drain mode independently of whether the I2C function is selected or another digital function. If the I2C function is selected, all three I2C modes, Standard mode, Fast-mode, and Fast-mode plus, are supported. A digital glitch filter can be configured for all functions. Pins PIO0_10 and PIO0_11 operate as high-current sink drivers (20 mA) independently of the programmed function.

6.4.7 Programmable glitch filter

All GPIO pins are equipped with a programmable, digital glitch filter. The filter rejects input pulses with a selectable duration of shorter than one, two, or three cycles of a filter clock (S_MODE = 1, 2, or 3). For each individual pin, the filter clock can be selected from one of seven peripheral clocks PCLK0 to 6, which are derived from the main clock using the IOCONCLKDIV0 to 6 registers. The filter can also be bypassed entirely. Any input pulses of duration Tpulse of either polarity will be rejected if: Tpulse TPCLKn  S_MODE Input pulses of one filter clock cycle longer may also be rejected: Tpulse TPCLKn (S_MODE + 1) Remark: The filtering effect is accomplished by requiring that the input signal be stable for (S_MODE +1) successive edges of the filter clock before being passed on to the chip. Enabling the filter results in delaying the signal to the internal logic and should be done only if specifically required by an application. For high-speed or time critical functions ensure that the filter is bypassed. If the delay of the input signal must be minimized, select a faster PCLK and a higher sample mode (S_MODE) to minimize the effect of the potential extra clock cycle. If the sensitivity to noise spikes must be minimized, select a slower PCLK and lower sample mode. Related registers and links:

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6.5 Register description

6.5.1 PIO0_17 register

Table 48. Register overview: I/O configuration (base address 0x4004 4000) Table 49. PIO0_17 register (PIO0_17, address 0x4004 4000) bit description

0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled.

6 INV Invert input 0

0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads

1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as

Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.2 PIO0_13 register

Table 50. PIO0_13 register (PIO0_13, address 0x4004 4004) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.3 PIO0_12 register

Table 51. PIO0_12 register (PIO0_12, address 0x4004 4008) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.4 PIO0_5 register

Table 52. PIO0_5 register (PIO0_5, ad dress 0x4004 400C) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.5 PIO0_4 register

Table 53. PIO0_ 4 register (PIO0_4, address 0x4004 4010) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled.

0 Input not inverted (HIGH on pin reads as 1; LOW on pin

1 Input inverted (HIGH on pin reads as 0, LOW on pin reads

Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.6 PIO0_3 register

Table 54. PIO0_3 register (PIO0_3, ad dress 0x4004 4014) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.7 PIO0_2 register

Table 55. PIO0_2 register (PIO0_2, ad dress 0x4004 4018) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.8 PIO0_11 register

Table 56. PIO0_11 register (PIO0_11, address 0x4004 401C) bit description 9:8 I2CMODE Selects I2C mode. function is GPIO (FUNC = 000). 0x0 Standard mode/ Fast-mode I2C. clock. Value 0x7 is reserved.

6.5.9 PIO0_10 register

Table 57. PIO0_10 register (PIO0_10, address 0x4004 4020) bit description 9:8 I2CMODE Selects I2C mode. function is GPIO (FUNC = 000). 0x0 Standard mode/ Fast-mode I2C. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.10 PIO0_16 register

Table 58. PIO0_16 register (PIO0_16, address 0x4004 4024) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.11 PIO0_15 register

Table 59. PIO0_15 register (PIO0_15, address 0x4004 4028) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.12 PIO0_1 register

Table 60. PIO0_1 register (PIO0_1, ad dress 0x4004 402C) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.13 PIO0_9 register

Table 61. PIO0_9 register (PIO0_9, ad dress 0x4004 4034) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.14 PIO0_8 register

Table 62. PIO0_8 register (PIO0_8, ad dress 0x4004 4038) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.15 PIO0_7 register

Table 63. PIO0_7 register (PIO0_7, ad dress 0x4004 403C) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.16 PIO0_6 register

Table 64. PIO0_6 register (PIO0_6, ad dress 0x4004 4040) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.17 PIO0_0 register

Table 65. PIO0_0 register (PIO0_0, ad dress 0x4004 4044) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

6.5.18 PIO0_14 register

Table 66. PIO0_14 register (PIO0_14, address 0x4004 4048) bit description 0x0 Inactive (no pull-down/pull-up resistor enabled). 0x1 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. Remark: This is not a true open-drain mode. 15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock.

7.1 How to read this chapter

7.2 Features

• GPIO port registers are located on the ARM Cortex M0+ I/O port for fast access.
• The ARM Cortex M0+ I/O port supports single-cycle access.
• GPIO ports – GPIO pins can be configured as input or output by software. – All GPIO pins default to inputs with interrupt disabled at reset. – Pin interrupt registers allow pins to be sensed and set individually.

7.3 Basic configuration

SYSAHBCLKCTRL register (Table 18, bit 6).

7.4 Pin description

package pins except supply and ground pins to their GPIO port pins. are assigned to LPC800 package pins.

7.5 General description

pin is configured as output. Table 67. GPIO pins available

7.6 Register description

I/O port. The I/O port supports single-cycle access. Remark: In all GPIO registers, bits that are not shown are reserved. GPIO port addresses can be read and written as bytes, halfwords, or words. may depend on an external source.

7.6.1 GPIO port byte pin registers

state of two pins, and read or write words to sense or set the state of four pins.

7.6.2 GPIO port wo rd pin registers

will set the pin’s output bit. Table 68. Register overview: GPIO port (base address 0xA000 0000) Table 69. GPIO port 0 byte pin registers (B[0:17], addresses 0xA000 0000 (B0) to 0xA000

0 PBYTE Read: state of the pin PIO0 _n, regardless of direction,

analog I/O always read as 0. Write: loads the pin’s output bit.

7.6.3 GPIO port direction registers

7.6.4 GPIO port mask registers

7.6.5 GPIO port pin registers

Table 70. GPIO port 0 word pin registers (W[0:17], addresses 0xA000 1000 (W0) to 0x5000 31:0 PWORD Read 0: pin is LOW. Read 0xFFFF FFFF: pin is HIGH. value other than 0 will set the output bit. Table 71. GPIO direction port 0 register (D IR0, address 0xA000 2000) bit description 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.

7.6.6 GPIO masked port pin registers

7.6.7 GPIO port set registers

Output bits can be set by writing ones to these registers, regardless of MASK registers. Reading from these register returns the port’s output bits, regardless of pin directions.

7.6.8 GPIO port clear registers

Table 73. GPIO port 0 pin register (PIN0, address 0xA000 2100) bit description 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. Table 74. GPIO masked port 0 pin register (MPIN0, address 0xA000 2180) bit description corresponding bit in the MASK register is 0. corresponding bit in the MASK register is 0. Table 75. GPIO set port 0 register (SET0, address 0xA000 2200) bit description 17:0 SETP0 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.

7.6.9 GPIO port toggle registers

registers, regardless of MASK registers.

7.7 Functional description

7.7.1 Reading pin state

• The state of a single pin can be read with 7 high-order zeros from a Byte Pin register.
• The state of a single pin can be read in all bits of a byte, halfword, or word from a Word Pin register.
• The state of multiple pins in a port can be read as a byte, halfword, or word from a PORT register.
• The state of a selected subset of the pins in a port can be read from a Masked Port (MPORT) register. Pins having a 1 in the port’s Mask register will read as 0 from its MPORT register.

7.7.2 GPIO output

1. The pin must be selected for GPIO operation in the switch matrix.
2. The pin must be selected for output by a 1 in its port’s DIR register.

If either or both of these conditions is (are) not met, writing to the pin has no effect. Table 76. GPIO clear port 0 register (CLR 0, address 0xA000 2280) bit description Table 77. GPIO toggle port 0 register (N OT0, address 0xA000 2300) bit description

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• Writing to a Byte Pin register loads the output bit from the least significant bit.
• Writing to a Word Pin register loads the output bit with the OR of all of the bits written. (This feature follows the definition of “truth” of a multi-bit value in programming languages.)
• Writing to a port’s PORT register loads the output bits of all the pins written to.
• Writing to a port’s MPORT register loads the output bits of pins identified by zeros in corresponding positions of the port’s MASK register.
• Writing ones to a port’s SET register sets output bits.
• Writing ones to a port’s CLR register clears output bits.
• Writing ones to a port’s NOT register toggles/complements/inverts output bits. The state of a port’s output bits can be read from its SET register. Reading any of the registers described in Section 7.7.1 returns the state of pins, regardless of their direction or alternate functions.

7.7.3 Masked I/O

A port’s MASK register defines which of its pins should be accessible in its MPORT register. Zeroes in MASK enable the corresponding pins to be read from and written to MPORT. Ones in MASK force a pin to read as 0 and its output bit to be unaffected by writes to MPORT. When a port’s MASK register contains all zeros, its PORT and MPORT registers operate identically for reading and writing. Applications in which interrupts can result in Masked GPIO operation, or in task switching among tasks that do Masked GPIO operation, must treat code that uses the Mask register as a protected/restricted region. This can be done by interrupt disabling or by using a semaphore. The simpler way to protect a block of code that uses a MASK register is to disable interrupts before setting the MASK register, and re-enable them after the last operation that uses the MPORT or MASK register. More efficiently, software can dedicate a semaphore to the MASK registers, and set/capture the semaphore controlling exclusive use of the MASK registers before setting the MASK registers, and release the semaphore after the last operation that uses the MPORT or MASK registers.

7.7.4 Recommended practices

The following lists some recommended uses for using the GPIO port registers:

• For initial setup after Reset or re-initialization, write the PORT registers.
• To change the state of one pin, write a Byte Pin or Word Pin register.
• To change the state of multiple pins at a time, write the SET and/or CLR registers.
• To change the state of multiple pins in a tightly controlled environment like a software state machine, consider using the NOT register. This can require less write operations than SET and CLR.
• To read the state of one pin, read a Byte Pin or Word Pin register.
• To make a decision based on multiple pins, read and mask a PORT register.

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8.1 How to read this chapter

The pin interrupt generator and the pattern match engine are available on all LPC800 parts.

8.2 Features

• Pin interrupts – Up to eight pins can be selected from all GPIO pins as edge- or level-sensitive interrupt requests. Each request creates a separate interrupt in the NVIC. – Edge-sensitive interrupt pins can interrupt on rising or falling edges or both. – Level-sensitive interrupt pins can be HIGH- or LOW-active.
• Pattern match engine – Up to 8 pins can be selected from all GPIO pins to contribute to a boolean expression. The boolean expression consists of specified levels and/or transitions on various combinations of these pins. – Each bit slice minterm (product term) comprising the specified boolean expression can generate its own, dedicated interrupt request. – Any occurrence of a pattern match can be programmed to also generate an RXEV notification to the ARM CPU. The RXEV signal can be connected to a pin. – Feature can be used, in conjunction with software, to create complex state machines based on pin inputs.

8.3 Basic configuration

• Pin interrupts: – Select up to eight external interrupt pins from all GPIO port pins in the SYSCON block (Table 32). The pin selection process is the same for pin interrupts and the pattern match engine. The two features are mutually exclusive. – Enable the clock to the pin interrupt register block in the SYSAHBCLKCTRL register (Table 18, bit 6). – If you want to use the pin interrupts to wake up the part from deep-sleep mode or power-down mode, enable the pin interrupt wake-up feature in the STARTERP0 register (Table 33). – Each selected pin interrupt is assigned to one interrupt in the NVIC (interrupts #24 to #31 for pin interrupts 0 to 7).
• Pattern match engine: – Select up to eight external pins from all GPIO port pins in the SYSCON block (Table 32). The pin selection process is the same for pin interrupts and the pattern match engine. The two features are mutually exclusive. UM10601 Chapter 8: LPC800 Pin interrupts/pattern match engine Rev. 1.0 — 7 November 2012 Preliminary user manual

(interrupts #24 to #31 for slices 0 to 7). movable function register (PINASSIGN8, Table 104).

8.3.1 Configure pins as pin interrupts or as inputs to the pattern match

1. Determine the pins that serve as pin interrupts on the LPC800 package. See the data

sheet for determining the GPIO port pin number associated with the package pin.

1. For each pin interrupt, program the GPIO port pin number into one of the eight

PINTSEL registers in the SYSCON block. function, including GPIO, can be assigned to this pin through the switch matrix.

1. Enable each pin interrupt in the NVIC.

interrupt detection levels or the pattern match boolean expression.

8.4 Pin description

interrupt select registers in the SYSCON block. See Section 8.3.1. The pattern match engine output is assigned to an external pin through the switch matrix. need to follow to assign the GPIO pattern match function to a pin on the LPC800 package.

8.5 General description

SYSCON block for these features. Table 78. SCT pin description

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8.5.1 Pin interrupts

From all available GPIO pins, up to eight pins can be selected in the system control block to serve as external interrupt pins (see Table 32). The external interrupt pins are connected to eight individual interrupts in the NVIC and are created based on rising or falling edges or on the input level on the pin.

8.5.2 Pattern match engine

The pattern match feature allows complex boolean expressions to be constructed from the same set of eight GPIO pins that were selected for the GPIO pin interrupts. The pattern match logic continuously monitors these eight inputs and generates interrupts when any one or more minterms (product terms) of the specified boolean expression is matched. A separate interrupt request is generated for each individual minterm. In addition, the pattern match module can be enabled to generate a Receive Event (RXEV) output to the ARM core when the entire boolean expression is true (i.e. when any minterm is matched). The RXEV output is also be routed to GPIO_INT_BMAT pin. This allows the GPIO module to provide a rudimentary programmable logic capability employing up to eight inputs and one output. The pattern match function utilizes the same eight interrupt request lines as the pin interrupts so these two features are mutually exclusive as far as interrupt generation is concerned. A control bit is provided to select whether interrupt requests are generated in response to the standard pin interrupts or to pattern matches. Note that, if the pin interrupts are selected, the RXEV request to the CPU can still be enabled for pattern matches. Remark: Pattern matching cannot be used to wake the part up from power-down modes. Pin interrupts must be selected in order to use the GPIO for wake-up. The pattern match module is constructed of eight bit-slice elements. Each bit slice is programmed to represent one component of one minterm (product term) within the boolean expression. The interrupt request associated with the last bit slice for a particular minterm will be asserted whenever that minterm is matched. (See bit slice drawing Figure 6 The pattern match capability can be used to create complex software state machines. Each minterm (and its corresponding individual interrupt) represents a different transition event to a new state. Software can then establish the new set of conditions (i.e new boolean expression) that will cause a transition out of the current state.

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8.5.2.1 Example

Assume the expression: (IN0)~(IN1)(IN3)^ + (IN1)(IN2) + (IN0)~(IN3)~(IN4) is specified through the registers PMSRC (Table 91) and PMCFG (Table 92). Each term in the boolean expression, (IN0), ~(IN1), (IN3)^, etc., represents one bit slice of the pattern match engine.

• In the first term (IN0)~(IN1)(IN3)^, bit slice 0 monitors for a high-level on input (IN0), bit slice 1 monitors for a low level on input (IN1) and bit slice 2 monitors for a rising-edge on input (IN3). If this combination is detected, that is if all three terms are true, the interrupt associated with bit slice 2 will be asserted.
• In the second term (IN1)(IN2), bit slice 3 monitors input (IN1) for a high level, bit slice 4 monitors input (IN2) for a high level. If this combination is detected, the interrupt associated with bit slice 4 will be asserted.
• In the third term (IN0)~(IN3)~(IN4), bit slice 5 monitors input (IN0) for a high level, bit slice 6 monitors input (IN3) for a low level, and bit slice 7 monitors input (IN4) for a low level. If this combination is detected, the interrupt associated with bit slice 7 will be asserted.
• The ORed result of all three terms asserts the RXEV request to the CPU and the GPIO_INT_BMAT output. That is, if any of the three terms are true, the output is asserted. Related links: Section 8.7.2 Fig 6. Pattern ma tch bit slice /g48/g56/g59 /g44/g49/g19 /g51/g48/g54/g53/g38 /g44/g81/g87/g85/g66/g53/g72/g84/g11/g76/g12 /g53/g76/g86/g72/g39/g72/g87/g72/g70/g87 /g11/g86/g87/g76/g70/g78/g92/g90/g76/g87/g75/g86/g92/g81/g70/g75 /g70/g79/g72/g68/g85/g12 /g44/g49/g20 /g44/g49/g21 /g44/g49/g22 /g44/g49/g23 /g44/g49/g24 /g44/g49/g25 /g44/g49/g26 /g41/g68/g79/g79/g39/g72/g87/g72/g70/g87 /g11/g86/g87/g76/g70/g78/g92/g90/g76/g87/g75/g86/g92/g81/g70/g75 /g70/g79/g72/g68/g85/g12 /g53/g76/g86/g72/g39/g72/g87/g72/g70/g87 /g11/g81/g82/g81/g16/g86/g87/g76/g70/g78/g92/g12 /g41/g68/g79/g79/g39/g72/g87/g72/g70/g87 /g11/g81/g82/g81/g16/g86/g87/g76/g70/g78/g92 /g48/g56/g59 /g51/g48/g38/g41/g42 /g19 /g20 /g21 /g22 /g23 /g24 /g25 /g26 /g41/g85/g82/g80/g51/g85/g72/g89/g76/g82/g88/g86 /g54/g79/g76/g70/g72 /g51/g85/g82/g71/g66/g40/g81/g71/g83/g87/g86/g11/g76/g12 /g55/g82/g49/g72/g91/g87/g54/g79/g76/g70/g72 /g38/g41/g42/g11/g76/g12 /g54/g53/g38/g11/g76/g12 /g51/g48/g38/g41/g42 /g51/g68/g87/g87/g72/g85/g81/g66/g48/g68/g87/g70/g75/g11/g76/g12

8.6 Register description

8.6.1 Pin interrupt mode register

one bit in the ISEL register determines whether the interrupt is edge or level sensitive.

8.6.2 Pin interrupt level or rising edge interrupt enable register

• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is enabled.

Table 79. Register overview: Pin interrupts/ pattern match engine (base address: 0xA000

0 Table 81

0 Table 84

0 Table 91

0 Table 92

Table 80. Pin interrupt mode register (I SEL, address 0xA000 4000) bit description configures the pin interrupt selected in PINTSELn.

• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is enabled. The IENF register configures the active level (HIGH or LOW) for this interrupt.

8.6.3 Pin interrupt level or risi ng edge interrupt set register

• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is set.
• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is set.

8.6.4 Pin interrupt level or risi ng edge interrupt clear register

• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is cleared.
• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is cleared.

Table 81. Pin interrupt level or rising edge in terrupt enable register (IENR, address 0xA000 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. Table 82. Pin interrupt level or rising edge interrupt set register (SIENR, address 0xA000 enabling interrupts. Bit n sets bit n in the IENR register. 1 = Enable rising edge or level interrupt.

8.6.5 Pin interrupt active level or fa lling edge interrupt enable register

• If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is enabled.
• If the pin interrupt mode is level sensitive (PMODE = 1), the active level of the level interrupt (HIGH or LOW) is configured.

8.6.6 Pin interrupt active level or falling edge interrupt set register

• If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is set.
• If the pin interrupt mode is level sensitive (PMODE = 1), the HIGH-active interrupt is selected.

Table 83. Pin interrupt level or rising edge in terrupt clear register (CIENR, address 0xA000 1 = Disable rising edge or level interrupt. Table 84. Pin interrupt active level or falling edge interrupt enable register (IENF, address

8.6.7 Pin interrupt active level or falling edge interrupt clear register

• If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is cleared.
• If the pin interrupt mode is level sensitive (PMODE = 1), the LOW-active interrupt is selected.

8.6.8 Pin interrupt rising edge register

PINTSELn registers, regardless of whether they are interrupt-enabled. Table 85. Pin interrupt active level or falling edge interrupt set register (SIENF, address enabling interrupts. Bit n sets bit n in the IENF register. Table 86. Pin interrupt active level or falling edge interrupt clear register (CIENF, address disabling interrupts. Bit n clears bit n in the IENF register. Table 87. Pin interrupt rising edge register (RISE, address 0xA000 401C) bit description Reset or the last time a one was written to this bit. last time a one was written to this bit. Write 1: clear rising edge detection for this pin.

8.6.9 Pin interrupt falling edge register

PINTSELn registers, regardless of whether they are interrupt-enabled.

8.6.10 Pin interrupt status register

the active level on the pin.

8.6.11 Pattern Match Inte rrupt Control Register

state of any pattern matches to be read. assertion) the two LSB’s of this register should be left at 0b00 to conserve power. Table 88. Pin interrupt falling edge register (FALL, address 0xA000 4020) bit description Reset or the last time a one was written to this bit. last time a one was written to this bit. Write 1: clear falling edge detection for this pin. Table 89. Pin interrupt status register (IST, address 0xA000 4024) bit description Read 0: interrupt is not being requested for this interrupt pin. Read 1: interrupt is being requested for this interrupt pin.

eliminates the possibility of spurious interrupts as the feature is being enabled.

8.6.12 Pattern Match Interrupt Bit-Slice Source register

bits in the PMCTRL register to zeros) will erase all edge-detect history. Table 90. Pattern match interrupt control register (PMCTRL, address 0x4004 C028)

0 SEL_PMATCH Specifies whether the 8 pin interrupts are controlled by

1 ENA_RXEV Enables the RXEV output to the ARM cpu and/or to a

0 Disabled. RXEV output to the cpu is disabled. 1 Enabled. RXEV output to the cpu is enabled. 31:24 PMAT - This field displays the current state of pattern matches. state of the appropriate inputs. Table 91. Pattern match bit-slice source register (PMSRC, address 0x4004 C02C)

0x0 Input 0. Selects pin interrupt input 0 as the source to bit slice 0. 0x1 Input 1. Selects pin interrupt input 1 as the source to bit slice 0. 0x2 Input 2. Selects pin interrupt input 2 as the source to bit slice 0. 0x3 Input 3. Selects pin interrupt input 3 as the source to bit slice 0. 0x4 Input 4. Selects pin interrupt input 4 as the source to bit slice 0. 0x5 Input 5. Selects pin interrupt input 5 as the source to bit slice 0. 0x6 Input 6. Selects pin interrupt input 6 as the source to bit slice 0. 0x7 Input 7. Selects pin interrupt input 7 as the source to bit slice 0. 0x0 Input 0. Selects pin interrupt input 0 as the source to bit slice 1. 0x1 Input 1. Selects pin interrupt input 1 as the source to bit slice 1. 0x2 Input 2. Selects pin interrupt input 2 as the source to bit slice 1. 0x3 Input 3. Selects pin interrupt input 3 as the source to bit slice 1. 0x4 Input 4. Selects pin interrupt input 4 as the source to bit slice 1. 0x5 Input 5. Selects pin interrupt input 5 as the source to bit slice 1. 0x6 Input 6. Selects pin interrupt input 6 as the source to bit slice 1. 0x7 Input 7. Selects pin interrupt input 7 as the source to bit slice 1. 0x0 Input 0. Selects pin interrupt input 0 as the source to bit slice 2. 0x1 Input 1. Selects pin interrupt input 1 as the source to bit slice 2. 0x2 Input 2. Selects pin interrupt input 2 as the source to bit slice 2. 0x3 Input 3. Selects pin interrupt input 3 as the source to bit slice 2. 0x4 Input 4. Selects pin interrupt input 4 as the source to bit slice 2. 0x5 Input 5. Selects pin interrupt input 5 as the source to bit slice 2. 0x6 Input 6. Selects pin interrupt input 6 as the source to bit slice 2. 0x7 Input 7. Selects pin interrupt input 7 as the source to bit slice 2. 0x0 Input 0. Selects pin interrupt input 0 as the source to bit slice 3. 0x1 Input 1. Selects pin interrupt input 1 as the source to bit slice 3. 0x2 Input 2. Selects pin interrupt input 2 as the source to bit slice 3. 0x3 Input 3. Selects pin interrupt input 3 as the source to bit slice 3. 0x4 Input 4. Selects pin interrupt input 4 as the source to bit slice 3. 0x5 Input 5. Selects pin interrupt input 5 as the source to bit slice 3. 0x6 Input 6. Selects pin interrupt input 6 as the source to bit slice 3. 0x7 Input 7. Selects pin interrupt input 7 as the source to bit slice 3.

0x0 Input 0. Selects pin interrupt input 0 as the source to bit slice 4. 0x1 Input 1. Selects pin interrupt input 1 as the source to bit slice 4. 0x2 Input 2. Selects pin interrupt input 2 as the source to bit slice 4. 0x3 Input 3. Selects pin interrupt input 3 as the source to bit slice 4. 0x4 Input 4. Selects pin interrupt input 4 as the source to bit slice 4. 0x5 Input 5. Selects pin interrupt input 5 as the source to bit slice 4. 0x6 Input 6. Selects pin interrupt input 6 as the source to bit slice 4. 0x7 Input 7. Selects pin interrupt input 7 as the source to bit slice 4. 0x0 Input 0. Selects pin interrupt input 0 as the source to bit slice 5. 0x1 Input 1. Selects pin interrupt input 1 as the source to bit slice 5. 0x2 Input 2. Selects pin interrupt input 2 as the source to bit slice 5. 0x3 Input 3. Selects pin interrupt input 3 as the source to bit slice 5. 0x4 Input 4. Selects pin interrupt input 4 as the source to bit slice 5. 0x5 Input 5. Selects pin interrupt input 5 as the source to bit slice 5. 0x6 Input 6. Selects pin interrupt input 6 as the source to bit slice 5. 0x7 Input 7. Selects pin interrupt input 7 as the source to bit slice 5. 0x0 Input 0. Selects pin interrupt input 0 as the source to bit slice 6. 0x1 Input 1. Selects pin interrupt input 1 as the source to bit slice 6. 0x2 Input 2. Selects pin interrupt input 2 as the source to bit slice 6. 0x3 Input 3. Selects pin interrupt input 3 as the source to bit slice 6. 0x4 Input 4. Selects pin interrupt input 4 as the source to bit slice 6. 0x5 Input 5. Selects pin interrupt input 5 as the source to bit slice 6. 0x6 Input 6. Selects pin interrupt input 6 as the source to bit slice 6. 0x7 Input 7. Selects pin interrupt input 7 as the source to bit slice 6. 0x0 Input 0. Selects pin interrupt input 0 as the source to bit slice 7. 0x1 Input 1. Selects pin interrupt input 1 as the source to bit slice 7. 0x2 Input 2. Selects pin interrupt input 2 as the source to bit slice 7. 0x3 Input 3. Selects pin interrupt input 3 as the source to bit slice 7. 0x4 Input 4. Selects pin interrupt input 4 as the source to bit slice 7. 0x5 Input 5. Selects pin interrupt input 5 as the source to bit slice 7. 0x6 Input 6. Selects pin interrupt input 6 as the source to bit slice 7. 0x7 Input 7. Selects pin interrupt input 7 as the source to bit slice 7.

8.6.13 Pattern Match Interrupt Bit-Slice Configuration register

conditions for each bit slice that will cause that bit slice to contribute to a pattern match. This bit is only cleared when the PMCFG or the PMSRC registers are written to. bits in the PMCTRL register to zeros) will erase all edge-detect history. Table 92. Pattern match bit slice configuration re gister (PMCFG, address 0x4004 C030) bit description of a product term in the boolean expression.

1. The interrupt request associated with this bit-slice will be asserted whenever a

match to that product term is detected.

1. The next bit slice will start a new, independent product term in the boolean

element controlled by this bit slice).

7 Reserved (Bit slice 7 is automatically considered a product end point) 0

0x0 Constant 1. This bit slice always contributes to a product term match. the last time the edge detection for this bit slice was cleared. cleared when the PMCFG or the PMSRC registers are written to. cleared when the PMCFG or the PMSRC registers are written to. specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input.

0x0 Constant 1. This bit slice always contributes to a product term match. the last time the edge detection for this bit slice was cleared. cleared when the PMCFG or the PMSRC registers are written to. cleared when the PMCFG or the PMSRC registers are written to. specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input. 0x0 Constant 1. This bit slice always contributes to a product term match. the last time the edge detection for this bit slice was cleared. cleared when the PMCFG or the PMSRC registers are written to. cleared when the PMCFG or the PMSRC registers are written to. specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input. Table 92. Pattern match bit slice configuration re gister (PMCFG, address 0x4004 C030) bit description …continued

0x0 Constant 1. This bit slice always contributes to a product term match. the last time the edge detection for this bit slice was cleared. cleared when the PMCFG or the PMSRC registers are written to. cleared when the PMCFG or the PMSRC registers are written to. specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input. 0x0 Constant 1. This bit slice always contributes to a product term match. the last time the edge detection for this bit slice was cleared. cleared when the PMCFG or the PMSRC registers are written to. cleared when the PMCFG or the PMSRC registers are written to. specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input.

0x0 Constant 1. This bit slice always contributes to a product term match. the last time the edge detection for this bit slice was cleared. cleared when the PMCFG or the PMSRC registers are written to. cleared when the PMCFG or the PMSRC registers are written to. specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input. 0x0 Constant 1. This bit slice always contributes to a product term match. the last time the edge detection for this bit slice was cleared. cleared when the PMCFG or the PMSRC registers are written to. cleared when the PMCFG or the PMSRC registers are written to. specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input.

8.7 Functional description

8.7.1 Pin interrupts

interrupt, and this register can also be written to clear interrupts. pins, as described in Table 93. 0x0 Constant 1. This bit slice always contributes to a product term match. the last time the edge detection for this bit slice was cleared. cleared when the PMCFG or the PMSRC registers are written to. cleared when the PMCFG or the PMSRC registers are written to. specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input. Table 93. Pin interrupt registers fo r edge- and level-sensitive pins IENR Enables rising-edge interrupts. Enables level interrupts. SIENR Write to enable rising-edge interrupts. Write to enable level interrupts. CIENR Write to disable rising-edge interrupts. Write to disable level interrupts. IENF Enables falling-edge interrupts. Selects active level. SIENF Write to enable falling-edge interrupts. Write to select high-active. CIENF Write to disable falling-edge interrupts. Write to select low-active.

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8.7.2 Pattern Match engine example

Suppose the desired boolean pattern to be matched is: (IN1) + (IN1 * IN2) + (~IN2 * ~IN3 * IN6fe) + (IN5 * IN7ev) with: IN6fe = (sticky) falling-edge on input 6 IN7ev = (non-sticky) event (rising or falling edge) on input 7 Each individual term in the expression shown above is controlled by one bit-slice. To specify this expression, program the pattern match bit slice source and configuration register fields as follows:

• PMSRC register (Table 91): – CLR_EDGEDET: A 1 may be written to bit 5 to clear any pre-existing edge detects on bit-slice 5, if that is what is desired. – SRC0: 001 - select input 1 for bit slice 0 – SRC1: 001 - select input 1 for bit slice 1 – SRC2: 010 - select input 2 for bit slice 2 – SRC3: 010 - select input 2 for bit slice 3 – SRC4: 011 - select input 3 for bit slice 4 – SRC5: 110 - select input 6 for bit slice 5 – SRC6: 101 - select input 5 for bit slice 6 – SRC7: 111 - select input 7 for bit slice 7
• PMCTRL register (Table 90): – Bit[0]: Setting this bit will select pattern matches to generate the pin interrupts in place of the normal pin interrupt mechanism. For this example, pin interrupt 0 will be asserted when a match is detected on the first product term (which, in this case, is just a high level on input 1). Pin interrupt 2 will be asserted in response to a match on the second product term. Pin interrupt 5 will be asserted when there is a match on the third product term. Pin interrupt 7 will be asserted on a match on the last term. – Bit[1]: Setting this bit will cause the RxEv signal to the ARM CPU to be asserted whenever a match occurs on ANY of the product terms in the expression. Otherwise, the RXEV line will not be used. – Bit[31:24]: At any given time, bits 0, 2, 5 and/or 7 may be high if the corresponding product terms are currently matching. – The remaining bits will always be low.

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9.1 How to read this chapter

The switch matrix is identical for all LPC800 parts. The USART2 and SPI1 functions are only available on parts LPC812M101FDH20 and LPC812M101FDH16 and the corresponding switch matrix select bits are reserved for all other parts.

9.2 Features

• Flexible assignment of digital peripheral functions to pins
• Enable/disable of analog functions

9.3 Basic configuration

Once configured, no clocks are needed for the switch matrix to function. The system clock is needed only to write to or read from the pin assignment registers. After the switch matrix is configured, disable the clock to the switch matrix block in the SYSAHBCLKCTRL register. Before activating a peripheral or enabling its interrupt, use the switch matrix to connect the peripheral to external pins. The boot loader assigns the SWD functions to pins PIO0_2 and PIO0_3. If the user code disables the SWD functions through the switch matrix to use the pins for other functions, the SWD port is disabled. Remark: For the purpose of programming the pin functions through the switch matrix, every pin except the power and ground pins is identified in a package-independent way by its GPIO port pin number. UM10601 Chapter 9: LPC800 Switch matrix Rev. 1.0 — 7 November 2012 Preliminary user manual

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9.3.1 Connect an internal signal to a package pin

The switch matrix connects all internal signals listed in the table of movable functions through the pin assignment registers to external pins on the package. External pins are identified by their default GPIO pin number PIO0_n. Follow these steps to connect an internal signal FUNC to an external pin. An example of a movable function is the UART transmit signal TXD: 1. Find the function FUNC in the list of movable function in Table 94 or in the data sheet. 2. Use the LPC800 data sheet to decide whic h pin x on the LPC800 package to connect FUNC to. 3. Use the pin description table to find the default GPIO function PIO0_n assigned to package pin x. m is the pin number. 4. Locate the pin assignment register for the fu nction FUNC in the switch matrix register description. 5. Disable any special functions on pin PIO0_n in the PINENABLE0 register. 6. Program the pin number n into the bits assigned to FUNC. FUNC is now connected to pin x on the package.

9.3.2 Enable an analog input or other special function

The switch matrix enables functions that can only be assigned to one pin. Examples are analog inputs, all GPIO pins, and the debug SWD pins. A pin is identified for the purpose of programming the switch matrix by its default GPIO port pin. Fig 7. Example: Connect function U0_RXD and U0_TXD to pins 8 and 14 on the SO20 package /g47/g51/g38/g27/g19/g19 /g54/g50/g21/g19 /g51/g44/g50/g19/g66/g20/g26 /g51/g44/g50/g19/g66/g20/g23 /g51/g44/g50/g19/g66/g20/g22 /g51/g44/g50/g19/g66/g19/g18/g36/g38/g48/g51/g66/g44/g20/g18/g55/g39/g50 /g51/g44/g50/g19/g66/g20/g21 /g51/g44/g50/g19/g66/g25/g18/g57/g39/g39/g38/g48/g51 /g53/g40/g54/g40/g55/g18/g51/g44/g50/g19/g66/g24 /g51/g44/g50/g19/g66/g26 /g51/g44/g50/g19/g66/g23/g18/g58/g36/g46/g40/g56/g51/g18/g55/g53/g54/g55 /g57 /g54/g54 /g54/g58/g38/g47/g46/g18/g51/g44/g50/g19/g66/g22/g18/g55/g38/g46 /g57/g39/g39 /g54/g58/g39/g44/g50/g18/g51/g44/g50/g19/g66/g21/g18/g55/g48/g54 /g51/g44/g50/g19/g66/g27/g18/g59/g55/g36/g47/g44/g49 /g51/g44/g50/g19/g66/g20/g20 /g51/g44/g50/g19/g66/g28/g18/g59/g55/g36/g47/g50/g56/g55 /g51/g44/g50/g19/g66/g20/g19 /g51/g44/g50/g19/g66/g20/g18/g36/g38/g48/g51/g66/g21/g18/g38/g47/g46/g44/g49/g18/g55/g39/g44 /g51/g44/g50/g19/g66/g20/g25 /g51/g44/g50/g19/g66/g20/g24 /g20 /g21 /g22 /g23 /g24 /g25 /g26 /g27 /g28 /g20/g19 /g20/g21 /g20/g20 /g20/g23 /g20/g22 /g20/g25 /g20/g24 /g20/g27 /g20/g26 /g21/g19 /g20/g28 /g51/g44/g50/g19/g66/g27/g3/g16/g33 /g83/g76/g81/g3/g81/g88/g80/g69/g72/g85/g3/g27 /g71/g76/g86/g68/g69/g79/g72/g3/g59/g55/g36/g47/g44/g49 /g51/g44/g49/g40/g49/g36/g37/g47/g40/g19/g3/g69/g76/g87/g3/g23/g3/g32/g3/g20 /g68/g86/g86/g76/g74/g81/g3/g41/g56/g49/g38/g3/g32/g3/g56/g19/g66/g55/g59/g39 /g51/g44/g49/g36/g54/g54/g44/g42/g49/g19/g3/g69/g76/g87/g86/g3/g26/g29/g19/g3/g32/g3/g19/g91/g27 /g73/g88/g81/g70/g87/g76/g82/g81/g3/g56/g19/g66/g55/g59/g39/g3 /g68/g86/g86/g76/g74/g81/g72/g71/g3/g87/g82/g3/g54/g50/g21/g19/g3/g83/g68/g70/g78/g68/g74/g72 /g83/g76/g81/g3/g20/g23 /g51/g44/g50/g19/g66/g20/g25/g3/g16/g33 /g83/g76/g81/g3/g81/g88/g80/g69/g72/g85/g3/g20/g25 /g68/g86/g86/g76/g74/g81/g3/g41/g56/g49/g38/g3/g32/g3/g56/g19/g66/g53/g59/g39 /g51/g44/g49/g36/g54/g54/g44/g42/g49/g19/g3/g69/g76/g87/g86/g3/g20/g24/g29/g27/g3/g32/g3/g19/g91/g20/g19 /g73/g88/g81/g70/g87/g76/g82/g81/g3/g56/g19/g66/g53/g59/g39/g3 /g68/g86/g86/g76/g74/g81/g72/g71/g3/g87/g82/g3/g54/g50/g21/g19/g3/g83/g68/g70/g78/g68/g74/g72 /g83/g76/g81/g3/g20/g19/g3

• If you want to assign a GPIO pin to a pin on any LPC800 package, disable any special function available on this pin in the PINENABLE0 register and do not assign any movable function to it. By default, all pins except pins PIO0_2, PIO0_3, and PIO0_5 are assigned to GPIO.
• For all other functions that are not in the table of movable functions, do the following: a. Locate the function in the pin description table in the data sheet. This shows the package pin for this function. b. Enable the function in the PINENABLE0 re gister. All other possible functions on this pins are now disabled.

9.4 General description

must be connected to external pins. pin that is not a power or ground pin. These functions are called movable functions. function is not used, it can be replaced by any other movable function. GPIOs are fixed-pin functions. Each GPIO is assigned to one and only one external pin. identified by their fixed-pin GPIO function.

9.4.1 Movable functions

Table 94. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix)

9.4.2 Switch matrix register interface

want the function to connect to. registers, are numbered 0 to 17.

1. Movable functions (PINASSIGN0 to 8):

Remark: You can assign more than one digital input function to one external pin.

1. Fixed-pin functions (PINENABLE0):

of fixed-pin functions are the oscillator pins or comparator inputs. selects or deselects the function. – On reset, all fixed-pin functions are deselected.

9.5 Register description

Table 95. Register overview: Switch matrix (base address 0x4000 C000)

9.5.1 Pin assign register 0

9.5.2 Pin assign register 1

Table 95. Register overview: Switch matrix (base address 0x4000 C000) …continued Table 96. Pin assign register 0 (PINASSIGN0, address 0x4000 C000) bit description Table 97. Pin assign register 1 (PINASSIGN1, address 0x4000 C004) bit description

9.5.3 Pin assign register 2

9.5.4 Pin assign register 3

9.5.5 Pin assign register 4

Table 98. Pin assign register 2 (PINASSIGN2, address 0x4000 C008) bit description Table 99. Pin assign register 3 (PINASSIGN3, address 0x4000 C00C) bit description Table 100. Pin assign register 4 (PINASSIGN4, address 0x4000 C010) bit description

9.5.6 Pin assign register 5

9.5.7 Pin assign register 6

Table 101. Pin assign register 5 (PINASSIGN5, address 0x4000 C014) bit description Table 102. Pin assign register 6 (PINASSIGN6, address 0x4000 C018) bit description

9.5.8 Pin assign register 7

9.5.9 Pin assign register 8

9.5.10 Pin enable register 0

Table 103. Pin assign register 7 (PINASSIGN7, address 0x4000 C01C) bit description Table 104. Pin assign register 8 (PINASSIGN8, address 0x4000 C020) bit description pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). Table 105. Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description and GPIO is assigned to this pin. 0 Enable ACMP_I1. This func tion is enabled on pin PIO0_0. can be assigned to pin PIO0_0.

register and enable ACMP_I2. 0 Enable ACMP_I2. This func tion is enabled on pin PIO0_1. can be assigned to pin PIO0_1. function can be assigned to this pin. This function is selected by default. 0 Enable SWCLK. This function is enabled on pin PIO0_3. function can be assigned to pin PIO0_3. function can be assigned to this pin. This function is selected by default. 0 Enable SWDIO. This function is enabled on pin PIO0_2. function can be assigned to pin PIO0_2. and GPIO is assigned to this pin. 0 Enable XTALIN. This function is enabled on pin PIO0_8. can be assigned to pin PIO0_8. and GPIO is assigned to this pin. 0 Enable XTALOUT. This function is enabled on pin PIO0_9. can be assigned to pin PIO0_9. function can be assigned to this pin. This function is selected by default. 0 Enable RESET . This function is enabled on pin PIO0_5. function can be assigned to pin PIO0_5. 0 Enable CLKIN. This function is enabled on pin PIO0_1.

and GPIO is assigned to this pin. 0 Enable VDDCMP. This function is enabled on pin PIO0_6. can be assigned to pin PIO0_6.

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 111 of 313

10.1 How to read this chapter

The SCT is available on all LPC800 parts.

10.2 Features

• Two 16-bit counters or one 32-bit counter.
• Counters clocked by bus clock or selected input.
• Up counters or up-down counters.
• State variable allows sequencing across multiple counter cycles.
• The following conditions define an event: a counter match condition, an input (or output) condition, a combination of a match and/or and input/output condition in a specified state, and the count direction.
• Events control outputs, interrupts, and the SCT states. – Match register 0 can be used as an automatic limit. – In bi-directional mode, events can be enabled based on the count direction. – Match events can be held until another qualifying event occurs.
• Selected events can limit, halt, start, or stop a counter.
• Supports: – 4 inputs – 4 outputs – 5 match/capture registers – 6 events – 2 states

10.3 Basic configuration

Configure the SCT as follows:

• Use the SYSAHBCLKCTRL register (Table 18) to enable the clock to the SCT register interface and peripheral clock. The LPC800 system clock is the input clock to the SCT clock processing and is the source of the SCT clock.
• Clear the SCT peripheral reset using the PRESETCTRL register (Table 7).
• The SCT combined interrupt is connected to slot #8 in the NVIC.
• Use the switch matrix to connect the SCT inputs and outputs to pins (see Section 10.4).

10.3.1 Use the SCT as a simple timer

To configure the SCT as a simple timer with match or capture functionality, follow these steps: UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) Rev. 1.0 — 7 November 2012 Preliminary user manual

1. Set up the SCT as one 32-bit timer or one or two 16-bit timers. See Table 108.
2. Preload the 32-bit timer or the 16-bit timers with a count value. See Table 114.
3. If you want to cr eate a match event when the timer reaches a match value:

a. Configure the register map for match registers. See Table 117. b. Configure one or more match registers with a match value. See Table 125. c. For each match value, cr eate a match event. See Table 130. d. If you want to create an interrupt on a match event, enable the event for interrupt.

1. If you want to capture a timer value on a capture signal:

a. Configure the register map for capture registers. See Table 117. b. Create one or more capture events. See Table 130. create an event. See Table 130.

1. Start the timer by writing to the CRTL register. See Table 109.
2. Read the capture registers to read the timer value at the time of the capture events.

10.4 Pin description

functions to pins on the LPC800 package.

10.5 General description

modulation, and input capture operations. Table 106. SCT pin description

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 113 of 313 NXP Semiconductors UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) The most basic user-programmable option is whether a SCT operates as two 16-bit counters or a unified 32-bit counter. In the two-counter case, in addition to the counter value the following operational elements are independent for each half:

• State variable
• Limit, halt, stop, and start conditions
• Values of Match/Capture registers, plus reload or capture control values In the two-counter case, the following operational elements are global to the SCT:
• Clock selection
• Inputs
• Events
• Outputs
• Interrupts Events, outputs, and interrupts can use match conditions from either counter. Remark: In this chapter, the term bus error indicates an SCT response that makes the processor take an exception. Fig 8. SCT block diagram /g83/g85/g72/g86/g70/g68/g79/g72/g85/g11/g86/g12 /g54/g38/g55/g3/g70/g79/g82/g70/g78/g86/g92/g86/g87/g72/g80/g3/g70/g79/g82/g70/g78

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 114 of 313 NXP Semiconductors UM10601 Chapter 10: LPC800 State Configurable Timer (SCT)

10.6 Register description

The register addresses of the State Configurable Timer are shown in Table 107. For most of the SCT registers, the register function depends on the setting of certain other register bits: 1. The UNIFY bit in the CONFIG register de termines whether the SCT is used as one 32-bit register (for operation as one 32-bit counter/timer) or as two 16-bit counter/timers named L and H. The setting of the UNIFY bit is reflected in the register map: – UNIFY = 1: Only one register is used (for operation as one 32-bit counter/timer). – UNIFY = 0: Access the L and H registers by a 32-bit read or write operation or can be read or written to individually (for operation as two 16-bit counter/timers). Typically, the UNIFY bit is configured by writing to the CONFIG register before any other registers are accessed. 2. The REGMODEn bits in the REGMODE register determine whether each set of Match/Capture registers uses the match or capture functionality: – REGMODEn = 1: Registers operate as match and reload registers. – REGMODEn = 0: Registers operate as capture and capture control registers. Fig 9. SCT counter and select logic /g54/g38/g55/g3/g70/g79/g82/g70/g78/g86/g92/g86/g87/g72/g80/g3/g70/g79/g82/g70/g78 /g56/g81/g76/g73/g76/g72/g71 /g70/g82/g88/g81/g87/g72/g85 /g47/g3/g70/g82/g88/g81/g87/g72/g85 /g43/g3/g70/g82/g88/g81/g87/g72/g85 /g83/g85/g72/g86/g70/g68/g79/g72/g85 /g83/g85/g72/g86/g70/g68/g79/g72/g85

Table 107. Register overview: State Configurable Timer (base address 0x5000 4000)

Table 107. Register overview: State Configurable Timer (base address 0x5000 4000) …continued

10.6.1 SCT configuration register

Table 108. SCT configuration register (CON FIG, address 0x5000 4000) bit description

0 UNIFY SCT operation 0

0 The SCT operates as two 16-bit counters named L and H. 1 The SCT operates as a unified 32-bit counter. 0x0 The bus clock clocks the SCT and prescalers. mode is the high-performance sampled-clock mode. 0x0 Rising edges on input 0. 0x1 Falling edges on input 0. 0x2 Rising edges on input 1. 0x3 Falling edges on input 1. 0x4 Rising edges on input 2. 0x5 Falling edges on input 2. 0x6 Rising edges on input 3. 0x7 Falling edges on input 3.

7 NORELAOD_L - A 1 in this bit prevents the lower match registers from being reloaded from their

8 NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their

time. This bit is not used when the UNIFY bit is set.

10.6.2 SCT control register

If UNIFY = 1 in the CONFIG register, only the _L bits are used. a single 32-bit read or write operation. 16:9 INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). the SCT clock, keep its bit 0 for faster response. selected by the CKSEL field, is not used.

17 AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto

LIMIT condition without the need to define an associated event. higher and lower registers when the UNIFY bit is set.

18 AUTOLIMIT_H - A one in this bit will cause a ma tch on match register 0 to be treated as a

de-facto LIMIT condition without the need to define an associated event. Table 108. SCT configuration register (CON FIG, address 0x5000 4000) bit description …continued Table 109. SCT control register (CTRL, address 0x5000 4004) bit description counter is counting down and a limit condition occurs or when the counter reaches 0.

1 STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events

register, this bit is cleared and counting resumes. Remark: Once set, only software can clear this bit to restore counter operation.

10.6.3 SCT limit register

If UNIFY = 1 in the CONFIG register, only the _L bits are used. a single 32-bit read or write operation. SCT limit register has occurred.

4 BIDIR_L L or unified counter direction select 0

0 The counter counts up to its limit condition, then is cleared to zero. 1 The counter counts up to its limit, then counts down to a limit condition or to 0. counting down and a limit condition occurs or when the counter reaches 0.

17 STOP_H - When this bit is 1 and HALT is 0, th e H counter does not, run but I/O events related

bit is cleared and counting resumes. you can change the halt and stop condition with one single write to this register.

20 BIDIR_H Direction select 0

0 The H counter counts up to its limit condition, then is cleared to zero. 1 The H counter counts up to its limit, then counts down to a limit condition or to 0. clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1.

occurs. This eliminates the need to define an event for the sole purpose of creating a limit.

10.6.4 SCT halt condition register

If UNIFY = 1 in the CONFIG register, only the _L bits are used. single 32-bit read or write operation.

10.6.5 SCT stop condition register

If UNIFY = 1 in the CONFIG register, only the _L bits are used. in a single 32-bit read or write operation. Table 110. SCT limit register (LIMIT, address 0x5000 4008) bit description counter (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20). Table 111. SCT halt condition register (HALT, address 0x5004 400C) bit description (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5).

10.6.6 SCT start condition register

If UNIFY = 1 in the CONFIG register, only the _L bits are used. in a single 32-bit read or write operation.

10.6.7 SCT counter register

independently under the control of the other registers. bus error. Software can read the counter registers at any time. Table 112. SCT stop condition register (S TOP, address 0x5000 4010) bit description (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). Table 113. SCT start condition register (START, address 0x5000 4014) bit description register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20).

10.6.8 SCT state register

If UNIFY = 1 in the CONFIG register, only the _L bits are used. in a single 32-bit read or write operation. the state and results in a bus error.

• set and clear outputs
• limit, stop, and start the counter
• cause interrupts
• modify the state variable The value of a state variable is completely under the control of the application. If an application does not use states, the value of the state variable remains zero, which is the default value. A state variable can be used to track and control multiple cycles of the associated counter in any desired operational sequence. The state variable is logically associated with a state machine diagram which represents the SCT configuration. See Section 10.6.22 and 10.6.23 for more about the relationship between states and events. The STATELD/STADEV fields in the event control registers of all defined events set all possible values for the state variable. The change of the state variable during multiple counter cycles reflects how the associated state machine moves from one state to the next.

Table 114. SCT counter register (COUNT, address 0x5000 4040) bit description Table 115. SCT state register (STATE, address 0x5000 4044) bit description

10.6.9 SCT input register

10.6.10 SCT match/capture registers mode register

match/capture registers, and the _H bits/registers control the H match/capture registers. register (Section 10.6.21). REGMODE_H is used only when the UNIFY bit is 0. Table 116. SCT input register (INPUT, address 0x5000 4048) bit description

10.6.11 SCT output register

The SCT supports 4 outputs, each of which has a corresponding bit in this register. not affect the outputs and results in an bus error. Software can read this register at any time to sense the state of the outputs.

10.6.12 SCT bidirectional output control register

Table 117. SCT match/capture registers mode register (REGMODE, address 0x5000 404C) bit 0, register 1 = bit 1,..., register 4 = bit 4). 0 = registers operate as match registers. 1 = registers operate as capture registers. bit 16, register 1 = bit 17,..., register 4 = bit 19). 0 = registers operate as match registers. 1 = registers operate as capture registers. Table 118. SCT output register (OUTPUT, address 0x5000 4050) bit description Table 119. SCT bidirectional output control register (OUTPUTDIRCTRL, address 0x5000 4054) bit description 0x0 Set and clear do not depend on any counter. 0x1 Set and clear are reversed when counte r L or the unified counter is counting down. 0x2 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x0 Set and clear do not depend on any counter. 0x1 Set and clear are reversed when counte r L or the unified counter is counting down. 0x2 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.

10.6.13 SCT conflict resolution register

same event. This SCT conflict resolution register resolves this conflict. set the event bits in both the Set and Clear registers. 0x0 Set and clear do not depend on any counter. 0x1 Set and clear are reversed when counte r L or the unified counter is counting down. 0x2 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x0 Set and clear do not depend on any counter. 0x1 Set and clear are reversed when counte r L or the unified counter is counting down. 0x2 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Table 120. SCT conflict resolution register (RES, address 0x5000 4058) bit description 0x1 Set output (or clear based on the SETCLR0 field). 0x2 Clear output (or set based on the SETCLR0 field). 0x1 Set output (or clear based on the SETCLR1 field). 0x2 Clear output (or set based on the SETCLR1 field). 0x1 Set output (or clear based on the SETCLR2 field). 0x2 Clear output n (or set based on the SETCLR2 field). 0x1 Set output (or clear based on the SETCLR3 field). 0x2 Clear output (or set based on the SETCLR3 field).

10.6.14 SCT flag enable register

register (Section 10.6.15) is also set.

10.6.15 SCT event flag register

and negates the SCT interrupt request if all enabled Flag bits are zero.

10.6.16 SCT conflict enable register

resolution register to request an IRQ.

10.6.17 SCT conflict flag register

negates the SCT interrupt request if all enabled Flag bits are zero. Table 121. SCT flag enable register (EVEN, address 0x5000 40F0) bit description this bit (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5). Table 123. SCT conflict enable register (CONEN, address 0x5000 40F8) bit description

10.6.18 SCT match registers 0 to 4 (REGMODEn bit = 0)

10.6.19 SCT capture register s 0 to 4 (REGMODEn bit = 1)

the corresponding Capture Control registers occurred. Table 124. SCT conflict flag register (CON FLAG, address 0x5000 40FC) bit description output 1 = bit 1,..., output 3 = bit 3).

30 BUSERRL The most recent bus error from this SCT involved writing CTR

31 BUSERRH The most recent bus error from this SCT involved writing CTR

Table 125. SCT match registers 0 to 4 (MATCH[0:4], address 0x5000 4100 (MATCH0) to bits of the 32-bit value to be compared to the unified counter. bits of the 32-bit value to be compared to the unified counter.

10.6.20 SCT match reload regist ers 0 to 4 (REGMODEn bit = 0)

10.6.21 SCT capture control regi sters 0 to 4 (REGMODEn bit = 1)

If UNIFY = 1 in the CONFIG register, only the _L bits are used. individually or in a single 32-bit read or write operation. corresponding Capture register from the counter. Table 126. SCT capture registers 0 to 4 (CAP [0:4], address 0x5000 4100 (CAP0) to 0x5000 of the 32-bit value at which this register was last captured. of the 32-bit value at which this register was last captured. Table 127. SCT match reload registers 0 to 4 (MATCHREL[0:4], address 0x5000 4200 bits of the 32-bit value to be loaded into the MATCHn register.

10.6.22 SCT event state mask registers 0 to 5

corresponding EVn_CTRL register. regardless of the current state. In simple applications that do not use states, write 0x01 to this register to enable an event.

10.6.23 SCT event cont rol registers 0 to 5

register. The other possible ingredient of an event is a selected input or output signal. bi-directional mode, events can also be enabled based on the direction of count. simultaneously occurring events all take place. Table 129. SCT event state mask registers 0 to 5 (EV[0:5]_STATE, addresses 0x5000 4300 Table 130. SCT event control register 0 to 5 (EV[0:5]_CTRL, address 0x5000 4304 (EV0_CTRL) to 0x5000 432C when the counter selected by the HEVENT bit is running.

0 Selects the L state and the L matc h register selected by MATCHSEL. 1 Selects the H state and the H matc h register selected by MATCHSEL.

5 OUTSEL Input/output select 0

0 Selects the inputs elected by IOSEL. 1 Selects the outputs selected by IOSEL. Bit 6 = 1: CTIN1/CTOUT0 selected. Bit 7 = 1: CTIN1/CTOU1 selected. Bit 8 = 1: CTIN2/CTOUT2 selected. BIt 9 = 1: CTIN3/CTOUT3 selected. 13:12 COMBMODE Selects how the specified matc h and I/O condition are used and combined. 0x0 OR. The event occurs when either the specified match or I/O condition occurs. 0x1 MATCH. Uses the specified match only. 0x2 IO. Uses the specified I/O condition only.

14 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when

this event is the highest-numbered event occurring for that state. 0 STATEV value is added into STATE (the carry-out is ignored). 1 STATEV value is loaded into STATE. STATELD and STATEV are both zero, there is no change to the STATE value.

20 MATCHMEM If this bit is one and the COMBMO DE field specifies a match component to the

when counting up, LESS THEN OR EQUAL TO the match value when counting down.

10.6.24 SCT output se t registers 0 to 3

10.6.25 SCT output clear registers 0 to 3

0x0 Direction independent. This event is tr iggered regardless of the count direction. 0x1 Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x2 Counting down. This event is triggered only during down-counting when BIDIR = 1. Table 131. SCT output set register (OUT[0:3]_SET, address 0x5000 4500 (OUT0_SET) to Table 132. SCT output clear register (OUT[0 :3]_CLR, address 0x5000 0504 (OUT0_CLR) to

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10.7 Functional description

10.7.1 Match logic

10.7.2 Capture logic

10.7.3 Event selection

State variables allow control of the SCT across more than one cycle of the counter. Counter matches, input/output edges, and state values are combined into a set of general-purpose events that can switch outputs, request interrupts, and change state values. Fig 10. Match logic /g32 /g38/g82/g88/g81/g87/g72/g85/g3/g47 /g38/g82/g88/g81/g87/g72/g85/g3/g43 /g48/g68/g87/g70/g75/g3/g76/g3/g43/g48/g68/g87/g70/g75 /g53/g72/g74/g3/g76/g3/g43 /g48/g68/g87/g70/g75 /g53/g72/g79/g82/g68/g71/g3 /g76/g3/g43 /g32/g48/g68/g87/g70/g75 /g53/g72/g74/g3/g76/g3/g47 /g48/g68/g87/g70/g75 /g53/g72/g79/g82/g68/g71/g3 /g76/g3/g47 /g48/g68/g87/g70/g75/g3/g76/g3/g47 /g56/g49/g44/g41/g60 Fig 11. Capture logic /g3 /g54/g38/g55/g3/g70/g79/g82/g70/g78

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10.7.4 Output generation

Figure 13 shows one output slice of the SCT.

10.7.5 Interrupt generation

The SCT generates one interrupt to the NVIC. Fig 12. Event selection /g86/g72/g79/g72/g70/g87 /g72/g89/g72/g81/g87/g3/g179/g76/g180/g86/g72/g79/g72/g70/g87 /g48/g36/g55/g38/g43/g54/g40/g47/g76 /g76/g81/g83/g88/g87/g86 /g44/g50/g54/g40/g47/g76 /g86/g72/g79/g72/g70/g87/g54/g55/g36/g55/g40/g48/g36/g54/g46/g76 /g38/g50/g48/g37/g48/g50/g39/g40/g76 /g44/g50/g38/g50/g49/g39/g76 /g82/g88/g87/g83/g88/g87/g86 /g50/g56/g55/g54/g40/g47/g76 /g43/g40/g57/g40/g49/g55/g76 /g43/g3/g54/g55/g36/g55/g40 /g47/g3/g54/g55/g36/g55/g40 /g43/g3/g80/g68/g87/g70/g75/g72/g86 /g47/g3/g80/g68/g87/g70/g75/g72/g86 Fig 13. Output slice i /g54/g72/g87/g3 /g85/g72/g74/g76/g86/g87/g72/g85/g3/g179/g76/g180 /g38/g79/g72/g68/g85/g3 /g85/g72/g74/g76/g86/g87/g72/g85/g3/g179/g76/g180 /g50/g56/g55/g3 /g85/g72/g74/g54/g72/g79/g72/g70/g87 /g40/g89/g72/g81/g87/g86 /g50/g88/g87/g83/g88/g87/g3/g179/g76/g180 /g49/g82/g38/g75/g68/g81/g74/g72/g38/g82/g81/g73/g79/g76/g70/g87/g3/g179/g76/g180 /g50/g76/g53/g40/g54 /g54/g40/g55/g38/g47/g53/g76 /g54/g38/g55/g3/g70/g79/g82/g70/g78 Fig 14. SCT interrupt generation /g40/g81/g68/g69/g79/g72 /g85/g72/g74/g76/g86/g87/g72/g85 /g40/g89/g72/g81/g87/g86 /g41/g79/g68/g74/g86 /g85/g72/g74/g76/g86/g87/g72/g85 /g49/g82/g3/g38/g75/g68/g81/g74/g72/g3 /g38/g82/g81/g73/g79/g76/g70/g87/g3/g72/g89/g72/g81/g87/g86 /g54/g38/g55/g3/g76/g81/g87/g72/g85/g85/g88/g83/g87 /g38/g82/g81/g73/g79/g76/g70/g87/g3 /g40/g81/g68/g69/g79/g72 /g85/g72/g74/g76/g86/g87/g72/g85 /g38/g82/g81/g73/g79/g76/g70/g87 /g41/g79/g68/g74/g86 /g85/g72/g74/g76/g86/g87/g72/g85

10.7.6 Clearing the prescaler

• Hardware reset
• Software writing to the counter register
• Software writing a 1 to the CLRCTR bit in the control register
• an event selected by a 1 in the counter limit register when BIDIR = 0 When BIDIR is 0, a limit event caused by an I/O signal can clear a non-zero prescaler. However, a limit event caused by a Match only clears a non-zero prescaler in one special case as described Section 10.7.7. A limit event when BIDIR is 1 does not clear the prescaler. Rather it clears the DOWN bit in the Control register, and decrements the counter on the same clock if the counter is enabled in that clock. 10.7.7 Match vs. I/O events Counter operation is complicated by the prescaler and by clock mode 01 in which the SCT clock is the bus clock. However, the prescaler and counter are enabled to count only when a selected edge is detected on a clock input.
• The prescaler is enabled when the clock mode is not 01, or when the input edge selected by the CLKSEL field is detected.
• The counter is enabled when the prescaler is enabled, and (PRELIM=0 or the prescaler is equal to the value in PRELIM). An I/O component of an event can occur in any SCT clock when its counter HALT bit is 0. In general, a Match component of an event can only occur in a UT clock when its counter HALT and STOP bits are both 0 and the counter is enabled. Table 133 shows when the various kinds of events can occur.

Table 133. Event conditions IO Any Event can occur whenever HALT = 0 (type A). OR Any From the IO component: Event can occur whenever HALT = 0 (A). STOP = 0 and the counter is enabled (C). AND RISE or FALL Event can occur whenever HALT = 0 (A).

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10.7.8 SCT operation

In its simplest, single-state configuration, the SCT operates as an event controlled one- or bidirectional counter. Events can be configured to be counter match events, an input or output level, transitions on an input or output pin, or a combination of match and input/output behavior. In response to an event, the SCT output or outputs can transition, or the SCT can perform other actions such as creating an interrupt or starting, stopping, or resetting the counter. Multiple simultaneous actions are allowed for each event. Furthermore, any number of events can trigger one specific action of the SCT. An action or multiple actions of the SCT uniquely define an event. A state is defined by which events are enabled to trigger an SCT action or actions in any stage of the counter. Events not selected for this state are ignored. In a multi-state configuration, states change in response to events. A state change is an additional action that the SCT can perform when the event occurs. When an event is configured to change the state, the new state defines a new set of events resulting in different actions of the SCT. Through multiple cycles of the counter, events can change the state multiple times and thus create a large variety of event controlled transitions on the SCT outputs and/or interrupts. Once configured, the SCT can run continuously without software intervention and can generate multiple output patterns entirely under the control of events.

• To configure the SCT, see Section 10.7.9.
• To start, run, and stop the SCT, see Section 10.7.10.
• To configure the SCT as simple event controlled counter/timer, see Section 10.7.11.

10.7.9 Configure the SCT

To set up the SCT for multiple events and states, perform the following configuration steps:

10.7.9.1 Configure the counter

1. Configure the L and H counters in the CO NFIG register by selecting two independent 16-bit counters (L counter and H counter) or one combined 32-bit counter in the UNIFY field. 2. Select the SCT clock sour ce in the CONFIG register (fields CLKMODE and CLKSEL) from any of the inputs or an internal clock.

10.7.9.2 Configure the match and capture registers

1. Select how many match and capture registers the application uses (total of up to 5): – In the REGMODE register, select for each of the 5 match/capture register pairs whether the register is used as a match register or capture register. 2. Define match conditions for each match register selected: – Each match register MATCH sets one match value, if a 32-bit counter is used, or two match values, if the L and H 16-bit counters are used. – Each match reload register MATCHRELOAD sets a reload value that is loaded into the match register when the counter reaches a limit condition or the value 0.

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10.7.9.3 Configure events and event responses

1. Define when each event can occur in the following way in the EVn_CTRL registers (up to 6, one register per event): – Select whether the event occurs on an input or output changing, on an input or output level, a match condition of the counter, or a combination of match and input/output conditions in field COMBMODE. – For a match condition: Select the match register that contains the match condition for the event to occur. Enter the number of the selected match register in field MATCHSEL. If using L and H counters, define whether the event occurs on matching the L or the H counter in field HEVENT. – For an SCT input or output level or transition: Select the input number or the output number that is associated with this event in fields IOSEL and OUTSEL. Define how the selected input or output triggers the event (edge or level sensitive) in field IOCOND. 2. Define what the effect of each event is on the SCT outputs in the OUTn_SET or OUTn_CLR registers (up to 4 outputs, one register per output): – For each SCT output, select which events set or clear this output. More than one event can change the output, and each event can change multiple outputs. 3. Define how each event affects the counter: – Set the corresponding event bit in the LIMIT register for the event to set an upper limit for the counter. When a limit event occurs in unidirectional mode, the counter is cleared to zero and begins counting up on the next clock edge. When a limit event occurs in bidirectional mode, the counter begins to count down from the current value on the next clock edge. – Set the corresponding event bit in the HALT register for the event to halt the counter. If the counter is halted, it stops counting and no new events can occur. The counter operation can only be restored by clearing the HALT_L and/or the HALT_H bits in the CTRL register. – Set the corresponding event bit in the STOP register for the event to stop the counter. If the counter is stopped, it stops counting. However, an event that is configured as a transition on an input/output can restart the counter. – Set the corresponding event bit in the START register for the event to restart the counting. Only events that are defined by an input changing can be used to restart the counter. 4. Define which events contribute to the SCT interrupt: – Set the corresponding event bit in the EVEN and the EVFLAG registers to enable the event to contribute to the SCT interrupt.

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10.7.9.4 Configure multiple states

1. In the EVn_STATE register for each event (up to 6 events, one register per event), select the state or states (up to 2) in which this event is allowed to occur. Each state can be selected for more than one event. 2. Determine how the event affects the system state: In the EVn_CTRL registers (up to 6 events, one register per event), set the new state value in the STATEV field for this event. If the event is the highest numbered in the current state, this value is either added to the existing state value or replaces the existing state value, depending on the field STATELD. Remark: If there are higher numbered events in the current state, this event cannot change the state. If the STATEV and STATELD values are set to zero, the state does not change.

10.7.9.5 Miscellaneous options

• There are a certain (selectable) number of capture registers. Each capture register can be programmed to capture the counter contents when one or more events occur.
• If the counter is in bidirectional mode, the effect of set and clear of an output can be made to depend on whether the counter is counting up or down by writing to the OUTPUTDIRCTRL register.

10.7.10 Run the SCT

1. Configure the SCT (see Section 10.7.9 “Configure the SCT”). 2. Write to the STATE register to define the initial state. By default the initial state is state 3. To start the SCT, write to the CTRL register: – Clear the counters. – Clear or set the STOP_L and/or STOP_H bits. Remark: The counter starts counting once the STOP bit is cleared as well. If the STOP bit is set, the SCT waits instead for an event to occur that is configured to start the counter. – For each counter, select unidirectional or bidirectional counting mode (field BIDIR_L and/or BIDIR_H). – Select the prescale factor for the counter clock (CTRL register). – Clear the HALT_L and/or HALT_H bit. By default, the counters are halted and no events can occur. 4. To stop the counters by software at any time, stop or halt the counter (write to STOP_L and/or STOP_H bits or HALT_L and/or HALT_H bits in the CTRL register). – When the counters are stopped, both an event configured to clear the STOP bit or software writing a zero to the STOP bit can start the counter again. – When the counter are halted, only a software write to clear the HALT bit can start the counter again. No events can occur. – When the counters are halted, software can set any SCT output HIGH or LOW directly by writing to the OUT register.

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10.7.11 Configure the SC T without using states

The SCT can be used as standard counter/timer with external capture inputs and match outputs without using the state logic. To operate the SCT without states, configure the SCT as follows:

• Write zero to the STATE register (zero is the default).
• Write zero to the STATELD and STATEV fields in the EVCTRL registers for each event.
• Write 0x1 to the EVn_STATE register of each event. Writing 0x1 enables the event. In effect, the event is allowed to occur in a single state which never changes while the counter is running.

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11.1 How to read this chapter

The MRT is available on all LPC800 parts.

11.2 Features

• 24-bit interrupt timer
• Four channels independently counting down from individually set values
• Repeat and one-shot interrupt modes

11.3 Basic configuration

Configure the MRT using the following registers:

• In the SYSAHBCLKCTRL register, set bit 10 (Table 18) to enable the clock to the register interface.
• Clear the MRT reset using the PRESETCTRL register (Table 7).
• The global MRT interrupt is connected to interrupt #10 in the NVIC.

11.4 Pin description

The MRT has no configurable pins.

11.5 General description

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each channel can be programmed with an independent time interval. Each channel operates independently from the other channels in one of the following modes:

• Repeat interrupt mode. See Section 11.5.1.
• One-shot interrupt mode. See Section 11.5.2. The modes for each timer are set in the timer’s control register. See Table 137. UM10601 Chapter 11: LPC800 Multi-Rate Timer (MRT) Rev. 1.0 — 7 November 2012 Preliminary user manual

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11.5.1 Repeat interrupt mode

The repeat interrupt mode generates repeated interrupts after a selected time interval. This mode can be used for software-based PWM or PPM applications. When the timer n is in idle state, writing a non-zero value IVALUE to the INTVALn register immediately loads the time interval value IVALUE - 1, and the timer begins to count down from this value. When the timer reaches zero, an interrupt is generated, the value in the INTVALn register IVALUE - 1 is reloaded automatically, and the timer starts to count down again. While the timer is running in repeat interrupt mode, you can perform the following actions:

• Change the interval value on the next timer cycle by writing a new value (>0) to the INTVALn register and setting the LOAD bit to 0. An interrupt is generated when the timer reaches zero. On the next cycle, the timer counts down from the new value.
• Change the interval value on-the-fly immediately by writing a new value (>0) to the INTVALn register and setting the LOAD bit to 1. The timer immediately starts to count down from the new timer interval value. An interrupt is generated when the timer reaches 0.
• Stop the timer at the end of time interval by writing a 0 to the INTVALn register and setting the LOAD bit to 0. An interrupt is generated when the timer reaches zero.
• Stop the timer immediately by writing a 0 to the INTVALn register and setting the LOAD bit to 1. No interrupt is generated when the INTVALn register is written. Fig 15. MRT block diagram /g37/g56/g54 /g16/g20/g3/g39/g40/g38 /g54/g55/g36/g55 /g44/g53/g52/g66/g42/g40/g49 /g55/g44/g48/g40/g53 /g38/g50/g49/g55/g53/g50/g47 /g61/g40/g53/g50/g54 /g3 /g44/g49/g55/g57/g36/g47 /g48/g56/g59 /g38/g43/g36/g49/g49/g40/g47/g19 /g38/g43/g36/g49/g49/g40/g47/g62/g20/g29/g22/g64 /g44/g53/g52/g19 /g44/g53/g52/g62/g20/g29/g22/g64 /g39/g52 /g39/g52

11.5.2 One-shot interrupt mode

• Update the INTVALn register with a new time interval value (>0) and set the LOAD bit to 1. The timer immediately reloads the new time interval, and starts counting down from the new value. No interrupt is generated when the TIME_INTVALn register is updated.
• Write a 0 to the INTVALn register and set the LOAD bit to 1. The timer immediately stops counting and moves to the idle state. No interrupt is generated when the INTVALn register is updated.

11.6 Register description

The reset values shown in Table 134 are POR reset values. Table 134. Register overview: MRT (base address 0x4000 4000) loaded into the TIMER0 register.

0 Table 135

0 Table 137

loaded into the TIMER1 register. loaded into the TIMER2 register.

11.6.1 Time interval register

loaded into the TIMER3 register. number of the first idle channel.

0 Table 139

Table 135. Time interval register (INTVAL[0:3], address 0x4000 4000 (INTVAL0) to 0x4000 starts the timer immediately.

• If LOAD = 1, the timer stops immediately.
• If LOAD = 0, the timer stops at the end of the time interval. 30:24 - Reserved. 0

31 LOAD Determines how the timer interval value IVALUE -1 is

loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. if the repeat mode is selected.

11.6.2 Timer register

The timer register holds the current timer value. This register is read-only.

11.6.3 Control register

The control register configures the the mode for each MRT and enables the interrupt. Table 136. Timer register (TIMER[0:3], address 0x4000 4004 (TIMER0) to 0x4000 4034 INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. Table 137. Control register (CTRL[0:3], address 0x4000 4008 (CTRL0) to 0x4000 4038 0x1 One-shot interrupt mode.

11.6.4 Status register

This register indicates the status of each MRT.

11.6.5 Idle channel register

considered idle when both flags is the STATUS register (RUN and INTFLAG) are zero. Table 138. Status register (STAT[0:3], address 0x4000 400C (STAT0) to 0x4000 403C (STAT3)) Writing a 1 to this bit clears the interrupt request. 0 Idle state. TIMERn is stopped. 1 Running. TIMERn is running. Table 139. Idle channel register (IDLE_ CH, address 0x4000 40F4) bit description channel. If all timer channels are running, CHAN = 0xF.

11.6.6 Global interrupt flag register

setting and clearing the INTFLAG bit in each of the STATUSn registers. Table 140. Global interrupt flag register (IRQ _FLAG, address 0x4000 40F8) bit description channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. channel 1 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. channel 2 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. channel 3 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.

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12.1 How to read this chapter

The watchdog timer is identical on all LPC800 parts.

12.2 Features

• Internally resets chip if not reloaded during the programmable time-out period.
• Optional windowed operation requires reload to occur between a minimum and maximum time-out period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to watchdog time-out.
• Programmable 24-bit timer with internal fixed pre-scaler.
• Selectable time period from 1,024 watchdog clocks (TWDCLK  256  4) to over 67 million watchdog clocks (TWDCLK  224  4) in increments of 4 watchdog clocks.
• “Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog reset to be disabled.
• Incorrect feed sequence causes immediate watchdog event if enabled.
• The watchdog reload value can optionally be protected such that it can only be changed after the “warning interrupt” time is reached.
• Flag to indicate Watchdog reset.
• The Watchdog clock (WDCLK) source is the WatchDog oscillator.
• The Watchdog timer can be configured to run in Deep-sleep or Power-down mode.
• Debug mode.

12.3 Basic configuration

The WWDT is configured through the following registers:

• Power to the register interface (WWDT PCLK clock): In the SYSAHBCLKCTRL register, set bit 17 in Table 18.
• Enable the WWDT clock source (the watchdog oscillator) in the PDRUNCFG register (Table 37). This is the clock source for the timer base.
• For waking up from a WWDT interrupt, enable the watchdog interrupt for wake-up in the STARTERP1 register (Table 34).

12.4 Pin description

The WWDT has no external pins. UM10601 Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) Rev. 1.0 — 7 November 2012 Preliminary user manual

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12.5 General description

The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a programmable time if it enters an erroneous state. When enabled, a watchdog reset is generated if the user program fails to feed (reload) the Watchdog within a predetermined amount of time. When a watchdog window is programmed, an early watchdog feed is also treated as a watchdog event. This allows preventing situations where a system failure may still feed the watchdog. For example, application code could be stuck in an interrupt service that contains a watchdog feed. Setting the window such that this would result in an early feed will generate a watchdog event, allowing for system recovery. The Watchdog consists of a fixed (divide by 4) pre-scaler and a 24-bit counter which decrements when clocked. The minimum value from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF to be loaded in the counter. Hence the minimum Watchdog interval is (T WDCLK  256  4) and the maximum Watchdog interval is (TWDCLK  224  4) in multiples of (TWDCLK  4). The Watchdog should be used in the following manner:

• Set the Watchdog timer constant reload value in the TC register.
• Set the Watchdog timer operating mode in the MOD register.
• Set a value for the watchdog window time in the WINDOW register if windowed operation is desired.
• Set a value for the watchdog warning interrupt in the WARNINT register if a warning interrupt is desired.
• Enable the Watchdog by writing 0xAA followed by 0x55 to the FEED register.
• The Watchdog must be fed again before the Watchdog counter reaches zero in order to prevent a watchdog event. If a window value is programmed, the feed must also occur after the watchdog counter passes that value. When the Watchdog Timer is configured so that a watchdog event will cause a reset and the counter reaches zero, the CPU will be reset, loading the stack pointer and program counter from the vector table as for an external reset. The Watchdog time-out flag (WDTOF) can be examined to determine if the Watchdog has caused the reset condition. The WDTOF flag must be cleared by software. When the Watchdog Timer is configured to generate a warning interrupt, the interrupt will occur when the counter matches the value defined by the WARNINT register.

12.5.1 Block diagram

The block diagram of the Watchdog is shown below in the Figure 16. The synchronization logic (PCLK - WDCLK) is not shown in the block diagram.

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12.5.2 Clocking and power control

The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB accesses to the watchdog registers and is derived from the system clock (see Figure 3). The WDCLK is used for the watchdog timer counting and is derived from the watchdog oscillator. The synchronization logic between the two clock domains works as follows: When the MOD and TC registers are updated by APB operations, the new value will take effect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog timer is counting on WDCLK, the synchronization logic will first lock the value of the counter on WDCLK and then synchronize it with PCLK, so that the CPU can read the WDTV register. Remark: Because of the synchronization step, software must add a delay of three WDCLK clock cycles between the feed sequence and the time the WDPROTECT bit is enabled in the MOD register. The length of the delay depends on the selected watchdog clock WDCLK. Fig 16. Windowed Watchdog timer block diagram /g90/g68/g87/g70/g75/g71/g82/g74/g3 /g76/g81/g87/g72/g85/g85/g88/g83/g87 /g58/g39/g53/g40/g54/g40/g55/g3 /g11/g48/g50/g39 /g62/g20/g64/g12 /g58/g39/g55/g50/g41/g3 /g11/g48/g50/g39 /g62/g21/g64/g12 /g58/g39/g44/g49/g55/g3 /g11/g48/g50/g39 /g62/g22/g64/g12 /g58/g39/g40/g49/g3 /g11/g48/g50/g39 /g62/g19/g64/g12 /g70/g75/g76/g83/g3/g85/g72/g86/g72/g87 /g183/g23 /g73/g72/g72/g71/g3/g72/g85/g85/g82/g85 /g73/g72/g72/g71/g3/g82/g78 /g90/g71/g66/g70/g79/g78 /g72/g81/g68/g69/g79/g72/g3/g70/g82/g88/g81/g87 /g48/g50/g39/g3 /g85/g72/g74/g76/g86/g87/g72/g85 /g70/g82/g80/g83/g68/g85/g72 /g58/g39/g55/g57 /g70/g82/g80/g83/g68/g85/g72 /g76/g81/g3 /g85/g68/g81/g74/g72 /g88/g81/g71/g72/g85/g73/g79/g82/g90 /g73/g72/g72/g71/g3/g86/g72/g84/g88/g72/g81/g70/g72/g3 /g71/g72/g87/g72/g70/g87/g3/g68/g81/g71/g3 /g83/g85/g82/g87/g72/g70/g87/g76/g82/g81 /g41/g40/g40/g39 /g73/g72/g72/g71/g3/g82/g78 /g73/g72/g72/g71/g3/g82/g78 /g70/g82/g80/g83/g68/g85/g72 /g19 /g76/g81/g87/g72/g85/g85/g88/g83/g87/g3 /g70/g82/g80/g83/g68/g85/g72 /g21/g23/g16/g69/g76/g87/g3/g71/g82/g90/g81/g3/g70/g82/g88/g81/g87/g72/g85 /g58/g39/g44/g49/g55/g57/g36/g47 /g58/g44/g49/g39/g50/g58 /g55/g38 /g86/g75/g68/g71/g82/g90/g3/g69/g76/g87 /g58/g39/g51/g53/g50/g55/g40/g38/g55 /g11/g48/g50/g39 /g62/g23/g64/g12 /g55/g38/g3/g90/g85/g76/g87/g72

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12.5.3 Using the WWDT lock features

The WWDT supports several lock features which can be enabled to ensure that the WWDT is running at all times:

• Disabling the WWDT clock source
• Changing the WWDT reload value

12.5.3.1 Disabling the WWDT clock source

If bit 5 in the WWDT MOD register is set, the WWDT clock source is locked and can not be disbled either by software or by hardware when Sleep, Deep-sleep or Power-down modes are entered. Therefore, the user must ensure that the watchdog oscillator for each power mode is enabled before setting bit 5 in the MOD register. In Deep power-down mode, no clock locking mechanism is in effect because no clocks are running. However, an additional lock bit in the PMU can be set to prevent the part from even entering Deep power-down mode (see Table 42

12.5.3.2 Changing the WWDT reload value

If bit 4 is set in the WWDT MOD register, the watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. The reload overwrite lock mechanism can only be disabled by a reset of any type.

12.6 Register description

The Watchdog Timer contains the registers shown in Table 141.

12.6.1 Watchdog mode register

must be performed before any changes to the WDMOD register take effect. Table 141. Register overview: Watchdog timer (base address 0x4000 4000) status of the Watchdog Timer.

0 Table 142

TC R/W 0x004 Watchdog timer constant register. FEED WO 0x008 Watchdog feed sequence register. with the value contained in WDTC. value of the Watchdog timer.

0 Table 147

Table 142. Watchdog mode register (MOD - 0x4000 4000) bit description 0 The watchdog timer is stopped. 1 The watchdog timer is running. written with a 1 it cannot be re-written with a 0. 0 A watchdog time-out will not cause a chip reset. 1 A watchdog time-out will cause a chip reset.

software. Both flags are cleared by an external reset or a Watchdog timer reset. error occurs, or when PROTECT =1 and an attempt is made to write to the TC register. This flag is cleared by software writing a 0 to this bit. software by writing a 0 to this bit. register in addition to the NVIC. value in WDWARNINT. Cleared by software. software and is only cleared by a reset.

0 The watchdog time-out value (TC) can be changed at

1 The watchdog time-out value (TC) can be changed only

5 LOCK A 1 in this bit prevents disabling or powering down the

software and is only cleared by any reset.

12.6.2 Watchdog Timer Constant register

time-out interval is TWDCLK 256 4. watchdog reset and set the WDTOF flag.

12.6.3 Watchdog Feed register

incorrect access to a Watchdog register during a feed sequence. returned to the interrupted task. Table 143. Watchdog operating modes selection 0 X (0 or 1) Debug/Operate without the Watchdog running. but watchdog reset will not. interrupt request will be generated. WDWINDOW will also cause a watchdog reset. Table 144. Watchdog Timer Constant register (TC - 0x4000 4004) bit description value read from a reserved bit is not defined.

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12.6.4 Watchdog Timer Value register

The WDTV register is used to read the current value of Watchdog timer counter. When reading the value of the 24-bit counter, the lock and synchronization procedure takes up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual value of the timer when it's being read by the CPU.

12.6.5 Watchdog Timer Warning Interrupt register

The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog interrupt. When the watchdog timer counter matches the value defined by WARNINT, an interrupt will be generated after the subsequent WDCLK. A match of the watchdog timer counter to WARNINT occurs when the bottom 10 bits of the counter have the same value as the 10 bits of WARNINT, and the remaining upper bits of the counter are all 0. This gives a maximum time of 1,023 watchdog timer counts (4,096 watchdog clocks) for the interrupt to occur prior to a watchdog event. If WARNINT is 0, the interrupt will occur at the same time as the watchdog event.

12.6.6 Watchdog Timer Window register

The WINDOW register determines the highest WDTV value allowed when a watchdog feed is performed. If a feed sequence occurs when WDTV is greater than the value in WINDOW, a watchdog event will occur. WINDOW resets to the maximum possible WDTV value, so windowing is not in effect. Table 145. Watchdog Feed register (F EED - 0x4000 4008) bit description bits. The value read from a reserved bit is not defined. Table 146. Watchdog Timer Value register (TV - 0x4000 400C) bit description value read from a reserved bit is not defined. Table 147. Watchdog Timer Warning Interrupt register (WARNINT - 0x4000 4014) bit Bit Symbol Description Reset Value 9:0 WARNINT Watchdog warning interrupt compare value. 0 31:10 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

12.7 Functional description

The following figures illustrate several aspects of Watchdog Timer operation. Table 148. Watchdog Timer Window register (WINDOW - 0x4000 4018) bit description 31:24 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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13.1 How to read this chapter

The analog comparator is available on all LPC800 parts.

13.2 Features

• Selectable external inputs can be used as either the positive or negative input of the comparator.
• The Internal voltage reference (0.9 V bandgap reference) can be used as either the positive or negative input of the comparator.
• 32-stage voltage ladder can be used as either the positive or negative input of the comparator.
• Voltage ladder source selectable between the supply pin VDD or VDDCMP pin.
• Voltage ladder can be separately powered down when not required.
• Interrupt capability

13.3 Basic configuration

Configure the analog comparator using the following registers:

• In the SYSAHBCLKCTRL register, set bit 19 (Table 18) to enable the clock to the register interface.
• You can enable or disable the power to the analog comparator through the PDRUNCFG register (Table 37
• Clear the analog comparator peripheral reset using the PRESETCTRL register (Table 7).
• The analog comparator interrupt is connected to interrupt #11 in the NVIC.
• Configure the analog comparator pin functions through the switch matrix. See Section 13.4.

13.3.1 Connect the compar ator output to the SCT

You can use the comparator output function (ACMP_O) to start or stop the SCT or, more generally, create an SCT event. To create an SCT event, connect AMP_O as follows: 1. Using the switch matrix, co nnect ACMP_O to a pin. See Table 149. 2. Using the switch matrix, connect any of th e SCT input functions to the same pin. See Table 106. The selected SCT input can now monitor the ACMP_O function. UM10601 Chapter 13: LPC800 Analog comparator Rev. 1.0 — 7 November 2012 Preliminary user manual

13.4 Pin description

and can only be assigned to special pins on the package. comparator output to any pin on the LPC800 package. See Section 9.3.2 to enable the analog comparator inputs and the reference voltage input.

13.5 General description

The analog comparator can compare voltage levels on external pins and internal voltages. The comparator has 8 inputs multiplexed separately to its positive and negative inputs. Input 0 of the multiplexers is the programmable voltage ladder output. Bits 2:1 control the external inputs ACMP_I[2:1]. Bits 6 of the multiplexers controls internal reference voltage input. Table 149. Analog comparator pin description

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13.5.1 Reference voltages

The voltage ladder can use two reference voltages, from the VDDCMP or the VDD pin. The voltage ladder selects one of 32 steps between the pin voltage and VSS inclusive. The voltage on VDDCMP should not exceed that on VDD .

13.5.2 Settling times

After the voltage ladder is powered on, it requires stabilization time until comparisons using it are accurate. Much shorter settling times apply after the LADSEL value is changed and when either or both voltage sources are changed. Software can deal with these factors by repeatedly reading the comparator output until a number of readings yield the same result.

13.5.3 Interrupts

The interrupt output comes from edge detection circuitry in this module. Rising edges, falling edges, or both edges can set the COMPEDGE bit and thus request an interrupt. COMPEDGE and the interrupt request are cleared when software writes a 1 to EDGECLR. Fig 20. Comparator block diagram /g19 /g26 /g19 /g22/g20 /g19 /g26 /g19/g20 /g57/g39/g39/g72/g91/g87/g17/g3/g57/g39/g39/g38/g48/g51 /g47/g36/g39/g53/g40/g41 /g47/g36/g39/g40/g49/g3/g9/g3/g81/g36/g38/g50/g48/g51/g66/g51/g39 /g47/g36/g39/g54/g40/g47 /g38/g50/g48/g51/g66/g57/g51/g66/g54/g40/g47 /g14 /g16 /g43/g60/g54 /g38/g50/g48/g51/g66/g57/g48/g66/g54/g40/g47 /g36/g38/g48/g51/g66/g44/g20 /g36/g38/g48/g51/g66/g44/g21 /g76/g81/g87/g72/g85/g81/g68/g79/g3/g19/g17/g28/g57/g3/g37/g36/g49/g39/g42/g36/g51 /g57/g50/g47/g55/g36/g42/g40/g3 /g47/g36/g39/g39/g40/g53/g3/g50/g56/g55 /g36/g38/g50/g48/g51/g66/g51/g39 /g39/g3/g3/g52 /g69/g88/g73 /g19 /g20/g39/g3/g3/g52 /g54/g60/g49/g38 /g21/g3/g50/g41/g3/g22/g3 /g54/g36/g48/g51/g47/g44/g49/g42 /g40/g39/g42/g40/g3/g39/g40/g55/g40/g38/g55 /g54/g3/g3/g52 /g53/g3/g3/g3/g3/g3/g3 /g38/g50/g48/g51/g54/g36 /g40/g39/g42/g40/g54/g40/g47 /g40/g39/g42/g40/g38/g47/g53/g3/g82/g85 /g36/g38/g50/g48/g51/g66/g53/g54/g55/g66/g49 /g38/g50/g48/g51/g40/g39/g42/g40 /g11/g87/g82/g3/g44/g49/g55/g40/g53/g53/g56/g51/g55/g12 /g69/g88/g73/g38/g50/g48/g51/g54/g55/g36/g55 /g87/g82/g3/g36/g38/g48/g51/g66/g50/g3 /g38/g50/g49/g55/g53/g50/g47/g3/g18/g3/g54/g55/g36/g55/g56/g54/g3/g53/g40/g42/g44/g54/g55/g40/g53/g3/g37/g44/g55/g54 /g36/g38/g50/g48/g51/g66/g53/g54/g55/g66/g49 /g57/g54/g54 /g57/g54/g54 /g57/g54/g54 /g57/g54/g54 /g81/g17/g70/g17

13.5.4 Comparator outputs

The comparator output (conditioned by COMPSA bit) can be routed to an external pin. registers don’t need to be written. Section 13.3.1 “Connect the comparator output to the SCT”.

13.6 Register description

13.6.1 Comparator control register

Table 150. Register overview: Analog comparator (base address 0x4002 4000) Table 151. Comparator control register (CTRL, address 0x4002 4000) bit description

6 COMPSA Comparator output control 0

0 Comparator output is used directly.

1 Comparator output is synchronized to the bus clock for

EDGECLR bit by first writing a 1 and then a 0.

13.6.2 Voltage ladder register

produced by the ladder is programmable in steps of 1/31. Table 152. Voltage ladder register (LAD, address 0x4002 4004) bit description

0 LADEN Voltage ladder enable 0

6 LADREF Selects the reference voltage Vref for the voltage ladder: 0

0 Supply pin V DD

1 VDDCMP pin

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14.1 How to read this chapter

The self wake-up timer is available on all LPC800 parts.

14.2 Features

• 32-bit loadable down-counter. Counter starts automatically when a count value is loaded. Time-out generates an interrupt/wake up request.
• The WKT resides in a separate, always-on power domain.
• The WKT supports two clock sources. One clock source originates from the always-on power domain.
• The WKT can be used for waking up the part from any low power mode, including Deep power-down mode, or for general-purpose timing.

14.3 Basic configuration

• In the SYSAHBCLKCTRL register, set bit 9 (Table 18) to enable the clock to the register interface.
• Clear the WKT reset using the PRESETCTRL register (Table 7).
• The WKT interrupt is connected to interrupt #15 in the NVIC.
• Enable the low power oscillator in the PMU (Table 45).
• Enable the IRC and IRC output in the PDRUNCFG register (Table 37).
• See Section 5.7.1 to enable the various power down modes.

14.4 Pin description

The WKT has no configurable pins.

14.5 General description

The self wake-up timer is a 32-bit, loadable down-counter. Writing any non-zero value to this timer automatically enables the counter and launches a count-down sequence. When the counter is being used as a wake up timer, this write can occur just prior to entering a reduced power mode. When a starting count value is loaded, the self wake-up timer automatically turns on, counts from the pre-loaded value down to zero, generates an interrupt and/or a wake up request, and then turns itself off until re-launched by a subsequent software write.

14.5.1 WKT clock sources

The self wake-up timer can be clocked from two alternative clock sources:

• A 750 kHz clock derived from the IRC oscillator. This is the default clock, UM10601 Chapter 14: LPC800 Self wake-up timer (WKT) Rev. 1.0 — 7 November 2012 Preliminary user manual

• A 10 kHz, low-power clock with a dedicated on-chip oscillator as clock source. The IRC-derived clock is much more accurate than the alternative, low-power clock. However, the IRC is not available in most low-power modes. This clock must not be selected when the timer is being used to wake up from a power mode where the IRC is disabled. The alternative clock source is a (nominally) 10 kHz, low-power clock, sourced from a dedicated oscillator. This oscillator resides in the always-on voltage domain, so it can be programmed to continue operating in Deep power-down mode when power is removed from the rest of the part. This clock is also be available during other low-power modes when the IRC clock is shut-down. The Low-Power oscillator is not accurate (approximately +/- 45% over process and temperature). The frequency measurement feature (if available<tbd>) can be used to determine what the actual frequency is before selecting a time-out value to write into the self wake-up timer. The frequency may still drift, however, while counting is in progress - particularly due to reduced chip temperature after a low-power mode is entered.

14.6 Register description

14.6.1 Control register

Table 153. Register overview: WKT (base address 0x4000 8000) COUNT R/W 0xC Counter register. Table 154. Control register (CTRL, address 0x4000 8000) bit description to approximately 95 minutes in 1.33 μs increments. wake up from one of these modes. this clock is limited to +/- 45 % over temperature and processing.

14.6.2 Count register

Do not write to this register while the counting is in progress. is recommended to read it twice in succession. 0 No time-out. The self wake-up timer has not timed out. Writing a 0 to has no effect. 0 No effect. Reading this bit always returns 0. 1 Clear the counter. Counting is halted until a new count value is loaded. Table 155. Counter register (COUNT, address 0x4000 800C) bit description and starts the count-down sequence. A read reflects the current value of the timer.

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15.1 How to read this chapter

USART0 and USART1 are available on all parts. USART2 is available on parts LPC812M101FDH16 and LPC812M101FDH20 only. Read this chapter for a description of the USART peripheral and the software interface. The LPC800 also provides an on-chip ROM-based USART API to configure and operate the USART. See Table 271.

15.2 Features

• 7, 8, or 9 data bits and 1 or 2 stop bits
• Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option.
• Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485 possible with software address detection and transceiver direction control.)
• Parity generation and checking: odd, even, or none.
• One transmit and one receive data buffer.
• RTS/CTS for hardware signaling for automatic flow control. Software flow control can be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an RTS output.
• Received data and status can optionally be read from a single register
• Break generation and detection.
• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.
• Built-in Baud Rate Generator.
• A fractional rate divider is shared among all UARTs.
• Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS detect, and receiver sample noise detected.
• Separate data and flow control loopback modes for testing.
• Baud rate clock can also be output in asynchronous mode.

15.3 Basic configuration

Remark: The on-chip USART API provides software routines to configure and use the USART. See Table 271. Configure USART0/1/2 for receiving and transmitting data:

• In the SYSAHBCLKCTRL register, set bit 14 to 16 (Table 18) to enable the clock to the register interface.
• Clear the USART0/1/2 peripheral resets using the PRESETCTRL register (Table 7). UM10601 Chapter 15: LPC800 USART0/1/2 Rev. 1.0 — 7 November 2012 Preliminary user manual

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• Enable or disable the USART0/1/2 interrupts in slots #3 to 5 in the NVIC.
• Configure the USART0/1/2 pin functions through the switch matrix. See Section 15.4.
• Configure the USART clock and baud rate. See Section 15.3.1. Configure the USART0/1/2 to wake up the part from low power modes:
• Configure the USART to receive and transmit data in synchronous slave mode. See Section 15.3.2.

15.3.1 Configure the US ART clock and baud rate

All three USARTs use a common peripheral clock (U_PCLK) and, if needed, a fractional baud rate generator.The peripheral clock and the fractional divider for the baud rate calculation are set up in the SYSCON block as follows (see Figure 21): 1. Configure the UART clock by writing a value UARTCLKDIV > 0 in the USART peripheral clock divider register. This is the divided main clock common to all USARTs. Section 4.6.14 “USART clock divider register” 2. If a fractional value is needed to obtain a particular baud rate, program the fractional divider. The fractional divider value is the fraction of MULT/DIV. The MULT value is programmed in the UARTFRGMULT register and the DIV value is programmed in the UARTFRGDIV register in the SYSCON block. U_PCLK = UARTCLKDIV/(1+MULT/DIV) The following rules apply for MULT and DIV: – Always set DIV to 256 by programming the UARTFRGDIV register with the value of 0xFF. – Program any value between 0 and 255 in the UARTFRGMULT register. – The fraction of MULT/DIV must be smaller than 1. Section 4.6.19 “ USART fractional generator multiplier value register” Section 4.6.18 “USART fractional generator divider value register” 3. In asynchronous mode: Configure the baud rate divider BRGVAL in the USARTn BRG register. The baud rate divider divides the common USART peripheral clock by a factor of 16 multiplied by the baud rate value to provide the baud rate = U_PCLK/16 x BRGVAL. Section 15.6.9 “ USART Baud Rate Generator register” 4. In synchronous mode: The serial clock is Un_SCLK = U_PCLK/BRGVAL

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15.3.2 Configure the USART for wake-up

The USART can wake up the system from sleep mode in asynchronous or synchronous mode on any enabled USART interrupt. If the USART is configured for synchronous slave mode, the USART block can create an interrupt on a received signal even when the USART block receives no clocks from the ARM Cortex-M0+ core - that is in Deep-sleep or Power-down mode. As long as the USART receives a clock signal from the master, it can receive up to one byte in the RXDATA register while in Deep-sleep or Power-down mode. Any interrupt raised as part of the receive data process can then wake up the part.

15.3.2.1 Wake-up from Sleep mode

• Configure the USART in either asynchronous mode or synchronous mode. See Table 158.
• Enable the USART interrupt in the NVIC.
• Any USART interrupt wakes up the part from sleep mode. Enable the USART interrupt in the INTENSET register (Table 161). Fig 21. USART clocking /g56/g36/g53/g55/g38/g47/g46/g39/g44/g57/g41/g53/g42 /g54/g60/g54/g38/g50/g49/g3/g69/g79/g82/g70/g78 /g80/g68/g76/g81/g3/g70/g79/g82/g70/g78 /g56/g66/g51/g38/g47/g46/g3/g32/g3/g56/g36/g53/g55/g38/g47/g46/g39/g44/g57/g18/g11/g20/g3/g14/g3/g48/g56/g47/g55/g18/g39/g44/g57/g12 /g56/g36/g53/g55/g41/g53/g42/g36/g39/g39 /g56/g36/g53/g55/g41/g53/g42/g39/g44/g57 /g56/g54/g36/g53/g55/g19 /g56/g54/g36/g53/g55/g19 /g37/g36/g56/g39/g18/g54/g40/g53/g44/g36/g47/g3/g38/g47/g50/g38/g46 /g42/g40/g49/g40/g53/g36/g55/g50/g53 /g56/g54/g36/g53/g55/g20 /g56/g54/g36/g53/g55/g20 /g37/g36/g56/g39/g18/g54/g40/g53/g44/g36/g47/g3/g38/g47/g50/g38/g46 /g42/g40/g49/g40/g53/g36/g55/g50/g53 /g56/g54/g36/g53/g55/g21 /g56/g54/g36/g53/g55/g21 /g37/g36/g56/g39/g18/g54/g40/g53/g44/g36/g47/g3/g38/g47/g50/g38/g46 /g42/g40/g49/g40/g53/g36/g55/g50/g53 /g56/g19/g66/g54/g38/g47/g46 /g56/g20/g66/g54/g38/g47/g46 /g56/g21/g66/g54/g38/g47/g46

15.3.2.2 Wake-up from Deep-sleep or Power-down mode

• Configure the USART in synchronous slave mode. See Table 158. You must connect the SCLK function to a pin and connect the pin to the master.
• Enable the USART interrupt in the STARTERP1 register. See Table 34 “Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit description”.
• Enable the USART interrupt in the NVIC.
• The USART wakes up the part from Deep-sleep or Power-down mode on all events that cause an interrupt and also are enabled in the INTENSET register. Typical wake-up events are: – A received start bit has been detected. – An address bit has been sent. – The RXDATA buffer has received one byte and is full. – Data are ready to be transmitted in the TXDATA buffer and a serial clock from the master has been received. – A change in the state of the CTS pin if the CTS function is connected. <tbd> – Remark: By enabling or disabling the interrupt in the INTENSET register (Table 161 ), you can customize when the wake-up occurs in the USART receive/transmit protocol.

15.4 Pin description

assigned to external pins through the switch matrix. functions to pins on the LPC800 package. Table 156. USART pin description USART RTS signal is configured to appear on a device pin. until CTS is again asserted (low).

15.5 General description

passed to the receiver buffer register to await access by the CPU. that data, formats it, and serializes it to the serial output, Un_TXD. rate clock without division. register. Many of the status flags are able to generate interrupts, as selected by software. U0_SCLK I/O any Serial clock input/output for USART0 in synchronous mode. if the SYNCMST bit in CFG register is set to 1.

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15.6 Register description

The reset value reflects the data stored in used bits only. It does not include the content of reserved bits. Table 157: Register overview: USART (base address 0x4006 4000 (USART0), 0x4006 8000 (USART1), 0x4006 C000 (USART2)) Name Access Offset Description Reset value Reference CFG R/W 0x000 USART Configuration regi ster. Basic USART configuration settings that typically are not changed during operation.

0 Table 158

CTRL R/W 0x004 USART Control register. US ART control settings that are more likely to change during operation.

0 Table 159

STAT R/W 0x008 USART Status register. The complete status value can be read here. Writing 1s clears some bits in the register. Some bits can be cleared by writing a 1 to them. 0x000E Table 160 INTENSET R/W 0x00C Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

0 Table 161

INTENCLR W 0x010 Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. - Table 162 RXDATA R 0x014 Receiver Data register. Contains the last character received. - Table 163 RXDATASTAT R 0x018 Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows software to recover incoming data and status together. - Table 164 TXDATA R/W 0x01C Transmit Data register. Data to be transmitted is written here. 0 Table 165 BRG R/W 0x020 Baud Rate Generator register. 16-bit integer baud rate divisor value.

0 Table 166

INTSTAT R 0x024 Interrupt status register. Reflects interrupts that are currently enabled. 0x0005 Table 167

15.6.1 USART Configuration register

that would normally be configured once in an application. Write the new configuration value, with the ENABLE bit set to 1. Table 158. USART Configuration register (CFG, address 0x4006 4000 (USART0), 0x4006 8000 transmitter has been reset and is therefore available. 1 Enabled. The USART is enabled for operation. number of 1s in a received character is expected to be even. number of 1s in a received character is expected to be odd. single stop bit is required for received data. 7 - Reserved. Only write 0 to this bit.

15.6.2 USART Control register

automatic flow control signal. internal CTS for flow control purposes. 0 Asynchronous mode is selected. 1 Synchronous mode is selected.

12 CLKPOL Selects the clock polarity and sampling edge of received

output on SCLK if it is connected to a pin.

Table 159. USART Control register (CTRL, address 0x4006 4004 (USART0), 0x4006 8004

1 Continuous break is sent immediately when this bit is set,

and remains until this bit is cleared. 0 Not disabled. USART transmitter is not disabled. used to facilitate software flow control. output while data is being transmitted in synchronous mode. character that is being received. independently from transmission on Un_TXD).

15.6.3 USART Status register

immediately upon detection and remain set until cleared by software action in STAT. Table 160. USART Status register (STAT, address 0x4006 4008 (USART0), 0x4006 8008 (USART1), 0x4006 receiver buffer. Cleared after a read of the RXDATA or RXDATASTAT registers. transmit buffer. Previous data may still be in the process of being transmitted.

4 CTS This bit reflects the current state of the CTS signal, regardless of the setting of

unless loopback mode is enabled. in the shift register is lost. 11 DELTARXBRK This bit is set when a change in the state of receiver break detection occurs.

12 START This bit is set when a start is detec ted on the receiver input and subsequently

Power-down mode immediately when a start is detected. Cleared by software.

[1] RO = Read-only, W1 = write 1 to clear.

15.6.4 USART Interrupt Enable read and set register

used to clear bits in this register. rate or configuration mismatch with the transmitting source. received character, if parity is enabled via the Parity field in the CFG register. is not updated during a received break. Table 161. USART Interrupt Enable read and set register (INTENSET, address 0x4006

0 RXRDYEN When 1, enables an interrupt when there is a received

character available to be read from the RXDATA register.

2 TXRDYEN When 1, enables an interrupt when the TXDATA register is

available to take another character to transmit.

5 DELTACTSEN When 1, enables an interrupt when there is a change in the

6 TXDISINTEN When 1, enables an interrupt when the transmitter is fully

description of the TXDISINT bit for details.

8 OVERRUNEN When 1, enables an interrupt when an overrun error

15.6.5 USART Interrupt Enable Clear register

The INTENCLR register is used to clear bits in the INTENSET register.

11 DELTARXBRKEN When 1, enables an interrupt when a change of state has

(break condition asserted or deasserted).

12 STARTEN When 1, enables an interrupt when a received start bit has

13 FRAMERREN When 1, enables an interrupt when a framing error has been

14 PARITYERREN When 1, enables an interrupt when a parity error has been

description of the RXNOISEINT bit in Table 160. Table 162. USART Interrupt Enable clear register (INTENCLR, address 0x4006

0 RXRDYCLR Writing 1 clears the corresponding bit in the INTENSET

2 TXRDYCLR Writing 1 clears the corresponding bit in the INTENSET

5 DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET

6 TXDISINTCLR Writing 1 clears the corresponding bit in the INTENSET

8 OVERRUNCLR Writing 1 clears the corresponding bit in the INTENSET

11 DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET

15.6.6 USART Receiver Data register

The RXDATA register contains the last character received before any overrun. Remark: Reading this register changes the status flags in the RXDATASTAT register.

15.6.7 USART Receiver Data with Status register

Remark: Reading this register changes the status flags.

12 STARTCLR Writing 1 clears the corresponding bit in the INTENSET

13 FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET

14 PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET

15 RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET

Table 163. USART Receiver Data register (RXDATA, address 0x4006 4014 (USART0), 0x4006 USART configuration settings. Table 164. USART Receiver Data with Status register (RXDATASTAT, address 0x4006 4018 USART configuration settings. with the transmitting source.

15.6.8 USART Transmitter Data Register

may then be written to TXDATA. Table 165. USART Transmitter Data Register (TXDATA, address 0x4006 401C (USART0), transmitted as soon as the transmit shift register is available.

15.6.9 USART Baud Rate Generator register

The Baud Rate Generator is a simple 16-bit integer divider controlled by the BRG register. clock used for USART internal operations. taking three samples of incoming data. the new BRGVAL. 4) Write to the CFG register to set the Enable bit to 1.

15.6.10 USART Interr upt Status register

descriptions of the interrupt flags. Table 166. USART Baud Rate Generator register (BRG, address 0x4006 4020 (USART0), baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. Table 167. USART Interrupt Status register (INTSTAT, address 0x4006 4024 (USART0),

15.7 Functional description

15.7.1 Clocking and Baud rates

and typically also setting up the FRG. See Figure 21.

15.7.1.1 Fractional Rate Generator (FRG)

peripheral clock is not a good multiple of standard (or otherwise desirable) baud rates. for the FRG, which will then not divide the input clock.

5 DELTACTS This bit is set when a change in the state of the CTS input is

11 DELTARXBRK This bit is set when a change in the state of receiver break

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 181 of 313 NXP Semiconductors UM10601 Chapter 15: LPC800 USART0/1/2 The base clock produced by the FRG cannot be perfectly symmetrical, so the FRG distributes the output clocks as evenly as is practical. Since the USART normally uses 16x overclocking, the jitter in the fractional rate clock in these cases tends to disappear in the ultimate USART output. For setting up the fractional divider use the following registers: Table 23 “USART fractional generator divider value register (UARTFRGDIV, address 0x4004 80F0) bit description” Table 24 “USART fractional generator multiplier value register (UARTFRGMULT, address 0x4004 80F4) bit description” For details see Section 15.3.1 “Configure the USART clock and baud rate”.

15.7.1.2 Baud Rate Generator (BRG)

The Baud Rate Generator (see Section 15.6.9) is used to divide the base clock to produce a rate 16 times the desired baud rate. Typically, standard baud rates can be generated by integer divides of higher baud rates.

15.7.1.3 Baud rate calculations

Base clock rates are 16x for asynchronous mode and 1x for synchronous mode.

15.7.2 Synchronous mode

Remark: Sync mode transmit and receive operate at the incoming clock rate in slave mode and the BRG selected rate (not divided by 16) in master mode.

15.7.3 Flow control

The USART supports both hardware and software flow control.

15.7.3.1 Hardware flow control

The USART supports hardware flow control using RTS and/or CTS signalling. If RTS is configured to appear on a device pin so that it can be sent to an external device, it indicates to an external device the ability of the receiver to receive more data. It can also be used internally to throttle the transmitter from the receiver, which can be especially useful if loopback mode is enabled. If connected to a pin, and if enabled to do so, the CTS input can allow an external device to throttle the USART transmitter. Both internal and external CTS can be used separately or together. Figure 23 shows an overview of RTS and CTS within the USART.

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15.7.3.2 Software flow control

Software flow control could include XON / XOFF flow control, or other mechanisms. these are supported by the ability to check the current state of the CTS input, and/or have an interrupt when CTS changes state (via the CTS and DELTACTS bits, respectively, in the STAT register), and by the ability of software to gracefully turn off the transmitter (via the TXDIS bit in the CTRL register). Fig 23. Hardware flow control using RTS and CTS /g55/g85/g68/g81/g86/g80/g76/g87/g87/g72/g85 /g53/g72/g70/g72/g76/g89/g72/g85 /g38/g41/g42 /g62/g38/g55/g54/g40/g49/g64/g56/g81/g66/g38/g55/g54 /g56/g81/g66/g53/g55/g54 /g70/g75/g68/g81/g74/g72/g3/g71/g72/g87/g72/g70/g87 /g54/g55/g36/g55 /g62/g38/g55/g54/g64 /g54/g55/g36/g55 /g62/g39/g40/g47/g55/g36/g38/g55/g54/g64 /g38/g41/g42/g62/g47/g50/g50/g51/g64 /g19 /g20

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16.1 How to read this chapter

The I2C-bus interface is available on all parts. Read this chapter if you want to understand the I2C operation and the software interface and want to learn how to use the I2C for wake-up from reduced power modes. The LPC800 provides an on-chip ROM-based I2C API to configure and operate the I2C. See Table 250 “I2C API calls”.

16.2 Features

• Independent Master, Slave, and Monitor functions.
• Supports both Multi-master and Multi-master with Slave functions.
• Multiple I2C slave addresses supported in hardware.
• One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple I2C bus addresses.
• 10-bit addressing supported with software assist.
• Supports SMBus.

16.3 Basic configuration

Configure I2C using the following registers:

• In the SYSAHBCLKCTRL register, set bit 5 (Table 18) to enable the clock to the register interface.
• Clear the I2C peripheral reset using the PRESETCTRL register (Table 7).
• Enable/disable the I2C interrupt in interrupt slots #8 in the NVIC.
• Configure the I2C pin functions through the switch matrix. See Section 16.4.
• The peripheral clock for the I2C is the system clock (see Figure 24). UM10601 Chapter 16: LPC800 I2C-bus interface Rev. 1.0 — 7 November 2012 Preliminary user manual Fig 24. I2C clocking /g38/g79/g82/g70/g78/g3/g71/g76/g89/g76/g71/g72/g85 /g44/g21/g38 /g54/g60/g54/g38/g50/g49 /g86/g92/g86/g87/g72/g80/g3/g70/g79/g82/g70/g78 /g54/g60/g54/g36/g43/g37/g38/g47/g46/g38/g55/g53/g47/g62/g24/g64 /g11/g44/g21/g38/g3/g70/g79/g82/g70/g78/g3/g72/g81/g68/g69/g79/g72/g12 /g44/g21/g38/g66/g51/g38/g47/g46 /g39/g44/g57/g57/g36/g47 /g39/g44/g57/g44/g21/g38/g3/g70/g79/g82/g70/g78

16.4 Pin description

1. Connect to special I2C open-drain pins (PIO0_10 and PIO0_11).
2. Connect to any other pin that can host a movable function..

I2C-bus specification up to Fast Mode Plus (up to 1 MHz I2C). capability of powering down the device without affecting the bus. any pin on the LPC800 package.

16.5 General description

The architecture of the I2C-bus interface is shown in Figure 25. Table 168. I2C-bus pin description compatibility with the full I2C-bus specification. compatibility with the full I2C-bus specification.

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16.6 Register description

The register functionalities can be grouped as follows:

• Common registers: – Table 170 “I2C Configuration register (CFG, address 0x4005 0000) bit description” – Table 171 “I2C Status register (STAT, address 0x4005 0004) bit description” – Table 178 “I2C Interrupt Status register (INTSTAT, address 0x4005 0018) bit description” – Table 174 “Interrupt Enable Set and read register (INTENSET, address 0x4005 0008) bit description” – Table 175 “Interrupt Enable Clear register (INTENCLR, address 0x4005 000C) bit description” – Table 176 “time-out register (TIMEOUT, address 0x4005 0010) bit description” – Table 177 “I2C Clock Divider register (DIV, address 0x4005 0014) bit description”
• Master function registers: – Table 179 “Master Control register (MSTCTL, address 0x4005 0020) bit description” – Table 180 “Master Time register (MSTTIME, address 0x4005 0024) bit description” Fig 25. I2C block diagram /g55/g76/g80/g72/g16/g82/g88/g87 /g44/g21/g38/g3/g80/g68/g86/g87/g72/g85/g3 /g73/g88/g81/g70/g87/g76/g82/g81 /g44/g21/g38/g3/g86/g79/g68/g89/g72/g3 /g73/g88/g81/g70/g87/g76/g82/g81 /g44/g21/g38/g19/g66/g54/g39/g36 /g44/g21/g38/g19/g66/g54/g38/g47 /g54/g38/g47/g3/g9/g3 /g54/g39/g36/g3 /g82/g88/g87/g83/g88/g87/g3 /g79/g82/g74/g76/g70 /g55/g76/g80/g76/g81/g74/g3 /g74/g72/g81/g72/g85/g68/g87/g76/g82/g81 /g19 /g20 /g19 /g20 /g38/g41/g42/g62/g47/g50/g50/g51/g64 /g48/g82/g81/g76/g87/g82/g85/g3 /g73/g88/g81/g70/g87/g76/g82/g81

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• Slave function registers: – Table 182 “Slave Control register (SLVCTL, address 0x4005 0040) bit description” – Table 182 “Slave Control register (SLVCTL, address 0x4005 0040) bit description” – Table 184 “Slave Address registers (SLVADR[0:3]- address 0x4005 0048 (SLVADR0) to 0x4005 0054 (SLVADR3)) bit description” – Table 185 “Slave address Qualifier 0 register (SLVQUAL0, address 0x4005 0058) bit description”
• Monitor function register: Table 186 “Monitor data register (MONRXDAT, address 0x4005 0080) bit description”

16.6.1 I2C Configuration register

0 Table 177

0 Table 178

Table 170. I2C Configuration register (CFG, address 0x4005 0000) bit description function is internally reset. 0 Disabled. The I 2C Master function is disabled. 1 Enabled. The I 2C Master function is enabled. 0 Disabled. The I 2C slave function is disabled. 1 Enabled. The I 2C slave function is enabled.

function is internally reset. 0 Disabled. The I 2C monitor function is disabled. 1 Enabled. The I 2C monitor function is enabled. will be automatically cleared. 0 Disabled. Time-out function is disabled. provided by the monitor function before it is overwritten. supplied by the monitor function.

16.6.2 I2C Status register

Access to bits in this register varies. RO = Read-only, W1 = write 1 to clear. this register are listed in Table 172 and Table 173. Table 171. I 2C Status register (STAT, address 0x4005 0004) bit description when a 1 is written to the MSTCONTINUE bit in the MSTCTL register. 0 No service needed. The Master functi on does not currently need service. is needed can be found in the adjacent MSTSTATE field. service for the Master function. All other values are reserved. 0x0 Idle. The Master function is avail able to be used for a new transaction. 0x1 Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. 0x2 Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. 0x3 Address. Slave Nacked address. 0x4 Data. Slave Nacked transmitted data. 0 No loss. No Arbitration Loss has occurred. 0 No Start/Stop Error has occurred. made, or software could attempt to insure that the bus has not stalled.

0 No service needed. The Slave function does not currently need service. is needed can be found in the adjacent SLVSTATE field. service for the Slave function. All other values are reserved. addresses has been matched by hardware. 0x1 Data available. Received data is available (Slave Receiver mode). the slave function status in real time. 0 Stretching. The slave function is currently stretching the I 2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. clock. Deep-sleep or Power-down mode could be entered at this time. 0x0 Slave address 0 was matched. 0x1 Slave address 1 was matched. 0x2 Slave address 2 was matched. 0x3 Slave address 3 was matched. Nack a matched address, or when there is a Stop detected on the bus. SLVSEL is not cleared if software Nacks data. 0 Not selected. The Slave func tion is not currently selected. 1 Selected. The Slave function is currently selected. Table 171. I

enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. description of SLVSEL for details on when that event occurs. 0 No data. The Monitor function does not currently have data available. 1 Data waiting. The Monitor functi on has data waiting to be read. 0 No overrun. Monitor data has not overrun. the CFG register. Writing 1 to this bit clears the flag. 0 Inactive. The Monitor function considers the I 2C bus to be inactive. 1 Active. The Monitor function considers the I 2C bus to be active. register . The flag can be cleared by writing a 1 to this bit. 2C bus is not idle, or this flag has been cleared by software. SCL Time-out flag. The flag is cleared by writing a 1 to this bit. 2C bus events have not caused a time-out. the time specified by the I2C TIMEOUT register. cleared by writing a 1 to this bit. 0 No time-out. SCL low time has not caused a time-out. 1 Time-out. SCL low time has caused a time-out. Table 171. I 2C Status register (STAT, address 0x4005 0004) bit description …continued

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16.6.3 Interrupt Enable Set and read register

The INTENSET register controls which I2C status flags generate interrupts. Writing a 1 to a bit position in this register enables an interrupt in the corresponding position in the STAT register, if an interrupt is supported there. Reading INTENSET indicates which interrupts are currently enabled. Table 174. Interrupt Enable Set and read register (INTENSET, address 0x4005 0008) bit Bit Symbol Value Description Reset value 0 MSTPENDINGEN Master Pend ing interrupt Enable. 0 0 The MstPending interrupt is disabled. 1 The MstPending interrupt is enabled. 3:1 - Reserved. Read value is undefined, only zero should be written. NA 4 MSTARBLOSSEN Master Arbitrat ion Loss interrupt Enable. 0 0 The MstArbLoss interrupt is disabled. 1 The MstArbLoss interrupt is enabled. 5 - Reserved. Read value is undefined, only zero should be written. NA 6 MSTSTSTPERREN Master Start/Sto p Error interrupt Enable. 0 0 The MstStStpErr interrupt is disabled. 1 The MstStStpErr interrupt is enabled. 7 - Reserved. Read value is undefined, only zero should be written. NA 8 SLVPENDINGEN Slave Pending interrupt Enable. 0 0 The SlvPending interrupt is disabled. 1 The SlvPending interrupt is enabled. 10:9 - Reserved. Read value is undefined, only zero should be written. NA 11 SLVNOTSTREN Slave Not Stre tching interrupt Enable. 0 0 The SlvNotStr interrupt is disabled. 1 The SlvNotStr interrupt is enabled. 14:12 - Reserved. Read value is undefined, only zero should be written. NA 15 SLVDESELEN Slave Deselect interrupt Enable. 0 0 The SlvDeSel interrupt is disabled. 1 The SlvDeSel interrupt is enabled. 16 MONRDYEN Monitor data Ready interrupt Enable. 0 0 The MonRdy interrupt is disabled. 1 The MonRdy interrupt is enabled. 17 MONOVEN Monitor Overrun interrupt Enable. 0 0 The MonOv interrupt is disabled. 1 The MonOv interrupt is enabled. 18 - Reserved. Read value is undefined, only zero should be written. NA

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16.6.4 Interrupt Enable Clear register

Writing a 1 to a bit position in INTENCLR clears the corresponding position in the INTENSET register, disabling that interrupt. INTENCLR is a write-only register. Bits that do not correspond to defined bits in INTENSET are reserved and only zeroes should be written to them. 19 MONIDLEEN Monitor Idle interrupt Enable. 0 0 The MonIdle interrupt is disabled. 1 The MonIdle interrupt is enabled. 23:20 - Reserved. Read value is undefined, only zero should be written. NA 24 EVENTTIMEOUTEN Event time -out interrupt Enable. 0 0 The Event time-out interrupt is disabled. 1 The Event time-out interrupt is enabled. 25 SCLTIMEOUTEN SCL time-out interrupt Enable. 0 0 The SCL time-out interrupt is disabled. 1 The SCL time-out interrupt is enabled. 31:26 - Reserved. Read value is undefined, only zero should be written. NA Bit Symbol Value Description Reset value Table 175. Interrupt Enable Clear regist er (INTENCLR, address 0x4005 000C) bit Bit Symbol Description Reset value 0 MSTPENDINGCLR Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. 3:1 - Reserved. Read value is undefined, only zero should be written. NA 4 MSTARBLOSSCLR Master Arbitration Loss interrupt clear. 0 5 - Reserved. Read value is undefined, only zero should be written. NA 6 MSTSTSTPERRCLR Master Start/Stop Error interrupt clear. 0 7 - Reserved. Read value is undefined, only zero should be written. NA 8 SLVPENDINGCLR Slave Pending interrupt clear. 0 10:9 - Reserved. Read value is undefined, only zero should be written. NA 11 SLVNOTSTRCLR Slave Not St retching interrupt clear. 0 14:12 - Reserved. Read value is undefined, only zero should be written. NA

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16.6.5 Time-out value register

The TIMEOUT register allows setting an upper limit to certain I2C bus times, informing by status flag and/or interrupt when those times are exceeded. Two time-outs are generated, software can elect to use either of them. EVENTTIMEOUT checks the time between bus events while the bus is not idle: Start, SCL rising, SCL falling, and Stop. The EVENTTIMEOUT status flag in the STAT register is set if the time between any two events becomes longer than the time configured in the TIMEOUT register. The EVENTTIMEOUT status flag can cause an interrupt if enabled to do so by the EVENTTIMEOUTEN bit in the INTENSET register. SCLTIMEOUT checks only the time that the SCL signal remains low, while the bus is not idle. The SCLTIMEOUT status flag in the STAT register is set if SCL remains low longer than the time configured in the TIMEOUT register. The SCLTIMEOUT status flag can cause an interrupt if enabled to do so by the SCLTIMEOUTEN bit in the INTENSET register. Also see Section 16.7.2 “ Time-out”. 15 SLVDESELCLR Slave Deselect interrupt clear. 0 16 MONRDYCLR Monitor data Ready interrupt clear. 0 17 MONOVCLR Monitor Overrun interrupt clear. 0 18 - Reserved. Read value is undefined, only zero should be written. NA 19 MONIDLECLR Monitor Idle interrupt clear. 0 23:20 - Reserved. Read value is undefined, only zero should be written. NA 24 EVENTTIMEOUTCLR Event time -out interrupt clear. 0 25 SCLTIMEOUTCLR SCL time-out interrupt clear. 0 31:26 - Reserved. Read value is undefined, only zero should be written. NA …continued Bit Symbol Description Reset value

16.6.6 I2C Clock Divider register

register for Master operation and the SLVTIME register for Slave operation. See Section 16.7.1.1 “Rate calculations” for details on bus rate setup.

16.6.7 I2C Interrupt Status register

detailed descriptions of the interrupt flags. Table 176. time-out register (TIMEOUT, address 0x4005 0010) bit description 3:0 TOMIN Time-out time value, bottom f our bits. These are hard-wired to 0xF. time-out resolution of 16 I2C function clocks. value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. Table 177. I 2C Clock Divider register (DIV, address 0x4005 0014) bit description that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C function. 0x0001 = PCLK is divided by 2 before use by the I2C function. 0x0002 = PCLK is divided by 3 before use by the I2C function. 0xFFFF = PCLK is divided by 65,536 before use by the I2C function.

16.6.8 Master Control register

Table 178. I 2C Interrupt Status register (INTSTAT, address 0x4005 0018) bit description Table 179. Master Control register (MSTCTL, address 0x4005 0020) bit description

16.6.9 Master Time

time, and transmitted data setup time. The I2C clock pre-divider is described in Table 177. Table 180. Master Time register (MSTTIME, address 0x4005 0024) bit description on the bus (masters or slaves) could lengthen this time.

16.6.10 Master Data register

Master function, and to transmit data using the Master function.

16.6.11 Slave Control register

The SLVCTL register contains bits that control various functions of the I2C Slave interface. masters in a multi-master system could shorten this time. Table 180. Master Time register (MSTTIME, address 0x4005 0024) bit description …continued Table 181. Master Data register (MSTDAT, address 0x4005 0028) bit description 7:0 DATA Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.

16.6.12 Slave Data register

Slave function and to transmit data using the Slave function. Table 182. Slave Control register (SLVCTL, address 0x4005 0040) bit description Table 183. Slave Data register (SLVDAT, address 0x4005 0044) bit description 7:0 DATA Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.

16.6.13 Slave Address registers

qualified by the setting of the SLVQUAL0 register. setting of the SLVQUAL0 register (see Section 16.6.14). of the 4 address registers can be programmed to respond to address 0.

16.6.14 Slave address Qualifier 0 register

The SLVQUAL0 register can alter how Slave Address 0 is interpreted. Table 184. Slave Address registers (SLVADR[0:3]- address 0x4005 0048 (SLVADR0) to 1 Ignored Slave Address n is ignored.

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16.6.15 Monitor data register

The read-only MONRXDAT register provides information about events on the I2C bus, primarily to facilitate debugging of the I2C during application development. All data addresses and data passing on the bus and whether these were acknowledged, as well as Start and Stop events, are reported. The Monitor function must be enabled by the MONEN bit in the CFG register. Monitor mode can be configured to stretch the I 2C clock if data is not read from the MONRXDAT register in time to prevent it, via the MONCLKSTR bit in the CFG register. This can help ensure that nothing is missed but can cause the monitor function to be somewhat intrusive (by potentially adding clock delays, depending on software response time). In order to improve the chance of collecting all Monitor information if clock stretching is not enabled, Monitor data is buffered such that it is available until the end of the next piece of information from the I 2C bus. Table 185. Slave address Qualifier 0 regist er (SLVQUAL0, address 0x4005 0058) bit Bit Symbol Value Description Reset Value 0 QUALMODE0 Reserved. Read value is undefined, only zero should be written.

0 The SLVQUAL0 field is used as a logical mask for

matching address 0.

1 The SLVQUAL0 field is used to extend address 0

matching in a range of addresses. 7:1 SLVQUAL0 Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). 31:8 - Reserved. Read value is undefined, only zero should be written. NA Table 186. Monitor data register (MONRXDAT, address 0x4005 0080) bit description Start, Repeated Start, and data Nack.

16.7 Functional description

16.7.1 Bus rates and timing considerations

operate if nothing slows it down.

16.7.1.1 Rate calculations

16.7.2 Time-out

do something to alleviate the condition. Two different types of time-out are supported. Master, Slave, or Monitor functions do not need to be enabled. Repeated Start event on the I2C bus. detected a Repeated Start event on the I2C bus.

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16.7.3 Ten-bit addressing

Ten-bit addressing is accomplished by the I2C master sending a second address byte to extend a particular range of standard 7-bit addresses. In the case of the master writing to the slave, the I2C frame simply continues with data after the 2 address bytes. For the master to read from a slave, it needs to reverse the data direction after the second address byte. This is done by sending a Repeated Start, followed by a repeat of the same standard 7-bit address, with a Read bit. The slave must remember that it had been addressed by the previous write operation and stay selected for the subsequent read with the correct partial I 2C address. For the Master function, the I2C is simply instructed to perform the 2-byte addressing as a normal write operation, followed either by more write data, or by a Repeated Start with a repeat of the first part of the 10-bit slave address and then reading in the normal fashion. For the Slave function, the first part of the address is automatically matched in the same fashion as 7-bit addressing. The Slave address qualifier feature (see Section 16.6.14) can be used to intercept all potential 10-bit addresses (first address byte values F0 through F6), or just one. In the case of Slave Receiver mode, data is received in the normal fashion after software matches the first data byte to the remaining portion of the 10-bit address. The Slave function should record the fact that it has been addressed, in case there is a follow-up read operation. For Slave Transmitter mode, the slave function responds to the initial address in the same fashion as for Slave Receiver mode, and checks that it has previously been addressed with a full 10-bit address. If the address matched is address 0, and address qualification is enabled, software must check that the first part of the 10-bit address is a complete match to the previous address before acknowledging the address.

16.7.4 Clocking and power considerations

The Master function of the I2C always requires a peripheral clock to be running in order to operate. The Slave function can operate without any internal clocking when the slave is not currently addressed. This means that reduced power modes up to Power-down mode can be entered, and the device will wake up when the I2C Slave function recognizes an address. Monitor mode can similarly wake up the device from a reduced power mode when information becomes available.

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17.1 How to read this chapter

SPI0 is available on all parts. SPI1 is available on parts LPC812M101FDH16 and LPC812M101FDH20 only.

17.2 Features

• Data frames of 1 to 16 bits supported directly. Larger frames supported by software.
• Master and slave operation.
• Data can be transmitted to a slave without the need to read incoming data. This can be useful while setting up an SPI memory, for instance.
• Control information can optionally be written along with data. This allows very versatile operation, including “any length” frames.
• One Slave Select input/output with selectable polarity and flexible usage. Remark: Texas Instruments SSI and National Microwire modes are not supported.

17.3 Basic configuration

Configure SPI0/1 using the following registers:

• In the SYSAHBCLKCTRL register, set bit 11 and 12 (Table 18) to enable the clock to the register interface.
• Clear the SPI0/1 peripheral resets using the PRESETCTRL register (Table 7).
• Enable/disable the SPI0/1 interrupts in interrupt slots #0 and 1 in the NVIC.
• Configure the SPI0/1 pin functions through the switch matrix. See Section 17.4.
• The peripheral clock for both SPIs is the system clock (see Figure 3 “LPC800 clock generation”).

17.3.1 Configure the SPIs for wake-up

The SPI can wake up the system from sleep mode in master or slave mode. UM10601 Chapter 17: LPC800 SPI0/1 Rev. 1.0 — 7 November 2012 Preliminary user manual Fig 26. SPI clocking /g38/g79/g82/g70/g78/g3/g71/g76/g89/g76/g71/g72/g85 /g39/g76/g89/g57/g68/g79 /g54/g51/g44/g3/g85/g68/g87/g72 /g3/g70/g79/g82/g70/g78 /g54/g51/g44/g19/g18/g20 /g54/g60/g54/g38/g50/g49 /g86/g92/g86/g87/g72/g80/g3/g70/g79/g82/g70/g78 /g54/g60/g54/g36/g43/g37/g38/g47/g46/g38/g55/g53/g47/g62/g20/g20/g15/g3/g20/g21/g64 /g11/g54/g51/g44/g19/g18/g20/g3/g70/g79/g82/g70/g78/g3/g72/g81/g68/g69/g79/g72/g12 /g54/g51/g44/g19/g18/g20/g66/g51/g38/g47/g46

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17.3.1.1 Wake-up from Sleep mode

• Configure the SPI in either master or slave mode. See Table 189.
• Enable the SPI interrupt in the NVIC.
• Any SPI interrupt wakes up the part from sleep mode. Enable the SPI interrupt in the INTENSET register (Table 192).

17.3.1.2 Wake-up from Deep-sleep or Power-down mode

• Configure the SPI in slave mode. See Table 189. You must connect the SCK function to a pin and connect the pin to the master.
• Enable the SPI interrupt in the STARTERP1 register. See Table 34 “Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit description”.
• Enable the SPI interrupt in the NVIC.
• The SPI wakes up the part from Deep-sleep or Power-down mode on the following events that cause an interrupt: – A change in the state of the SSEL pin. – <tbd>. Remark: Enable the interrupt for each wake-up event in the INTENSET register (Table 192).

17.4 Pin description

The SPI signals are movable functions and are assigned to external pins through the switch matrix. See Section 9.3.1 “Connect an internal signal to a package pin” to assign the SPI functions to pins on the LPC800 package.

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17.5 General description

17.6 Register description

RXIgnore, individual interrupt enables. Table 188. Register overview: SPI (base address 0x4005 8000 (SPI0) and 0x4008 C000

0 Table 192

Table 188. Register overview: SPI (base address 0x4005 8000 (SPI0) and 0x4008 C000 (SPI1))

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17.6.1 SPI Configuration register

The CFG register contains information for the general configuration of the SPI. Typically, this information is not changed during operation. Some configurations, such as CPOL, CPHA, and LSBF should not be made while the SPI is not fully idle. See the description of the Idle status (in Table 191) for more information. Remark: If the interface is re-configured from Master mode to Slave mode or the reverse (an unusual case), the SPI should be disabled and re-enabled with the new configuration. Table 189. SPI Configuration register (CFG, addresses 0x4005 8000 (SPI0) , 0x4005 C000 (SPI1)) bit Bit Symbol Value Description Reset value 0 Enable SPI enable. 0 0 Disabled. The SPI is disabled and the internal state machine and counters are reset. 1 Enabled. The SPI is enabled for operation. 1 - Reserved. Read value is undefined, only zero should be written. NA 2 Master Master mode select. 0 0 Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. 1 Master mode. The SPI will operate in mast er mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. 3 LSBF LSB First mode enable. 0 0 Standard. Data is transmitted and received in standard MSB first order. 1 Reverse. Data is transmitted and received in reverse order (LSB first). 4 CPHA Clock Phase select. 0 0 Change. The SPI captures serial data on the fi rst clock transition of the frame (when the clock changes away from the rest state). Data is changed on the following edge. 1 Capture. The SPI changes serial data on the fi rst clock transition of the frame (when the clock changes away from the rest state). Data is captured on the following edge. 5 CPOL Clock Polarity select. 0 0 Low. The rest state of the cl ock (between frames) is low. 1 High. The rest state of the clock (between frames) is high. 6 - Reserved. Read value is undefined, only zero should be written. NA 7 LOOP Loopback mode enable. Loopback mode appl ies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. 0 Disabled. 1 Enabled. 8 SPOL SSEL Polarity select. 0 0 Low. The SSEL pin is active low. The value in the SSEL fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL is not inverted relative to the pins. 1 High. The SSEL pin is acti ve high. The value in the SSEL fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL is inverted relative to the pins. 31:9 - Reserved. Read value is undefined, only zero should be written. NA

17.6.2 SPI Delay register

delays apply only to master mode, and are all stated in SPI clocks. Table 190. SPI Delay register (DLY, addresses 0x4005 8004 (SPI0) , 0x4005 C004 (SPI1)) bit description There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 7:4 POST_DELAY Controls the amount of time between the end of a data frame and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 11:8 FRAME_DELAY Controls the minimum amount of time between adjacent data frames. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 15:12 TRANSFER_DELAY Controls the minimum amount of ti me that the SSEL is deasserted between transfers. 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.

17.6.3 SPI Status register

to corresponding bits of STAT. attempting to resume operation. In this register, the following notation is used: RO = Read-only, W1 = write 1 to clear.. Table 191. SPI Status register (STAT, addresses 0x4005 8008 (SPI0) , 0x4005 C008 (SPI1)) bit description the receiver buffer. Cleared after a read of the RXDAT register. is moved to the transmit shift register. lost. Data received by the SPI should be considered undefined if RxOv is set. begins. This flag is cleared by software. any specified FrameDelay and TransferDelay to be inserted.

0 RO/W1

the process of sending data.

[1] RO = Read-only, W1 = write 1 to clear.

17.6.4 SPI Interrupt Enable read and Set register

for details of the interrupts. Table 192. SPI Interrupt Enable read and Set register (INTENSET, addresses 0x4005 800C (SPI0) , 0x4005 C00C 0 No interrupt will be generated when receiver data is available. 1 An interrupt will be generated when receiver data is available in the RXDAT register.

1 TXRDYEN Determines whether an interrupt occurs when the transmitter holding register is

0 No interrupt will be generated when the transmitter holding register is available. 1 An interrupt will be generated when data may be written to TXDAT. RXDAT register when it is already in use. transmission to begin when a receiver overrun would otherwise occur. 0 No interrupt will be generated when a receiver overrun occurs. 1 An interrupt will be generated if a receiver overrun occurs. happens in slave mode when there is a need to transmit data when none is available. 0 No interrupt will be generated when the transmitter underruns. 1 An interrupt will be generated if the transmitter underruns.

0 No interrupt will be generated when any Slave Select transitions from deasserted to

1 An interrupt will be generated when any Slav e Select transitions from deasserted to

0 No interrupt will be generated when all assert ed Slave Selects transition to deasserted. 1 An interrupt will be generated when all asserted Slave Selects transition to deasserted.

17.6.5 SPI Interrupt Enable Clear register

The INTENCLR register is used to clear interrupt enable bits in the INTENSET register.

17.6.6 SPI Receiver Data register

data. The value of SSEL can be read along with the data. For details on the slave select process, see Section 17.7.4. Table 193. SPI Interrupt Enable clear register (INTENCLR, addresses 0x4005 8010 (SPI0) , Table 194. SPI Receiver Data register (RXD AT, addresses 0x4005 8014 (SPI0) , 0x4005 C014 15:0 RXDAT Receiver Data. This contains the next piece of received data. slave select pin is configured by the related SPOL bit in CFG.

17.6.7 SPI Transmitter Da ta and Control register

separate write of control information for each piece of data. registers simply provide two ways to access them. For details on the slave select process, see Section 17.7.4. Section 17.7.5 “Data lengths greater than 16 bits”. Table 195. SPI Transmitter Data and Control register (TXDATCTL, addresses 0x4005 8018 (SPI0) , 0x4005 C018 16 TXSSELN Transmit Slave Select . Th is field controls what is output for SSEL in master mode. will not be deasserted at the end of this data. deasserted at the end of this piece of data. support for frame lengths greater than 16 bits. 0 Data not EOF. This piece of data transmit ted is not treated as the end of a frame. FRAME_DELAY time to be inserted before subsequent data is transmitted. read unneeded data from the receiver to simplify the transmit process. unneeded received data. No receiver flags are generated.

17.6.8 SPI Transmitter Data Register

17.6.9 SPI Transmitter Control register

The TXCTL register provides a way to separately access control information for the SPI. TXDAT register. Data written to TXDATCTL overwrites the TXCTL register. then be written along with data. greater than 16 bits are supported by implementing multiple sequential frames. a length of one SCK time following the single clock seen on the SCK pin. 0x0 = Data frame is 1 bit in length. 0x1 = Data frame is 2 bits in length. 0x2 = Data frame is 3 bits in length. 0xF = Data frame is 16 bits in length. Table 196. SPI Transmitter Data Register (TXDAT, addresses 0x4005 801ST (SPI0) , 0x4005

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17.6.10 SPI Divider register

The DIV register determines the clock used by the SPI in master mode. For details on clocking, see Section 17.7.3 “Clocking and data rates”.

17.6.11 SPI Interrupt Status register

The read-only INTSTAT register provides a view of those interrupt flags that are currently enabled. This can simplify software handling of interrupts. See Table 191 for detailed descriptions of the interrupt flags. Table 197. SPI Transmitter Control register (TXCTL, addresses 0x4005 8020 (SPI0) , 0x4005 Table 198. SPI Divider register (DIV, addresses 0x4005 8024 (SPI0) , 0x4005 C024(SPI1)) bit Bit Symbol Description Reset Value 15:0 DIVVAL Rate divider value,1. Specifie s how the PCLK for the SPI is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in PCLK/1, the value 1 results in PCLK/2, up to the maximum possible divide value of 0xFFFF, which results in PCLK/65536. 31:16 - Reserved. Read value is undefined, only zero should be written. NA Table 199. SPI Interrupt Status register (INTSTAT, addresses 0x4005 8028 (SPI0) , 0x4005

17.7 Functional description

17.7.1 Operating modes: clock and phase selection

Figure 28. CPOL and CPHA are configured by bits in the CFG register (Section 17.6.1). state). Data is changed on the following edge. state). Data is captured on the following edge.

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17.7.2 Frame delays

Several delays can be specified for SPI frames. These include:

• Pre_delay: delay after SSEL is asserted before data clocking begins
• Post_delay: delay at the end of a data frame before SSEL is deasserted
• Frame_delay: delay between data frames when SSEL is not deasserted
• Transfer_delay: minimum duration of SSEL in the deasserted state between transfers

17.7.2.1 Pre_delay and Post_delay

Pre_delay and Post_delay are illustrated by the examples in Figure 29. The Pre_delay value controls the amount of time between SSEL being asserted and the beginning of the subsequent data frame. The Post_delay value controls the amount of time between the end of a data frame and the deassertion of SSEL. Fig 29. Pre_delay and Post_delay /g51/g85/g72/g16/g68/g81/g71/g3/g83/g82/g86/g87/g16/g71/g72/g79/g68/g92/g29/g3/g38/g51/g43/g36/g3/g32/g3/g19/g15/g3/g51/g85/g72/g66/g71/g72/g79/g68/g92/g3/g32/g3/g21/g15/g3/g51/g82/g86/g87/g66/g71/g72/g79/g68/g92/g3/g32/g3/g20 /g48/g82/g71/g72/g3/g21/g3/g11/g38/g51/g50/g47/g3/g32/g3/g20/g12/g3/g3/g3/g3/g54/g38/g46 /g48/g44/g54/g50 /g48/g50/g54/g44 /g54/g54/g40/g47 /g48/g54/g37 /g48/g54/g37 /g47/g54/g37 /g47/g54/g37 /g51/g85/g72/g66/g71/g72/g79/g68/g92 /g51/g82/g86/g87/g66/g71/g72/g79/g68/g92 /g48/g82/g71/g72/g3/g19/g3/g11/g38/g51/g50/g47/g3/g32/g3/g19/g12/g3/g3/g3/g3/g54/g38/g46 /g51/g85/g72/g16/g68/g81/g71/g3/g83/g82/g86/g87/g16/g71/g72/g79/g68/g92/g29/g3/g38/g51/g43/g36/g3/g32/g3/g20/g15/g3/g51/g85/g72/g66/g71/g72/g79/g68/g92/g3/g32/g3/g21/g15/g3/g51/g82/g86/g87/g66/g71/g72/g79/g68/g92/g3/g32/g3/g20 /g48/g82/g71/g72/g3/g22/g3/g11/g38/g51/g50/g47/g3/g32/g3/g20/g12/g3/g3/g3/g3/g54/g38/g46 /g54/g54/g40/g47 /g51/g85/g72/g66/g71/g72/g79/g68/g92 /g51/g82/g86/g87/g66/g71/g72/g79/g68/g92 /g48/g82/g71/g72/g3/g20/g3/g11/g38/g51/g50/g47/g3/g32/g3/g19/g12/g3/g3/g3/g3/g54/g38/g46 /g39/g68/g87/g68/g3/g73/g85/g68/g80/g72 /g39/g68/g87/g68/g3/g73/g85/g68/g80/g72 /g48/g54/g37 /g47/g54/g37 /g48/g54/g37 /g47/g54/g37

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17.7.2.2 Frame_delay

The Frame_delay value controls the amount of time at the end of each frame. This delay is inserted when the EOF bit = 1. Frame_delay is illustrated by the examples in Figure 30. Note that frame boundaries occur only where specified. This is because frame lengths can be any size, involving multiple data writes. See Section 17.7.5 for more information. Fig 30. Frame_delay /g41/g85/g68/g80/g72/g3/g71/g72/g79/g68/g92/g29/g3/g38/g51/g43/g36/g3/g32/g3/g19/g15/g3/g41/g85/g68/g80/g72/g66/g71/g72/g79/g68/g92/g3/g32/g3/g21/g15/g3/g51/g85/g72/g66/g71/g72/g79/g68/g92/g3/g32/g3/g19/g15/g3/g51/g82/g86/g87/g66/g71/g72/g79/g68/g92/g3/g32/g3/g19 /g48/g82/g71/g72/g3/g21/g3/g11/g38/g51/g50/g47/g3/g32/g3/g20/g12/g3/g3/g3/g3/g54/g38/g46 /g41/g85/g68/g80/g72/g66/g71/g72/g79/g68/g92 /g48/g82/g71/g72/g3/g19/g3/g11/g38/g51/g50/g47/g3/g32/g3/g19/g12/g3/g3/g3/g3/g54/g38/g46 /g48/g54/g37 /g47/g54/g37 /g48/g54/g37 /g47/g54/g37/g48/g44/g54/g50 /g48/g50/g54/g44 /g54/g54/g40/g47 /g48/g54/g37 /g48/g54/g37 /g54/g72/g70/g82/g81/g71/g3/g71/g68/g87/g68/g3/g73/g85/g68/g80/g72 /g47/g54/g37 /g47/g54/g37 /g41/g85/g68/g80/g72/g3/g71/g72/g79/g68/g92/g29/g3/g38/g51/g43/g36/g3/g32/g3/g20/g15/g3/g41/g85/g68/g80/g72/g66/g71/g72/g79/g68/g92/g3/g32/g3/g21/g15/g3/g51/g85/g72/g66/g71/g72/g79/g68/g92/g3/g32/g3/g19/g15/g3/g51/g82/g86/g87/g66/g71/g72/g79/g68/g92/g3/g32/g3/g19 /g48/g54/g37 /g47/g54/g37 /g48/g54/g37 /g47/g54/g37/g48/g44/g54/g50 /g48/g50/g54/g44 /g54/g54/g40/g47 /g48/g82/g71/g72/g3/g20/g3/g11/g38/g51/g50/g47/g3/g32/g3/g19/g12/g3/g3/g3/g3/g54/g38/g46 /g48/g82/g71/g72/g3/g22/g3/g11/g38/g51/g50/g47/g3/g32/g3/g20/g12/g3/g3/g3/g3/g54/g38/g46 /g41/g85/g68/g80/g72/g66/g71/g72/g79/g68/g92 /g48/g54/g37 /g48/g54/g37 /g54/g72/g70/g82/g81/g71/g3/g71/g68/g87/g68/g3/g73/g85/g68/g80/g72/g41/g76/g85/g86/g87/g3/g71/g68/g87/g68/g3/g73/g85/g68/g80/g72 /g41/g76/g85/g86/g87/g3/g71/g68/g87/g68/g3/g73/g85/g68/g80/g72 /g47/g54/g37 /g47/g54/g37

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17.7.2.3 Transfer_delay

The Transfer_delay value controls the minimum amount of time that SSEL is deasserted between transfers, because the EOT bit = 1. When Transfer_delay = 0, SSEL may be deasserted for a minimum of one SPI clock time. Transfer_delay is illustrated by the examples in Figure 31. Fig 31. Transfer_delay /g41/g85/g68/g80/g72/g3/g71/g72/g79/g68/g92/g29/g3/g38/g51/g43/g36/g3/g32/g3/g19/g15/g3/g41/g85/g68/g80/g72/g66/g71/g72/g79/g68/g92/g3/g32/g3/g21/g15/g3/g51/g85/g72/g66/g71/g72/g79/g68/g92/g3/g32/g3/g19/g15/g3/g51/g82/g86/g87/g66/g71/g72/g79/g68/g92/g3/g32/g3/g19 /g48/g82/g71/g72/g3/g21/g3/g11/g38/g51/g50/g47/g3/g32/g3/g20/g12/g3/g3/g3/g3/g54/g38/g46 /g41/g85/g68/g80/g72/g66/g71/g72/g79/g68/g92 /g48/g82/g71/g72/g3/g19/g3/g11/g38/g51/g50/g47/g3/g32/g3/g19/g12/g3/g3/g3/g3/g54/g38/g46 /g48/g54/g37 /g47/g54/g37 /g48/g54/g37 /g47/g54/g37/g48/g44/g54/g50 /g48/g50/g54/g44 /g54/g54/g40/g47 /g48/g54/g37 /g48/g54/g37 /g54/g72/g70/g82/g81/g71/g3/g71/g68/g87/g68/g3/g73/g85/g68/g80/g72 /g47/g54/g37 /g47/g54/g37 /g41/g85/g68/g80/g72/g3/g71/g72/g79/g68/g92/g29/g3/g38/g51/g43/g36/g3/g32/g3/g20/g15/g3/g41/g85/g68/g80/g72/g66/g71/g72/g79/g68/g92/g3/g32/g3/g21/g15/g3/g51/g85/g72/g66/g71/g72/g79/g68/g92/g3/g32/g3/g19/g15/g3/g51/g82/g86/g87/g66/g71/g72/g79/g68/g92/g3/g32/g3/g19 /g48/g54/g37 /g47/g54/g37 /g48/g54/g37 /g47/g54/g37/g48/g44/g54/g50 /g48/g50/g54/g44 /g54/g54/g40/g47 /g48/g82/g71/g72/g3/g20/g3/g11/g38/g51/g50/g47/g3/g32/g3/g19/g12/g3/g3/g3/g3/g54/g38/g46 /g48/g82/g71/g72/g3/g22/g3/g11/g38/g51/g50/g47/g3/g32/g3/g20/g12/g3/g3/g3/g3/g54/g38/g46 /g41/g85/g68/g80/g72/g66/g71/g72/g79/g68/g92 /g48/g54/g37 /g48/g54/g37 /g54/g72/g70/g82/g81/g71/g3/g71/g68/g87/g68/g3/g73/g85/g68/g80/g72/g41/g76/g85/g86/g87/g3/g71/g68/g87/g68/g3/g73/g85/g68/g80/g72 /g41/g76/g85/g86/g87/g3/g71/g68/g87/g68/g3/g73/g85/g68/g80/g72 /g47/g54/g37 /g47/g54/g37

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17.7.3 Clocking and data rates

In order to use the SPI, clocking details must be defined. This includes configuring the system clock and selection of the clock divider value in DIV. See Figure 26.

17.7.3.1 Data rate calculations

The SPI interface is designed to operate asynchronously from any on-chip clocks, and without the need for overclocking. In slave mode, this means that the SCK from the external master is used directly to run the transmit and receive shift registers and other logic. The upper rate limit depends on the speed of the logic and pin electronics, and signalling quality in the external connections. In master mode, the SPI rate clock produced by the SPI clock divider is used directly as the outgoing SCK. Again, the upper rate limit depends on the speed of the logic and pin electronics, and signalling quality in the external connections. The SPI clock divider is an integer divider. The SPI in master mode can be set to run at the same speed as the selected PCLK, or at lower integer divide rates. The SPI rate will be = PCLK_SPIn / DIVVAL. In slave mode, the clock is taken from the SCK input and the SPI clock divider is not used.

17.7.4 Slave select

The SPI block provides for one Slave Select input in slave mode or output in master mode. The SSEL can be set for normal polarity (active low), or can be inverted (active high). Representation of the SSEL in a register is always active low. If the SSEL is inverted, this is done as the signal leaves/enters the SPI block. In slave mode, the asserted SSEL that is connected to a pin will activate the SPI. In master mode, the SSEL that is connected to a pin will be output as defined in the SPI registers. In master mode, the Slave Select is configured by the TXSSE LN field, which appears in both the CCD and DETECT registers. In slave mode, the state of the SSEL is saved along with received data in the RXSSELN field of the RXDAT register.

17.7.5 Data lengths greater than 16 bits

The SPI interface handles data frame sizes from 1 to 16 bits directly. Larger sizes can be handled by splitting data up into groups of 16 bits or less. For example, 24 bits can be supported as 2 groups of 16 bits and 8 bits or 2 groups of 12 bits, among others. Frames of any size, including greater than 32 bits, can supported in the same way. Details of how to handle larger data widths depend somewhat on other SPI configuration options. For instance, if it is intended for Slave Selects to be deasserted between frames, then this must be suppressed when a larger frame is split into more than one part. Sending 2 groups of 12 bits with SSEL deasserted between 24-bit increments, for instance, would require changing the value of the EOF bit on alternate 12-bit frames.

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17.7.6 Data stalls

A stall for Master transmit data can happen in modes 0 and 2 when SCK cannot be returned to the rest state until the MSB of the next data frame can be driven on MOSI. In this case, the stall happens just before the final clock edge of data if the next piece of data is not yet available. A stall for Master receive can happen when a receiver overrun would otherwise occur if the transmitter was not stalled. In modes 0 and 2, this occurs if the previously received data is not read before the end of the next piece of is received. This stall happens one clock edge earlier than the transmitter stall. In modes 1 and 3, the same kind of receiver stall can occur, but just before the final clock edge of the received data. Also, a transmitter stall will not happen in modes 1 and 3 because the transmitted data is complete at the point where a stall would otherwise occur, so it is not needed. Stalls are reflected in the STAT register by the Stalled status flag, which indicates the current SPI status.

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18.1 How to read this chapter

The CRC engine is available on all LPC800 parts.

18.2 Features

• Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. – CRC-CCITT: x16 + x12 + x5 + 1 – CRC-16: x16 + x15 + x2 + 1 – CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
• Bit order reverse and 1’s complement programmable setting for input data and CRC sum.
• Programmable seed number setting.
• Supports CPU PIO back-to-back transfer.
• Accept any size of data width per write: 8, 16 or 32-bit. – 8-bit write: 1-cycle operation – 16-bit write: 2-cycle operation (8-bit x 2-cycle) – 32-bit write: 4-cycle operation (8-bit x 4-cycle)

18.3 Basic configuration

Enable the clock to the CRC engine in the SYSAHBCLKCTRL register (Table 18, bit 13).

18.4 Pin description

The CRC engine has no configurable pins.

18.5 General description

The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. UM10601 Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine Rev. 1.0 — 7 November 2012 Preliminary user manual

18.6 Description

18.7 Register description

Table 201. Register overview: CRC en gine (base address 0x5000 0000)

18.7.1 CRC mode register

18.7.2 CRC seed register

18.7.3 CRC checksum register

results are valid and the checksum computation is complete.

18.7.4 CRC data register

Table 202. CRC mode register (MODE, ad dress 0x5000 0000) bit description

2 BIT_RVS_WR Data bit order:

3 CMPL_WR Data complement:

4 BIT_RVS_SUM CRC sum bit order:

5 CMPL_SUM CRC sum complement:

Table 203. CRC seed register (SEED, address 0x5000 0004) bit description CRC calculation in progresses. Table 204. CRC checksum register (SUM, address 0x5000 0008) bit description

Table 205. CRC data register (WR_DATA, address 0x5000 0008) bit description accept back-to-back transactions.

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18.8 Functional description

The following sections describe the register settings for each supported CRC standard:

18.8.1 CRC-CCITT set-up

Polynomial = x16 + x12 + x5 + 1 Seed Value = 0xFFFF Bit order reverse for data input: NO 1's complement for data input: NO Bit order reverse for CRC sum: NO 1's complement for CRC sum: NO CRC_MODE = 0x0000 0000 CRC_SEED = 0x0000 FFFF

18.8.2 CRC-16 set-up

Polynomial = x16 + x15 + x2 + 1 Seed Value = 0x0000 Bit order reverse for data input: YES 1's complement for data input: NO Bit order reverse for CRC sum: YES 1's complement for CRC sum: NO CRC_MODE = 0x0000 0015 CRC_SEED = 0x0000 0000

18.8.3 CRC-32 set-up

Polynomial = x32+ x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 Seed Value = 0xFFFF FFFF Bit order reverse for data input: YES 1's complement for data input: NO Bit order reverse for CRC sum: YES 1's complement for CRC sum: YES CRC_MODE = 0x0000 0036 CRC_SEED = 0xFFFF FFFF

19.1 How to read this chapter

The flash controller is identical on all LPC800 parts.

19.2 Features

• Controls flash access time.
• Provides registers for flash signature generation.

19.3 General description

19.4 Register description

19.4.1 Flash configuration register

with various access times by writing to the FLASHCFG register at address 0x4003 C010. Table 206. Register overview: FMC (base address 0x4004 0000)

19.4.2 Flash signature start address register

19.4.3 Flash signatur e stop address register

19.4.4 Flash signature generation result register

embedded signature generator. Table 207. Flash configuration register (FLA SHCFG, address 0x4003 C010) bit description number of system clocks used for flash access. frequencies of up to 20 MHz). frequencies of up to 30 MHz). Table 208. Flash Module Signature Start regist er (FMSSTART - 0x4003 C020) bit description 31:17 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Table 209. Flash Module Signature Stop regist er (FMSSTOP - 0x4003 C024) bit description specified by STOPA is included in the address range). The address is in units of memory words, not bytes. 31 STRTBIST When this bit is written to 1, signature generation starts.

19.5 Functional description

19.5.1 Flash signature generation

contents against a calculated signature (e.g. during programming). signature generation should also be placed outside of the flash memory.

19.5.1.1 Signature generation address and control registers

stop addresses must be aligned to 32-bit boundaries. Signature generation is started by setting the STRTBIST bit in the FMSSTOP register.

19.5.1.2 Signature generation

register, and the stop address to the FMSSTOP register. address, which is done in the STOP bits of the same register. Table 210. FMSW0 register bit descri ption (FMSW0, address: 0x4003 C02C)

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19.5.1.3 Content verification

The signature as it is read from the FMSW0 register must be equal to the reference signature. The following pseudo-code shows the algorithm to derive the reference signature: sign = 0 FOR address = FMSSTART.START to FMSSTOP.STOPA FOR i = 0 TO 30{ nextSign[i] = f_Q[addredd[i] XOR sign[i + 1] nextSign[31] = f_q[address[31] XOR sign[0] XOR sign[10] XOR sign[30] XOR sign[31] sign = nextSign signature32 = sign

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20.1 How to read this chapter

The Boot ROM is identical for all LPC800 parts.

20.2 Features

• 8 kB on-chip boot ROM
• Contains the boot loader with In-System Programming (ISP) facility and the following APIs: – In Application Programming (IAP) of flash memory – Power profiles for optimizing power consumption and system performance – USART drivers – I2C drivers

20.3 General description

20.3.1 Boot loader

The boot loader controls initial operation after reset and also provides the means to accomplish programming of the flash memory via USART. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system. The boot loader code is executed every time the part is powered on or reset. The boot loader can execute the ISP command handler or the user application code. A LOW level after reset at the PIO0_1 pin is considered as an external hardware request to start the ISP command handler via USART. For details on the boot process, see Section 20.4.3 “ Boot process”. Remark: SRAM location 0x1000 0000 to 0x1000 0050 is not used by the bootloader and the memory content in this area is retained during reset. SRAM memory is not retained when the part powers down or enters Deep power-down mode. Assuming that power supply pins are on their nominal levels when the rising edge on RESET pin is generated, it may take up to <tbd>3 ms before PIO0_1 is sampled and the decision whether to continue with user code or ISP handler is made. If PIO0_1 is sampled low and the watchdog overflow flag is set, the external hardware request to start the ISP command handler is ignored. If there is no request for the ISP command handler execution (PIO0_1 is sampled HIGH after reset), a search is made for a valid user program. If a valid user program is found then the execution control is transferred to it. If a valid user program is not found, the auto-baud routine is invoked. Remark: The sampling of pin PIO0_1 can be disabled through programming flash location 0x0000 02FC (see Section 21.3.3 “ Code Read Protection (CRP)”). UM10601 Chapter 20: LPC800 Boot ROM Rev. 1.0 — 7 November 2012 Preliminary user manual

20.3.2 ROM-based APIs

Table 211. API calls

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20.4 Functional description

20.4.1 Boot pins

When pin PIO0_1 is pulled LOW on reset, the part enters ISP mode and the ISP command handler starts up. In ISP mode, pins PIO0_0 is connected to function U0_RXD and pin PIO0_4 is connected to function U0_TXD on the USART0 block.

20.4.2 Memory map after any reset

The boot block is 8 kB in size. The boot block is located in the memory region starting from the address 0x1FFF 0000. The bootloader is designed to run from this memory area, but both the ISP and IAP software use parts of the on-chip RAM. The RAM usage is described later in this chapter. The interrupt vectors residing in the boot block of the on-chip flash memory also become active after reset, i.e., the bottom 512 bytes of the boot block are also visible in the memory region starting from the address 0x0000 0000.

20.4.3 Boot process

During the boot process, the boot loader checks if there is valid user code in flash. The criterion for valid user code is as follows: The reserved Cortex-M0+ exception vector location 7 (offset 0x0000 001C in the vector table) should contain the 2’s complement of the check-sum of table entries 0 through 6. This causes the checksum of the first 8 table entries to be 0. The bootloader code checksums the first 8 locations in sector 0 of the flash. If the result is 0, then execution control is transferred to the user code. If the signature is not valid, the auto-baud routine synchronizes with the host via serial port USART0. The host should send a ’?’ (0x3F) as a synchronization character and wait for a response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity. The auto-baud routine measures the bit time of the received synchronization character in terms of its own frequency (the 12 MHz IRC frequency) and programs the baud rate generator of the serial port. It also sends an ASCII string ("Synchronized<CR><LF>") to the host. In response, the host should send the same string ("Synchronized<CR><LF>"). The boot loader auto-baud routine looks at the received characters to verify synchronization. If synchronization is verified then "OK<CR><LF>" string is sent to the host. The host should respond by sending the crystal frequency (in kHz) at which the part is running. The response is required for backward compatibility of the boot loader code and, on the LPC800, is ignored. The boot loader configures the part to run at the 12 MHz IRC frequency. Once the crystal frequency response is received, the part is initialized and the ISP command handler is invoked. For safety reasons an "Unlock" command is required before executing the commands resulting in flash erase/write operations and the "Go" command. The rest of the commands can be executed without the unlock command. The Unlock command is required to be executed once per ISP session. The Unlock command is explained in Table 218 “ UART ISP Unlock command”.

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20.4.4 Boot process flowchart

(1) This step is included for backward compatibility and the response is ignored by the boot loader. Fig 35. Boot process flowchart /g53/g40/g54/g40/g55 /g44/g49/g44/g55/g44/g36/g47/g44/g61/g40 /g53/g40/g38/g40/g44/g57/g40/g3/g38/g53/g60/g54/g55/g36/g47/g3/g41/g53/g40/g52/g56/g40/g49/g38/g60/g11/g20/g12 /g53/g56/g49/g3/g56/g36/g53/g55/g3/g44/g54/g51/g3/g38/g50/g48/g48/g36/g49/g39/g3/g43/g36/g49/g39/g47/g40/g53 /g53/g56/g49/g3/g36/g56/g55/g50/g16/g37/g36/g56/g39 /g38/g53/g51/g20/g18/g21/g18/g22 /g40/g49/g36/g37/g47/g40/g39/g34/g3 /g58/g36/g55/g38/g43/g39/g50/g42 /g41/g47/g36/g42/g3/g54/g40/g55/g34 /g38/g53/g51/g22/g18/g49/g50/g66/g44/g54/g51 /g40/g49/g36/g37/g47/g40/g39/g34 /g3/g40/g49/g55/g40/g53/g3/g44/g54/g51 /g48/g50/g39/g40/g34 /g11/g51/g44/g50/g19/g66/g20/g3/g32/g3/g47/g50/g58/g12 /g56/g54/g40/g53/g3/g38/g50/g39/g40 /g57/g36/g47/g44/g39/g34 /g56/g54/g40/g53/g3/g38/g50/g39/g40 /g57/g36/g47/g44/g39/g34 /g36/g56/g55/g50/g16/g37/g36/g56/g39 /g54/g56/g38/g38/g40/g54/g54/g41/g56/g47/g34 /g40/g59/g40/g38/g56/g55/g40/g3/g44/g49/g55/g40/g53/g49/g36/g47 /g56/g54/g40/g53/g3/g38/g50/g39/g40 /g40/g49/g36/g37/g47/g40/g3/g39/g40/g37/g56/g42 /g92/g72/g86 /g92/g72/g86 /g92/g72/g86 /g92/g72/g86 /g92/g72/g86 /g92/g72/g86 /g92/g72/g86 /g81/g82 /g81/g82 /g81/g82 /g81/g82 /g81/g82/g81/g82 /g81/g82 /g81/g82 /g36 /g36 /g69/g82/g82/g87/g3/g73/g85/g82/g80 /g3/g56/g36/g53/g55

21.1 How to read this chapter

See Table 212 for different flash configurations.

21.2 Features

• In-System Programming: In-System programming (ISP) is programming or reprogramming the on-chip flash memory, using the bootloader software and UART serial port.
• In-Application Programming: In-Application (IAP) programming is performing erase and write operation on the on-chip flash memory, as directed by the end-user application code.
• You can use ISP and IAP when the part resides in the end-user board.
• Flash page write and erase supported.

21.3 General description

21.3.1 Flash configuration

between page numbers, sector numbers, and memory addresses. Table 212. LPC800 flash configurations Table 213. LPC800 flash configuration

21.3.2 Flash content protection mechanism

consists of single bit error correction with Hamming code. protected by the second 6-bit ECC byte, etc. data containing the specified memory location and the matching ECC byte are evaluated. matching ECC value calculated and stored in the ECC memory. When a sector of Flash memory is erased, the corresponding ECC bits are also erased. memory in groups of 4 bytes (or multiples of 4), aligned as described above.

21.3.3 Code Read Protection (CRP)

location at 0x0000 02FC. IAP commands are not affected by the code read protection.

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• Write to RAM command should not access RAM below 0x1000 0300. Access to addresses below 0x1000 0200 is disabled.
• Copy RAM to flash command can not write to Sector 0.
• Erase command can erase Sector 0 only when all sectors are selected for erase.
• Compare command is disabled.
• Read Memory command is disabled. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. Since compare command is disabled in case of partial updates the secondary loader should implement checksum mechanism to verify the integrity of the flash. CRP2 0x87654321 Access to chip via the SWD pins is disabled. The following ISP commands are disabled:
• Read Memory
• Write to RAM
• Go
• Copy RAM to flash
• Compare When CRP2 is enabled the ISP erase command only allows erasure of all user sectors. CRP3 0x43218765 Access to chip via the SWD pins is dis abled. ISP entry by pulling PIO0_1 LOW is disabled if a valid user code is present in flash sector 0. This mode effectively disables ISP override using PIO0_1 pin. It is up to the user’s application to provide a flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART. Caution: If CRP3 is selected, no future factory testing can be performed on the device.

Table 215. Code Read Protection hardware/software interaction

CODE_READ_PROTECTION_ENABLED.

21.3.3.1 ISP entry protection

21.4 API description

21.4.1 UART ISP commands

been completely executed and the new ISP command can be given by the host. Table 216. ISP commands allowed for different CRP levels

21.4.1.1 Unlock <Unlock code>

21.4.1.2 Set Baud Rate <Baud Rate> <stop bit>

Table 217. UART ISP command summary Table 218. UART ISP Unlock command Description This command is used to unlock Flash Write, Erase, and Go commands. Example "U 23130<CR><LF>" unlocks the Flash Write/Erase & Go commands. Table 219. UART ISP Set Baud Rate command after the command handler sends the CMD_SUCCESS return code. Example "B 57600 1<CR><LF>" sets the serial port to baud rate 57600 bps and 1 stop bit.

21.4.1.3 Echo <setting>

21.4.1.4 Write to RAM <start address> <number of bytes>

21.4.1.5 Read Memory <address> <number of bytes>

Table 220. UART ISP Echo command sends the received serial data back to the host. Example "A 0<CR><LF>" turns echo off. Table 221. UART ISP Write to RAM command 0x1000 0300 is disabled for CRP1. Example "W 268436224 4<CR><LF>" writes 4 bytes of data to address 0x1000 0300.

21.4.1.6 Prepare sector(s) for write operation <start sector number> <end sector

This command makes flash write/erase operation a two step process.

21.4.1.7 Copy RAM to flash <Flash address> <RAM address> <no of bytes>

1. The smallest amount of data that can be written to flash by the copy RAM to flash

command is 64 byte (equal to one page).

1. One page consists of 16 flash words (lines), and the smallest amount that can be

application of ECC to the flash write operation, see Section 21.3.2.

1. To avoid write disturbance (a mechanism intrinsic to flash memories), an erase should

the erase operation then erases the entire sector. pages have been erased previously). Table 222. UART ISP Read Memory command Number of Bytes: Number of bytes to be read. Count should be a multiple of 4. blocked when code read protection is enabled. Example "R 268435456 4<CR><LF>" reads 4 byt es of data from address 0x1000 0000. Table 223. UART ISP Prepare sector( s) for write operation command End Sector Number: Should be greater than or equal to start sector number. same "Start" and "End" sector numbers. Example "P 0 0<CR><LF>" prepares the flash sector 0.

21.4.1.8 Go <address> <mode>

Table 224. UART ISP Copy RAM to flash command written. The destination address should be a 64 byte boundary. RAM Address (SRC): Source RAM address from where data bytes are to be read. automatically protected again once the copy command is successfully executed. code read protection is enabled. 0x1000 0800 to the flash address 0. Table 225. UART ISP Go command Input Address: Flash or RAM address from which the code execution is to be started. This address should be on a word boundary. Mode: T (Execute program in Thumb Mode). enabled. The command must be used with an address of 0x0000 0200 or greater. Example "G 512 T<CR><LF>" branches to address 0x0000 0200 in Thumb mode.

21.4.1.9 Erase sector(s) <start sector number> <end sector number>

21.4.1.10 Blank check sector(s) <sector number> <end sector number>

21.4.1.11 Read Part Identification number

Table 226. UART ISP Erase sector command End Sector Number: Should be greater than or equal to start sector number. erasure of all user sectors when the code read protection is enabled. Example "E 2 3<CR><LF>" erases the flash sectors 2 and 3. Table 227. UART ISP Blank check sector command End Sector Number: Should be greater than or equal to start sector number. Description This command is used to blank check one or more sectors of on-chip flash memory. Example "I 2 3<CR><LF>" blank c hecks the flash sectors 2 and 3. Table 228. UART ISP Read Pa rt Identification command Return Code CMD_SUCC ESS followed by part identification number in ASCII (see Table 229). Description This command is used to read the part identification number.

21.4.1.12 Read Boot code version number

21.4.1.13 Compare <address1> <address2> <no of bytes>

21.4.1.14 ReadUID

Table 229. Part identification numbers Table 230. UART ISP Read Boot Code version number command Return Code CMD_SUCCESS fo llowed by 2 bytes of boot code version number in ASCII format. It is to be interpreted as <byte1(Major)>.<byte0(Minor)>. Description This command is used to read the boot code version number. Table 231. UART ISP Compare command Input Address1 (DST): Starting flash or RAM address of data bytes to be compared. This address should be a word boundary. Address2 (SRC): Starting flash or RAM address of data bytes to be compared. This address should be a word boundary. Number of Bytes: Number of bytes to be compared; should be a multiple of 4. Description This command is used to compare the memory contents at two locations. 0x1000 8000 to the 4 bytes from the flash address 0x2000. Table 232. UART ISP ReadUID command format. The word sent at the lowest address is sent first. Description This command is used to read the unique ID.

21.4.1.15 UART ISP Return Codes

21.4.2 IAP commands

maximum number of parameters is 5, passed to the "Copy RAM to FLASH" command. Table 233. UART ISP Return Codes Summary been completely and successfully executed. 1 INVALID_COMMAND Invalid command. 2 SRC_ADDR_ERROR Source address is not on word boundary. 3 DST_ADDR_ERROR Destination addres s is not on a correct boundary. 4 SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map.

5 DST_ADDR_NOT_MAPPED Destination addres s is not mapped in the memory

6 COUNT_ERROR Byte count is not multiple of 4 or is not a permitted

7 INVALID_SECTOR Sector number is invalid or end sector number is

greater than start sector number. 8 SECTOR_NOT_BLANK Sector is not blank.

9 SECTOR_NOT_PREPARED_FOR_

10 COMPARE_ERROR Source and destination data not equal. 11 BUSY Flash programming hardware interface is busy.

12 PARAM_ERROR Insufficient number of parameters or invalid

13 ADDR_ERROR Address is not on word boundary. value is taken in to consideration where applicable. 15 CMD_LOCKED Command is locked. 16 INVALID_CODE Unlock code is invalid. 17 INVALID_BAUD_RATE Invalid baud rate setting. 18 INVALID_STOP_BIT Invalid stop bit setting.

19 CODE_READ_PROTECTION_

Code read protection enabled.

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0002 A-05) up to 4 parameters can be passed in the r0, r1, r2 and r3 registers

respectively. Additional parameters are passed on the stack. Up to 4 parameters can be returned in the r0, r1, r2 and r3 registers respectively. Additional parameters are returned indirectly via memory. Some of the IAP calls require more than 4 parameters. If the ARM suggested scheme is used for the parameter passing/returning then it might create problems due to difference in the C compiler implementation from different vendors. The suggested parameter passing scheme reduces such risk. The flash memory is not accessible during a write or erase operation. IAP commands, which results in a flash write/erase operation, use 32 bytes of space in the top portion of the on-chip RAM for execution. The user program should not be use this space if IAP flash programming is permitted in the application.

21.4.2.1 Prepare sector(s) for write operation (IAP)

This command makes flash write/erase operation a two step process. Table 234. IAP Command Summary Table 235. IAP Prepare sector(s) for write operation command

21.4.2.2 Copy RAM to flash (IAP)

See Section 21.4.1.4 for limitations on the write-to-flash process. same "Start" and "End" sector numbers. Table 236. IAP Copy RAM to flash command address should be a 64 byte boundary. address should be a word boundary. Param2: Number of bytes to be written. Should be 64 | 128 | 256 | 512 | 1024. Param3: System Clock Frequency (CCLK) in kHz. successfully executed. The boot sector can not be written by this command.

21.4.2.3 Erase Sector(s) (IAP)

21.4.2.4 Blank check sector(s) (IAP)

21.4.2.5 Read Part Identification number (IAP)

Table 237. IAP Erase Sector(s) command Param2: System Clock Frequency (CCLK) in kHz. sector use the same "Start" and "End" sector numbers. Table 238. IAP Blank check sector(s) command Result1: Contents of non blank word location. Table 239. IAP Read Part Identification command Result Result0: Part Identification Number. Description This command is used to read the part identification number.

21.4.2.6 Read Boot code version number (IAP)

21.4.2.7 Compare <address1> <address2> <no of bytes> (IAP)

Table 240. IAP Read Boot Code version number command Description This command is used to read the boot code version number. Table 241. IAP Compare command address should be a word boundary. address should be a word boundary. Param2: Number of bytes to be compared; should be a multiple of 4. Result Result0: Offset of the first mismatch if the Status Code is COMPARE_ERROR. Description This command is used to compare the memory contents at two locations.

21.4.2.8 Reinvoke ISP (IAP)

21.4.2.9 ReadUID (IAP)

21.4.2.10 Erase page

21.4.2.11 IAP Status Codes

Table 242. IAP Reinvoke ISP internal flash memory and the PIO0_1 pin is not accessible to force the ISP mode. Table 243. IAP ReadUID command Result Result0: The first 32-bit word (at the lowest address). Result1: The second 32-bit word. Result2: The third 32-bit word. Result3: The fourth 32-bit word. Description This command is used to read the unique ID. Table 244. IAP Erase page command Param2: System Clock Frequency (CCLK) in kHz. Description This command is used to erase a page or multiple pages of on-chip flash memory. To erase a single page use the same "start" and "end" page numbers. Table 245. IAP Status Codes Summary 0 CMD_SUCCESS Command is executed successfully. 1 INVALID_COMMAND Invalid command. 2 SRC_ADDR_ERROR Source address is not on a word boundary. 3 DST_ADDR_ERROR Destination address is not on a correct boundary.

21.5 Functional description

21.5.1 UART Commun ication protocol

terminated ASCII strings. Data is sent and received in plain binary format.

21.5.1.1 UART ISP command format

21.5.1.2 UART ISP response format

Response_n<CR><LF>" "Data" (Data only for Read commands).

21.5.1.3 UART ISP data format

The data stream is in plain binary format.

21.5.2 Memory and interr upt use for ISP and IAP

21.5.2.1 Interrupts during UART ISP

4 SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map.

5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory

7 INVALID_SECTOR Sector number is invalid. 8 SECTOR_NOT_BLANK Sector is not blank.

9 SECTOR_NOT_PREPARED_

10 COMPARE_ERROR Source and destination data is not same. 11 BUSY Flash programming hardware interface is busy.

21.5.2.2 Interrupts during IAP

application code starts executing the interrupt vectors from the user flash area are active. does not use or disable interrupts.

21.5.2.3 RAM used by ISP command handler

540 byte and grows downwards.

21.5.2.4 RAM used by IAP command handler

21.5.3 Debugging

21.5.3.1 Comparing flash images

internal SRAM, or the flash memory respectively.

21.5.3.2 Serial Wire Debug (SWD) flash programming interface

"Copy RAM to flash" repeatedly with proper offset. Table 246. Memory mapping in debug mode

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22.1 How to read this chapter

The power profiles are available for all LPC800 parts.

22.2 Features

• Includes ROM-based application services
• Power Management services
• Clocking services

22.3 General description

The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile. The power configuration routine configures the LPC800 for one of the following power modes:

• Default mode corresponding to power configuration after reset.
• CPU performance mode corresponding to optimized processing capability.
• Efficiency mode corresponding to optimized balance of current consumption and CPU performance.
• Low-current mode corresponding to lowest power consumption. In addition, the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock. Remark: Disable all interrupts before making calls to the power profile API. You can re-enable the interrupts after the power profile API calls have completed. The API calls to the ROM are performed by executing functions which are pointed by a pointer within the ROM Driver Table. Figure 37 shows the pointer structure used to call the Power Profiles API. UM10601 Chapter 22: LPC800 Power profile API ROM driver Rev. 1.0 — 7 November 2012 Preliminary user manual

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22.4 API description

The power profile API provides functions to configure the system clock and optimize the system setting for lowest power consumption. Fig 37. Power profiles pointer structure /g3 /g51/g87/g85/g3/g87/g82/g3/g53/g50/g48/g3/g39/g85/g76/g89/g72/g85/g3/g87/g68/g69/g79/g72/g3 /g3 /g51/g87/g85/g3/g87/g82/g3/g39/g72/g89/g76/g70/g72/g3/g55/g68/g69/g79/g72/g3/g21/g3 /g3 /g3 /g51/g87/g85/g3/g87/g82/g3/g39/g72/g89/g76/g70/g72/g3/g55/g68/g69/g79/g72/g3/g20 /g3 /g51/g87/g85/g3/g87/g82/g3/g39/g72/g89/g76/g70/g72/g3/g55/g68/g69/g79/g72/g3/g19 /g171/g3 /g51/g87/g85/g3/g87/g82/g3/g39/g72/g89/g76/g70/g72/g3 /g55/g68/g69/g79/g72/g3/g81 /g3 /g86/g72/g87/g66/g83/g79/g79 /g3 /g86/g72/g87/g66/g83/g82/g90/g72/g85/g3 /g3/g51/g82/g90/g72/g85/g3/g36/g51/g44/g3/g73/g88/g81/g70/g87/g76/g82/g81/g3/g87/g68/g69/g79/g72 /g3 /g53/g50/g48/g3/g39/g85/g76/g89/g72/g85/g3/g55/g68/g69/g79/g72 /g3 /g19/g91/g20/g41/g41/g41/g3/g20/g41/g41/g27 /g14/g19/g91/g19/g19 /g14/g19/g91/g19/g23 /g14/g19/g91/g19/g27 /g14/g19/g91/g19/g38 /g51/g87/g85/g3/g87/g82/g3/g51/g82/g90/g72/g85/g36/g51/g44/g3/g55/g68/g69/g79/g72 Fig 38. LPC800 clock configuration for power API use /g54/g60/g54/g3/g51/g47/g47 /g76/g85/g70/g66/g82/g86/g70/g66/g70/g79/g78 /g86/g92/g86/g66/g82/g86/g70/g66/g70/g79/g78 /g38/g47/g46/g44/g49 /g76/g85/g70/g66/g82/g86/g70/g66/g70/g79/g78 /g90/g71/g87/g66/g82/g86/g70/g66/g70/g79/g78 /g48/g36/g44/g49/g38/g47/g46/g54/g40/g47 /g54/g60/g54/g51/g47/g47/g38/g47/g46/g54/g40/g47 /g38/g47/g50/g38/g46 /g39/g44/g57/g44/g39/g40/g53 /g54/g60/g54/g36/g43/g37/g38/g47/g46/g38/g55/g53/g47/g62/g20/g64 /g11/g53/g50/g48/g3/g72/g81/g68/g69/g79/g72/g12/g54/g60/g54/g36/g43/g37/g38/g47/g46/g38/g55/g53/g47/g62/g81/g64 /g11/g81/g3/g72/g81/g68/g69/g79/g72/g12 /g38/g47/g50/g38/g46 /g39/g44/g57/g44/g39/g40/g53/g51/g72/g85/g76/g83/g75/g72/g85/g68/g79/g86 /g80/g68/g76/g81/g3/g70/g79/g82/g70/g78 /g86/g92/g86/g87/g72/g80/g3/g70/g79/g82/g70/g78 /g86/g92/g86/g66/g83/g79/g79/g70/g79/g78/g76/g81 /g86/g92/g86/g66/g83/g79/g79/g70/g79/g78/g82/g88/g87 /g80 /g36/g53/g48 /g38/g50/g53/g55/g40/g59/g16/g48/g19 /g53/g50/g48 /g81 /g54/g60/g54/g36/g43/g37/g38/g47/g46/g39/g44/g57

to lower system power consumption. PLL (Table 8) and the system/AHB clock divider must be set to 1 (Table 15). PLL clock out (if necessary). (PLL_CMD_SUCCESS) or not (in which case the result code identifies what went wrong). Table 247. Power profile API calls Table 248. set_pll routine

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 262 of 313 NXP Semiconductors UM10601 Chapter 22: LPC800 Power profile API ROM driver #define CPU_FREQ_EQU 0 #define CPU_FREQ_LTE 1 #define CPU_FREQ_GTE 2 #define CPU_FREQ_APPROX 3 /* set_pll result0 options */ #define PLL_CMD_SUCCESS 0 #define PLL_IN VAL I D _F RE Q 1 #define PLL_INV ALID_MODE 2 #define PLL_FREQ_NOT_FOUND 3 #define PLL_NOT_LOCKED 4 For a simplified clock configuration scheme see Figure 38. For more details see Figure 3.

22.4.1.1 Param0: system PLL input frequency and Param1: expected system clock

set_pll looks for a setup in which the system PLL clock does not exceed 50 MHz. It easily finds a solution when the ratio between the expected system clock and the system PLL input frequency is an integer value, but it can also find solutions in other cases. The system PLL input frequency (Param0) must be between 10000 to 25000 kHz (10 MHz to 25 MHz) inclusive. The expected system clock (Param1) must be between 1 and 50000 kHz inclusive. If either of these requirements is not met, set_pll returns PLL_INVALID_FREQ and returns Param0 as Result1 since the PLL setting is unchanged.

22.4.1.2 Param2: mode

The first priority of set_pll is to find a setup that generates the system clock at exactly the rate specified in Param1. If it is unlikely that an exact match can be found, input parameter mode (Param2) should be used to specify if the actual system clock can be less than or equal, greater than or equal or approximately the value specified as the expected system clock (Param1). A call specifying CPU_FREQ_EQU will only succeed if the PLL can output exactly the frequency requested in Param1. CPU_FREQ_LTE can be used if the requested frequency should not be exceeded (such as overall current consumption and/or power budget reasons). CPU_FREQ_GTE helps applications that need a minimum level of CPU processing capabilities. CPU_FREQ_APPROX results in a system clock that is as close as possible to the requested value (it may be greater than or less than the requested value). If an illegal mode is specified, set_pll returns PLL_INVALID_MODE. If the expected system clock is out of the range supported by this routine, set_pll returns PLL_FREQ_NOT_FOUND. In these cases the current PLL setting is not changed and Param0 is returned as Result1.

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22.4.1.3 Param3: system PLL lock time-out

It should take no more than 100 s for the system PLL to lock if a valid configuration is selected. If Param3 is zero, set_pll will wait indefinitely for the PLL to lock. A non-zero value indicates how many times the code will check for a successful PLL lock event before it returns PLL_NOT_LOCKED. In this case the PLL settings are unchanged and Param0 is returned as Result1. Remark: The time it takes the PLL to lock depends on the selected PLL input clock source (IRC/system oscillator) and its characteristics. The selected source can experience more or less jitter depending on the operating conditions such as power supply and/or ambient temperature. This is why it is suggested that when a good known clock source is used and a PLL_NOT_LOCKED response is received, the set_pll routine should be invoked several times before declaring the selected PLL clock source invalid. Hint: setting Param3 equal to the system PLL frequency [Hz] divided by 10000 will provide more than enough PLL lock-polling cycles. 22.4.2 set_power This routine configures the device’s internal power control settings according to the calling arguments. The goal is to reduce active power consumption while maintaining the feature of interest to the application close to its optimum. Remark: The set_power routine was designed for systems employing the configuration of SYSAHBCLKDIV = 1 (System clock divider register, see Table 17 and Figure 38). Using this routine in an application with the system clock divider not equal to 1 might not improve microcontroller’s performance as much as in setups when the main clock and the system clock are running at the same rate. set_power returns a result code that reports whether the power setting was successfully changed or not.

Table 249. set_power routine

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22.4.2.1 Param0: main clock

The main clock is the clock rate the microcontroller uses to source the system’s and the peripherals’ clock. It is configured by either a successful execution of the clocking routine call or a similar code provided by the user. This operand must be an integer between 1 to 50 MHz inclusive. If a value out of this range is supplied, set_power returns PWR_INVALID_FREQ and does not change the power control system.

22.4.2.2 Param1: mode

The input parameter mode (Param1) specifies one of four available power settings. If an illegal selection is provided, set_power returns PWR_INVALID_MODE and does not change the power control system. PWR_DEFAULT keeps the device in a baseline power setting similar to its reset state. PWR_CPU_PERFORMANCE configures the microcontroller so that it can provide more processing capability to the application. CPU performance is 30% better than the default option. PWR_EFFICIENCY setting was designed to find a balance between active current and the CPU’s ability to execute code and process data. In this mode the device outperforms the default mode both in terms of providing higher CPU performance and lowering active current. PWR_LOW_CURRENT is intended for those solutions that focus on lowering power consumption rather than CPU performance.

22.4.2.3 Param2: system clock

The system clock is the clock rate at which the microcontroller core is running when set_power is called. This parameter is an integer between from 1 and 50 MHz inclusive.

22.5 Functional description

22.5.1 Clock control

22.5.1.1 Invalid frequency (device maximum clock rate exceeded)

command[0] = 12000; command[1] = 60000; command[2] = CPU_FREQ_EQU; command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock and a system clock of exactly 60 MHz. The application was ready to infinitely wait for the PLL to lock. But the expected system clock of 60 MHz exceeds the maximum of 50 MHz. Therefore set_pll returns PLL_INVALID_FREQ in result[0] and 12000 in result[1] without changing the PLL settings.

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22.5.1.2 Invalid frequency selection (system clock divider restrictions)

command[0] = 12000; command[1] = 40; command[2] = CPU_FREQ_LTE; command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock, a system clock of no more than 40 kHz and no time-out while waiting for the PLL to lock. Since the maximum divider value for the system clock is 255 and running at 40 kHz would need a divide by value of 300, set_pll returns PLL_INVALID_FREQ in result[0] and 12000 in result[1] without changing the PLL settings.

22.5.1.3 Exact solution cannot be found (PLL)

command[0] = 12000; command[1] = 25000; command[2] = CPU_FREQ_EQU; command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock and a system clock of exactly 25 MHz. The application was ready to infinitely wait for the PLL to lock. Since there is no valid PLL setup within earlier mentioned restrictions, set_pll returns PLL_FREQ_NOT_FOUND in result[0] and 12000 in result[1] without changing the PLL settings.

22.5.1.4 System clock less than or equal to the expected value

command[0] = 12000; command[1] = 25000; command[2] = CPU_FREQ_LTE; command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock, a system clock of no more than 25 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and 24000 in result[1]. The new system clock is 24 MHz.

22.5.1.5 System clock greater than or equal to the expected value

command[0] = 12000; command[1] = 25000; command[2] = CPU_FREQ_GTE; command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock, a system clock of at least 25 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and 36000 in result[1]. The new system clock is 36 MHz.

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22.5.1.6 System clock approximately equal to the expected value

command[0] = 12000; command[1] = 16500; command[2] = CPU_FREQ_APPROX; command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock, a system clock of approximately 16.5 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and 16000 in result[1]. The new system clock is 16 MHz.

22.5.2 Power control

22.5.2.1 Invalid frequency (device maximum clock rate exceeded)

command[0] = 30; command[1] = PWR_CPU_PERFORMANCE; command[2] = 40; (*rom)->pWRD->set_powe r(command, result); The above setup would be used in a system running at the main and system clock of 30 MHz, with a need for maximum CPU processing power. Since the specified 40 MHz clock is above the 30 MHz maximum, set_power returns PWR_INVALID_FREQ in result[0] without changing anything in the existing power setup.

22.5.2.2 An applicable power setup

command[0] = 24; command[1] = PWR_CPU_EFFICIENCY; command[2] = 24; (*rom)->pWRD->set_powe r(command, result); The above code specifies that an application is running at the main and system clock of 24 MHz with emphasis on efficiency. set_power returns PWR_CMD_SUCCESS in result[0] after configuring the microcontroller’s internal power control features.

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23.1 How to read this chapter

The I2C-bus ROM API is available on all LPC800 parts.

23.2 Features

• Simple I2C drivers to send and receive data on the I2C-bus.
• Polled and interrupt-driven receive and transmit functions for master and slave modes.

23.3 General description

The drivers are callable for use by any application program to send or receive data on the I2C bus. With the I2C drivers it is easy to produce working projects using the I2C interface. The ROM routines allow the user to operate the I2C interface as a Master or a Slave. The software routines do not implement arbitration to make a Master switch to a Slave mode in the midst of a transmission. Although multi-master arbitration is not implemented in these I2C drivers, it is possible to use them in a system design with more than one master. If the flag returned from the driver indicates that the message was not successful due to loss of arbitration, the application just resends the message. UM10601 Chapter 23: LPC800 I2C-bus ROM API Rev. 1.0 — 7 November 2012 Preliminary user manual

23.4 API description

Table 250. I2C API calls

23.4.1 ISR handler

23.4.2 I2C Master Transmit Polling

23.4.3 I2C Master Receive Polling

Table 251. ISR handler Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. the I2C ISR when using I2C Rom Driver interrupt mode. Table 252. I2C Master Transmit Polling Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. Table 253. I2C Master Receive Polling Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. completed, the function returns to the line after the call.

23.4.4 I2C Master Transm it and Receive Polling

23.4.5 I2C Master Transmit Interrupt

23.4.6 I2C Master Receive Interrupt

Table 254. I2C Master Transmit and Receive Polling Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. the slave address with the R/W bit =1 is in the first byte of the receive buffer. completed, the function returns to the line after the call. Table 255. I2C Master Transmit Interrupt Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. the callback function is called. Table 256. I2C Master Receive Interrupt Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. basis. When task is completed, the callback function is called.

23.4.7 I2C Master Transmit Receive Interrupt

23.4.8 I2C Slave Receive Polling

23.4.9 I2C Slave Transmit Polling

Table 257. I2C Master Transmit Receive Interrupt Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. basis. When task is completed, the callback function is called. Table 258. I2C Slave Receive Polling Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. Table 259. I2C Slave Transmit Polling Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. returns to the line after the call.

23.4.10 I2C Slave Receive Interrupt

23.4.11 I2C Slave Transmit Interrupt

23.4.12 I2C Set Slave Address

23.4.13 I2C Get Memory Size

Table 260. I2C Slave Receive Interrupt Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. the callback function is called. Table 261. I2C Slave Transmit Interrupt Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. the callback function is called. Table 262. I2C Set Slave Address Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. Slave_addr_0_3 - unint32 variable. 7-bit slave address . Slave_mask_0_3 - unint32 variable. Slave address mask. supports four 7-bit slave addresses and masks. Table 263. I2C Get Memory Size

23.4.14 I2C Setup

23.4.15 I2C Set Bit Rate

23.4.16 I2C Get Firmware Version

23.4.17 I2C Get Status

Description Returns the number of bytes in SRAM needed by the I2C driver. Table 264. I2C Setup Input parameter I2C_base addr - unint32 variable. Base address for I2C peripherals. Start_of_ram - unint32 pointer. Pointer to allocated SRAM. Description Returns a handle to the allocated SRAM area. Table 265. I2C Set Bit Rate Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. P_clk_in_hz - unint32 variable. The Peripheral Clock in Hz. Bitrate_in_bps - unint32 variable. Requested I2C operating frequency in Hz. Description Configures the I2C duty-cycle registers (SCLH and SCLL). Table 266. I2C Get Firmware Version Return I2C ROM Driver version number. Table 267. I2C Get Status Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. Description Returns status code. The stat us code indicates the state of the I2C bus. Refer to I2C Status Code Table.

23.4.18 I2C time-out value

23.4.19 Error codes

23.4.20 I2C Status code

23.4.21 I2C ROM driver variables

usage. Depending on the operating mode, some variables can be omitted.

23.4.21.1 I2C Handle

Table 268. I2C time-out value Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. timeout feature is disabled. Description Returns status code. The stat us code indicates the state of the I2C bus. Refer to I2C Status Code Table. Table 269. Error codes 0 Successful completion Functi on was completed successfully.

1 General error -

0x0006 0007 ERR_I2C_GENERAL_FAILURE Failure detected on I2C bus. of 0x04 is loaded into SCLH and SCLL. Table 270. I2C Status code

1 MASTER_SEND

2 MASTER_RECEIVE

3 SLAVE_SEND

4 SLAVE_RECEIVE

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 277 of 313 NXP Semiconductors UM10601 Chapter 23: LPC800 I2C-bus ROM API After the definition of the handle, the handle must be initialized with I2C base address and RAM reserved for the I2C ROM driver by making a call to the i2c_setup() function. The callback function type must be defined if interrupts for the I2C ROM driver are used: typedef void (*I2C_CALLBK_T) (uint32_t err_code, uint32_t n) The callback function will be called by the I2C ROM driver upon completion of a task when interrupts are used.

23.4.22 PARAM and RESULT structure

The I2C ROM driver input parameters consist of two structures, a PARAM structure and a RESULT structure. The PARAM structure contains the parameters passed to the I2C ROM driver and the RESULT structure contains the results after the I2C ROM driver is called. The PARAM structure is as follows: typedef struct i2c_A { //parameters passed to ROM function uint32_t num_bytes_send ; uint32_t num_bytes_rec ; uint8_t *buffer_ptr_send ; uint8_t *buffer_ptr_rec ; I2C_CALLBK_T func_pt; // callback function pointer uint8_t stop_flag; uint8_t dummy[3] ; // required for word alignment } I2C_PARAM ; The RESULT structure is as follows: typedef struct i2c_R { // RESULTs struct--results are here when returned uint32_t n_bytes_sent ; uint32_t n_bytes_recd ; } I2C_RESULT ;

23.4.23 Error structure

The error code returned by the I2C ROM driver is an enum structure. The Error structure is as follows: typedef enum LPC_OK=0, /**< enum value returned on Success */ ERROR, ERR_I2C_BASE = 0x00060000, /*0x00060001*/ ERR_I2C_NAK=ERR_I2C_BASE+1, /*0x00060002*/ ERR_I2C_BUFFER_OVERFLOW, /*0x00060003*/ ERR_I2C_BYTE_COUNT_ERR, /*0x00060004*/ ERR_I2C_LOSS_OF_ARBRITRATION, /*0x00060005*/ ERR_I2C_SLAVE_NOT_ADDRESSED, /*0x00060006*/ ERR_I2C_LOSS_OF_ARBRITRATION_NAK_BIT, /*0x00060007*/ ERR_I2C_GENERAL_FAILURE, /*0x00060008*/ ERR_I2C_REGS_SET_TO_DEFAULT

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 278 of 313 NXP Semiconductors UM10601 Chapter 23: LPC800 I2C-bus ROM API } ErrorCode_t;

23.4.24 I2C Mode

The i2c_get_status() function returns the current status of the I2C engine. The return codes can be defined as an enum structure: typedef enum I2C_mode { IDLE, MASTER_SEND, MASTER_RECEIVE, SLAVE_SEND, SLAVE_RECEIVE } I2C_MODE_T ;

23.4.25 I2C ROM driver pointer

The I2C ROM driver resides in the address 0x1FFF1FF8. The address must be declared to allow access to the ROM driver: #define ROM_DRIVERS_PTR ((ROM *)(*((unsigned int *)0x1FFF1FF8)))

23.5 Functional description

23.5.1 I2C Set-up

Before calling any setup functions in the I2C ROM, the application program is responsible for doing the following: 1. Enable the clock to the I2C peripheral. 2. Enable the two pins required for the SCL and SDA outputs of the I2C peripheral. 3. Allocate a RAM area for dedicated use of the I2C ROM Driver. After the I2C block is configured, the I2C ROM driver variables have to be set up: 1. Initialize pointer to th e I2C API function table. 2. Declare the PARAM and RESULT struct. 3. Declare Error Code struct. 4. Declare the transmit and receive buffer. If interrupts are used, then additional driver variables have to be set up: 1. Declare the I2C_CALLBK_ T type. 2. Declare callback functions. 3. Declare I2C ROM Driver ISR within the I2C ISR. 4. Enable I2 C interrupt.

23.5.2 I2C Master mode set-up

The I2C ROM Driver support polling and interrupts. In the master mode, 7-bit and 10-bit addressing are supported. The setup is as follows:

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 279 of 313 NXP Semiconductors UM10601 Chapter 23: LPC800 I2C-bus ROM API 1. Allocate SRAM for the I2C ROM Driver by making a call to the i2c_get_mem_size() function. 2. Create the I2C handle by making a call to the i2c_setup() function. 3. Set the I2C operating frequency by making a call to the i2c_set_bitrate() function. pI2cApi = ROM_DRIVERS_PTR->pI2CD; //setup I2C function table pointer size_in_bytes = pI2cApi->i2c_get_mem_size(); i2c_handle = pI2cApi->i2c_setup(LPC_I2C_BASE, (uint32_t *)&I2C_Handle[0] ); error_code = pI2cApi->i2c_set_bitrate((I2C_HANDLE_T*)i2c_handle, PCLK_in_Hz, bps_in_hz);

23.5.3 I2C Slave mode set-up

The I2C ROM Driver support polling and interrupts in the slave mode. In the slave mode, only 7-bit addressing is supported. The set-up is as follows: 1. Allocate SRAM for the I2C ROM Driver by making a call to the i2c_get_mem_size() function. 2. Create the I2C handle by making a call to the i2c_setup() function. 3. Set the I2C operating frequency by making a call to the i2c_set_bitrate() function. 4. Set the slave address by making a ca ll to the i2c_set_slave_addr() function. The I2C ROM driver allows setting up to 4 slave addresses and 4 address masks as well as possibly enabling the General Call address. The four slave address bytes are packed into the 4 byte variable. Slave address byte 0 is the least significant byte and Slave address byte 3 is the most significant byte. The Slave address mask bytes are ordered the same way in the other 32 bit variable. When in slave receive mode, all of these addresses (or groups if masks are used) will be monitored for a match. If the General Call bit (least significant bit of any of the four slave address bytes) is set, then the General Call address of 0x00 is monitored as well. pI2cApi = ROM_DRIVERS_PTR->pI2CD; //setup I2C function table pointer size_in_bytes = pI2cApi->i2c_get_mem_size(); i2c_handle = pI2cApi->i2c_setup(LPC_I2C_BASE, (uint32_t *)&I2C_Handle[0] ); error_code = pI2cApi->i2c_set_bitrate((I2C_HANDLE_T*)i2c_handle, PCLK_in_Hz, bps_in_hz); error_code = pI2cApi->i2c_set_slave_addr((I2C_HANDLE_T*)i2c_handle, slave_addr, slave_addr_mask) ; Fig 41. I2C slave mode set-up address packing /g1007/g1005/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g1006/g1009/g3 /g3/g3/g3/g1006/g1008 /g3/g3/g3/g3/g1006/g1007/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g1005/g1011 /g3/g3/g3/g3/g1005/g1010/g3/g3/g3/g3 /g1005/g1009/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3 /g3/g3/g3/g3/g3/g3/g3/g1013/g3 /g3/g3/g3/g3/g1012/g3/g1011/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3/g3 /g1005/g3 /g3/g3/g3 /g3 /g1004/g3 /g94/g367/g258/g448/g286/g3/g4/g282/g282/g396/g286/g400/g400/g3/g1007/g3 /g39/g18/g3 /g94/g367/g258/g448/g286/g3/g4/g282/g282/g396/g286/g400/g400/g3/g1006/g3 /g39/g18/g3 /g94/g367/g258/g448/g286/g3/g4/g282/g282/g396/g286/g400/g400/g3/g1005/g3 /g39/g18/g3 /g94/g367/g258/g448/g286/g3/g4/g282/g282/g396/g286/g400/g400/g3/g1004/g3 /g39/g18/g3 /g3

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23.5.4 I2C Master Transmit/Receive

The Master mode drivers give the user the choice of either polled (wait for the message to finish) or interrupt driven routines (non-blocking). Polled routines are recommended for testing purposes or very simple I2C applications. These routines allow the Master to send to Slaves with 7-bit or 10-bit addresses. The following routines are polled routines : err_code i2c_master_transmit_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) err_code i2c_master_receive_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) err_code i2c_master_tx_rx_poll (I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) The following routines are interrupt driven routines: err_code i2c_master_transmit_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) err_code i2c_master_receive_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) err_code i2c_master_tx_rx_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) Where:

• err_code is the return state of the function. An “0” indicates success. All non-zero indicates an error. Refer to Error Table.
• I2C_PARM* is a structure with parameters passed to the function. Refer to Section 23.4.22.
• I2C_RESULT* is a containing the results after the function executes. To initiate a master mode write/read the I2C_PARAM has to be setup. The I2C_PARAM is a structure with various variables needed by the I2C ROM Driver to operate correctly. The structure contains the following:
• Number of bytes to be transmitted.
• Number of bytes to be receive.
• Pointer to the transmit buffer.
• Pointer to the receive buffer.
• Pointer to callback function.
• Stop flag. The RESULT structure contains the results after the function executes. The structure contains the following:
• Number of bytes transmitted.
• Number of bytes received. Remark: The number of bytes transmitted will be updated for i2c_master_transmit_intr() and i2c_master_transmit_poll(). The number of bytes received will only be update on i2c_master_receive_poll(), i2c_master_receive_intr(), i2c_master_tx_rx_poll(), and i2c_master_tx_rx_intr().

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 281 of 313 NXP Semiconductors UM10601 Chapter 23: LPC800 I2C-bus ROM API In all the master mode routines, the transmit buffer’s first byte must be the slave address with the R/W bit set to “0”. To enable a master read, the receive buffer’s first byte must be the slave address with the R/W bit set to “1”. The following conditions must be fulfilled to use the I2C driver routines in master mode:

• For 7-bit addressing, the first byte of the send buffer must have the slave address in the most significant 7 bits and the least significant (R/W) bit = 0. Example: Slave address 0x53, first byte is 0xA6.
• For 7-bit addressing, the first byte of the receive buffer must have the slave address in the most significant 7 bits and the least significant (R/W) bit = 1. Example: Slave Addr 0x53, first byte 0xA7.
• For 10-bit address, the first byte of the transmit buffer must have the slave address most significant 2 bits with the (R/W) bit =0. The second byte must contain the remaining 8-bit of the slave address.
• For 10-bit address, the first byte of the receive buffer must have the slave address most significant 2 bits with the (R/W) bit =1. The second byte must contain the remaining 8-bit of the slave address.
• The number of bytes to be transmitted should include the first byte of the buffer which is the slave address byte. Example: 2 data bytes + 7-bit slave addr = 3.
• The application program must enable I2C interrupts. When I2C interrupt occurs, the i2c_isr_handler function must be called from the application program. When using the interrupt function calls, the callback functions must be define. Upon the completion of a read/write as specified by the PARAM structure, the callback functions will be invoked.

23.5.5 I2C Slave Mode Transmit/Receive

In slave mode, polled routines are intended for testing purposes. It is up to the user to decide whether to use the polled or interrupt driven mode. While operating the Slave driver in polled mode can be useful for program development and debugging, most applications will need the interrupt-driven versions of Slave Receive and Transmit in the final software. The following routines are polled routines: err_code i2c_slave_receive_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) err_code i2c_slave_transmit_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) The following routines are interrupt driven routines: err_code i2c_slave_receive_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) err_code i2c_slave_transmit_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) Where:

• err_code is the return state of the function. An 0 indicates success. All non-zero indicates an error. Refer to the Error Code Table.
• I2C_PARM is a structure with parameters passed to the function. Section 23.4.22.

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• I2C_RESULT is a containing the results after the function executes. Section 23.4.22. To initiate a master-mode write/read the I2C_PARAM has to be setup. The I2C_PARAM is a structure with various variables needed by the I2C ROM Driver to operate correctly. The structure contains the following:
• Number of bytes to be transmitted.
• Number of bytes to be received.
• Pointer to the transmit buffer.
• Pointer to the receive buffer.
• Pointer to callback function.
• Stop flag. The RESULT structure contains the results after the function executes. The structure contains the following:
• Number of bytes transmitted.
• Number of bytes received. Remark: The number of bytes transmitted is updated only for i2c_slave_send_poll() and i2c_slave_send_intr(). The number of bytes received is updated only for i2c_slave_receive_poll() and i2c_slave_receive_intr(). To initiate a slave mode communication, the receive function is called. This can be either the polling or interrupt driven function, i2c_slave_receive_poll() or i2c_slave_receive_intr(), respectively. The receive buffer should be as large or larger than any data or command that will be received. If the amount of data exceed the receive buffer size, an error code will be returned. In slave-receive mode, the driver receives data until one of the following are true:
• Address matching set in the set_slave_addr() function with the R/W bit set to 1
• STOP or repeated START is received
• An error condition is detected When using the interrupt function calls, the callback functions must be define. Upon the completion of a read/write as specified by the PARAM structure, the callback functions will be invoked.

23.5.6 I2C time-out feature

//timeout: Timeout time value. Specifies the timeout interval value in increments of // 16 I2C function clocks (Min value is 16). // if timeout = 0, timeout feature is disabled // if timeout != 0, time value is timeout*16 i2c function clock. ErrorCode_t i2c_set_timeout(I2C_HANDLE_T* h_i2c, uint32_t timeout) I2C_DRIVER_TypeDef *h ; // declare pointer to i2c structure [handle] h = (I2C_DRIVER_TypeDef*) h_i2c ; //assign handle pointer address if (timeout != 0){ h->i2c_base->TimeOut = (timeout - 1)<<4;

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 283 of 313 NXP Semiconductors UM10601 Chapter 23: LPC800 I2C-bus ROM API // Enable timeout feature h->i2c_base->CFG |= BI2C_TIMEOUT_EN; else // disable timeout feature h->i2c_base->CFG &= ~BI2C_TIMEOUT_EN; return(LPC_OK) ; }//i2c_set_timeout

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24.1 How to read this chapter

The USART ROM driver routines are available on all LPC800 parts.

24.2 Features

• Send and receive characters in asynchronus UART mode
• Send and receive multiple characters (line) in asynchronous UART mode

24.3 General description

The UART API handles sending and receiving characters using any of the USART blocks in asynchronous mode. Remark: Because all USARTS share a common fractional divider, the uart_init routine returns the value for the common divider. UM10601 Chapter 24: LPC800 USART API ROM driver routines Rev. 1.0 — 7 November 2012 Preliminary user manual Fig 42. USART driver routines pointer structure /g3 /g51/g87/g85/g3/g87/g82/g3/g53/g50/g48/g3/g39/g85/g76/g89/g72/g85/g3/g87/g68/g69/g79/g72/g3 /g3 /g51/g87/g85/g3/g87/g82/g3/g39/g72/g89/g76/g70/g72/g3/g55/g68/g69/g79/g72/g3/g21/g3 /g3 /g3 /g51/g87/g85/g3/g87/g82/g3/g39/g72/g89/g76/g70/g72/g3/g55/g68/g69/g79/g72/g3/g20 /g3 /g51/g87/g85/g3/g87/g82/g3/g39/g72/g89/g76/g70/g72/g3/g55/g68/g69/g79/g72/g3/g19 /g171/g3 /g51/g87/g85/g3/g87/g82/g3/g39/g72/g89/g76/g70/g72/g3 /g55/g68/g69/g79/g72/g3/g81 /g3 /g3 /g3 /g86/g76/g71/g76/g89/g80/g82/g71 /g88/g76/g71/g76/g89/g80/g82/g71 /g3/g3 /g3 /g3/g56/g36/g53/g55/g3/g71/g85/g76/g89/g72/g85/g3/g85/g82/g88/g87/g76/g81/g72/g86/g3/g73/g88/g81/g70/g87/g76/g82/g81/g3/g87/g68/g69/g79/g72 /g3 /g53/g50/g48/g3/g39/g85/g76/g89/g72/g85/g3/g55/g68/g69/g79/g72 /g3 /g19/g91/g20/g41/g41/g41/g3/g20/g41/g41/g27 /g14/g19/g91/g19/g19 /g14/g19/g91/g19/g23 /g14/g19/g91/g19/g27 /g14/g19/g91/g20/g19 /g14/g19/g91/g20/g23 /g14/g19/g91/g21/g23 /g14/g19/g91/g19/g38 /g51/g87/g85/g3/g87/g82/g3/g39/g72/g89/g76/g70/g72/g3/g55/g68/g69/g79/g72/g3/g22 /g51/g87/g85/g3/g87/g82/g3/g39/g72/g89/g76/g70/g72/g3/g55/g68/g69/g79/g72/g3/g23 /g51/g87/g85/g3/g87/g82/g3/g56/g36/g53/g55/g3/g71/g85/g76/g89/g72/g85/g3/g85/g82/g88/g87/g76/g81/g72/g86 /g3/g88/g68/g85/g87/g66/g74/g72/g87/g66/g80/g72/g80/g66/g86/g76/g93/g72 /g88/g68/g85/g87/g66/g86/g72/g87/g88/g83 /g17/g17/g17 /g3/g88/g68/g85/g87/g66/g76/g86/g85 /g17/g17/g17

24.4 API description

24.4.1 UART get memory size

Table 271. UART API calls Table 272. uart_get_mem_size Return Memory size in bytes. Description Get the memory size needed by one Min UART instance.

24.4.2 UART setup

24.4.3 UART init

24.4.4 UART get character

24.4.5 UART put character

Table 273. uart_setup Input parameter base_addr: Base address of register for this uart block. space can be obtained by the uart_get_mem_size function. Return The handle to corresponding uart instance. Table 274. uart_init Input parameter handle: The handle to the uart instance. set: configuration for uart operation. Return Fractional divider value if System cl ock is not integer multiples of baud rate. Description Setup baud rate and operation mode for uart, then enable uart. Table 275. uart_get_char Input parameter handle: The handle to the uart instance. received. In case Echo is enabled, the received data is sent out immediately. Table 276. uart_put_char Input parameter handle: The handle to the uart instance. Description Send one Char through uart. This function is only returned after data is sent.

24.4.6 UART get line

24.4.7 UART put line

24.4.8 UART interrupt service routine

24.4.9 Error codes

Table 277. uart_get_line Input parameter handle: The handle to the uart instance. param: Refer to UART_PARAM_T definition. ERR_UART_RECEIVE_ON - UART receive is ongoing. Description Receive multiple bytes from UART. Table 278. uart_put_line Input parameter handle: The handle to the uart instance. param: Refer to UART_PARAM_T definition. ERR_UART_SEND_ON - UART sending is ongoing. Description Send string (end with \\0) or raw data through UART. Table 279. uart_isr Input parameter handle: The handle to the uart instance. interrupt must be enabled. This function is invoked by the user ISR. Table 280. Error codes

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24.4.10 UART ROM driver variables

24.4.10.1 UART_CONFIG structure

Typdef struct UART_CONFIG { uint32_t sys_clk_in_hz; // Sytem clock in hz. uint32_t baudrate_in_hz; // Baudrate in hz uint8_t config; //bit1:0 // 00: 7 bits length, 01: 8 bits lenght, others: reserved //bit3:2 // 00: No Parity, 01: reserved, 10: Even, 11: Odd //bit4 // 0: 1 Stop bit, 1: 2 Stop bits uint8_t sync_mod; //bit0: 0(Async mode), 1(Sync mode) //bit1: 0(Un_RXD is sampled on the falling edge of SCLK) // 1(Un_RXD is sampled on the rising edge of SCLK) //bit2: 0(Start and stop bits are transmitted as in asynchronous //mode) // 1(Start and stop bits are not transmitted) //bit3: 0(the UART is a slave on Sync mode) // 1(the UART is a master on Sync mode) uint16_t error_en; //Bit0: OverrunEn, bit1: UnderrunEn, bit2: FrameErrEn, // bit3: ParityErrEn, bit4: RxNoiseEn

24.4.10.2 UART_HANDLE_T

The handle to the instance of the UART driver. Each UART has one handle, so there can be several handles for up to three UART blocks. This handle is created by Init API and used by the transfer functions for the corresponding UART block. typedef void UART_HANDLE_T ; // define TYPE for uart handle pointer

24.4.10.3 UART_PARAM_T

typedef struct uart_A { // parms passed to uart driver function uint8_t * buffer ; // The pointer of buffer. // For uart_get_line function, buffer for receiving data. // For uart_put_line function, buffer for transmitting data. uint32_t size; // [IN] The size of buffer. //[OUT] The number of bytes transmitted/received. uint16_t transfer_mode ; // 0x00: For uart_get_line function, transfer without // termination. // For uart_put_line function, transfer without termination. // 0x01: For uart_get_line function, stop transfer when // <CR><LF> are received. // For uart_put_line function, transfer is stopped after // reaching \\0. <CR><LF> characters are sent out after that. // 0x02: For uart_get_line function, stop transfer when <LF> // is received. // For uart_put_line function, transfer is stopped after // reaching \\0. A <LF> character is sent out after that. //0x03: For uart_get_line function, RESERVED.

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 289 of 313 NXP Semiconductors UM10601 Chapter 24: LPC800 USART API ROM driver routines // For uart_put_line function, transfer is stopped after // reaching \\0. uint16_t driver_mode; //0x00: Polling mode, function is blocked until transfer is // finished. // 0x01: Intr mode, function exit immediately, callback function // is invoked when transfer is finished. //0x02: RESERVED UART_CALLBK_T callback_func_pt; // callback function } UART_PARAM_T ;

24.5 Functional description

<tbd>

25.1 How to read this chapter

The debug functionality is identical for all LPC800 parts.

25.2 Features

• Supports ARM Serial Wire Debug mode.
• Direct debug access to all memories, registers, and peripherals.
• No target resources are required for the debugging session.
• Four breakpoints.
• Two data watchpoints that can also be used as triggers.
• Supports JTAG boundary scan.
• Micro Trace Buffer (MTB) supported.

25.3 General description

Support for boundary scan and Micro Trace Buffer is available.

25.4 Pin description

assigned to special pins on the package. The SWD functions are enabled by default. See Section 9.3.2 to enable the analog comparator inputs and the reference voltage input. Section 25.5.3). There is no access to the boundary scan pins through the switch matrix. Table 281. SWD pin description (SWD). This pin is pulled up internally.

25.5 Functional description

25.5.1 Debug limitations

the CPU is stopped. Other peripherals are not affected.

25.5.2 Debug connections for SWD

GPIO, but it should not be held LOW on power-up or reset. Table 282. JTAG boundary scan pin description for JTAG boundary scan when the RESET pin is LOW.

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25.5.3 Boundary scan

The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC11Uxx is in reset. To perform boundary scan testing, follow these steps: 1. Erase any user code residing in flash. 2. Power up the part with the RESET pin pulled HIGH externally. 3. Wait for at least 250 s. 4. Pull the RESET pin LOW externally. 5. Perform boundary scan operations. 6. Once the boundary scan operations are completed, assert the TRST pin to enable the SWD debug mode and release the RESET pin (pull HIGH). Remark: The JTAG interface cannot be used for debug purposes. Remark: POR, BOD reset, or a LOW on the TRST pin puts the test TAP controller in the Test-Logic Reset state. The first TCK clock while RESET = HIGH places the test TAP in Run-Test Idle mode. The VTREF pin on the SWD connector enables the debug connector to match the target voltage. Fig 43. Connecting the SWD pins to a standard SWD connector /g53/g40/g54/g40/g55 /g54/g76/g74/g81/g68/g79/g86/g3/g73/g85/g82/g80/g3/g54/g58/g39/g3/g70/g82/g81/g81/g72/g70/g87/g82/g85 /g54/g58/g39/g44/g50 /g54/g58/g38/g47/g46 /g57/g39/g39 /g42/g81/g71 /g57/g55/g53/g40/g41 /g54/g58/g39/g44/g50 /g54/g58/g38/g47/g46 /g81/g54/g53/g54/g55 /g42/g49/g39 /g47/g51/g38/g27/g19/g19 /g44/g54/g51/g3/g72/g81/g87/g85/g92 /g51/g44/g50/g19/g66/g20

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26.1 Packages

Chapter 26: LPC800 Packages and pin description Rev. 1.0 — 7 November 2012 Preliminary user manual Fig 44. Pin configuration DIP8 package (LPC810M021FN8) /g53/g40/g54/g40/g55/g18/g51/g44/g50/g19/g66/g24/g51/g44/g50/g19/g66/g19/g18/g36/g38/g48/g51/g66/g44/g20/g18/g55/g39/g50 /g51/g44/g50/g19/g66/g23/g18/g58/g36/g46/g40/g56/g51/g18/g55/g53/g54/g55/g57/g54/g54 /g54/g58/g38/g47/g46/g18/g51/g44/g50/g19/g66/g22/g18/g55/g38/g46/g57/g39/g39 /g54/g58/g39/g44/g50/g18/g51/g44/g50/g19/g66/g21/g18/g55/g48/g54/g51/g44/g50/g19/g66/g20/g18/g36/g38/g48/g51/g66/g44/g21/g18/g38/g47/g46/g44/g49/g18/g55/g39/g44 /g68/g68/g68/g16/g19/g19/g24/g26/g23/g26 /g20 /g21 /g22 /g23 /g25 /g24 /g27 /g26 /g39/g44/g51/g27 Fig 45. Pin configuration TSSOP16 package /g47/g51/g38/g27/g20/g20/g48/g19/g19/g20/g41/g39/g43/g20/g25 /g47/g51/g38/g27/g20/g21/g48/g20/g19/g20/g41/g39/g43/g20/g25 /g55/g54/g54/g50/g51/g20/g25 /g51/g44/g50/g19/g66/g20/g22 /g51/g44/g50/g19/g66/g19/g18/g36/g38/g48/g51/g66/g44/g20/g18/g55/g39/g50 /g51/g44/g50/g19/g66/g20/g21 /g51/g44/g50/g19/g66/g25/g18/g57/g39/g39/g38/g48/g51 /g53/g40/g54/g40/g55/g18/g51/g44/g50/g19/g66/g24 /g51/g44/g50/g19/g66/g26 /g51/g44/g50/g19/g66/g23/g18/g58/g36/g46/g40/g56/g51/g18/g55/g53/g54/g55 /g57/g54/g54 /g54/g58/g38/g47/g46/g18/g51/g44/g50/g19/g66/g22/g18/g55/g38/g46 /g57/g39/g39 /g54/g58/g39/g44/g50/g18/g51/g44/g50/g19/g66/g21/g18/g55/g48/g54 /g51/g44/g50/g19/g66/g27/g18/g59/g55/g36/g47/g44/g49 /g51/g44/g50/g19/g66/g20/g20 /g51/g44/g50/g19/g66/g28/g18/g59/g55/g36/g47/g50/g56/g55 /g51/g44/g50/g19/g66/g20/g19 /g51/g44/g50/g19/g66/g20/g18/g36/g38/g48/g51/g66/g44/g21/g18/g38/g47/g46/g44/g49/g18/g55/g39/g44 /g68/g68/g68/g16/g19/g19/g22/g26/g19/g26 /g20 /g21 /g22 /g23 /g24 /g25 /g26 /g27 /g20/g19 /g28 /g20/g21 /g20/g20 /g20/g23 /g20/g22 /g20/g25 /g20/g24 Fig 46. Pin configuration SO20 package (LPC812M101FD20) /g54/g50/g21/g19 /g51/g44/g50/g19/g66/g20/g26 /g51/g44/g50/g19/g66/g20/g23 /g51/g44/g50/g19/g66/g20/g22 /g51/g44/g50/g19/g66/g19/g18/g36/g38/g48/g51/g66/g44/g20/g18/g55/g39/g50 /g51/g44/g50/g19/g66/g20/g21 /g51/g44/g50/g19/g66/g25/g18/g57/g39/g39/g38/g48/g51 /g53/g40/g54/g40/g55/g18/g51/g44/g50/g19/g66/g24 /g51/g44/g50/g19/g66/g26 /g51/g44/g50/g19/g66/g23/g18/g58/g36/g46/g40/g56/g51/g18/g55/g53/g54/g55 /g57 /g54/g54 /g54/g58/g38/g47/g46/g18/g51/g44/g50/g19/g66/g22/g18/g55/g38/g46 /g57/g39/g39 /g54/g58/g39/g44/g50/g18/g51/g44/g50/g19/g66/g21/g18/g55/g48/g54 /g51/g44/g50/g19/g66/g27/g18/g59/g55/g36/g47/g44/g49 /g51/g44/g50/g19/g66/g20/g20 /g51/g44/g50/g19/g66/g28/g18/g59/g55/g36/g47/g50/g56/g55 /g51/g44/g50/g19/g66/g20/g19 /g51/g44/g50/g19/g66/g20/g18/g36/g38/g48/g51/g66/g21/g18/g38/g47/g46/g44/g49/g18/g55/g39/g44 /g51/g44/g50/g19/g66/g20/g25 /g51/g44/g50/g19/g66/g20/g24 /g68/g68/g68/g16/g19/g19/g22/g26/g24/g25 /g20 /g21 /g22 /g23 /g24 /g25 /g26 /g27 /g28 /g20/g19 /g20/g21 /g20/g20 /g20/g23 /g20/g22 /g20/g25 /g20/g24 /g20/g27 /g20/g26 /g21/g19 /g20/g28

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26.2 Pin description

The pin description table Table 283 shows the pin functions that are fixed to specific pins on each package. These fixed-pin functions are selectable between the GPIO, comparator, SWD, and the XTAL pins. By default, the GPIO function is selected except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in boundary scan mode only. Movable function for the I2C, USART, SPI, and SCT pin functions can be assigned through the switch matrix to any pin that is not power or ground in place of the pin’s fixed functions. The following exceptions apply: For full I2C-bus compatibility, assign the I2C functions to the open-drain pins PIO0_11 and PIO0_10. Do not assign more than one output to any pin. However, more than one input can be assigned to a pin. Pin PIO0_4 triggers a wake-up from Deep power-down mode. If you need to wake up from Deep power-down mode via an external pin, do not assign any movable function to this pin. The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to PIO0_4 by hardware when the part is in boundary scan mode. Fig 47. Pin configuration TSSOP20 package /g47/g51/g38/g27/g20/g21/g48/g20/g19/g20/g41/g39/g43/g21/g19 /g55/g54/g54/g50/g51/g21/g19 /g51/g44/g50/g19/g66/g20/g26 /g51/g44/g50/g19/g66/g20/g23 /g51/g44/g50/g19/g66/g20/g22 /g51/g44/g50/g19/g66/g19/g18/g36/g38/g48/g51/g66/g44/g20/g18/g55/g39/g50 /g51/g44/g50/g19/g66/g20/g21 /g51/g44/g50/g19/g66/g25/g18/g57/g39/g39/g38/g48/g51 /g53/g40/g54/g40/g55/g18/g51/g44/g50/g19/g66/g24 /g51/g44/g50/g19/g66/g26 /g51/g44/g50/g19/g66/g23/g18/g58/g36/g46/g40/g56/g51/g18/g55/g53/g54/g55 /g57 /g54/g54 /g54/g58/g38/g47/g46/g18/g51/g44/g50/g19/g66/g22/g18/g55/g38/g46 /g57/g39/g39 /g54/g58/g39/g44/g50/g18/g51/g44/g50/g19/g66/g21/g18/g55/g48/g54 /g51/g44/g50/g19/g66/g27/g18/g59/g55/g36/g47/g44/g49 /g51/g44/g50/g19/g66/g20/g20 /g51/g44/g50/g19/g66/g28/g18/g59/g55/g36/g47/g50/g56/g55 /g51/g44/g50/g19/g66/g20/g19 /g51/g44/g50/g19/g66/g20/g18/g36/g38/g48/g51/g66/g44/g21/g18/g38/g47/g46/g44/g49/g18/g55/g39/g44 /g51/g44/g50/g19/g66/g20/g25 /g51/g44/g50/g19/g66/g20/g24 /g68/g68/g68/g16/g19/g19/g22/g26/g26/g24 /g20 /g21 /g22 /g23 /g24 /g25 /g26 /g27 /g28 /g20/g19 /g20/g21 /g20/g20 /g20/g23 /g20/g22 /g20/g25 /g20/g24 /g20/g27 /g20/g26 /g21/g19 /g20/g28

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 295 of 313 NXP Semiconductors UM10601 Chapter 26: LPC800 Packages and pin description Table 283. Pin description table (fixed pins) PIO0_0/ACMP_I1/ TDO 19 16 8 [5] I/O I; PU PIO0_0 — General purpose digital input/output port 0 pin 0. In ISP mode, this is the USART0 receive pin U0_RXD. In boundary scan mode: TDO (Test Data Out). AI - ACMP_I1 — Analog comparator input 1. PIO0_1/ACMP_I2/ CLKIN/TDI 12 9 5 [5] I/O I; PU PIO0_1 — General purpose digital input/output pin. ISP entry pin. A LOW level on this pin during reset starts the ISP command handler. In boundary scan mode: TDI (Test Data In). AI - ACMP_I2 — Analog comparator input 2. I- CLKIN — External clock input. SWDIO/PIO0_2/TMS 7 6 4 [2] I/O I; PU SWDIO — Serial Wire Debug I/O. SWDIO is enabled by default on this pin. In boundary scan mode: TMS (Test Mode Select). I/O - PIO0_2 — General purpose digital input/output pin. SWCLK/PIO0_3/ TCK 65 3 [2] I/O I; PU SWCLK — Serial Wire Clock. SWCLK is enabled by default on this pin. In boundary scan mode: TCK (Test Clock). I/O - PIO0_3 — General purpose digital input/output pin. PIO0_4/WAKEUP/ TRST 54 2 [6] I/O I; PU PIO0_4 — General purpose digital input/output pin. In ISP mode, this is the USART0 transmit pin U0_TXD. In boundary scan mode: TRST (Test Reset). This pin triggers a wake-up from Deep power-down mode. If you need to wake up from Deep power-down mode via an external pin, do not assign any movable function to this pin. Pull this pin HIGH externally to enter Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. RESET /PIO0_5 4 3 1 [4] I/O I; PU RESET — External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. I- PIO0_5 — General purpose digital input/output pin. PIO0_6/VDDCMP 18 15 - [9] I/O I; PU PIO0_6 — General purpose digital input/output pin. AI - VDDCMP — Alternate reference voltage for the analog comparator. PIO0_7 17 14 - [2] I/O I; PU PIO0_7 — General purpose digital input/output pin. PIO0_8/XTALIN 14 11 - [8] I/O I; PU PIO0_8 — General purpose digital input/output pin. I- XTALIN — Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.95 V. PIO0_9/XTALOUT 13 10 - [8] I/O I; PU PIO0_9 — General purpose digital input/output pin. O- XTALOUT — Output from the oscillator circuit. PIO0_10 9 8 - [3] II A PIO0_10 — General purpose digital input/output pin. Assign I2C functions to this pin when true open-drain pins are needed for a signal compliant with the full I2C specification.

DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA Preliminary user manual Rev. 1.0 — 7 November 2012 296 of 313 NXP Semiconductors UM10601 Chapter 26: LPC800 Packages and pin description [1] Pin state at reset for default function: I = Input; AI = Anal og Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level ); IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad providing digital I/O functions with conf igurable pull-up/pull-down resistors and configurable hysteresis; includes high-current output driver. [3] True open-drain pin. I 2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. Do not use this pad for high-speed applications like the SPI clock. [4] RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. [5] 5 V tolerant pin providing standard digita l I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant. [6] 5 V tolerant pad providing digital I/O functions with conf igurable pull-up/pull-down resistors and configurable hysteresis. In Deep power-down mode, pulling this pin LOW wakes up the chip. [7] 5 V tolerant pad providing digital I/O functions with conf igurable pull-up/pull-down resistors and configurable hysteresis. [8] 5 V tolerant pin providing standard digital I/O functions wi th configurable modes, configurable hysteresis, and analog I/O for the system oscillator. When configured as an analog I/O, the digital section of the pin is disabled, and the pin is not 5 V tolerant. [9] Not a 5 V tolerant pin due to special analog functionality. Pi n provides standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O. When configured as an analog I/O, the digital section of the pin is disabled PIO0_11 8 7 - [3] II A PIO0_11 — General purpose digital input/output pin. Assign I2C functions to this pin when true open-drain pins are needed for a signal compliant with the full I2C specification. PIO0_12 3 2 - [2] I/O I; PU PIO0_12 — General purpose digital input/output pin. PIO0_13 2 1 - [2] I/O I; PU PIO0_13 — General purpose digital input/output pin. PIO0_14 20 - - [7] I/O I; PU PIO0_14 — General purpose digital input/output pin. PIO0_15 11 - - [7] I/O I; PU PIO0_15 — General purpose digital input/output pin. PIO0_16 10 - - [7] I/O I; PU PIO0_16 — General purpose digital input/output pin. PIO0_17 1 - - [7] I/O I; PU PIO0_17 — General purpose digital input/output pin. VDD 15 12 6 - - 3.3 V supply voltage. VSS 16 13 7 - Ground. Table 284. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix) U0_TXD O Transmitter output for USART0. U0_RXD I Receiver input for USART0. O Request To Send output for USART0. U0_CTS I Clear To Send input for USART0. U0_SCLK I/O Serial clock input/output for USART0 in synchronous mode. U1_TXD O Transmitter output for USART1. U1_RXD I Receiver input for USART1. O Request To Send output for USART1. U1_CTS I Clear To Send input for USART1. U1_SCLK I/O Serial clock input/output for USART1 in synchronous mode. U2_TXD O Transmitter output for USART2.

U2_RXD I Receiver input for USART2. U2_RTS O Request To Send output for USART2. U2_CTS I Clear To Send input for USART2. U2_SCLK I/O Serial clock input/output for USART2 in synchronous mode. SPI0_SCK I/O Serial clock for SPI0. SPI0_MOSI I/O Master Out Slave In for SPI0. SPI0_MISO I/O Master In Slave Out for SPI0. SPI0_SSEL I/O Slave select for SPI0. SPI1_SCK I/O Serial clock for SPI1. SPI1_MOSI I/O Master Out Slave In for SPI1. SPI1_MISO I/O Master In Slave Out for SPI1. SPI1_SSEL I/O Slave select for SPI1. 2C-bus clock input/output (open-drain if assigned to pin PIO0_10). Plus is selected in the I/O configuration register. I2C0_SDA I/O I 2C-bus data input/output (open-drain if assigned to pin PIO0_11). Fast-mode Plus is selected in the I/O configuration register. ACMP_O O Analog comparator output. GPIO_INT_BMAT O Output of the pattern match engine.

27.1 Abbreviations

27.2 References

Table 285. Abbreviations

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27.3 Legal information

27.3.1 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

27.3.2 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

27.3.3 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V.

27.4 Tables

Table 3. Connection of interrupt sources to the NVIC . .10 Table 5. Register overview: System configuration (base Table 6. System memory remap register Table 7. Peripheral reset control register (PRESETCTRL, Table 8. System PLL cont rol register (SYSPLLCTRL, Table 9. System PLL status register (SYSPLLSTAT, Table 10. System oscillator control register (SYSOSCCTRL, Table 11. Watchdog oscillator control register Table 12. System reset stat us register (SYSRSTSTAT, Table 13. System PLL clock source select register Table 14. System PLL clock source update enable register Table 15. Main clock source select register (MAINCLKSEL, Table 16. Main clock source update enable register Table 17. System clock divi der register (SYSAHBCLKDIV, Table 18. System clock control register Table 19. USART clock divider register (UARTCLKDIV, Table 20. CLKOUT clock so urce select register Table 21. CLKOUT clock source update enable register Table 22. CLKOUT clock divi der registers (CLKOUTDIV, Table 23. USART fractional generator divider value register Table 24. USART fractional generator multiplier value Table 25. External trace buffer command register Table 26. POR captured PIO status register 0 Table 27. IOCON glitch filter clock divider registers 6 to 0 Table 28. BOD control register (BODCTRL, address 0x4004 Table 29. System tick timer calibration register Table 30. IRQ latency register (IRQLATENCY , address Table 31. NMI source selection register (NMISRC, address Table 32. Pin interrupt select registers (PINTSEL[0:7], Table 33. Start logic 0 pin wake-up enable register 0 Table 34. Start logic 1 interrupt wake-up enable register Table 35. Deep-sleep configuration register Table 36. Wake-up configurat ion register (PDAWAKECFG, Table 37. Power configuration register (PDRUNCFG, Table 38. Device ID register (DEVICE_ID, address 0x4004 Table 41. Wake-up sources for reduced power modes . . 43 Table 42. Register overview: PMU (base address 0x4002 Table 43. Power control register (PCON, address 0x4002 Table 44. General purpose registers 0 to 3 (GPREG[0:3], Table 45. Deep power down control register (DPDCTRL, Table 48. Register overview: I/O configuration (base Table 49. PIO0_17 register (PIO0_17, address 0x4004 Table 50. PIO0_13 register (PIO0_13, address 0x4004

Table 51. PIO0_12 register (PIO0_12, address 0x4004 Table 52. PIO0_5 register (P IO0_5, address 0x4004 400C) Table 53. PIO0_4 register (P IO0_4, address 0x4004 4010) Table 54. PIO0_3 register (P IO0_3, address 0x4004 4014) Table 55. PIO0_2 register (P IO0_2, address 0x4004 4018) Table 56. PIO0_11 register (PIO0_11, address 0x4004 Table 57. PIO0_10 register (PIO0_10, address 0x4004 Table 58. PIO0_16 register (PIO0_16, address 0x4004 Table 59. PIO0_15 register (PIO0_15, address 0x4004 Table 60. PIO0_1 register (P IO0_1, address 0x4004 402C) Table 61. PIO0_9 register (P IO0_9, address 0x4004 4034) Table 62. PIO0_8 register (P IO0_8, address 0x4004 4038) Table 63. PIO0_7 register (P IO0_7, address 0x4004 403C) Table 64. PIO0_6 register (P IO0_6, address 0x4004 4040) Table 65. PIO0_0 register (P IO0_0, address 0x4004 4044) Table 66. PIO0_14 register (PIO0_14, address 0x4004 Table 68. Register overview: GPIO port (base address Table 69. GPIO port 0 byte pin registers (B[0:17], addresses Table 70. GPIO port 0 word pin registers (W[0:17], Table 71. GPIO direction port 0 register (DIR0, address Table 72. GPIO mask port 0 register (MASK0, address Table 73. GPIO port 0 pin register (PIN0, address 0xA000 Table 74. GPIO masked port 0 pin register (MPIN0, address Table 75. GPIO set port 0 regi ster (SET0, address 0xA000 Table 76. GPIO clear port 0 register (CLR0, address 0xA000 Table 77. GPIO toggle port 0 register (NOT0, address Table 79. Register overview: Pin interrupts/pattern match Table 80. Pin interrupt mode register (ISEL, address Table 81. Pin interrupt level or rising edge interrupt enable Table 82. Pin interrupt level or rising edge interrupt set Table 83. Pin interrupt level or rising edge interrupt clear Table 84. Pin interrupt active level or falling edge interrupt Table 85. Pin interrupt active level or falling edge interrupt Table 86. Pin interrupt active level or falling edge interrupt Table 87. Pin interrupt rising edge register (RISE, address Table 88. Pin interrupt falling edge register (FALL, address Table 89. Pin interrupt status register (IST, address 0xA000 Table 90. Pattern match interrupt control register (PMCTRL, Table 91. Pattern match bit-sl ice source register (PMSRC, Table 92. Pattern match bit sl ice configuration register Table 93. Pin interrupt registers for edge- and Table 94. Movable functions (assign to pins PIO0_0 to Table 95. Register overview: Switch matrix (base address Table 96. Pin assign register 0 (PINASSIGN0, address Table 97. Pin assign register 1 (PINASSIGN1, address Table 98. Pin assign register 2 (PINASSIGN2, address Table 99. Pin assign register 3 (PINASSIGN3, address Table 100. Pin assign register 4 (PINASSIGN4, address Table 101. Pin assign register 5 (PINASSIGN5, address Table 102. Pin assign register 6 (PINASSIGN6, address Table 103. Pin assign register 7 (PINASSIGN7, address Table 104. Pin assign register 8 (PINASSIGN8, address

Table 105. Pin enable register 0 (PINENABLE0, address Table 107. Register overview: State Configurable Timer Table 108. SCT configuration register (CONFIG, address Table 109. SCT control register (CTRL, address 0x5000 Table 110. SCT limit register (LIMIT, address 0x5000 4008) Table 111. SCT halt condition register (HALT, address Table 112. SCT stop condition register (STOP, address Table 113. SCT start condition register (START, address Table 114. SCT counter register (COUNT, address 0x5000 Table 115. SCT state register (STATE, address 0x5000 Table 116. SCT input register (INPUT, address 0x5000 Table 117. SCT match/capture registers mode register Table 118. SCT output register (OUTPUT, address 0x5000 Table 119. SCT bidirectional output control register Table 120. SCT conflict resolution register (RES, address Table 121. SCT flag enable register (EVEN, address 0x5000 Table 122. SCT event flag register (EVFLAG, address Table 123. SCT conflict enable register (CONEN, address Table 124. SCT conflict flag register (CONFLAG, address Table 125. SCT match registers 0 to 4 (MATCH[0:4], (MATCH4)) bit description (REGMODEn bit = 0) . Table 126. SCT capture registers 0 to 4 (CAP[0:4], address Table 127. SCT match reload registers 0 to 4 Table 128. SCT capture control registers 0 to 4 Table 129. SCT event state mask registers 0 to 5 Table 130. SCT event control register 0 to 5 (EV[0:5]_CTRL, Table 131. SCT output set register (OUT[0:3]_SET, address Table 132. SCT output clear register (OUT[0:3]_CLR, Table 134. Register overview: MRT (base address 0x4000 Table 135. Time interval register (INTVAL[0:3], address Table 136. Timer register (TIMER[0:3], address 0x4000 4004 Table 137. Control register (CTRL[0:3], address 0x4000 Table 138. Status register (STAT[0:3], address 0x4000 400C Table 139. Idle channel register (IDLE_CH, address 0x4000 Table 140. Global interrupt flag register (IRQ_FLAG, address Table 141. Register overview: Watchdog timer (base Table 142. Watchdog mode register (MOD - 0x4000 4000) Table 144. Watchdog Timer Constant register (TC - 0x4000 Table 145. Watchdog Feed register (FEED - 0x4000 4008) Table 146. Watchdog Timer Value register (TV - 0x4000 Table 147. Watchdog Timer Warning Interrupt register Table 148. Watchdog Timer Window register (WINDOW - Table 150. Register overview: Analog comparator (base Table 151. Comparator control register (CTRL, address Table 152. Voltage ladder register (LAD, address 0x4002 Table 153. Register overview: WKT (base address 0x4000 Table 154. Control register (CTRL, address 0x4000 8000) bit Table 155. Counter register (COUNT, address 0x4000 800C)

Table 158. USART Configuration register (CFG, address Table 159. USART Control register (CTRL, address 0x4006 Table 160. USART Status register (STAT, address 0x4006 Table 161. USART Interrupt Enable read and set register Table 162. USART Interrupt Enable clear register Table 163. USART Receiver Data register (RXDATA, Table 164. USART Receiver Data with Status register Table 165. USART Transmitter Data Register (TXDATA, Table 166. USART Baud Rate Generator register (BRG, Table 167. USART Interrupt Status register (INTSTAT, Table 170. I2C Configuration register (CFG, address 0x4005 Table 174. Interrupt Enable Set and read register Table 175. Interrupt Enable Clear register (INTENCLR, Table 176. time-out register (TIMEOUT, address 0x4005 Table 177. I2C Clock Divider register (DIV, address 0x4005 Table 178. I2C Interrupt Status register (INTSTAT, address Table 179. Master Control register (MSTCTL, address Table 180. Master Time register (MSTTIME, address 0x4005 Table 181. Master Data register (MSTDAT, address 0x4005 Table 182. Slave Control register (SLVCTL, address 0x4005 Table 183. Slave Data register (SLVDAT, address 0x4005 Table 184. Slave Address registers (SLVADR[0:3]- address Table 185. Slave address Qualifier 0 register (SLVQUAL0, Table 186. Monitor data register (MONRXDAT, address Table 188. Register overview: SPI (base address 0x4005 Table 189. SPI Configuration register (CFG, addresses Table 190. SPI Delay register (DLY , addresses 0x4005 8004 Table 191. SPI Status register (STAT, addresses 0x4005 Table 192. SPI Interrupt Enable read and Set register Table 193. SPI Interrupt Enable clear register (INTENCLR, Table 194. SPI Receiver Data register (RXDAT, addresses Table 195. SPI Transmitter Data and Control register Table 196. SPI Transmitter Data Register (TXDAT, Table 197. SPI Transmitter Control register (TXCTL, Table 198. SPI Divider register (DIV, addresses 0x4005 8024 Table 199. SPI Interrupt Status register (INTSTAT, addresses Table 201. Register overview: CRC engine (base address

Table 202. CRC mode register (MODE, address 0x5000 Table 203. CRC seed register (SEED, address 0x5000 Table 204. CRC checksum register (SUM, address 0x5000 Table 205. CRC data register (WR_DATA, address 0x5000 Table 206. Register overview: FMC (base address 0x4004 Table 207. Flash configuration register (FLASHCFG, Table 208. Flash Module Signature Start register Table 209. Flash Module Signature Stop register (FMSSTOP Table 210. FMSW0 register bit description (FMSW0, Table 215. Code Read Protection hardware/software Table 216. ISP commands allowed for different CRP levels . Table 223. UART ISP Prepare sector(s) for write operation Table 227. UART ISP Blank check sector command . . .248 Table 228. UART ISP Read Part Identification command248 Table 230. UART ISP Read Boot Code version number Table 235. IAP Prepare sector(s) for write operation Table 240. IAP Read Boot Code version number command. Table 254. I2C Master Transmit and Receive Polling . . . 272 Table 284. Movable functions (assign to pins PIO0_0 to

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27.5 Figures

Fig 7. Example: Connect function U0_RXD and U0_TXD Fig 17. Early watchdog feed with windowed mode enabled 154 Fig 18. Correct watchdog feed with windowed mode Fig 38. LPC800 clock configuration for power API use .260 Fig 43. Connecting the SWD pins to a standard SWD Fig 44. Pin configuration DI P8 package (LPC810M021FN8) 293 Fig 46. Pin configuration SO20 package

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27.6 Contents

Chapter 1: LPC800 Introductory information Chapter 2: LPC800 Memory mapping Chapter 3: LPC800 Nested Vectored Interrupt Controller (NVIC) Chapter 4: LPC800 System configuration (SYSCON) 4.3.2 Configure the main clock and system clock . . 14

4.3.3 Set up the system oscillator using XTALIN and

4.6.16 CLKOUT clock source update enable register 27

4.6.18 USART fractional generator divider value register

4.6.19 USART fractional generator multiplier value

4.6.22 IOCON glitch filter clock divider registers 6 to 0 .

4.6.29 Start logic 1 interrupt wake-up enable register 34

Chapter 5: LPC800 Reduced power modes and Power Management Unit (PMU)

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8.3.1 Configure pins as pin in terrupts or as inputs to the

8.6.2 Pin interrupt level or rising edge interrupt enable

8.6.3 Pin interrupt level or rising edge interrupt set

8.6.4 Pin interrupt level or rising edge interrupt clear

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8.6.5 Pin interrupt active level or falling edge interrupt

8.6.6 Pin interrupt active level or falling edge interrupt

8.6.7 Pin interrupt active le vel or falling edge interrupt

8.6.12 Pattern Match Interrupt Bit-Slice Source register.

8.6.13 Pattern Match Interrupt Bit-Slice Configuration

Chapter 9: LPC800 Switch matrix 9.3.1 Connect an internal signal to a package pin. 101 9.3.2 Enable an analog input or other special function . 101 Chapter 10: LPC800 State Configurable Timer (SCT) 10.6.10 SCT match/capture registers mode register. 123

10.6.19 SCT capture registers 0 to 4 (REGMODEn bit = 1)

10.6.20 SCT match reload registers 0 to 4 (REGMODEn

10.6.21 SCT capture control registers 0 to 4 (REGMODEn

10.7.9.2 Configure the match and capture registers . 135 Chapter 11: LPC800 Multi-Rate Timer (MRT)

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17.7.1 Operating modes: clock and phase selection 220

Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine Chapter 19: LPC800 Flash controller 19.4.4 Flash signature generatio n result register . . 233

19.5.1.1 Signature generat ion address and control

Chapter 20: LPC800 Boot ROM

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21.4.1.6 Prepare sector(s) for write operation <start sector

21.4.1.7 Copy RAM to flash <Flash address> <RAM

21.4.1.9 Erase sector(s) <start sector number> <end

21.4.1.10 Blank check sector(s) <sector number> <end

21.4.2.1 Prepare sector(s) for write operation (IAP) . 252

21.4.2.7 Compare <address1> <address2> <no of bytes>

21.5.2 Memory and interrupt use for ISP and IAP . 257

21.5.3.2 Serial Wire Debug (SWD) flash programming

Chapter 22: LPC800 Power profile API ROM driver

22.4.1.1 Param0: system PLL input frequency and

22.5.1.1 Invalid frequency (device maximum clock rate

22.5.1.2 Invalid frequency se lection (system clock divider

22.5.1.4 System clock less than or equal to the expected

22.5.1.5 System clock grea ter than or equal to the

22.5.1.6 System clock approxim ately equal to the expected

22.5.2.1 Invalid frequency (device maximum clock rate

Chapter 23: LPC800 I2C-bus ROM API

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DRAFT DRAFT DRAFT DRDRAFT DRAFT DRAFT DRAF DRAFT DRAFT DRA FT D RAFT DR AFT D DRA FT DRAFT DRAFT DRAFT DRAFT DRAFT DRA NXP Semiconductors UM10601 Chapter 27: Supplementary information © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 November 2012 Document identifier: UM10601 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 313