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UBA2017AT reference design for 420 V (DC) Rev. 1 — 13 August 2012 User manual Document information Info Content Keywords UBA2017AT, dimmable, 2 x T5 35 W ballast Abstract This user manual describes the performance, technical data and wiring of the 420 V (DC) UBA2017AT reference design. This dimmable design drives two 35 W T5 lamps.
User manual Rev. 1 — 13 August 2012 2 of 24 Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors UM10561 UBA2017AT reference design for 420 V (DC)
Revision history
v.1 20120813 first issue
User manual Rev. 1 — 13 August 2012 3 of 24 NXP Semiconductors UM10561 UBA2017AT reference design for 420 V (DC) 1. Introduction The UBA2017AT reference design is intended to serve as an example of a dimmable two lamp ballast. This user manual describes the specification and use of the UBA2017AT board. This reference ballast design is intended to drive two T5 35 W lamps. 2. Safety warning Connected the board to the DC voltage. Avoid touching the board while it is connected to the mains voltage. An isolated housing is mandatory when used in uncontrolled, non-laboratory environments. WARNING Lethal voltage and fire ignition hazard The non-insulated high voltages that are present when operating this product, constitute a risk of electric shock, personal injury, death and/or ignition of fire. This product is intended for evaluation purposes only. It shall be operated in a designated test area by personnel qualified according to local requirements and labor laws to work with non-insulated mains voltages and high-voltage circuits. This product shall never be operated unattended. a. Top view. b. Bottom view. Fig 1. Photograph of the UBA2017AT reference design
not connect the (floating) DIM input. Remark: The chassis connection must connect to the earth using mounting hole MH1. Table 1. Specifications for the reference board Table 2. Ballast performance
User manual Rev. 1 — 13 August 2012 5 of 24 NXP Semiconductors UM10561 UBA2017AT reference design for 420 V (DC)
3.1 Dimming without using an external voltage source
The ballast is dimmed using a voltage source of 1 V (DC) to 10 V (DC) connected to connector X1. It is also possible to dim using an external logarithmic potentiometer of 470 k (for example, no external voltage supply is available). The potentiometer must connect pins 5 (gray wire, DIM) and 4 (violet wire, DIM+) of connector X1. 4. Performance data
4.1 Dimming curve
Measured using an AC coupled current probe. Fig 3. RMS lamp discharge current as function of the DIM input voltage Vi(dim) (V) 0 108462 aaa-003764 120 160 200 Idch
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4.2 Sum of Squares (SoS) and maximum lead current curves
(1) SoS (maximum). (2) SoS measured. (3) SoS target. (4) SoS (minimum). a. SoS results (1) I LH (maximum). (2) I LH (measured). (3) I LL (maximum). (4) I LL (measured). b. Maximum RMS lead current check Fig 4. Sum of Squares and maximum lead current check Idch (mA) 0 18016080 12040 aaa-003765 0.02 0.04 0.00 0.06 0.08 SoS (A2) -0.02 (1) (2) (3) (4) aaa-003766 (3) (4) Idch (A) 0 20016080 12040 100 200 300 I (A) (1) (2)
User manual Rev. 1 — 13 August 2012 7 of 24 NXP Semiconductors UM10561 UBA2017AT reference design for 420 V (DC) 5. Board Information The input section includes:
- the fuse
- surge protection against fast AC transients The DC voltage connects to a buffer capacitor to supply the half-bridge circuit. The lamp connects to the half-bridge circuit. The UBA2017AT IC controls the half-bridge circuit. A low-voltage control input is present to control the dimming of the lamp light output. The half-bridge consists of two NMOST transistors which provide the voltage to power the resonant circuit. The resonant circuit includes a transformer for electrode preheating and heating. The type of ballast presented here is used for most ballast for lamp powers above 25 W. It is a cost-effective application.
5.1 Half-bridge operating principle
This topology supports dimming and preheat times below 1 s for T5 lamps. It uses an additional transformer for preheating/heating the filaments. Fig 5. Block diagram aaa-003767 FUSE420 V (DC) input voltage
1 V to 10 V
User manual Rev. 1 — 13 August 2012 8 of 24 NXP Semiconductors UM10561 UBA2017AT reference design for 420 V (DC) When the lamp is off, two resonant frequencies can be distinguished. A main resonant frequency fres and a second frequency fsec. Approaching fres ignites the lamp: (1) Preheating the electrodes near fsec increases the preheat current without increasing the filament current during normal operation. In dimmable applications, this aids compliance with the lamp sum of squares requirement. (2) Rx is used to limit the voltage when both lamps are removed. An equalizer transformer Teq is used to equalize the lamp current which is needed in deep dim settings. The UBA2017AT controller starts at 100 kHz and sweeps down until the preheat frequency is reached. The resistor on pin PH/EN sets the preheat frequency. During preheat, the LC tank voltage remains below 200 V to prevent early ignition and glow. Fig 6. Half-bridge topology Cres 4.7 nF lamp Y lamp X Cfil TyC 4 μH TxC 4 μH TyB 4 μH TxB 4 μH Cfil TyA 127 μH TxA 127 μH TeqA 2 x 33 mH 2 1 Lres 2 mH 2 5 TeqB34 CDC 220 nF Qhighside Qlowside Rx 10 kΩ Cx 56 nF
420 V (DC)
2 Lres Cres fsec LTxA LTyA
User manual Rev. 1 — 13 August 2012 9 of 24 NXP Semiconductors UM10561 UBA2017AT reference design for 420 V (DC)
5.2 Schematic diagrams
See Figure 8 for a detailed overview of the application. (1) LC tank voltage. (2) I fil. Fig 7. Half-bridge frequency resp onse with lamp not ignited aaa-001536 f (kHz) 40 100 8060 0.4 0.6 0.2 0.8 1.0 current (A) 0.8 1.2 0.4 1.6 2.0 Voltage (kV) (1) (2)
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User manual Rev. 1 — 13 August 2012 11 of 24 NXP Semiconductors UM10561 UBA2017AT reference design for 420 V (DC)
5.3 Functional description
The DC supply voltage is applied to the board and current flows through R3 and R4 to the supply of the controller (VDD pin). When the current through R3 and R4 is higher than 240 A (Istb(VDD)) of the controller the VDD voltage rises. When the VDD voltage is above
4.2 V (Vrst(VDD)), the half-bridge circuit low-side MOSFET switches on and the floating
supply capacitor C32 is pre-charged. The controller starts oscillating when the VDD voltage is above the 12.4 V (Vstartup(VDD)). The HB gate drivers start oscillating at 100 kHz (fsw(high)). The dV/dt supply using capacitor C8 takes over the VDD supply to supply the IC with enough energy for the gate drivers. The preheat timer starts and the controller sweeps down the frequency from 100 kHz to the preheat frequency. The PH/EN pin sets the preheat frequency level. The oscillator remains at the preheat frequency until the preheat timer has ended. When the preheat ends, the controller sweeps down the half-bridge switching frequency. The lamp ignites when the LC tank voltage reaches the lamp ignition voltage. The ignition frequency is typically 60 kHz. The lamp current increases and the LC tank voltage decreases. The controller senses the lamp current and LC tank voltage. The controller assumes that the lamp is on when the lamp current is high enough and the LC tank voltage is low enough for 3 ms. The representation of the states is V IFB > Vth(lod)IFB and VVFB < Vth(lod)VFB for td(lod). The controller enters burn state. In burn state, all the protective features are activated. The controller closes the lamp current control loop and the oscillator regulates the half-bridge switching frequency. The half-bridge frequency is controlled. It reaches the set point when the average absolute IFB pin voltage equals the DIM pin voltage.
5.3.1 Start-up current and relamp function
The VDD supply of the IC is charged using a start-up current derived from the rectified mains voltage. Resistors R3 and R4 provide the current path and determines the start-up voltage level. When the lamp is removed while set to deep dimming, the protection must trigger the controller to shut down. In this board, transistor Q7 pulls down the VDD voltage. The signals Lamp1 and Lamp2 sense the filaments of the lamps and control transistor Q7. The pull down by Q7 is released when all lamps are inserted.
User manual Rev. 1 — 13 August 2012 12 of 24 NXP Semiconductors UM10561 UBA2017AT reference design for 420 V (DC) 6. Waveforms (1) V EOL. (2) V FB. (3) V DD. (4) V CPT. a. Timing, supply and feedback signals (1) V GLHB. (2) V SHHB. (3) V CPT. b. Half-bridge signals at start-up Fig 9. Normal start-up operation
User manual Rev. 1 — 13 August 2012 13 of 24 NXP Semiconductors UM10561 UBA2017AT reference design for 420 V (DC) a. Lamp ignition (1) V lamp. (2) V DD. (3) V CPT. (4) V FB. b. Start-up with the high-side filaments disconnected Fig 10. Start-up operation
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Table 3. Bill of materials
1 PCB 7022-001-21961 NXP Semiconductors
Table 3. Bill of materials …continued
1729157 Phoenix Contact
1727065 Phoenix Contact
- Inductor appearance and dimensions
9.1 Half-bridge inductor
Wurth Electronics Midcom Inc.; part number: 760801080. Table 4. Half-bridge inductor electrical specifications
9.2 Heater transformer
Table 5. Heater transformer electrical specifications
9.3 Dim transformer
Wurth Electronics Midcom Inc.; part number: 750311081. Table 6. Dim transformer electrical specifications
9.4 Equalizing transformer
Table 7. Equalizing transfor mer electrical specifications
Table 8. Abbreviations
User manual Rev. 1 — 13 August 2012 23 of 24 NXP Semiconductors UM10561 UBA2017AT reference design for 420 V (DC) 11. Legal information
11.1 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.
11.2 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Evaluation products — This product is provided on an “as is” and “with all faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
11.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
NXP Semiconductors UM10561 UBA2017AT reference design for 420 V (DC) © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 August 2012 Document identifier: UM10561 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 12. Contents