UM10360

NXP Semiconductors

LPC17xx User manual Rev. 01-4 January 2010

Manufacturer: NXP Semiconductors

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Rev. 01 — 4 January 2010 User manual Document information Info Content Keywords LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1759, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller Abstract LPC17xx user manual

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 2 of 835 Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors UM10360 LPC17xx user manual

Revision history

1 20100104 LPC17xx user manual revision. Modifications:

“Draft” status removed.
Editorial updates and typographical corrections throughout the user manual.
LPC1758, LPC1767, and LPC1768 have been added to the keywords list on the front cover, the ordering information in section Section 1–4, and the part identification number table in Section 32–7.11.
The note about DMA operation in Sleep mode was removed from Section 4–8.1.
In Table 8–81, the CLKOUT function was removed from the description of P1.25.
In section the Ethernet chapter, in Section 10–16.1 and Section 10–17.2, it has been noted that the external PHY must be initialized and PHY clocks received by the Ethernet block prior to further initialization of the Ethernet block. Also, in Section 10–17.1, under the heading "Ownership of descriptors", the sentence about AHB arbitration was removed. A general and more correct discussion of the subject was added in Section 2–5.
The UART fractional baud rate generator is disabled in auto baud mode (see
In section Section 14–4.12 and Section 15–4.16, the description of the value of the DLL register has been is corrected to read "the value of the DLL register must be greater than 2".
The description of RPM calculation in the QEI chapter (see Section 26–4.3), definitions for the formula values are added, and the description improved. The description of the position and index compare registers incorrectly indicated that the less than,equal to, and greater than compare could be selected. It is changed to only indicate “equal to”.
A description of Flash signature generation has been added in Section 32–10.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 3 of 835 1. Introduction The LPC17xx is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation. The ARM Cortex-M3 is a next generation core that offers system enhancements such as modernized debug features and a higher level of support block integration. High speed versions (LPC1769 and LPC1759) operate at up to a 120 MHz CPU frequency. Other versions operate at up to an 100 MHz CPU frequency. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branches. The peripheral complement of the LPC17xx includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, a USB interface that can be configured as either Host, Device, or OTG, 8 channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3 I 2C interfaces, 2-input plus 2-output I2S interface, 8 channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power RTC with separate battery supply, and up to 70 general purpose I/O pins. UM10360 Chapter 1: LPC17xx Introductory information Rev. 01 — 4 January 2010 User manual

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 4 of 835 NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information 2. Features Refer to Section 1–4.1 for details of features on specific part numbers.

ARM Cortex-M3 processor, running at frequencies of up to 120 MHz on high speed versions (LPC1769 and LPC1759), up to 100 MHz on other versions. A Memory Protection Unit (MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. The combination of an enhanced flash memory accelerator and location of the flash memory on the CPU local code/data bus provides high code performance from flash.
Up to 64 kB on-chip SRAM includes: – Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access. – Up to two 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose instruction and data storage.
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I 2S, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, GPIO, and for memory-to-memory transfers.
Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time.
Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA. A single level of write buffering allows the CPU to continue without waiting for completion of APB writes if the APB was not already busy.
Serial interfaces: – Ethernet MAC with RMII interface and dedicated DMA controller. – USB 2.0 full-speed controller that can be configured for either device, Host, or OTG operation with an on-chip PHY for device and Host functions and a dedicated DMA controller. – Four UARTs with fractional baud rate generation, internal FIFO, IrDA, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support. – Two-channel CAN controller. – Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller. – SPI controller with synchronous, serial, full duplex communication and programmable data length. SPI is included as a legacy peripheral and can be used instead of SSP0. – Three enhanced I2C-bus interfaces, one with an open-drain output supporting the full I2C specification and Fast mode plus with data rates of 1Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 5 of 835 NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information – I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S interface can be used with the GPDMA. The I2S interface supports 3-wire data transmit and receive or 4-wire combined transmit and receive connections, as well as master clock output.

Other peripherals: – 70 (100 pin package) or 52 (80-pin package) General Purpose I/O (GPIO) pins with configurable pull-up/down resistors, open drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast access, and support Cortex-M3 bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any pin of ports 0 and 2 can be used to generate an interrupt. – 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller. – 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. – Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests. – One motor control PWM with support for three-phase motor control. – Quadrature encoder interface that can monitor one external quadrature encoder. – One standard PWM/timer block with external count input. – Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers, allowing system status to be stored when the rest of the chip is powered off. Battery power can be supplied from a standard 3 V Lithium button cell. The RTC will continue working when the battery voltage drops to as low as 2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode. – Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock. – Cortex-M3 system tick timer, including an external clock input option. – Repetitive interrupt timer provides programmable and repeating timed interrupts.
Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire Trace Port options.
Emulation trace module supports real-time trace.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources.
Non-maskable Interrupt (NMI) input.
Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, or the USB clock.
The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, Power-down, and Deep power-down modes.

Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI).
Each peripheral has its own clock divider for further power savings.
Brownout detect with separate threshold for interrupt and forced reset.
On-chip Power-On Reset (POR).
On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
4 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a system clock.
An on-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.
A second, dedicated PLL may be used for the USB interface in order to allow added flexibility for the Main PLL settings.
Versatile pin function selection feature allows many possibilities for using on-chip peripheral functions.
Available as 100-pin LQFP (14 x 14 x 1.4 mm) and 80-pin LQFP (12 x 12 x 1.4 mm) packages. 3. Applications
eMetering
Lighting
Industrial networking
Alarm systems
White goods
Motor control

4.1 Part options summary

Table 1. Ordering information Table 2. Ordering options for LPC17xx parts

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 8 of 835 NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information 5. Simplified block diagram Fig 1. LPC1768 simplified block diagram AHB to APB bridge AHB to APB bridge APB slave group 1APB slave group 0 Note: shaded peripheral blocks support General Purpose DMA RTC Power Domain Multilayer AHB Matrix I2C2 I2S UARTs 2 & 3 SSP0 Real Time Clock 20 bytes of backup registers SSP1 UARTs 0 & 1 CAN 1 & 2 I2C 0 & 1 SPI0 Capture/Compare Timers 0 & 1 Watchdog Timer PWM1 12-bit ADC Pin Connect Block GPIO Interrupt Ctl 32 kHz oscillator DMA controller Clock Generation, Power Control, Brownout Detect, and other system functions RST Xtalin Xtalout Clocks and Controls Ethernet PHY interface Ethernet MAC USB device, host, OTG USB interface JTAG interface ARM Cortex-M3 Test/Debug Interface System bus D-code bus I-code bus ROM 8 kB SRAM 64 kB Trace Port Trace Module High Speed GPIO Capture/Compare Timers 2 & 3 External Interrupts DAC System Control Motor Control PWM Quadrature Encoder Repetitive Interrupt Timer Flash 512 kB Flash Accelerator

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 9 of 835 NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information 6. Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and D-code buses which are faster and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. The LPC17xx uses a multi-layer AHB matrix to connect the Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals on different slaves ports of the matrix to be accessed simultaneously by different bus masters. Details of the multilayer matrix connections are shown in Figure 1–2 APB peripherals are connected to the CPU via two APB busses using separate slave ports from the multilayer AHB matrix. This allows for better performance by reducing collisions between the CPU and the DMA controller. The APB bus bridges are configured to buffer writes so that the CPU or DMA controller can write to APB devices without always waiting for APB write completion. 7. ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with Wakeup Interrupt Controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 User Guide that is appended to this manual.

7.1 Cortex-M3 Configuration Options

The LPC17xx uses the r2p0 version of the Cortex-M3 CPU, which includes a number of configurable options, as noted below. System options:

The Nested Vectored Interrupt Controller (NVIC) is included. The NVIC includes the SYSTICK timer.
The Wakeup Interrupt Controller (WIC) is included. The WIC allows more powerful options for waking up the CPU from reduced power modes.
A Memory Protection Unit (MPU) is included.
A ROM Table in included. The ROM Table provides addresses of debug components to external debug systems. Debug related options:

A JTAG debug interface is included.
Serial Wire Debug is included. Serial Wire Debug allows debug operations using only 2 wires, simple trace functions can be added with a third wire.
The Embedded Trace Macrocell (ETM) is included. The ETM provides instruction trace capabilities.
The Data Watchpoint and Trace (DWT) unit is included. The DWT allows data address or data value matches to be trace information or trigger other events. The DWT includes 4 comparators and counters for certain internal events.
An Instrumentation Trace Macrocell (ITM) is included. Software can write to the ITM in order to send messages to the trace port.
The Trace Port Interface Unit (TPIU) is included. The TPIU encodes and provides trace information to the outside world. This can be on the Serial Wire Viewer pin or the 4-bit parallel trace port.
A Flash Patch and Breakpoint (FPB) is included. The FPB can generate hardware breakpoints and remap specific addresses in code space to SRAM as a temporary method of altering non-volatile code. The FPB include 2 literal comparators and 6 instruction comparators. 8. On-chip flash memory system The LPC17xx contains up to 512 kB of on-chip flash memory. A new two-port flash memory accelerator maximizes performance for use with the two fast AHB-Lite buses. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. 9. On-chip Static RAM The LPC17xx contains up to 64 kB of on-chip static RAM memory. Up to 32 kB of SRAM, accessible by the CPU and all three DMA controllers are on a higher-speed bus. Devices containing more than 32 kB SRAM have two additional 16 kB SRAM blocks, each situated on separate slave ports on the AHB multilayer matrix. This architecture allows the possibility for CPU and DMA accesses to be separated in such a way that there are few or no delays for the bus masters.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 11 of 835 NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information 10. Block diagram Fig 2. LPC1768 block diagram, CPU and buses Multilayer AHB Matrix AHB to APB bridge AHB to APB bridge JTAG interface Debug Port Ethernet PHY interface SRAM 16 kB SRAM 16 kB EMULATION TRACE MODULE ARM Cortex-M3 TEST/DEBUG INTERFACE USB device, host, OTG USB interface DMA controller Ethernet MAC System bus D-code bus I-code bus DMAC regs USB regs Ethernet regs clock generation, power control, and other system functions SRAM 32 kB ROM 8 kB Flash 512 kB Flash Accelerator RST Xtalin Xtalout X32Kin X32Kout APB slave group 1 Note: shaded peripheral blocks support General Purpose DMA Capture/compare timers 2 & 3 I2C2 I2S UARTs 2 & 3 SSP0 External interrupts DAC System control Motor control PWM Quadrature encoder APB slave group 0 RTC Power Domain Real Time Clock SSP1 UARTs 0 & 1 CAN 1 & 2 I2C 0 & 1 SPI0 Capture/compare timers 0 & 1 Watchdog timer PWM1 12-bit ADC Pin connect block GPIO interrupt control 32 kHz oscillator Backup registers (20 bytes) Repetitive interrupt timer ultra-low power regulator Vbat voltage regulator clocks and controls internal power Vdd CLK OUT HS GPIO

Memory map and peripheral addressing

shows how this space is used on the LPC17xx. which is described later in this section. Table 3. LPC17xx memory usage and details 0x0000 0000 - 0x0007 FFFF For devices with 512 kB of flash memory. 0x0000 0000 - 0x0003 FFFF For devices with 256 kB of flash memory. 0x0000 0000 - 0x0001 FFFF For devices with 128 kB of flash memory. 0x0000 0000 - 0x0000 FFFF For devices with 64 kB of flash memory. 0x0000 0000 - 0x0000 7FFF For devices with 32 kB of flash memory. On-chip SRAM 0x1000 0000 - 0x1000 7FFF For devices with 32 kB of local SRAM. 0x1000 0000 - 0x1000 3FFF For devices with 16 kB of local SRAM. 0x1000 0000 - 0x1000 1FFF For devices with 8 kB of local SRAM. Boot ROM 0x1FFF 0000 - 0x1FFF 1FFF 8 kB Boot ROM with flash services. devices with 32 kB or 64 kB of total SRAM. devices with 64 kB of total SRAM.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 13 of 835 NXP Semiconductors UM10360 Chapter 2: LPC17xx Memory map Fig 3. LPC17xx system memory map 0x5000 0000 0x5000 4000 0x5000 8000 0x5000 C000 0x5020 0000AHB peripherals Ethernet controller USB controller reserved 127- 4 reserved GPDMA controller APB0 peripherals 0x4000 4000 0x4000 8000 0x4000 C000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4002 C000 0x4003 4000 0x4003 0000 0x4003 8000 0x4003 C000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 C000 0x4005 C000 0x4006 0000 0x4008 0000 0x4002 4000 0x4001 C000 0x4001 4000 0x4000 0000WDT TIMER0 TIMER1 UART0 UART1 reserved I2C0 SPI RTC + backup registers GPIO interrupts pin connect SSP1 ADC CAN AF RAM CAN AF registers CAN common CAN1 CAN2 22 - 19 reserved I2C1 31 - 24 reserved APB1 peripherals 0x4008 0000 0x4008 8000 0x4008 C000 0x4009 0000 0x4009 4000 0x4009 8000 0x4009 C000 0x400A 0000 0x400A 4000 0x400A 8000 0x400A C000 0x400B 0000 0x400B 4000 0x400B 8000 0x400B C000 0x400C 0000 0x400F C000 0x4010 0000 SSP0 DAC Timer 2 Timer 3 UART2 UART3 reserved I2S I2C2 1 - 0 reserved reserved repetitive interrupt timer reserved motor control PWM 30 - 16 reserved system control31 reserved reserved 32 kB local static RAM reserved reserved private peripheral bus 0x0000 00000 GB 0.5 GB 4 GB 1 GB 0x0008 0000 0x1000 0000 0x1000 8000 0x1FFF 0000 0x1FFF 2000 0x2007 C000 0x2008 4000 0x2009 C000 0x200A 0000 0x2200 0000 0x2400 0000 0x4000 0000 0x4008 0000 0x4010 0000 0x4200 0000 0x4400 0000 0x5000 0000 0x5020 0000 0xE000 0000 0xE010 0000 0xFFFF FFFF reserved reserved GPIO reserved reserved reserved reserved APB0 peripherals AHB periherals APB1 peripherals AHB SRAM bit band alias addressing peripheral bit band alias addressing AHB SRAM (2 blocks of 16 kB) LPC1768 memory space 512 kB on-chip flash QEI PWM1 8 kB boot ROM 0x0000 0000 0x0000 0100 active interrupt vectors + 256 byte I-code/D-code memory space

UM10360_1 © NXP B.V. 2010. All rights reserved. peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. simplifying the address decoding for each peripheral. example, it is not possible to read or write the upper byte of a word register separately. multiple locations within each 16 kB range. Table 4. APB0 peripherals and base addresses

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 16 of 835 NXP Semiconductors UM10360 Chapter 2: LPC17xx Memory map 6. Bus fault exceptions The LPC17xx generates Bus Fault exception if an access is attempted for an address that is in a reserved or unassigned address region. The regions are areas of the memory map that are not implemented for a specific derivative. These include all spaces marked “reserved” in Figure 2–3 For these areas, both attempted data access and instruction fetch generate an exception. In addition, a Bus Fault exception is generated for any instruction fetch that maps to an AHB or APB peripheral address. Within the address space of an existing APB peripheral, an exception is not generated in response to an access to an undefined address. Address decoding within each peripheral is limited to that needed to distinguish defined registers within the peripheral itself. For example, an access to address 0x4000 D000 (an undefined address within the UART0 space) may result in an access to the register defined at address 0x4000 C000. Details of such address aliasing within a peripheral space are not defined in the LPC17xx documentation and are not a supported feature. If software executes a write directly to the flash memory, the flash accelerator will generate a Bus Fault exception. Flash programming must be accomplished by using the specified flash programming interface provided by the Boot Code. Note that the Cortex-M3 core stores the exception flag along with the associated instruction in the pipeline and processes the exception only if an attempt is made to execute the instruction fetched from the disallowed address. This prevents accidental aborts that could be caused by prefetches that occur when code is executed very near a memory boundary.

Reset
Brown-Out Detection
External Interrupt Inputs
Miscellaneous System Controls and Status
Code Security vs. Debugging Each type of function has its own register(s) if any are required and unneeded bits are defined as reserved in order to allow future expansion. Unrelated functions never share the same register addresses 2. Pin description Table 3–6 shows pins that are associated with System Control block functions. UM10360 Chapter 3: LPC17xx System control Rev. 01 — 4 January 2010 User manual

Table 6. Pin summary the processor from Sleep, Deep-sleep, or Power-down modes. EINT1 Input External Interrupt Input 1 - See the EINT0 description above. EINT2 Input External Interrupt Input 2 - See the EINT0 description above. EINT3 Input External Interrupt Input 3 - See the EINT0 description above. begin execution at address 0x0000 0000.

UM10360_1 © NXP B.V. 2010. All rights reserved. appear in the description of each function. (POR), and Brown Out Detect (BOD). the following block diagram (see Figure 3–4). Table 7. Summary of system control registers

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 19 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control On the assertion of a reset source external to the Cortex-M3 CPU (POR, BOD reset, External reset, and Watchdog reset), the IRC starts up. After the IRC-start-up time (maximum of 60 μs on power-up) and after the IRC provides a stable clock output, the reset signal is latched and synchronized on the IRC clock. Then the following two sequences start simultaneously: 1. The 2-bit IRC wake-up timer starts counting when the synchronized reset is de-asserted. The boot code in the ROM starts when the 2-bit IRC wake-up timer times out. The boot code performs the boot tasks and may jump to the flash. If the flash is not ready to access, the Flash Accelerator will insert wait cycles until the flash is ready. 2. The flash wake-up timer (9-bit) starts counting when the synchronized reset is de-asserted. The flash wakeup-timer generates the 100 μs flash start-up time. Once it times out, the flash initialization sequence is started, which takes about 250 cycles. When it’s done, the Flash Accelerator will be granted access to the flash. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. Figure 3–5 shows an example of the relationship between the RESET, the IRC, and the processor status when the LPC17xx starts up after reset. See Section 4–3.2 “Main oscillator” for start-up of the main oscillator if selected by the user code. Fig 4. Reset block diagram including the wake-up timer C Q S APB read of PDBIT in PCON power-down C Q S FOSC to other blocks WAKE-UP TIMER watchdog reset external reset START COUNT 2 n internal RC oscillator Reset to the on-chip circuitry Reset to PCON.PD write “1” from APB reset EINT0 wake-up EINT1 wake-up EINT2 wake-up POR BOD EINT3 wake-up RTC wake-up BOD wake-up Ethernet MAC wake-up USB need_clk wake-up CAN wake-up GPIO0 port wake-up GPIO2 port wake-up

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 20 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control Fig 5. Example of start-up after reset valid threshold processor status VDD(REG)(3V3) IRC status RESET GND 60 μs 1 μs; IRC stability count boot time boot code executing user code boot code execution finishes; user code starts IRC starts IRC stable supply ramp-up time

4.1 Reset Source Identificati on Register (RSID - 0x400F C180)

Table 8. Reset Source Identification register (RSID - address 0x400F C180) bit description

0 POR Assertion of the POR signal sets this bit, and clears all of the other bits in

affected by any of the other sources of Reset. is not affected by WDT or BOD reset.

2 WDTR This bit is set when the Watchdog Timer times out and the WDTRESET bit

3 BODR This bit is set when the V

the BOD reset trip level and recovers, the BODR bit will be set to 1. is asserted (nominally 1 V), the BODR bit is cleared. above the BOD reset trip level, the BODR will be set to 1. This bit is not affected by External Reset nor Watchdog Reset. read from a reserved bit is not defined.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 22 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control 5. Brown-out detection The LPC17xx includes a Brown-Out Detector (BOD) that provides 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below the BOD interrupt trip level (typically 2.2 V under nominal room temperature conditions), the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading the Raw Interrupt Status Register. The second stage of low-voltage detection asserts Reset to inactivate the LPC17xx when the voltage on the VDD(REG)(3V3) pins falls below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). This Reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the Power-On Reset circuitry maintains the overall Reset. Both the BOD reset interrupt level and the BOD reset trip level thresholds include some hysteresis. In normal operation, this hysteresis allows the BOD reset interrupt level detection to reliably interrupt, or a regularly-executed event loop to sense the condition. But when Brown-Out Detection is enabled to bring the LPC17xx out of Power-down mode (which is itself not a guaranteed operation -- see Section 4–8.7 “ Power Mode Control register (PCON - 0x400F C0C0)”), the supply voltage may recover from a transient before the wake-up timer has completed its delay. In this case, the net result of the transient BOD is that the part wakes up and continues operation after the instructions that set Power-down mode, without any interrupt occurring and with the BOD bit in the RSID being 0. Since all other wake-up conditions have latching flags (see Section 3–6.2 “External Interrupt flag register (EXTINT - 0x400F C140)” and Section 27–6.2), a wake-up of this type, without any apparent cause, can be assumed to be a Brown-Out that has gone away.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 23 of 835 NXP Semiconductors UM10360 Chapter 3: LPC17xx System control 6. External interrupt inputs TheLPC17xx includes four External Interrupt Inputs as selectable pin functions. The logic of an individual external interrupt is represented in Figure 3–6. In addition, external interrupts have the ability to wake up the CPU from Power-down mode. Refer to Section 4–8.8 “Wake-up from Reduced Power Modes” for details. Fig 6. External interrupt logic R S Q D Q S GLITCH FILTER wakeup enable (one bit of EXTWAKE) APB Read of EXTWAKE EINTi to wakeup timer PCLK interrupt flag (one bit of EXTINT) APB read of EXTINT to VIC EINTi APB Bus Data EXTMODEi reset write 1 to EXTINTi EXTPOLARi R S Q PCLK D Q PCLK

6.1 Register description

and edge sensitivity parameters. [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

6.2 External Interrupt flag re gister (EXTINT - 0x400F C140)

cause an interrupt if interrupts from the pin are enabled. event that was just triggered by activity on the EINT pin will not be recognized in future. “External Interrupt Polarity register (EXTPOLAR - 0x400F C14C)”. Power-down mode will fail. The same goes for external interrupt handling. More details on Power-down mode will be discussed in the following chapters. Table 9. External Interrupt registers whether each pin is edge- or level-sensitive.

6.3 External Interrupt Mode re gister (EXTMODE - 0x400F C148)

pins selected for other functions may cause interrupts from those functions). Table 10. External Interrupt Flag register (EXTINT - address 0x400F C140) bit description

0 EINT0 In level-sensitive mode, this bit is set if the EINT0 function is selected for

1 EINT1 In level-sensitive mode, this bit is set if the EINT1 function is selected for

when the pin is in its active state.

2 EINT2 In level-sensitive mode, this bit is set if the EINT2 function is selected for

3 EINT3 In level-sensitive mode, this bit is set if the EINT3 function is selected for

read from a reserved bit is not defined.

6.4 External Interrupt Polarity register (EXTPOLAR - 0x400F C14C)

In level-sensitive mode, the bits in this register select whether the corresponding pin is high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or falling-edge sensitive. Only pins that are selected for the EINT function Only pins that are selected for the EINT function (see Section 8–5) and enabled in the appropriate NVIC register) can cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions). Note: Software should only change a bit in this register when its interrupt is disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could be set by changing the polarity and not having the EXTINT cleared. Table 11. External Interrupt Mode register (EXTMODE - address 0x400F C148) bit

description

Bit Symbol Value Description Reset value 0 EXTMODE0 0 Level-sensitivity is selected for EINT0 .0 1E I N T 0 is edge sensitive. 1 EXTMODE1 0 Level-sensitivity is selected for EINT1 .0 1E I N T 1 is edge sensitive. 2 EXTMODE2 0 Level-sensitivity is selected for EINT2 .0 1E I N T 2 is edge sensitive. 3 EXTMODE3 0 Level-sensitivity is selected for EINT3 .0 1E I N T 3 is edge sensitive. 31:4 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 12. External Interrupt Polarity re gister (EXTPOLAR - address 0x400F C14C) bit Bit Symbol Value Description Reset value

0 EXTPOLAR0 0 EINT0 is low-active or falling-edge sensitive (depending on

EXTMODE0). 1E I N T 0 is high-active or rising-edge sensitive (depending on EXTMODE0).

1 EXTPOLAR1 0 EINT1 is low-active or falling-edge sensitive (depending on

EXTMODE1). 1E I N T 1 is high-active or rising-edge sensitive (depending on EXTMODE1).

2 EXTPOLAR2 0 EINT2 is low-active or falling-edge sensitive (depending on

EXTMODE2). 1E I N T 2 is high-active or rising-edge sensitive (depending on EXTMODE2).

3 EXTPOLAR3 0 EINT3 is low-active or falling-edge sensitive (depending on

EXTMODE3). 1E I N T 3 is high-active or rising-edge sensitive (depending on EXTMODE3). 31:4 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Bit Symbol Value Description Reset value

Other system contro ls and status flags

7.1 System Controls and Status register (SCS - 0x400F C1A0)

accomplished by setting the OSCEN bit in the SCS register, as described in Table 3-13. OSCRANGE bit in the SCS register. Table 13. System Controls and Status regist er (SCS - address 0x400F C1A0) bit description

0 The frequency range of the main oscillator is 1 MHz

1 The frequency range of the main oscillator is

0 The main oscillator is disabled.

1 The main oscillator is enabled, and will start up if

0 The main oscillator is not ready to be used as a

1 The main oscillator is ready to be used as a clock

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 29 of 835 1. Summary of clocking an d power control functions This section describes the generation of the various clocks needed by the LPC17xx and options of clock source selection, as well as power control and wake-up from reduced power modes. Functions described in the following subsections include:

Oscillators
Clock source selection
PLLs
Clock dividers
APB dividers
Power control
Wake-up timer
External clock output UM10360 Chapter 4: LPC17xx Clocking and power control Rev. 01 — 4 January 2010 User manual Fig 7. Clock generation for the LPC17xx USB Clock Divider osc_clk irc_osc system clock select CLKSRCSEL[1:0] USB PLL settings (PLL1...) USB clock divider setting USBCLKCFG[3:0] PCLK_WDT Peripheral Clock Divider wd_clk usb_clk pclk1 pclk8 pclk4 pclk2 USB PLL (PLL1) main PLL settings (PLL0...) USB PLL select (PLL1CON) Main PLL (PLL0) CPU Clock Divider pllclk CPU PLL select (PLL0CON) cclk watchdog clock select WDCLKSEL[1:0] rtc_clk CPU clock divider setting CCLKCFG[7:0] sysclk

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 31 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 3. Oscillators The LPC17xx includes three independent oscillators. These are the Main Oscillator, the Internal RC Oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. This can be seen in Figure 4–7. Following Reset, the LPC17xx will operate from the Internal RC Oscillator until switched by software. This allows systems to operate without any external crystal, and allows the boot loader code to operate at a known frequency.

3.1 Internal RC oscillator

The Internal RC Oscillator (IRC) may be used as the clock source for the watchdog timer, and/or as the clock that drives PLL0 and subsequently the CPU. The precision of the IRC does not allow for use of the USB interface, which requires a much more precise time base in order to comply with the USB specification. Also, the IRC should not be used with the CAN1/2 block if the CAN baud rate is higher than 100 kbit/s.The nominal IRC frequency is 4 MHz. Upon power-up or any chip reset, the LPC17xx uses the IRC as the clock source. Software may later switch to one of the other available clock sources.

3.2 Main oscillator

The main oscillator can be used as the clock source for the CPU, with or without using PLL0. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the Main PLL (PLL0). The oscillator output is called OSC_CLK. The clock selected as the PLL0 input is PLLCLKIN and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc. elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL0 is active and connected. Refer to Section 4–5 “ PLL0 (Phase Locked Loop 0)” for details. The on-board oscillator in the LPC17xx can operate in one of two modes: slave mode and oscillation mode. In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (CC in Figure 4–8, drawing a), with an amplitude between 200 mVrms and 1000 mVrms. This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTAL2 pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 4–8, drawings b and c, and in Table 4–15 and Table 4–16. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 4–8, drawing c, represents the parallel package capacitance and should not be larger than 7 pF. Parameters FC, CL, RS and CP are supplied by the crystal manufacturer.

1 MHz - 5 MHz 10 pF < 300 Ω 18 pF, 18 pF

5 MHz - 10 MHz 10 pF < 300 Ω 18 pF, 18 pF

10 MHz - 15 MHz 10 pF < 160 Ω 18 pF, 18 pF

15 MHz - 20 MHz 10 pF < 80 Ω 18 pF, 18 pF

Table 16. Recommended values for C X1/X2 in oscillation mode (crystal and external

15 MHz - 20 MHz 10 pF < 180 Ω 18 pF, 18 pF

20 MHz - 25 MHz 10 pF < 160 Ω 18 pF, 18 pF

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 33 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control point, software can control switching to the main oscillator as a clock source. Prior to starting the main oscillator, a frequency range must be selected by configuring the OSCRANGE bit in the SCS register.

3.3 RTC oscillator

The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can be used as the clock source for PLL0 and CPU and/or the watchdog timer.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 34 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 4. Clock source selection multiplexer Several clock sources may be chosen to drive PLL0 and ultimately the CPU and on-chip peripheral devices. The clock sources available are the main oscillator, the RTC oscillator, and the Internal RC oscillator. The clock source selection can only be changed safely when PLL0 is not connected. For a detailed description of how to change the clock source in a system using PLL0 see Section 4–5.13 “PLL0 setup sequence”. Note the following restrictions regarding the choice of clock sources:

The IRC oscillator should not be used (via PLL0) as the clock source for the USB subsystem.
The IRC oscillator should not be used (via PLL0) as the clock source for the CAN controllers if the CAN baud rate is higher than 100 kbit/s.

4.1 Clock Source Select regist er (CLKSRCSEL - 0x400F C10C)

The CLKSRCSEL register contains the bits that select the clock source for PLL0. Table 17. Clock Source Select register (CLKSRCSEL - address 0x400F C10C) bit Bit Symbol Value Description Reset value 1:0 CLKSRC Selects the clock source for PLL0 as follows: 0

00 Selects the Internal RC oscillator as the PLL0 clock source

(default). 01 Selects the main oscillator as the PLL0 clock source. 10 Selects the RTC oscillator as the PLL0 clock source. 11 Reserved, do not use this setting. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device. 31:2 - 0 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 35 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 5. PLL0 (Phase Locked Loop 0) PLL0 accepts an input clock frequency in the range of 32 kHz to 50 MHz. The clock source is selected in the CLKSRCSEL register (see Section 4–4). The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU, peripherals, and optionally the USB subsystem. Note that the USB subsystem has its own dedicated PLL (see Section 4–6). PLL0 can produce a clock up to the maximum allowed for the CPU, which is 120 MHz on high speed versions (LPC1769 and LPC1759), and 100 MHz on other versions.

5.1 PLL0 operation

The PLL input, in the range of 32 kHZ to 50 MHz, may initially be divided down by a value "N", which may be in the range of 1 to 256. This input division provides a greater number of possibilities in providing a wide range of output frequencies from the same input frequency. Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value "M", in the range of 6 through 512, plus additional values listed in Table 4–21. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency. There are additional dividers at the output of PLL0 to bring the frequency down to what is needed for the CPU, peripherals, and potentially the USB subsystem. PLL0 output dividers are described in the Clock Dividers section following the PLL0 description. A block diagram of PLL0 is shown in Figure 4–9 PLL activation is controlled via the PLL0CON register. PLL0 multiplier and divider values are controlled by the PLL0CFG register. These two registers are protected in order to prevent accidental alteration of PLL0 parameters or deactivation of the PLL. Since all chip operations, including the Watchdog Timer, could be dependent on PLL0 if so configured (for example when it is providing the chip clock), accidental changes to the PLL0 setup values could result in unexpected or fatal behavior of the microcontroller. The protection is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are provided in the description of the PLL0FEED register. PLL0 is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL0 must be configured, enabled, and connected to the system by software. It is important that the setup procedure described in Section 4–5.13 “ PLL0 setup sequence” is followed or PLL0 might not operate at all!

5.1.1 PLL0 and startup/boot code interaction

When there is no valid user code (determined by the checksum word) in the user flash or the ISP enable pin (P2.10) is pulled low on startup, the ISP mode will be entered and the boot code will setup the PLL with the IRC. Therefore it can not be assumed that the PLL is disabled when the user opens a debug session to debug the application code. The user startup code must follow the steps described in this chapter to disconnect the PLL.

5.2 PLL0 register description

PLL0 is controlled by the registers shown in Table 4–18. More detailed descriptions follow. [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

5.3 PLL0 Control register (PLL0CON - 0x400F C080)

allows it to attempt to lock to the current settings of the multiplier and divider values. Table 18. PLL0 registers valid PLL0 feed sequence has taken place. the PLL0, as well as the PLL0 status.

5.4 PLL0 Configuration re gister (PLL0CFG - 0x400F C084)

“PLL0 frequency calculation”. Table 19. PLL Control register (PLL0CON - address 0x400F C080) bit description value read from a reserved bit is not defined. Table 20. PLL0 Configuration register (PLL0CFG - address 0x400F C084) bit description are 6 through 512 and those listed in Table 4–21. PLL0 frequency calculation”. value read from a reserved bit is not defined. 4–5.10 “PLL0 frequency calculation”. value read from a reserved bit is not defined.

5.5 PLL0 Status regist er (PLL0STAT - 0x400F C088)

5.6 PLL0 Interrupt: PLOCK0

PLOCK0 interrupt prior to exiting. Table 22. PLL Status register (PLL0STA T - address 0x400F C088) bit description used by PLL0, and is one less than the actual multiplier. 15 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. currently used by PLL0, and is one less than the actual divider. PLEC0 bit in PLL0CON (see Table 4–19) after a valid PLL0 feed. 26 PLOCK0 Reflects the PLL0 Lock status. When zero, PLL0 is not locked. 31:27 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

5.7 PLL0 Modes

The combinations of PLLE0 and PLLC0 are shown in Table 4–23.

5.8 PLL0 Feed register (PLL0FEED - 0x400F C08C)

Write the value 0xAA to PLL0FEED.
Write the value 0x55 to PLL0FEED.

access in the same address space (0x400F C000 to 0x400F FFFF) between them.

5.9 PLL0 and Power-down mode

at the same time, before PLL lock is established.

5.10 PLL0 frequency calculation

Table 23. PLL control bit combinations 0 0 PLL0 is turned off and disconnected. PLL0 outputs the unmodified clock input. 1 1 PLL0 is active and has been connected as the system clock source. Table 24. PLL Feed register (PLL0FEED - address 0x400F C08C) bit description PLL0 configuration and control register changes to take effect. value read from a reserved bit is not defined.

FIN is in the range of 32 kHz to 50 MHz.
FCCO is in the range of 275 MHz to 550 MHz. The equation can be solved for other PLL parameters: M = (FCCO × N) / (2 × FIN) N = (2 × M × FIN) / FCCO FIN = (FCCO × N) / (2 × M) Allowed values for M: At higher oscillator frequencies, in the MHz range, values of M from 6 through 512 are allowed. This supports the entire useful range of both the main oscillator and the IRC. For lower frequencies, specifically when the RTC is used to clock PLL0, a set of 65 additional M values have been selected for supporting baud rate generation, CAN/USB operation, and obtaining integer MHz frequencies. These values are shown in Table 4–26.

Table 25. PLL frequency parameter FIN the frequency of PLLCLKIN from the Clock Source Selection Multiplexer. NSEL0 field + 1). N is an integer from 1 through 32. MSEL0 field + 1). Not all potential values are supported. See below. FREF PLL internal reference frequency, FIN divided by N.

5.11 Procedure for determining PLL0 settings

Determine if the app lication requires use of the USB interface, and whether it will be

(i.e. an integer multiple of 96 MHz), within a very small tolerance.

Choose the desired processor operating frequency (CCLK). This may be based on

CCO result in lower power dissipation.

Choose a value for the PLL input frequency (F IN). This can be a clock obtained from

to clock the USB subsystem, this affects the choice of the main oscillator frequency.

Calculate values for M and N to produce a sufficiently accurate F CCO frequency. The

-1 will be written to the NSEL0 field in PLL0CFG. available from NXP for this purpose. Table 26. Additional Multiplier Values for use with a Low Frequency Clock Input

5.12 Examples of PLL0 settings

based on different system requirements.

The USB interface will not be used in the application, or will be clocked by PLL1.
The desired CPU rate is 100 MHz.
An external 10 MHz crystal or clock source will be used as the system clock source. Calculations: M = (FCCO × N) / (2 × FIN) A smaller value for the PLL pre-divide (N) as well as a smaller value of the multiplier (M), both result in better PLL operational stability and lower output jitter. Lower values of FCCO also save power. So, the process of determining PLL setup parameters involves looking for the smallest N and M values giving the lowest FCCO value that will support the required CPU and/or USB clocks. It is usually easier to work backward from the desired output clock rate and determine a target FCCO rate, then find a way to obtain that FCCO rate from the available input clock. Potential precise values of FCCO are integer multiples of the desired CPU clock. In this example, it is clear that the smallest frequency for FCCO that can produce the desired CPU clock rate and is within the PLL0 operating range of 275 to 550 MHz is 300 MHz (3 × 100 MHz). Assuming that the PLL pre-divide is 1 (N = 1), the equation above gives M = ((300 × 106 × 1) / (2 × 10 × 106) = 300 / 20 = 15. Since the result is an integer, there is no need to look any further for a good set of PLL0 configuration values. The value written to PLL0CFG would be 0x0E (N - 1 = 0; M - 1 = 14 gives 0x0E). The PLL output must be further divided in order to produce the CPU clock. This is accomplished using a separate divider that is described later in this chapter, see Section 4–7.1.

Table 27. Summary of PLL0 examples 1 • The PLL0 clock source is 10 MHz.

PLL0 is not used as the USB clock source, or the USB interface is not used.
The desired CPU clock is 100 MHz. 2 • The PLL0 clock source is 4 MHz.
PLL0 is used as the USB clock source.
The desired CPU clock is 60 MHz. 3 • The PLL0 clock source is the 32.768 kHz RTC clock.
PLL0 is not used as the USB clock source, or the USB interface is not used.
The desired CPU clock is 72 MHz.

The USB interface will be used in the application and will be clocked from PLL0.
The desired CPU rate is 60 MHz.
An external 4 MHz crystal or clock source will be used as the system clock source. This clock source could be the Internal RC oscillator (IRC). Calculations: M = (FCCO × N) / (2 × FIN) Because supporting USB requires a precise 48 MHz clock with a 50% duty cycle, that need must be addressed first. Potential precise values of FCCO are integer multiples of the 2 × the 48 MHz USB clock. The 2 × insures that the clock has a 50% duty cycle, which would not be the case for a division of the PLL output by an odd number. The possibilities for the FCCO rate when the USB is used are 288 MHz, 384 MHz, and 480 MHz. The smallest frequency for FCCO that can produce a valid USB clock rate and is within the PLL0 operating range is 288 MHz (3 × 2 × 48 MHz). Start by assuming N = 1, since this produces the smallest multiplier needed for PLL0. So, M = ((288 × 106) × 1) / (2 × (4 × 106)) = 288 / 8 = 36. The result is an integer, which is necessary to obtain a precise USB clock. The value written to PLL0CFG would be 0x23 The potential CPU clock rate can be determined by dividing FCCO by the desired CPU frequency: 288 × 106 /6 0 × 106 = 4.8. The nearest integer value for the CPU Clock Divider is then 5, giving us 57.6 MHz as the nearest value to the desired CPU clock rate. If it is important to obtain exactly 60 MHz, an FCCO rate must be found that can be divided down to both 48 MHz and 60 MHz. As previously noted, the possibilities for the FCCO rate when the USB is used are 288 MHz, 384 MHz, and 480 MHz. Of these, only is 480 MHz is also evenly divisible by 60. Divided by 10, this gives the 48 MHz with a 50% duty cycle needed by the USB subsystem. Divided by 8, it gives 60 MHz for the CPU clock. PLL0 settings for 480 MHz are N = 1 and M = 60. The PLL output must be further divided in order to produce both the CPU clock and the USB clock. This is accomplished using separate dividers that are described later in this chapter. See Section 4–7.1 and Section 4–7.2.

The USB interface will not be used in the application, or will be clocked by PLL1.
The desired CPU rate is 72 MHz
The 32.768 kHz RTC clock source will be used as the system clock source Calculations: M = (F CCO × N) / (2 × FIN) The smallest integer multiple of the desired CPU clock rate that is within the PLL0 operating range is 288 MHz (4 × 72 MHz). Using the equation above and assuming that N = 1, M = ((288× 106) × 1) / (2 × 32,768) = 4,394.53125. This is not an integer, so the CPU frequency will not be exactly 72 MHz with this setting. Since this example is less obvious, it may be useful to make a table of possibilities for different values of N (see below). Beyond N = 5, the value of M is out of range or not supported, so the table stops at that point. In the third column of the table, the calculated M value is rounded to the nearest integer. If this results in CCLK being above the maximum operating frequency, it is allowed if it is not more than 1/2 % above the maximum frequency. In general, larger values of FREF result in a more stable PLL when the input clock is a low frequency. Even the first table entry shows a very small error of just over 1 hundredth of a percent, or 107 parts per million (ppm). If that is not accurate enough in the application, the second case gives a much smaller error of 7 ppm. There are no allowed combinations that give a smaller error than that. Remember that when a frequency below about 1 MHz is used as the PLL0 clock source, not all multiplier values are available. As it turns out, all of the rounded M values found in Table 4–28 of this example are supported, which may be confirmed in Table 4–26. If PLL0 calculations suggest use of unsupported multiplier values, those values must be disregarded and other values examined to find the best fit. The value written to PLL0CFG for the second table entry would be 0x12254 (N - 1 = 1 = 0x1; M - 1 = 8788 = 0x2254). The PLL output must be further divided in order to produce the CPU clock. This is accomplished using a separate divider that is described later in this chapter, see Section 4–7.1.

Table 28. Potential values for PLL example

5.13 PLL0 setup sequence

The following sequence must be followed step by step in order to have PLL0 initialized and running: 1. Disconnect PLL0 with one feed se quence if PLL0 is already connected. 2. Disable PLL0 with one feed sequence. 3. Change the CPU Clock Divider setting to sp eed up operation without PLL0, if desired. 4. Write to the Clock Source Selection Control register to change the clock source if needed. 5. Write to the PLL0CFG and make it effe ctive with one feed sequence. The PLL0CFG can only be updated when PLL0 is disabled. 6. Enable PLL0 with one feed sequence. 7. Change the CPU Clock Divider setting for the operation with PLL0. It is critical to do this before connecting PLL0. 8. Wait for PLL0 to achieve lock by monitoring the PLOCK0 bit in the PLL0STAT register, or using the PLOCK0 interrupt, or wait for a fixed time when the input clock to PLL0 is slow (i.e. 32 kHz). The value of PLOCK0 may not be stable when the PLL reference frequency (FREF, the frequency of REFCLK, which is equal to the PLL input frequency divided by the pre-divider value) is less than 100 kHz or greater than 20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time has passed. This time is 500 µs when FREF is greater than 400 kHz and 200 / FREF seconds when FREF is less than 400 kHz. 9. Connect PLL0 with one feed sequence. It is very important not to merge any steps above. For example, do not update the PLL0CFG and enable PLL0 simultaneously with the same feed sequence.

PLL1 (Phase Locked Loop 1)

possibility of generating the USB clock from PLL0. selected to drive the USB subsystem (see Figure 4–7). provided in the description of the PLL1FEED register.

6.1 PLL1 register description

PLL1 is controlled by the registers shown in Table 4–29. More detailed descriptions follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic zero. Table 29. PLL1 registers

UM10360_1 © NXP B.V. 2010. All rights reserved. [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. valid PLL1 feed sequence has taken place. they will not reflect the current PL1L state. controlling PLL1, as well as PLL1 status.

6.2 PLL1 Control register (PLL1CON - 0x400F C0A0)

The PLL1CON register contains the bits that enable and connect PLL1. Enabling PLL1 allows it to attempt to lock to the current settings of the multiplier and divider values. Connecting PLL1 causes the USB subsystem to run from the PLL1 output clock. Changes to the PLL1CON register do not take effect until a correct PLL feed sequence has been given (see Section 4–6.6 and Section 4–6.3). Fig 10. PLL1 block diagram CD /2P CLOCK SYNCHRONIZATION PD CCLK PLLC PLOCK FOSC PLLE PHASE- FREQUENCY DETECTOR bypass MSEL[4:0] CD MSEL<4:0> FOUT DIV-BY-M CCO FCCO PSEL[1:0] direct 0 0 1PD PD

6.3 PLL1 Configuration regi ster (PLL1CFG - 0x400F C0A4)

values are found in Section 4–6.9.

6.4 PLL1 Status register (PLL1STAT - 0x400F C0A8)

Table 30. PLL1 Control register (PLL1CON - address 0x400F C0A0) bit description PLL1STAT register, Table 4–32. value read from a reserved bit is not defined. Table 31. PLL Configuration register (PLL1C FG - address 0x400F C0A4) bit description value read from a reserved bit is not defined.

6.4.1 PLL1 modes

The combinations of PLLE1 and PLLC1 are shown in Table 4–33.

6.5 PLL1 Interrupt: PLOCK1

PLL and continue with other functions without having to wait for the PLL to achieve lock. When the interrupt occurs, the PLL may be connected, and the interrupt disabled. disable the PLOCK1 interrupt prior to exiting. Table 32. PLL1 Status register (PLL1STAT - address 0x400F C0A8) bit description 7 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. cleared when Power-down mode is activated. 10 PLOCK1 Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency. 31:11 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Table 33. PLL1 control bit combinations 0 0 PLL1 is turned off and disconnected. connected without also being enabled.

6.6 PLL1 Feed register (PLL1FEED - 0x400F C0AC)

Write the value 0xAA to PLL1FEED.
Write the value 0x55 to PLL1FEED.

access in the same address space (0x400F C000 to 0x400F FFFF) between them.

6.7 PLL1 and Power-down mode

connect the PLL at the same time, before PLL lock is established. attempt to set the PD bit will fail, leaving the PLLs in the current state. Table 34. PLL1 Feed register (PLL1FEED - address 0x400F C0AC) bit description PLL1 configuration and control register changes to take effect. value read from a reserved bit is not defined.

6.8 PLL1 frequency calculation

FOSC is in the range of 10 MHz to 25 MHz.
USBCLK is 48 MHz.
FCCO is in the range of 156 MHz to 320 MHz.

6.9 Procedure for determining PLL1 settings

The desired PLL1 output frequency is USBCLK = 48 MHz.
Choose an oscillator frequency (F OSC). USBCLK must be the whole (non-fractional)
Calculate the value of M to configure the MSEL1 bits. M = USBCLK / F OSC. In this

value written to the MSEL1 bits in PLL1CFG is M − 1 (see Table 4–37).

Find a value for P to configure the PSEL1 bits, such that F CCO is within its defined

value written to the PSEL1 bits in PLL1CFG is ‘01’ for P = 2 (see Table 4–36). Table 35. Elements determining PLL frequency

UM10360_1 © NXP B.V. 2010. All rights reserved. Table 36. PLL1 Divider values Values allowed for using PLL1 with USB are highlighted. Table 37. PLL1 Multiplier values Values allowed for using PLL1 with USB are highlighted.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 55 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 7. Clock dividers The output of the PLL0 must be divided down for use by the CPU and the USB subsystem (if used with PLL0, see Section 4–6). Separate dividers are provided such that the CPU frequency can be determined independently from the USB subsystem, which always requires 48 MHz with a 50% duty cycle for proper operation.

7.1 CPU Clock Configuration regi ster (CCLKCFG - 0x400F C104)

The CCLKCFG register controls the division of the PLL0 output before it is used by the CPU. When PLL0 is bypassed, the division may be by 1. When PLL0 is running, the output must be divided in order to bring the CPU clock frequency (CCLK) within operating limits. An 8-bit divider allows a range of options, including slowing CPU operation to a low rate for temporary power savings without turning off PLL0. Note: when the USB interface is used in an application, CCLK must be at least 18 MHz in order to support internal operations of the USB subsystem. Fig 11. PLLs and clock dividers USB Clock Divider osc_clk USB PLL settings (PLL1...) USB clock divider setting USBCLKCFG[3:0] usb_clk USB PLL (PLL1) main PLL settings (PLL0...) USB PLL select (PLL1CON) Main PLL (PLL0) CPU Clock Divider pllclk CPU PLL select (PLL0CON) cclk CPU clock divider setting CCLKCFG[7:0] sysclk Table 38. CPU Clock Configuration register (CCLKCFG - address 0x400F C104) bit Bit Symbol Value Description Reset value 7:0 CCLKSEL Selects the divide value fo r creating the CPU clock (CCLK) from the PLL0 output. 0x00 0 to 1 Not allowed, the CPU clock will always be greater than 100 MHz. 2 PLL0 output is divided by 3 to produce the CPU clock. 3 PLL0 output is divided by 4 to produce the CPU clock. 4 PLL0 output is divided by 5 to produce the CPU clock. 255 PLL0 output is divided by 256 to produce the CPU clock. 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 56 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control The CCLK is derived from the PLL0 output signal, divided by CCLKSEL + 1. Having CCLKSEL = 1 results in CCLK being one half the PLL0 output, CCLKSEL = 3 results in CCLK being one quarter of the PLL0 output, etc.

7.2 USB Clock Configuration regi ster (USBCLKCFG - 0x400F C108)

This register is used only if the USB PLL (PLL1) is not connected (via the PLLC1 bit in PLL1CON). If PLL1 is connected, its output is automatically used as the USB clock source, and PLL1 must be configured to supply the correct 48 MHz clock to the USB subsystem. If PLL1 is not connected, the USB subsystem will be driven by PLL0 via the USB clock divider. The USBCLKCFG register controls the division of the PLL0 output before it is used by the USB subsystem.The PLL0 output must be divided in order to bring the USB clock frequency to 48 MHz with a 50% duty cycle. A 4-bit divider allows obtaining the correct USB clock from any even multiple of 48 MHz (i.e. any multiple of 96 MHz) within the PLL operating range. Remark: The Internal RC oscillator should not be used to drive PLL0 when the USB is using PLL0 as a clock source because a more precise clock is needed for USB specification compliance (see Table 4–17

7.3 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 -

0x400F C1A8 and PCLKSEL1 - 0x400F C1AC) A pair of bits in a Peripheral Clock Selection register controls the rate of the clock signal that will be supplied to the corresponding peripheral as specified in Table 4–40, Table 4–41 and Table 4–42. Remark: The peripheral clock for the RTC block is fixed at CCLK/8. Table 39. USB Clock Configuration register (USBCLKCFG - address 0x400F C108) bit Bit Symbol Value Description Reset value 3:0 USBSEL Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 PLL0 output is divided by 10. PLL0 output must be 480 MHz. 31:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 57 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control [1] PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used. Table 40. Peripheral Clock Se lection register 0 (PCLKSEL0 - address 0x400F C1A8) bit Bit Symbol Description Reset value 1:0 PCLK_WDT Peripheral clock selection for WDT. 00 3:2 PCLK_TIMER0 Peripheral clock selection for TIMER0. 00 5:4 PCLK_TIMER1 Peripheral clock selection for TIMER1. 00 7:6 PCLK_UART0 Peripheral clock selection for UART0. 00 9:8 PCLK_UART1 Peripheral clock selection for UART1. 00 11:10 - Reserved. NA 13:12 PCLK_PWM1 Peripheral clock selection for PWM1. 00 15:14 PCLK_I2C0 Peripheral clock selection for I 2C0. 00 17:16 PCLK_SPI Peripheral clock selection for SPI. 00 19:18 - Reserved. NA 21:20 PCLK_SSP1 Peripheral clock selection for SSP1. 00 23:22 PCLK_DAC Peripheral clock selection for DAC. 00 25:24 PCLK_ADC Peripheral clock selection for ADC. 00 27:26 PCLK_CAN1 Peripheral clock selection for CAN1. [1] 00 29:28 PCLK_CAN2 Peripheral clock selection for CAN2. [1] 00 31:30 PCLK_ACF Peripheral clock selection for CAN acceptance filtering. [1] 00 Table 41. Peripheral Clock Se lection register 1 (PCLKSEL1 - address 0x400F C1AC) bit Bit Symbol Description Reset value 1:0 PCLK_QEI Peripheral clock selection for the Quadrature Encoder Interface. 3:2 PCLK_GPIOINT Peripheral clock selection for GPIO interrupts. 00 5:4 PCLK_PCB Peripheral clock selection for the Pin Connect block. 00 7:6 PCLK_I2C1 Peripheral clock selection for I 2C1. 00 9:8 - Reserved. NA 11:10 PCLK_SSP0 Peripheral clock selection for SSP0. 00 13:12 PCLK_TIMER2 Peripheral clock selection for TIMER2. 00 15:14 PCLK_TIMER3 Peripheral clock selection for TIMER3. 00 17:16 PCLK_UART2 Peripheral clock selection for UART2. 00 19:18 PCLK_UART3 Peripheral clock selection for UART3. 00 21:20 PCLK_I2C2 Peripheral clock selection for I 2C2. 00 23:22 PCLK_I2S Peripheral clock selection for I 2S. 00 25:24 - Reserved. NA 27:26 PCLK_RIT Peripheral clock selection for Repetitive Interrupt Timer. 00 29:28 PCLK_SYSCON Peripheral clock select ion for the System Control block. 00 31:30 PCLK_MC Peripheral clock selection for the Motor Control PWM. 00

00 PCLK_peripheral = CCLK/4 00

01 PCLK_peripheral = CCLK

10 PCLK_peripheral = CCLK/2

11 PCLK_peripheral = CCLK/8, except for CAN1, CAN2, and

CAN filtering when “11” selects = CCLK/6.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 59 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 8. Power control The LPC17xx supports a variety of power control features: Sleep mode, Deep Sleep mode, Power-down mode, and Deep Power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, re-configuring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Entry to any reduced power mode begins with the execution of either a WFI (Wait For Interrupt) or WFE (Wait For Exception) instruction by the Cortex-M3. The Cortex-M3 internally supports two reduced power modes: Sleep and Deep Sleep. These are selected by the SLEEPDEEP bit in the cortex-M3 System Control Register. Power-down and Deep Power-down modes are selected by bits in the PCON register. See Table 4–44 . The same register contains flags that indicate whether entry into each reduced power mode actually occurred. The LPC17xx also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the Real Time Clock. Reduced power modes have some limitation during debug, see Section 33–5 for more information.

8.1 Sleep mode

Note: Sleep mode on the LPC17xx corresponds to the Idle mode on LPC2xxx series devices. The name is changed because ARM has incorporated portions of reduced power mode control into the Cortex-M3. LPC17xx documentation uses the Cortex-M3 terminology where applicable. When Sleep mode is entered, the clock to the core is stopped, and the SMFLAG bit in PCON is set, see Table 4–44.Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a Reset or an interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. Wake-up from Sleep mode will occur whenever any enabled interrupt occurs.

8.2 Deep Sleep mode

Note: Deep Sleep mode on the LPC17xx corresponds to the Sleep mode on LPC23xx and LPC24xx series devices. The name is changed because ARM has incorporated portions of reduced power mode control into the Cortex-M3. LPC17xx documentation uses the Cortex-M3 terminology where applicable. When the chip enters the Deep Sleep mode, the main oscillator is powered down, nearly all clocks are stopped, and the DSFLAG bit in PCON is set, see Table 4–44. The IRC remains running and can be configured to drive the Watchdog Timer, allowing the

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 60 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control Watchdog to wake up the CPU. The 32 kHz RTC oscillator is not stopped and RTC interrupts may be used as a wake-up source. The flash is left in the standby mode allowing a quick wake-up. The PLLs are automatically turned off and disconnected. The CCLK and USBCLK clock dividers automatically get reset to zero. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep Sleep mode and the logic levels of chip pins remain static. The Deep Sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep Sleep mode reduces chip power consumption to a very low value. On the wake-up of Deep Sleep mode, if the IRC was used before entering Deep Sleep mode, a 2-bit IRC timer starts counting and the code execution and peripherals activities will resume after the timer expires (4 cycles). If the main external oscillator was used, the 12-bit main oscillator timer starts counting and the code execution will resume when the timer expires (4096 cycles). The user must remember to re-configure any required PLLs and clock dividers after the wake-up. Wake-up from Deep Sleep mode can be brought about by NMI, External Interrupts EINT0 through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect, an RTC Alarm interrupt, a Watchdog Timer timeout, a USB input pin transition (USB activity interrupt), or a CAN input pin transition, when the related interrupt is enabled. Wake-up will occur whenever any enabled interrupt occurs.

8.3 Power-down mode

Power-down mode does everything that Deep Sleep mode does, but also turns off the flash memory. Entry to Power-down mode causes the PDFLAG bit in PCON to be set, see Table 4–44 . This saves more power, but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are stopped. The RTC remains running if it has been enabled and RTC interrupts may be used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are automatically turned off and disconnected. The CCLK and USBCLK clock dividers automatically get reset to zero. Upon wake-up from Power-down mode, if the IRC was used before entering Power-down mode, after IRC-start-up time (about 60 μs), the 2-bit IRC timer starts counting and expiring in 4 cycles. Code execution can then be resumed immediately following the expiration of the IRC timer if the code was running from SRAM. In the meantime, the flash wake-up timer measures flash start-up time of about 100 μs. When it times out, access to the flash is enabled. The user must remember to re-configure any required PLLs and clock dividers after the wake-up. Wake-up from Power-down mode can be brought about by NMI, External Interrupts EINT0 through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect, an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), or a CAN input pin transition, when the related interrupt is enabled.

8.4 Deep Power-down mode

Power-down mode causes the DPDFLAG bit in PCON to be set, see Table 4–44. applied, or the RTC interrupt is enabled and an RTC interrupt is generated.

8.5 Peripheral power control

detailed in the description of the PCONP register.

8.6 Register description

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. Table 43. Power Control registers

8.7 Power Mode Control re gister (PCON - 0x400F C0C0)

in the PCON register, as described in Table 4–44. [1] Only one of these flags will be valid at a specific time. [2] Hardware reset only for a power-up of core power or by a brownout detect event. [3] Hardware reset only for a power-up event on Vbat. Table 44. Power Mode Control register (PCON - address 0x400F C0C0) bit description mode. See Section 4–8.7.1 below for details. Power-down mode. See Section 4–8.7.1 below for details. a wake-up source from the reduced power mode will be lost. Power-down and Deep Sleep modes. circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. See the Section 3–5 for details of Brown-Out detection. value read from a reserved bit is not defined. entered. Cleared by software writing a one to this bit. entered. Cleared by software writing a one to this bit. successfully entered. Cleared by software writing a one to this bit. is successfully entered. Cleared by software writing a one to this bit. value read from a reserved bit is not defined.

8.7.1 Encoding of Reduced Power Modes

three reduced power modes supported by the LPC17xx.

8.8 Wake-up from Reduced Power Modes

wake up the processor if it is in either Deep Sleep mode or Power-down mode. reduced power mode. This can save time and power by avoiding an immediate wake-up. application specific setup, and exit to await a normal peripheral interrupt.

8.9 Power Control for Peripheral s register (PCONP - 0x400F C0C4)

the Pin Connect block, and the System Control block). saving features may be found in the chapter describing that peripheral. Table 45. Encoding of reduced power modes

00 Execution of WFI or WFE enters either Sleep or Deep Sleep mode as defined by the

SLEEPDEEP bit in the Cortex-M3 System Control Register.

01 Execution of WFI or WFE enters Power-down mode if the SLEEPDEEP bit in the

Cortex-M3 System Control Register is 1. 10 Reserved, this setting should not be used.

11 Execution of WFI or WFE enters Deep Power-down mode if the SLEEPDEEP bit in

the Cortex-M3 System Control Register is 1.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 64 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control Each bit in PCONP controls one peripheral as shown in Table 4–46. If a peripheral control bit is 1, that peripheral is enabled. If a peripheral control bit is 0, that peripheral’s clock is disabled (gated off) to conserve power. For example if bit 19 is 1, the I2C1 interface is enabled. If bit 19 is 0, the I2C1 interface is disabled. Important: valid read from a peripheral register and valid write to a peripheral register is possible only if that peripheral is enabled in the PCONP register! Table 46. Power Control for Peripherals re gister (PCONP - address 0x400F C0C4) bit Bit Symbol Description Reset value 0- R e s e r v e d . N A 1 PCTIM0 Timer/Counter 0 power/clock control bit. 1 2 PCTIM1 Timer/Counter 1 power/clock control bit. 1 3 PCUART0 UART0 power/clock control bit. 1 4 PCUART1 UART1 power/clock control bit. 1 5- R e s e r v e d . N A 6 PCPWM1 PWM1 power/clock control bit. 1 7 PCI2C0 The I 2C0 interface power/clock control bit. 1 8 PCSPI The SPI interface power/clock control bit. 1 9 PCRTC The RTC power/clock control bit. 1 10 PCSSP1 The SSP 1 interface power/clock control bit. 1 11 - Reserved. NA 12 PCADC A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN. 13 PCCAN1 CAN Controller 1 power/clock control bit. 0 14 PCCAN2 CAN Controller 2 power/clock control bit. 0 15 - Reserved. NA 16 PCRIT Repetitive Interrupt Timer power/clock control bit. 0

17 PCMCPWM Motor Control PWM 0

18 PCQEI Quadrature Encoder Interface power/clock control bit. 0 19 PCI2C1 The I 2C1 interface power/clock control bit. 1 20 - Reserved. NA 21 PCSSP0 The SSP0 interface power/clock control bit. 1 22 PCTIM2 Timer 2 power/clock control bit. 0 23 PCTIM3 Timer 3 power/clock control bit. 0 24 PCUART2 UART 2 power/clock control bit. 0 25 PCUART3 UART 3 power/clock control bit. 0 26 PCI2C2 I 2C interface 2 power/clock control bit. 1 27 PCI2S I 2S interface power/clock control bit. 0 28 - Reserved. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 65 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control Note that the DAC peripheral does not have a control bit in PCONP. To enable the DAC, its output must be selected to appear on the related pin, P0.26, by configuring the PINSEL1 register. See Section 8–5.2 “Pin Function Select Register 1 (PINSEL1 - 0x4002 C004)”.

8.10 Power control usage notes

After every reset, the PCONP register contains the value that enables selected interfaces and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper configuring via peripheral dedicated registers, the user’s application might have to access the PCONP in order to start using some of the on-board peripherals. Power saving oriented systems should have 1s in the PCONP register only in positions that match peripherals really used in the application. All other bits, declared to be "Reserved" or dedicated to the peripherals not used in the current application, must be cleared to 0.

8.11 Power domains

The LPC17xx provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the Real Time Clock. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. Whenever the device core power is present, that power is used to operate the RTC, causing no power drain from a battery when main power is available. 29 PCGPDMA GPDMA function power/clock control bit. 0 30 PCENET Ethernet block power/clock control bit. 0 31 PCUSB USB interface power/clock control bit. 0 Bit Symbol Description Reset value

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 66 of 835 NXP Semiconductors UM10360 Chapter 4: LPC17xx Clocking and power control 9. Wake-up timer The LPC17xx begins operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to begin quickly. If the main oscillator or one or both PLLs are needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power-on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer. The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of V DD(REG)(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. Once a clock is detected, the Wake-up Timer counts a fixed number of clocks (4,096), then sets the flag (OSCSTAT bit in the SCS register) that indicates that the main oscillator is ready for use. Software can then switch to the main oscillator and start any required PLLs. Refer to the Main Oscillator description in this chapter for details.

External clock output pin

brought out on the CLKOUT function available on the P1.27 pin, as shown in Figure 4–12.

10.1 Clock Output Confi guration register (CLKOUTCFG - 0x400F C1C8)

the ability of the pin to switch with reasonable logic levels. Table 47. Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description 0000 Selects the CPU clock as the CLKOUT source. 0001 Selects the main oscillator as the CLKOUT source.

0010 Selects the Internal RC oscillator as the CLKOUT source

0011 Selects the USB clock as the CLKOUT source. 0100 Selects the RTC oscillator as the CLKOUT source. others Reserved, do not use these settings.

8 CLKOUT_EN CLKOUT enable control, allows switching the CLKOUT

with the CLKOUT_EN bit below. bits. The value read from a reserved bit is not defined.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 69 of 835 1. Introduction The flash accelerator block in the LPC17xx allows maximization of the performance of the Cortex-M3 processor when it is running code from flash memory, while also saving power. The flash accelerator also provides speed and power improvements for data accesses to the flash memory. 2. Flash accelerator blocks The flash accelerator is divided into several functional blocks:

AHB-Lite bus interface, accessible by the Cortex-M3 I-code and D-code buses, as well as by the General Purpose DMA Controller
An array of eight 128-bit buffers
Flash accelerator control logic, including address compare and flash control
A flash memory interface Figure 5–13 shows a simplified diagram of the flash accelerator blocks and data paths. In the following descriptions, the term “fetch” applies to an explicit flash read request from the CPU. “Prefetch” is used to denote a flash read of instructions beyond the current processor fetch address.

2.1 Flash memory bank

There is one bank of flash memory controlled by the LPC17xx flash accelerator. Flash programming operations are not controlled by the flash accelerator, but are handled as a separate function. A Boot ROM contains flash programming algorithms that may be called as part of the application program, and a loader that may be run to allow programming of the flash memory. UM10360 Chapter 5: LPC17xx Flash accelerator Rev. 01 — 4 January 2010 User manual Fig 13. Simplified block diagram of the flash accelerator showing potential bus connections Flash Accelerator Control Flash Interface AHB-Lite bus interface Buffer Array Flash Memory Bus MatrixDCode bus ICode bus Cortex-M3 CPU General Purpose DMA Controller DMA Master Port Combined AHB Flash Accelerator

2.2 Flash programming Issues

cause a new fetch to be initiated after the flash operation has completed. [1] Reset Value reflects the data stored in defined bits only. It does not include reserved bits content. Table 48. Summary of flash accelerator registers FLASHCFG Flash Accelerator Configuration Register. Controls flash access timing. See Table 5–49.

Flash Accelerator Configuration register (FLASHCFG - 0x400F C000)

FLASHCFG control internal flash accelerator functions and should not be altered. guarantees synchronization of the flash accelerator to CPU operation. include four 32-bit instructions, eight 16-bit instructions or some combination of the two. to carry out the buffer replacement strategy. flash memory’s address space is presented to the flash accelerator. Table 49. Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000) bit description Warning: improper setting of this value may result in incorrect operation of the device. Important Note: Frequency values shown below are estimates at this time. 0000 Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock. 0001 Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock. 0010 Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock. 0011 Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock. 0100 Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only. 0101 Flash accesses use 6 CPU clocks. This “s afe” setting will work under any conditions. Other Intended for potential future higher speed devices.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 72 of 835 NXP Semiconductors UM10360 Chapter 5: LPC17xx Flash accelerator If a flash instruction fetch and a flash data access from the CPU occur at the same time, the multilayer matrix gives precedence to the data access. This is because a stalled data access always slows down execution, while a stalled instruction fetch often does not. When the flash data access is concluded, any flash fetch or prefetch that had been in progress is re-initiated. Branches and other program flow changes cause a break in the sequential flow of instruction fetches described above. Buffer replacement strategy in the flash accelerator attempts to maximize the chances that potentially reusable information is retained until it is needed again. If an attempt is made to write directly to the flash memory without using the normal flash programming interface (via Boot ROM function calls), the flash accelerator generates an error condition. The CPU treats this error as a data abort. The GPDMA handles error conditions as described in Section 31–4.1.6.3. When an Instruction Fetch is not satisfied by existing contents of the buffer array, nor has a prefetch been initiated for that flash line, the CPU will be stalled while a fetch is initiated for the related 128-bit flash line. If a prefetch has been initiated but not yet completed, the CPU is stalled for a shorter time since the required flash access is already in progress. Typically, a flash prefetch is begun whenever an access is made to a just prefetched address, or to a buffer whose immediate successor is not already in another buffer. A prefetch in progress may be aborted by a data access, in order to minimize CPU stalls. A prefetched flash line is latched within the flash memory, but the flash accelerator does not capture the line in a buffer until the CPU presents an address that is contained within the prefetched flash line. If the core presents an instruction address that is not already buffered and is not contained in the prefetched flash line, the prefetched line will be discarded. Some special cases include the possibility that the CPU will request a data access to an address already contained in an instruction buffer. In this case, the data will be read from the buffer as if it was a data buffer. The reverse case, if the CPU requests an instruction address that can be satisfied from an existing data buffer, causes the instruction to be supplied from the data buffer, and the buffer to be changed into an instruction buffer. This causes the buffer to be handled differently when the flash accelerator is determining which buffer is to be overwritten next.

Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3
Tightly coupled interrupt controller provides low interrupt latency
Controls system exceptions and peripheral interrupts
In the LPC17xx, the NVIC supports 35 vectored interrupts
32 programmable interrupt priority levels, with hardware priority level masking
Relocatable vector table
Non-Maskable Interrupt
Software interrupt generation 2. Description The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. Refer to the Cortex-M3 User Guide Section 34–4.2 for details of NVIC operation. 3. Interrupt sources Table 6–50 lists the interrupt sources for each peripheral function. Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may represent more than one interrupt source, as noted. Exception numbers relate to where entries are stored in the exception vector table. Interrupt numbers are used in some other contexts, such as software interrupts. In addition, the NVIC handles the Non-Maskable Interrupt (NMI). In order for NMI to operate from an external signal, the NMI function must be connected to the related device pin (P2.10 / EINT0n / NMI). When connected, a logic 1 on the pin will cause the NMI to be processed. For details, refer to the Cortex-M3 User Guide that is an appendix to this User Manual. UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) Rev. 01 — 4 January 2010 User manual

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 76 of 835 NXP Semiconductors UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) 4. Vector table remapping The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register (VTOR) contained in the Cortex-M3. The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table should be located on a 256 word (1024 byte) boundary to insure alignment on LPC17xx family devices. Refer to Section 34–4.3.5 of the Cortex-M3 User Guide appended to this manual for details of the Vector Table Offset feature. ARM describes bit 29 of the VTOR (TBLOFF) as selecting a memory region, either code or SRAM. For simplicity, this bit can be thought as simply part of the address offset since the split between the “code” space and the “SRAM” space occurs at the location corresponding to bit 29 in a memory address. Examples: To place the vector table at the beginning of the “local” static RAM, starting at address 0x1000 0000, place the value 0x1000 0000 in the VTOR register. This indicates address 0x1000 0000 in the code space, since bit 29 of the VTOR equals 0. To place the vector table at the beginning of the AHB static RAM, starting at address 0x2007 C000, place the value 0x2007 C000 in the VTOR register. This indicates address 0x2007 C000 in the SRAM space, since bit 29 of the VTOR equals 1.

UM10360_1 © NXP B.V. 2010. All rights reserved. The following table summarizes the registers in the NVIC as implemented in the LPC17xx. The Cortex-M3 User Guide Section 34–4.2 provides a functional description of the NVIC. Table 51. NVIC register map pending state for specific peripheral functions. interrupt pending state for specific peripheral functions. current interrupt active state for specific peripheral functions.

5.1 Interrupt Set-Enable Register 0 register (ISER0 - 0xE000 E100)

registers (Section 6–5.3 and Section 6–5.4). Table 52. Interrupt Set-Enable Regist er 0 register (ISER0 - 0xE000 E100) 0 ISE_WDT Watchdog Timer Interrupt Enable. Write: writing 0 has no effect, writing 1 enables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ISE_TIMER0 Timer 0 Interrupt Enable. See functional description for bit 0. 2 ISE_TIMER1 Timer 1. Interrupt Enable. See functional description for bit 0. 3 ISE_TIMER2 Timer 2 Interrupt Enable. See functional description for bit 0. 4 ISE_TIMER3 Timer 3 Interrupt Enable. See functional description for bit 0. 5 ISE_UART0 UART0 Interrupt Enable. See functional description for bit 0. 6 ISE_UART1 UART1 Interrupt Enable. See functional description for bit 0. 7 ISE_UART2 UART2 Interrupt Enable. See functional description for bit 0. 8 ISE_UART3 UART3 Interrupt Enable. See functional description for bit 0. 9 ISE_PWM PWM1 Interrupt Enable. See functional description for bit 0.

10 ISE_I2C0 I

2C0 Interrupt Enable. See functional description for bit 0. 11 ISE_I2C1 I 2C1 Interrupt Enable. See functional description for bit 0. 12 ISE_I2C2 I 2C2 Interrupt Enable. See functional description for bit 0. 13 ISE_SPI SPI Interrupt Enable. See functional description for bit 0. 14 ISE_SSP0 SSP0 Interrupt Enable. See functional description for bit 0. 15 ISE_SSP1 SSP1 Interrupt Enable. See functional description for bit 0. 16 ISE_PLL0 PLL0 (Main PLL) Interrupt Enable. See functional description for bit 0. 17 ISE_RTC Real Time Clock (RTC) Interrupt Enable. See functional description for bit 0. 18 ISE_EINT0 External Interrupt 0 Interrupt Enable. See functional description for bit 0. 19 ISE_EINT1 External Interrupt 1 Interrupt Enable. See functional description for bit 0. 20 ISE_EINT2 External Interrupt 2 Interrupt Enable. See functional description for bit 0. 21 ISE_EINT3 External Interrupt 3 Interrupt Enable. See functional description for bit 0. 22 ISE_ADC ADC Interrupt Enable. See functional description for bit 0. 23 ISE_BOD BOD Interrupt Enable. See functional description for bit 0. 24 ISE_USB USB Interrupt Enable. See functional description for bit 0. 25 ISE_CAN CAN Interrupt Enable. See functional description for bit 0. 26 ISE_DMA GPDMA Interrupt Enable. See functional description for bit 0.

27 ISE_I2S I

2S Interrupt Enable. See functional description for bit 0. 28 ISE_ENET Ethernet Interrupt Enable. See functional description for bit 0. 29 ISE_RIT Repetitive Interrupt Timer Interrupt Enable. See functional description for bit 0. 30 ISE_MCPWM Motor Control PWM Interrupt Enable. See functional description for bit 0. 31 ISE_QEI Quadrature Encoder Interface Interrupt Enable. See functional description for bit 0.

5.2 Interrupt Set-Enable Register 1 register (ISER1 - 0xE000 E104)

Table 53. Interrupt Set-Enable Regist er 1 register (ISER1 - 0xE000 E104) 0 ISE_PLL1 PLL1 (USB PLL) Interrupt Enable. Write: writing 0 has no effect, writing 1 enables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ISE_USBACT USB Activity Interrupt Enable. See functional description for bit 0. 2 ISE_CANACT CAN Activity Interrupt Enable. See functional description for bit 0.

5.3 Interrupt Clear-Enable Regi ster 0 (ICER0 - 0xE000 E180)

registers (Section 6–5.1 and Section 6–5.2). Table 54. Interrupt Clear-Enable Register 0 (ICER0 - 0xE000 E180) 0 ICE_WDT Watchdog Timer Interrupt Disable. Write: writing 0 has no effect, writing 1 disables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ICE_TIMER0 Timer 0 Interrupt Disable. See functional description for bit 0. 2 ICE_TIMER1 Timer 1. Interrupt Disable. See functional description for bit 0. 3 ICE_TIMER2 Timer 2 Interrupt Disable. See functional description for bit 0. 4 ICE_TIMER3 Timer 3 Interrupt Disable. See functional description for bit 0. 5 ICE_UART0 UART0 Interrupt Disable. See functional description for bit 0. 6 ICE_UART1 UART1 Interrupt Disable. See functional description for bit 0. 7 ICE_UART2 UART2 Interrupt Disable. See functional description for bit 0. 8 ICE_UART3 UART3 Interrupt Disable. See functional description for bit 0. 9 ICE_PWM PWM1 Interrupt Disable. See functional description for bit 0.

10 ICE_I2C0 I

2C0 Interrupt Disable. See functional description for bit 0. 11 ICE_I2C1 I 2C1 Interrupt Disable. See functional description for bit 0. 12 ICE_I2C2 I 2C2 Interrupt Disable. See functional description for bit 0. 13 ICE_SPI SPI Interrupt Disable. See functional description for bit 0. 14 ICE_SSP0 SSP0 Interrupt Disable. Se e functional description for bit 0. 15 ICE_SSP1 SSP1 Interrupt Disable. Se e functional description for bit 0. 16 ICE_PLL0 PLL0 (Main PLL) Interrupt Disable. See functional description for bit 0. 17 ICE_RTC Real Time Clock (RTC) Interrupt Disable. See functional description for bit 0. 18 ICE_EINT0 External Interrupt 0 Interrupt Disable. See functional description for bit 0. 19 ICE_EINT1 External Interrupt 1 Interrupt Disable. See functional description for bit 0. 20 ICE_EINT2 External Interrupt 2 Interrupt Disable. See functional description for bit 0. 21 ICE_EINT3 External Interrupt 3 Interrupt Disable. See functional description for bit 0. 22 ICE_ADC ADC Interrupt Disable. See functional description for bit 0. 23 ICE_BOD BOD Interrupt Disable. See functional description for bit 0. 24 ICE_USB USB Interrupt Disable. See functional description for bit 0. 25 ICE_CAN CAN Interrupt Disable. See functional description for bit 0. 26 ICE_DMA GPDMA Interrupt Disable. See functional description for bit 0.

27 ICE_I2S I

2S Interrupt Disable. See functional description for bit 0. 28 ICE_ENET Ethernet Interrupt Disable. See functional description for bit 0. 29 ICE_RIT Repetitive Interrupt Timer Interrupt Disable. See functional description for bit 0. 30 ICE_MCPWM Motor Control PWM Interrupt Disable. See functional description for bit 0. 31 ICE_QEI Quadrature Encoder Interface Interrupt Disable. See functional description for bit 0.

5.4 Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184)

Table 55. Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184) 0 ICE_PLL1 PLL1 (USB PLL) Interrupt Disable. Write: writing 0 has no effect, writing 1 disables the interrupt. Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ICE_USBACT USB Activity Interrupt Disable. See functional description for bit 0. 2 ICE_CANACT CAN Activity Interrupt Disable. See functional description for bit 0.

5.5 Interrupt Set-Pending Register 0 register (ISPR0 - 0xE000 E200)

Table 56. Interrupt Set-Pending Regist er 0 register (ISPR0 - 0xE000 E200) 0 ISP_WDT Watchdog Timer Interrupt Pending set. Write: writing 0 has no effect, writing 1 changes the interrupt state to pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 ISP_TIMER0 Timer 0 Interrupt Pending set. See functional description for bit 0. 2 ISP_TIMER1 Timer 1. Interrupt Pending set. See functional description for bit 0. 3 ISP_TIMER2 Timer 2 Interrupt Pending set. See functional description for bit 0. 4 ISP_TIMER3 Timer 3 Interrupt Pending set. See functional description for bit 0. 5 ISP_UART0 UART0 Interrupt Pending set. See functional description for bit 0. 6 ISP_UART1 UART1 Interrupt Pending set. See functional description for bit 0. 7 ISP_UART2 UART2 Interrupt Pending set. See functional description for bit 0. 8 ISP_UART3 UART3 Interrupt Pending set. See functional description for bit 0. 9 ISP_PWM PWM1 Interrupt Pending set. See functional description for bit 0.

10 ISP_I2C0 I

2C0 Interrupt Pending set. See functional description for bit 0. 11 ISP_I2C1 I 2C1 Interrupt Pending set. See functional description for bit 0. 12 ISP_I2C2 I 2C2 Interrupt Pending set. See functional description for bit 0. 13 ISP_SPI SPI Interrupt Pending set. See functional description for bit 0. 14 ISP_SSP0 SSP0 Interrupt Pending set. S ee functional description for bit 0. 15 ISP_SSP1 SSP1 Interrupt Pending set. S ee functional description for bit 0. 16 ISP_PLL0 PLL0 (Main PLL) Interrupt Pending set. See functional description for bit 0. 17 ISP_RTC Real Time Clock (RTC) Interrupt Pending set. See functional description for bit 0. 18 ISP_EINT0 External Interrupt 0 Interrupt Pending set. See functional description for bit 0. 19 ISP_EINT1 External Interrupt 1 Interrupt Pending set. See functional description for bit 0. 20 ISP_EINT2 External Interrupt 2 Interrupt Pending set. See functional description for bit 0. 21 ISP_EINT3 External Interrupt 3 Interrupt Pending set. See functional description for bit 0. 22 ISP_ADC ADC Interrupt Pending set. See functional description for bit 0. 23 ISP_BOD BOD Interrupt Pending set. See functional description for bit 0. 24 ISP_USB USB Interrupt Pending set. See functional description for bit 0. 25 ISP_CAN CAN Interrupt Pending set. See functional description for bit 0. 26 ISP_DMA GPDMA Interrupt Pending set. See functional description for bit 0.

27 ISP_I2S I

2S Interrupt Pending set. See functional description for bit 0. 28 ISP_ENET Ethernet Interrupt Pending set. See functional description for bit 0. 29 ISP_RIT Repetitive Interrupt Timer Interrupt Pending set. See functional description for bit 0. 30 ISP_MCPWM Motor Control PWM Interrupt Pending set. See functional description for bit 0. 31 ISP_QEI Quadrature Encoder Interface Interrupt Pending set. See functional description for bit 0.

5.6 Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204)

Table 57. Interrupt Set-Pending Regist er 1 register (ISPR1 - 0xE000 E204) 0 ISP_PLL1 PLL1 (USB PLL) Interrupt Pending set. Write: writing 0 has no effect, writing 1 changes the interrupt state to pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 ISP_USBACT USB Activity Interrupt Pending set. See functional description for bit 0. 2 ISP_CANACT CAN Activity Interrupt Pending set. See functional description for bit 0.

5.7 Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280)

Table 58. Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280) 0 ICP_WDT Watchdog Timer Interrupt Pending clear. Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 ICP_TIMER0 Timer 0 Interrupt Pending clear. See functional description for bit 0. 2 ICP_TIMER1 Timer 1. Interrupt Pending clear. See functional description for bit 0. 3 ICP_TIMER2 Timer 2 Interrupt Pending clear. See functional description for bit 0. 4 ICP_TIMER3 Timer 3 Interrupt Pending clear. See functional description for bit 0. 5 ICP_UART0 UART0 Interrupt Pending clear. See functional description for bit 0. 6 ICP_UART1 UART1 Interrupt Pending clear. See functional description for bit 0. 7 ICP_UART2 UART2 Interrupt Pending clear. See functional description for bit 0. 8 ICP_UART3 UART3 Interrupt Pending clear. See functional description for bit 0. 9 ICP_PWM PWM1 Interrupt Pending clear. See functional description for bit 0.

10 ICP_I2C0 I

2C0 Interrupt Pending clear. See functional description for bit 0. 11 ICP_I2C1 I 2C1 Interrupt Pending clear. See functional description for bit 0. 12 ICP_I2C2 I 2C2 Interrupt Pending clear. See functional description for bit 0. 13 ICP_SPI SPI Interrupt Pending clear. See functional description for bit 0. 14 ICP_SSP0 SSP0 Interrupt Pending clear. See functional description for bit 0. 15 ICP_SSP1 SSP1 Interrupt Pending clear. See functional description for bit 0. 16 ICP_PLL0 PLL0 (Main PLL) Interrupt Pending clear. See functional description for bit 0. 17 ICP_RTC Real Time Clock (RTC) Interrupt Pending clear. See functional description for bit 0. 18 ICP_EINT0 External Interrupt 0 Interrupt Pending clear. See functional description for bit 0. 19 ICP_EINT1 External Interrupt 1 Interrupt Pending clear. See functional description for bit 0. 20 ICP_EINT2 External Interrupt 2 Interrupt Pending clear. See functional description for bit 0. 21 ICP_EINT3 External Interrupt 3 Interrupt Pending clear. See functional description for bit 0. 22 ICP_ADC ADC Interrupt Pending clear. See functional description for bit 0. 23 ICP_BOD BOD Interrupt Pending clear. See functional description for bit 0. 24 ICP_USB USB Interrupt Pending clear. See functional description for bit 0. 25 ICP_CAN CAN Interrupt Pending clear. See functional description for bit 0. 26 ICP_DMA GPDMA Interrupt Pending clear. See functional description for bit 0.

27 ICP_I2S I

2S Interrupt Pending clear. See functional description for bit 0. 28 ICP_ENET Ethernet Interrupt Pending clear. See functional description for bit 0. 29 ICP_RIT Repetitive Interrupt Timer Interrupt Pending clear. See functional description for bit 0. 30 ICP_MCPWM Motor Control PWM Interrupt Pending clear. See functional description for bit 0. 31 ICP_QEI Quadrature Encoder Interface Interrupt Pending clear. See functional description for bit 0.

5.8 Interrupt Clear-Pending Register 1 register (ICPR1 - 0xE000 E284)

Table 59. Interrupt Set-Pending Regist er 1 register (ISPR1 - 0xE000 E204) 0 ICP_PLL1 PLL1 (USB PLL) Interrupt Pending clear. Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending. Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 ICP_USBACT USB Activity Interrupt Pending clear. See functional description for bit 0. 2 ICP_CANACT CAN Activity Interrupt Pending clear. See functional description for bit 0.

5.9 Interrupt Active Bit Regi ster 0 (IABR0 - 0xE000 E300)

interrupts can have their active state read via the IABR1 register (Section 6–5.10). Table 60. Interrupt Ac tive Bit Register 0 (IABR0 - 0xE000 E300) 0 IAB_WDT Watchdog Timer Interrupt Active. Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active. 1 IAB_TIMER0 Timer 0 Interrupt Active. See functional description for bit 0. 2 IAB_TIMER1 Timer 1. Interrupt Active. See functional description for bit 0. 3 IAB_TIMER2 Timer 2 Interrupt Active. See functional description for bit 0. 4 IAB_TIMER3 Timer 3 Interrupt Active. See functional description for bit 0. 5 IAB_UART0 UART0 Interrupt Active. See functional description for bit 0. 6 IAB_UART1 UART1 Interrupt Active. See functional description for bit 0. 7 IAB_UART2 UART2 Interrupt Active. See functional description for bit 0. 8 IAB_UART3 UART3 Interrupt Active. See functional description for bit 0. 9 IAB_PWM PWM1 Interrupt Active. See functional description for bit 0.

10 IAB_I2C0 I

2C0 Interrupt Active. See functional description for bit 0. 11 IAB_I2C1 I 2C1 Interrupt Active. See functional description for bit 0. 12 IAB_I2C2 I 2C2 Interrupt Active. See functional description for bit 0. 13 IAB_SPI SPI Interrupt Active. See functional description for bit 0. 14 IAB_SSP0 SSP0 Interrupt Active. See functional description for bit 0. 15 IAB_SSP1 SSP1 Interrupt Active. See functional description for bit 0. 16 IAB_PLL0 PLL0 (Main PLL) Interrupt Active. See functional description for bit 0. 17 IAB_RTC Real Time Clock (RTC) Interrupt Active. See functional description for bit 0. 18 IAB_EINT0 External Interrupt 0 Interrupt Active. See functional description for bit 0. 19 IAB_EINT1 External Interrupt 1 Interrupt Active. See functional description for bit 0. 20 IAB_EINT2 External Interrupt 2 Interrupt Active. See functional description for bit 0. 21 IAB_EINT3 External Interrupt 3 Interrupt Active. See functional description for bit 0. 22 IAB_ADC ADC Interrupt Active. See functional description for bit 0. 23 IAB_BOD BOD Interrupt Active. See functional description for bit 0. 24 IAB_USB USB Interrupt Active. See functional description for bit 0. 25 IAB_CAN CAN Interrupt Active. See functional description for bit 0. 26 IAB_DMA GPDMA Interrupt Active. See functional description for bit 0.

27 IAB_I2S I

2S Interrupt Active. See functional description for bit 0. 28 IAB_ENET Ethernet Interrupt Active. See functional description for bit 0. 29 IAB_RIT Repetitive Interrupt Timer Interrupt Active. See functional description for bit 0. 30 IAB_MCPWM Motor Control PWM Interrupt Active. See functional description for bit 0. 31 IAB_QEI Quadrature Encoder Interface Interrupt Active. See functional description for bit 0.

5.10 Interrupt Active Bit Regi ster 1 (IABR1 - 0xE000 E304)

asserting an interrupt to the NVIC, and may also be pending if there are enabled. Table 61. Interrupt Ac tive Bit Register 1 (IABR1 - 0xE000 E304) 0 IAB_PLL1 PLL1 (USB PLL) Interrupt Active. Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active. 1 IAB_USBACT USB Activity Interrupt Active . See functional description for bit 0. 2 IAB_CANACT CAN Activity Interrupt Active. See functional description for bit 0.

5.11 Interrupt Priority Regi ster 0 (IPR0 - 0xE000 E400)

have one of 32 priorities, where 0 is the highest priority.

5.12 Interrupt Priority Regi ster 1 (IPR1 - 0xE000 E404)

interrupt can have one of 32 priorities, where 0 is the highest priority.

5.13 Interrupt Priority Regi ster 2 (IPR2 - 0xE000 E408)

interrupt can have one of 32 priorities, where 0 is the highest priority. Table 62. Interrupt Priority Register 0 (IPR0 - 0xE000 E400) 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_WDT Watchdog Timer Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_TIMER0 Timer 0 Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_TIMER1 Timer 1 Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 31:27 IP_TIMER2 Timer 2 Interrupt Priority. See functional description for bits 7-3. Table 63. Interrupt Priority Register 1 (IPR1 - 0xE000 E404) 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_TIMER3 Timer 3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_UART0 UART0 Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_UART1 UART1 Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 31:27 IP_UART2 UART2 Interrupt Priority. See functional description for bits 7-3. Table 64. Interrupt Priority Register 2 (IPR2 - 0xE000 E408) 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_UART3 UART3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_PWM PWM Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 2C0 Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 2C1 Interrupt Priority. See functional description for bits 7-3.

5.14 Interrupt Priority Regi ster 3 (IPR3 - 0xE000 E40C)

interrupt can have one of 32 priorities, where 0 is the highest priority.

5.15 Interrupt Priority Regi ster 4 (IPR4 - 0xE000 E410)

interrupt can have one of 32 priorities, where 0 is the highest priority.

5.16 Interrupt Priority Regi ster 5 (IPR5 - 0xE000 E414)

interrupt can have one of 32 priorities, where 0 is the highest priority. Table 65. Interrupt Priority Register 3 (IPR3 - 0xE000 E40C) 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_I2C2 I 2C2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_SPI SPI Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_SSP0 SSP0 Interrupt Pr iority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 31:27 IP_SSP1 SSP1 Interrupt Pr iority. See functional description for bits 7-3. Table 66. Interrupt Priority Register 4 (IPR4 - 0xE000 E410) 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_PLL0 PLL0 (Main PLL) Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_RTC Real Time Clock (RTC) Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_EINT0 External Interrupt 0 Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 31:27 IP_EINT1 External Interrupt 1 Interrupt Priority. See functional description for bits 7-3. Table 67. Interrupt Priority Register 5 (IPR5 - 0xE000 E414) 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_EINT2 External Interrupt 2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_EINT3 External Interrupt 3 Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_ADC ADC Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 31:27 IP_BOD BOD Interrupt Priority. See functional description for bits 7-3.

5.17 Interrupt Priority Regi ster 6 (IPR6 - 0xE000 E418)

interrupt can have one of 32 priorities, where 0 is the highest priority.

5.18 Interrupt Priority Regi ster 7 (IPR7 - 0xE000 E41C)

interrupt can have one of 32 priorities, where 0 is the highest priority.

5.19 Interrupt Priority Regi ster 8 (IPR8 - 0xE000 E420)

The IPR8 register controls the priority of the ninth and last group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 68. Interrupt Priority Register 6 (IPR6 - 0xE000 E418) 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_USB USB Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_CAN CAN Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_DMA GPDMA Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 2S Interrupt Priority. See functional description for bits 7-3. Table 69. Interrupt Priority Register 7 (IPR7 - 0xE000 E41C) 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_ENET Ethernet Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_RIT Repetitive Interrupt Timer Interrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_MCPWM Motor Control PWM Interrupt Priority. See functional description for bits 7-3. 26:24 Unimplemented These bits ignore writes, and read as 0. 31:27 IP_QEI Quadrature Encoder Interface Interrupt Pr iority. See functional description for bits 7-3. Table 70. Interrupt Priority Register 8 (IPR8 - 0xE000 E420) 2:0 Unimplemented These bits ignore writes, and read as 0. 7:3 IP_PLL1 PLL1 (USB PLL) Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority. 10:8 Unimplemented These bits ignore writes, and read as 0. 15:11 IP_USBACT USB Activity Inte rrupt Priority. See functional description for bits 7-3. 18:16 Unimplemented These bits ignore writes, and read as 0. 23:19 IP_CANACT CAN Activity Interrupt Priority. See functional description for bits 7-3. 31:24 Unimplemented These bits ignore writes, and read as 0.

5.20 Software Trigger Interrupt Register (STIR - 0xE000 EF00)

peripheral interrupts, not system exceptions. register (see Section 34–4.3.8). Table 71. Software Trigger Interrup t Register (STIR - 0xE000 EF00) Table 6–50). The range allowed for the LPC17xx is 0 to 111.

1.1 LPC17xx pin description

I/O pins on the LPC17xx are 5V tolerant and have input hysteresis unless indicated in the table below. Crystal pins, power pins, and reference voltage pins are not 5V tolerant. In addition, when pins are selected to be A to D converter inputs, they are no longer 5V tolerant and must be limited to the voltage at the ADC positive reference pin (VREFP). UM10360 Chapter 7: LPC17xx Pin configuration Rev. 01 — 4 January 2010 User manual Fig 14. LPC176x LQFP100 pin configuration Fig 15. LPC175x LQFP80 pin configuration 100 002aad945_1 002aae158

UM10360_1 © NXP B.V. 2010. All rights reserved. Table 72. Pin description the pin connect block. Pins 12, 13, 14, and 31 of this port are not available. 46 37 I/O P0[0] — General purpose digital input/output pin. I RD1 — CAN1 receiver input. O TXD3 — Transmitter output for UART3. I2C-bus specification, see Section 19–4 for details). 47 38 I/O P0[1] — General purpose digital input/output pin. O TD1 — CAN1 transmitter output. I RXD3 — Receiver input for UART3. I2C-bus specification, see Section 19–4 for details). ADC input, digital section of the pad is disabled. O TXD0 — Transmitter output for UART0. I AD0[7] — A/D converter 0, input 7. ADC input, digital section of the pad is disabled. I RXD0 — Receiver input for UART0. I AD0[6] — A/D converter 0, input 6. 81 - I/O P0[4] — General purpose digital input/output pin. the slave. Corresponds to the signal SCK in the I2S bus specification. I RD2 — CAN2 receiver input. I CAP2[0] — Capture input for Timer 2, channel 0. P0[5] — General purpose digital input/output pin. O TD2 — CAN2 transmitter output. I CAP2[1] — Capture input for Timer 2, channel 1. 79 64 I/O P0[6] — General purpose digital input/output pin. the receiver. Corresponds to the signal SD in the I2S bus specification. I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0. 78 63 I/O P0[7] — General purpose digital input/output pin. the slave. Corresponds to the signal SCK in the I2S bus specification. I/O SCK1 — Serial Clock for SSP1. O MAT2[1] — Match output for Timer 2, channel 1.

UM10360_1 © NXP B.V. 2010. All rights reserved. 77 62 I/O P0[8] — General purpose digital input/output pin. I/O MISO1 — Master In Slave Out for SSP1. O MAT2[2] — Match output for Timer 2, channel 2. 76 61 I/O P0[9] — General purpose digital input/output pin. the receiver. Corresponds to the signal SD in the I2S bus specification. I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer 2, channel 3. P0[10] — General purpose digital input/output pin. O TXD2 — Transmitter output for UART2. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). O MAT3[0] — Match output for Timer 3, channel 0. P0[11] — General purpose digital input/output pin. I RXD2 — Receiver input for UART2. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer 3, channel 1. P0[15] — General purpose digital input/output pin. O TXD1 — Transmitter output for UART1. I/O SCK0 — Serial clock for SSP0. I/O SCK — Serial clock for SPI. P0[16] — General purpose digital input/output pin. I RXD1 — Receiver input for UART1. I/O SSEL0 — Slave Select for SSP0. I/O SSEL — Slave Select for SPI. P0[17] — General purpose digital input/output pin. I CTS1 — Clear to Send input for UART1. I/O MISO0 — Master In Slave Out for SSP0. I/O MISO — Master In Slave Out for SPI. P0[18] — General purpose digital input/output pin. I DCD1 — Data Carrier Detect input for UART1. I/O MOSI0 — Master Out Slave In for SSP0. I/O MOSI — Master Out Slave In for SPI. 59 - I/O P0[19] — General purpose digital input/output pin. I DSR1 — Data Set Ready input for UART1. I2C-bus specification, see Section 19–4 for details). Table 72. Pin description …continued

UM10360_1 © NXP B.V. 2010. All rights reserved. 58 - I/O P0[20] — General purpose digital input/output pin. to be an RS-485/EIA-485 output enable signal. I2C-bus specification, see Section 19–4 for details). P0[21] / RI1 / RD1 57 - I/O P0[21] — General purpose digital input/output pin. I RI1 — Ring Indicator input for UART1. I RD1 — CAN1 receiver input. P0[22] / RTS1 / TD1 56 44 I/O P0[22] — General purpose digital input/output pin. an RS-485/EIA-485 output enable signal. O TD1 — CAN1 transmitter output. ADC input, digital section of the pad is disabled. I AD0[0] — A/D converter 0, input 0. the slave. Corresponds to the signal SCK in the I2S bus specification. I CAP3[0] — Capture input for Timer 3, channel 0. ADC input, digital section of the pad is disabled. I AD0[1] — A/D converter 0, input 1. I CAP3[1] — Capture input for Timer 3, channel 1. ADC input, digital section of the pad is disabled. I AD0[2] — A/D converter 0, input 2. the receiver. Corresponds to the signal SD in the I2S bus specification. O TXD3 — Transmitter output for UART3. ADC input or DAC output, the digital section of the pad is disabled. I AD0[3] — A/D converter 0, input 3. O AOUT — D/A converter output. I RXD3 — Receiver input for UART3. I2C lines. Open-drain configuration applies to all functions on this pin. I/O USB_SDA — USB port I2C serial data (OTG transceiver).

UM10360_1 © NXP B.V. 2010. All rights reserved. I2C lines. Open-drain configuration applies to all functions on this pin. I/O USB_SCL — USB port I2C serial clock (OTG transceiver). specification, revision 2.0 (Full-speed and Low-speed mode only). I/O USB_D+ — USB bidirectional D+ line. specification, revision 2.0 (Full-speed and Low-speed mode only). I/O USB_D− — USB bidirectional D− line. 95 76 I/O P1[0] — General purpose digital input/output pin. O ENET_TXD0 — Ethernet transmit data 0. 94 75 I/O P1[1] — General purpose digital input/output pin. O ENET_TXD1 — Ethernet transmit data 1. 93 74 I/O P1[4] — General purpose digital input/output pin. O ENET_TX_EN — Ethernet transmit data enable. P1[8] — General purpose digital input/output pin. I ENET_CRS — Ethernet carrier sense. P1[9] — General purpose digital input/output pin. I ENET_RXD0 — Ethernet receive data. P1[10] — General purpose digital input/output pin. I ENET_RXD1 — Ethernet receive data. P1[14] — General purpose digital input/output pin. I ENET_RX_ER — Ethernet receive error. P1[15] — General purpose digital input/output pin. I ENET_REF_CLK — Ethernet reference clock. P1[16] — General purpose digital input/output pin. O ENET_MDC — Ethernet MIIM clock.

I/O P1[17] — General purpose digital input/output pin.

I/O ENET_MDIO — Ethernet MIIM data input and output.

UM10360_1 © NXP B.V. 2010. All rights reserved. 32 25 I/O P1[18] — General purpose digital input/output pin. not configured or during global suspend. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I CAP1[0] — Capture input for Timer 1, channel 0. 33 26 I/O P1[19] — General purpose digital input/output pin. O MCOA0 — Motor control PWM channel 0, output A. O USB_PPWR — Port Power enable signal for USB port. I CAP1[1] — Capture input for Timer 1, channel 1. P1[20] — General purpose digital input/output pin. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I/O SCK0 — Serial clock for SSP0. 35 - I/O P1[21] — General purpose digital input/output pin. O MCABORT — Motor control PWM, active low fast abort. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I/O SSEL0 — Slave Select for SSP0. 36 28 I/O P1[22] — General purpose digital input/output pin. O MCOB0 — Motor control PWM channel 0, output B. I USB_PWRD — Power Status for USB port (host power switch). O MAT1[0] — Match output for Timer 1, channel 0. 37 29 I/O P1[23] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. 38 30 I/O P1[24] — General purpose digital input/output pin. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I/O MOSI0 — Master Out Slave in for SSP0. P1[25] — General purpose digital input/output pin. O MCOA1 — Motor control PWM channel 1, output A. O MAT1[1] — Match output for Timer 1, channel 1. 40 32 I/O P1[26] — General purpose digital input/output pin. O MCOB1 — Motor control PWM channel 1, output B. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I CAP0[0] — Capture input for Timer 0, channel 0.

UM10360_1 © NXP B.V. 2010. All rights reserved. 43 - I/O P1[27] — General purpose digital input/output pin. O CLKOUT — Clock output pin. I USB_OVRCR — USB port Over-Current status. I CAP0[1] — Capture input for Timer 0, channel 1. P1[28] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A. I PCAP1[0] — Capture input for PWM1, channel 0. O MAT0[0] — Match output for Timer 0, channel 0. P1[29] — General purpose digital input/output pin. O MCOB2 — Motor control PWM channel 2, output B. I PCAP1[1] — Capture input for PWM1, channel 1. O MAT0[1] — Match output for Timer 0, channel 0. ADC input, digital section of the pad is disabled. I VBUS — Monitors the presence of USB bus power. Note: This signal must be HIGH for USB reset to occur. I AD0[4] — A/D converter 0, input 4. ADC input, digital section of the pad is disabled. I/O SCK1 — Serial Clock for SSP1. I AD0[5] — A/D converter 0, input 5. the pin connect block. Pins 14 through 31 of this port are not available. P2[0] — General purpose digital input/output pin. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. O TXD1 — Transmitter output for UART1. P2[1] — General purpose digital input/output pin. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I RXD1 — Receiver input for UART1. P2[2] — General purpose digital input/output pin. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I CTS1 — Clear to Send input for UART1. O TRACEDATA[3] — Trace data, bit 3. P2[3] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I DCD1 — Data Carrier Detect input for UART1. O TRACEDATA[2] — Trace data, bit 2.

UM10360_1 © NXP B.V. 2010. All rights reserved. 69 54 I/O P2[4] — General purpose digital input/output pin. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I DSR1 — Data Set Ready input for UART1. O TRACEDATA[1] — Trace data, bit 1. 68 53 I/O P2[5] — General purpose digital input/output pin. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. to be an RS-485/EIA-485 output enable signal. O TRACEDATA[0] — Trace data, bit 0. P2[6] — General purpose digital input/output pin. I PCAP1[0] — Capture input for PWM1, channel 0. I RI1 — Ring Indicator input for UART1. 66 51 I/O P2[7] — General purpose digital input/output pin. I RD2 — CAN2 receiver input. an RS-485/EIA-485 output enable signal. 65 50 I/O P2[8] — General purpose digital input/output pin. O TD2 — CAN2 transmitter output. O TXD2 — Transmitter output for UART2. O ENET_MDC — Ethernet MIIM clock. 64 49 I/O P2[9] — General purpose digital input/output pin. under software control. Used with the SoftConnect USB feature. I RXD2 — Receiver input for UART2. I/O ENET_MDIO — Ethernet MIIM data input and output. ns glitch filter providing digital I/O functions with TTL levels and hysteresis. I EINT0 — External interrupt 0 input. I NMI — Non-maskable interrupt input. ns glitch filter providing digital I/O functions with TTL levels and hysteresis. I EINT1 — External interrupt 1 input. the slave. Corresponds to the signal SCK in the I2S bus specification.

UM10360_1 © NXP B.V. 2010. All rights reserved. ns glitch filter providing digital I/O functions with TTL levels and hysteresis. I EINT2 — External interrupt 2 input. ns glitch filter providing digital I/O functions with TTL levels and hysteresis. I EINT3 — External interrupt 3 input. the receiver. Corresponds to the signal SD in the I2S bus specification. 27 - I/O P3[25] — General purpose digital input/output pin. O MAT0[0] — Match output for Timer 0, channel 0. O PWM1[2] — Pulse Width Modulator 1, output 2. 26 - I/O P3[26] — General purpose digital input/output pin. I STCLK — System tick timer clock input. O MAT0[1] — Match output for Timer 0, channel 1. O PWM1[3] — Pulse Width Modulator 1, output 3. 82 65 I/O P4[28] — General purpose digital input/output pin. I RX_MCLK — I2S receive master clock. O MAT2[0] — Match output for Timer 2, channel 0. O TXD3 — Transmitter output for UART3. 85 68 I/O P4[29] — General purpose digital input/output pin. I TX_MCLK — I2S transmit master clock. O MAT2[1] — Match output for Timer 2, channel 1. I RXD3 — Receiver input for UART3. T D O / S W O 11O TDO — Test Data out for JTAG interface. O SWO — Serial wire trace output. T D I 22I TDI — Test Data in for JTAG interface. TMS / SWDIO 3 3 I TMS — Test Mode Select for JTAG interface. I/O SWDIO — Serial wire debug data input/output. TRST 44I TRST — Test Reset for JTAG interface. TCK / SWDCLK 5 5 I TCK — Test Clock for JTAG interface. I SWDCLK — Serial wire clock. RTCK 100 - I/O RTCK — JTAG interface control signal.

UM10360_1 © NXP B.V. 2010. All rights reserved. [1] Pad provides special analog functionality. LPC17xx is in a Reset state. glitch filter, TTL levels and hysteresis. XTAL1 22[1] 19[1] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 23[1] 20[1] O Output from the oscillator amplifier. RTCX1 16[1] 13[1] I Input to the RTC oscillator circuit. RTCX2 18[1] 15[1] O Output from the RTC oscillator circuit. but should be isolated to minimize noise and error. on-chip voltage regulator only. to 3.3v if the ADC and DAC are not used. this pin should be tied to 3.3v if the ADC and DAC are not used. used as a reference for ADC and DAC.

UM10360_1 © NXP B.V. 2010. All rights reserved. Table 8–73 shows the functions of the PINSEL registers in the LPC17xx. between the pin and the on chip peripherals. not mapped to a related pin should be considered undefined. or used to contribute to the GPIO interrupt feature.

Pin function select register values

these registers correspond to specific device pins. Table 73. Summary of PINSEL registers Table 74. Pin function select register bits

00 Primary (default) function, typically GPIO port 00

01 First alternate function

10 Second alternate function

11 Third alternate function

UM10360_1 © NXP B.V. 2010. All rights reserved. for each pin. Details for a specific derivative may be found in the appropriate data sheet. one pin for some reason, the peripheral will receive its input from the lowest port number.

Pin mode select register values

for unused pins as in the PINSEL registers. indeterminate state) if it is temporarily not driven. the pin direction. This combination simulates an open drain output. Table 75. Pin Mode Select register Bits 01 Repeater mode (see text below). 10 Pin has neither pull-up nor pull-down resistor enabled. 11 Pin has an on-chip pull-down resistor enabled.

However, when the pin value is 1, PINMODE applies since this state turns off the pin’s

being pulled low by the pin’s own output. Table 76. Open Drain Pin Mo de Select register Bits 1 Pin is in the open drain mode.

UM10360_1 © NXP B.V. 2010. All rights reserved. The Pin Control Module contains 11 registers as shown in Table 8–77 below. [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. this module are reset to '0'. Table 77. Pin Connect Block Register Map

5.1 Pin Function Select regi ster 0 (PINSEL0 - 0x4002 C000)

pin. For other functions, the direction is controlled automatically. [1] Not available on 80-pin package.

5.2 Pin Function Select Regi ster 1 (PINSEL1 - 0x4002 C004)

a pin. For other functions the direction is controlled automatically. Table 78. Pin function select register 0 (P INSEL0 - address 0x4002 C000) bit description Table 79. Pin function select register 1 (P INSEL1 - address 0x4002 C004) bit description

5.3 Pin Function Select regi ster 2 (PINSEL2 - 0x4002 C008)

5.4 Pin Function Select Regist er 3 (PINSEL3 - 0x4002 C00C)

a pin. For other functions, direction is controlled automatically. Table 80. Pin function select register 2 (P INSEL2 - address 0x4002 C008) bit description Table 81. Pin function select register 3 (P INSEL3 - address 0x4002 C00C) bit description

5.5 Pin Function Select Regi ster 4 (PINSEL4 - 0x4002 C010)

a pin. For other functions, direction is controlled automatically. [1] Not available on 80-pin package. Table 82. Pin function select register 4 (P INSEL4 - address 0x4002 C010) bit description

5.6 Pin Function Select Regist er 7 (PINSEL7 - 0x4002 C01C)

a pin. For other functions, direction is controlled automatically. [1] Not available on 80-pin package.

5.7 Pin Function Select Regi ster 9 (PINSEL9 - 0x4002 C024)

a pin. For other functions, direction is controlled automatically.

5.8 Pin Function Select Regi ster 10 (PINSEL10 - 0x4002 C028)

Only bit 3 of this register is used to control the Trace function on pins P2.2 through P2.6. Table 83. Pin function select register 7 (P INSEL7 - address 0x4002 C01C) bit description Table 84. Pin function select register 9 (P INSEL9 - address 0x4002 C024) bit description Table 85. Pin function select register 10 (PINSEL10 - address 0x4002 C028) bit description 0 TPIU interface is disabled.

5.9 Pin Mode select regist er 0 (PINMODE0 - 0x4002 C040)

This register controls pull-up/pull-down resistor configuration for Port 0 pins 0 to 15. [1] Not available on 80-pin package.

5.10 Pin Mode select regist er 1 (PINMODE1 - 0x4002 C044)

details see Section 8–4 “Pin mode select register values”. Table 86. Pin Mode select register 0 (PINMODE0 - address 0x4002 C040) bit description 00 P0.0 pin has a pull-up resistor enabled. 01 P0.0 pin has repeater mode enabled. 10 P0.0 pin has neither pull-up nor pull-down. 11 P0.0 has a pull-down resistor enabled. Table 87. Pin Mode select register 1 (PINMODE1 - address 0x4002 C044) bit description

5.11 Pin Mode select regist er 2 (PINMODE2 - 0x4002 C048)

details see Section 8–4 “Pin mode select register values”.

5.12 Pin Mode select register 3 (PINMODE3 - 0x4002 C04C)

details see Section 8–4 “Pin mode select register values”. Table 88. Pin Mode select register 2 (PINMODE2 - address 0x4002 C048) bit description Table 89. Pin Mode select register 3 (PIN MODE3 - address 0x4002 C04C) bit description

5.13 Pin Mode select regist er 4 (PINMODE4 - 0x4002 C050)

details see Section 8–4 “Pin mode select register values”. [1] Not available on 80-pin package. Table 90. Pin Mode select register 4 (PINMODE4 - address 0x4002 C050) bit description

5.14 Pin Mode select register 7 (PINMODE7 - 0x4002 C05C)

This register controls pull-up/pull-down resistor configuration for Port 3 pins 16 to 31. For details see Section 8–4 “Pin mode select register values”. [1] Not available on 80-pin package.

5.15 Pin Mode select regist er 9 (PINMODE9 - 0x4002 C064)

This register controls pull-up/pull-down resistor configuration for Port 4 pins 16 to 31. For details see Section 8–4 “Pin mode select register values”.

5.16 Open Drain Pin Mode select re gister 0 (PINMODE_OD0 - 0x4002 C068)

This register controls the open drain mode for Port 0 pins. For details see Section 8–4 “Pin mode select register values”. Table 91. Pin Mode select register 7 (PIN MODE7 - address 0x4002 C05C) bit description Table 92. Pin Mode select register 9 (PINMODE9 - address 0x4002 C064) bit description Table 93. Open Drain Pin Mode select regist er 0 (PINMODE_OD0 - address 0x4002 C068) bit _OD0 Symbol Value Description Reset value 0 P0.00OD[3] Port 0 pin 0 open drain mode control. 0 0 P0.0 pin is in the normal (not open drain) mode. 1 P0.0 pin is in the open drain mode. 1 P0.01OD[3] Port 0 pin 1 open drain mode control, see P0.00OD 0 2 P0.02OD Port 0 pin 2 open drain mode control, see P0.00OD 0 3 P0.03OD Port 0 pin 3 open drain mode control, see P0.00OD 0 4 P0.04OD Port 0 pin 4 open drain mode control, see P0.00OD 0 5 P0.05OD Port 0 pin 5 open drain mode control, see P0.00OD 0 6 P0.06OD Port 0 pin 6 open drain mode control, see P0.00OD 0 7 P0.07OD Port 0 pin 7 open drain mode control, see P0.00OD 0 8 P0.08OD Port 0 pin 8 open drain mode control, see P0.00OD 0 9 P0.09OD Port 0 pin 9 open drain mode control, see P0.00OD 0

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 114 of 835 NXP Semiconductors UM10360 Chapter 8: LPC17xx Pin connect block [1] Not available on 80-pin package. [2] Port 0 pins 27 and 28 should be set up using t he I2CPADCFG register if they are used for an I2C-bus. Bits 27 and 28 of PINMODE_OD0 do not have any affect on these pins, they are special open drain I2C-bus compatible pins. [3] Port 0 bits 1:0, 11:10, and 20:19 may potentially be used for I 2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.

5.17 Open Drain Pin Mode select register 1 (PINMODE_OD1 -

0x4002 C06C) This register controls the open drain mode for Port 1 pins. For details see Section 8–4 “Pin mode select register values”. 10 P0.10OD [3] Port 0 pin 10 open drain mode control, see P0.00OD 0 11 P0.11OD [3] Port 0 pin 11 open drain mode control, see P0.00OD 0 14:12 - Reserved. NA 15 P0.15OD Port 0 pin 15 open drain mode control, see P0.00OD 0 16 P0.16OD Port 0 pin 16 open drain mode control, see P0.00OD 0 17 P0.17OD Port 0 pin 17 open drain mode control, see P0.00OD 0 18 P0.18OD Port 0 pin 18 open drain mode control, see P0.00OD 0 19 P0.19OD [3] Port 0 pin 19 open drain mode control, see P0.00OD 0 20 P0.20OD [3] Port 0 pin 20open drain mode control, see P0.00OD 0 21 P0.21OD Port 0 pin 21 open drain mode control, see P0.00OD 0 22 P0.22OD Port 0 pin 22 open drain mode control, see P0.00OD 0 23 P0.23OD Port 0 pin 23 open drain mode control, see P0.00OD 0 24 P0.24OD Port 0 pin 24open drain mode control, see P0.00OD 0 25 P0.25OD Port 0 pin 25 open drain mode control, see P0.00OD 0 26 P0.26OD Port 0 pin 26 open drain mode control, see P0.00OD 0 28:27 - [2] Reserved. NA 29 P0.29OD Port 0 pin 29 open drain mode control, see P0.00OD 0 30 P0.30OD Port 0 pin 30 open drain mode control, see P0.00OD 0 31 - Reserved. NA _OD0 Symbol Value Description Reset value Table 94. Open Drain Pin Mode select regist er 1 (PINMODE_OD1 - address 0x4002 C06C) bit _OD1 Symbol Value Description Reset value 0 P1.00OD Port 1 pin 0 open drain mode control. 0 0 P1.0 pin is in the normal (not open drain) mode. 1 P1.0 pin is in the open drain mode. 1 P1.01OD Port 1 pin 1 open drain mode control, see P1.00OD 0 3:2 - Reserved. NA 4 P1.04OD Port 1 pin 4 open drain mode control, see P1.00OD 0

5.18 Open Drain Pin Mode select re gister 2 (PINMODE_OD2 - 0x4002 C070)

This register controls the open drain mode for Port 2 pins. For details see Section 8–4 “Pin mode select register values”. 7:5 - Reserved. NA 8 P1.08OD Port 1 pin 8 open drain mode control, see P1.00OD 0 9 P1.09OD Port 1 pin 9 open drain mode control, see P1.00OD 0 10 P1.10OD Port 1 pin 10 open drain mode control, see P1.00OD 0 13:11 - Reserved. NA 14 P1.14OD Port 1 pin 14 open drain mode control, see P1.00OD 0 15 P1.15OD Port 1 pin 15 open drain mode control, see P1.00OD 0 16 P1.16OD [1] Port 1 pin 16 open drain mode control, see P1.00OD 0 17 P1.17OD [1] Port 1 pin 17 open drain mode control, see P1.00OD 0 18 P1.18OD Port 1 pin 18 open drain mode control, see P1.00OD 0 19 P1.19OD Port 1 pin 19 open drain mode control, see P1.00OD 0 20 P1.20OD Port 1 pin 20open drain mode control, see P1.00OD 0 21 P1.21OD [1] Port 1 pin 21 open drain mode control, see P1.00OD 0 22 P1.22OD Port 1 pin 22 open drain mode control, see P1.00OD 0 23 P1.23OD Port 1 pin 23 open drain mode control, see P1.00OD 0 24 P1.24OD Port 1 pin 24open drain mode control, see P1.00OD 0 25 P1.25OD Port 1 pin 25 open drain mode control, see P1.00OD 0 26 P1.26OD Port 1 pin 26 open drain mode control, see P1.00OD 0 27 P1.27OD [1] Port 1 pin 27 open drain mode control, see P1.00OD 0 28 P1.28OD Port 1 pin 28 open drain mode control, see P1.00OD 0 29 P1.29OD Port 1 pin 29 open drain mode control, see P1.00OD 0 30 P1.30OD Port 1 pin 30 open drain mode control, see P1.00OD 0 31 P1.31OD Port 1 pin 31 open drain mode control. 0 _OD1 Symbol Value Description Reset value Table 95. Open Drain Pin Mode select regist er 2 (PINMODE_OD2 - address 0x4002 C070) bit _OD2 Symbol Value Description Reset value 0 P2.00OD Port 2 pin 0 open drain mode control. 0 0 P2.0 pin is in the normal (not open drain) mode. 1 P2.0 pin is in the open drain mode. 1 P2.01OD Port 2 pin 1 open drain mode control, see P2.00OD 0 2 P2.02OD Port 2 pin 2 open drain mode control, see P2.00OD 0 3 P2.03OD Port 2 pin 3 open drain mode control, see P2.00OD 0 4 P2.04OD Port 2 pin 4 open drain mode control, see P2.00OD 0

5.19 Open Drain Pin Mode select re gister 3 (PINMODE_OD3 - 0x4002 C074)

This register controls the open drain mode for Port 3 pins. For details see Section 8–4 “Pin mode select register values”. [1] Not available on 80-pin package.

5.20 Open Drain Pin Mode select re gister 4 (PINMODE_OD4 - 0x4002 C078)

This register controls the open drain mode for Port 4 pins. For details see Section 8–4 “Pin mode select register values”. 5 P2.05OD Port 2 pin 5 open drain mode control, see P2.00OD 0 6 P2.06OD Port 2 pin 6 open drain mode control, see P2.00OD 0 7 P2.07OD Port 2 pin 7 open drain mode control, see P2.00OD 0 8 P2.08OD Port 2 pin 8 open drain mode control, see P2.00OD 0 9 P2.09OD Port 2 pin 9 open drain mode control, see P2.00OD 0 10 P2.10OD Port 2 pin 10 open drain mode control, see P2.00OD 0 11 P2.11OD [1] Port 2 pin 11 open drain mode control, see P2.00OD 0 12 P2.12OD [1] Port 2 pin 12 open drain mode control, see P2.00OD 0 13 P2.13OD [1] Port 2 pin 13 open drain mode control, see P2.00OD 0 31:14 - Reserved. NA _OD2 Symbol Value Description Reset value Table 96. Open Drain Pin Mode select regist er 3 (PINMODE_OD3 - address 0x4002 C074) bit _OD3 Symbol Value Description Reset value 24:0 - Reserved. NA 25 P3.25OD [1] Port 3 pin 0 open drain mode control. 0 0 P3.25 pin is in the normal (not open drain) mode. 1 P3.25 pin is in the open drain mode. 26 P3.26OD [1] Port 3 pin 26 open drain mode control, see P3.25OD 0 31:27 - Reserved. NA Table 97. Open Drain Pin Mode select regist er 4 (PINMODE_OD4 - address 0x4002 C078) bit _OD4 Symbol Value Description Reset value 27:0 - Reserved. NA

5.21 I 2C Pin Configuration register (I2CPADCFG - 0x4002 C07C)

The I2CPADCFG register allows configuration of the I2C pins for the I2C0 interface only, in order to support various I2C-bus operating modes. For use in standard or Fast Mode I2C, the 4 bits in I2CPADCFG should be 0, the default value for this register. For Fast Mode Plus, the SDADRV0 and SCLDRV0 bits should be 1. For non-I2C use of these pins, it may be desirable to turn off I2C filtering and slew rate control by setting SDAI2C0 and SCLI2C0 to 1. See Table 8–98 below. 28 P4.28OD Port 4 pin 28 open drain mode control. 0 0 P4.28 pin is in the normal (not open drain) mode. 1 P4.28 pin is in the open drain mode. 29 P4.28OD Port 4 pin 29 open drain mode control, see P4.28OD 0 31:30 - Reserved. NA _OD4 Symbol Value Description Reset value Table 98. I 2C Pin Configuration register (I2CPADCFG - address 0x4002 C07C) bit I2CPADCFG Symbol Value Description Reset value 0 SDADRV0 Drive mode control for the SDA0 pin, P0.27. 0 0 The SDA0 pin is in the standard drive mode. 1 The SDA0 pin is in Fast Mode Plus drive mode. 1 SDAI2C0 I2C mode control for the SDA0 pin, P0.27. 0

0 The SDA0 pin has I2C glitch filtering and slew rate

control enabled.

1 The SDA0 pin has I2C glitch filtering and slew rate

control disabled. 2 SCLDRV0 Drive mode control for the SCL0 pin, P0.28. 0 0 The SCL0 pin is in the standard drive mode. 1 The SCL0 pin is in Fast Mode Plus drive mode.

3 SCLI2C0

I2C mode control for the SCL0 pin, P0.28. 0

0 The SCL0 pin has I2C glitch filtering and slew rate

control enabled.

1 The SCL0 pin has I2C glitch filtering and slew rate

control disabled. 31:4 - Reserved. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 118 of 835 1. Basic configuration GPIOs are configured using the following registers: 1. Power: always enabled. 2. Pins: See Section 8–3 for GPIO pins and their modes. 3. Wake-up: GPIO ports 0 and 2 can be used for wake-up if needed, see (Section 4–8.8). 4. Interrupts: Enable GPIO interrupts in IO0/2IntEnR ( Table 9–113) or IO0/2IntEnF (Table 9–115). Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 2. Features

2.1 Digital I/O ports

Accelerated GPIO functions: – GPIO registers are located on a peripheral AHB bus for fast I/O timing. – Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. – All GPIO registers are byte, half-word, and word addressable. – Entire port value can be written in one instruction. – GPIO registers are accessible by the GPDMA.
Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port.
All GPIO registers support Cortex-M3 bit-banding.
GPIO registers are accessible by the GPDMA controller to allow DMA of data to or from GPIOs, synchronized to any DMA request.
Direction control of individual port bits.
All I/Os default to input with pullup after reset.

2.2 Interrupt generating digital ports

Port 0 and Port 2 can provide a single interrupt for any combination of port pins.
Each port pin can be programmed to generate an interrupt on a rising edge, a falling edge, or both.
Edge detection is asynchronous, so it may operate when clocks are not present, such as during Power-down mode. With this feature, level triggered interrupts are not needed.
Each enabled interrupt contributes to a wake-up signal that can be used to bring the part out of Power-down mode. UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Rev. 01 — 4 January 2010 User manual

Registers provide a software view of pending rising edge interrupts, pending falling edge interrupts, and overall pending GPIO interrupts.
GPIO0 and GPIO2 interrupts share the same position in the NVIC with External Interrupt 3. 3. Applications
General purpose I/O
Driving LEDs or other indicators
Controlling off-chip devices
Sensing digital inputs, detecting edges
Bringing the part out of Power-down mode 4. Pin description [1] P0[14:12] are not available. [2] P1[2], P1[3], P1[7:5], P1[13:11] are not available.

Table 99. GPIO pin description available in a particular device.

UM10360_1 © NXP B.V. 2010. All rights reserved. specific GPIO port usage can be found in Section 8–3. GPIO ports. These registers are located on an AHB bus for fast read and write timing. [1] Reset value reflects the data stored in used bits only. It does not include reserved bits content. Table 100. GPIO register map (local bus ac cessible registers - enhanced GPIO features) individually controls the direction of each port pin. register. Only bits enabled by 0 in FIOMASK can be altered. enabled by 0 in FIOMASK can be altered.

5.1 GPIO port Direction register F IOxDIR (FIO0DIR to FIO4DIR- 0x2009

additional registers allow easier and faster access to the physical port pins. Table 101. GPIO interrupt register map Table 102. Fast GPIO port Direction register FIO0DIR to FIO4DIR - addresses 0x2009 C000 to controls pin Px.0, bit 31 in FIOxDIR controls pin Px.31.

5.2 GPIO port output Set register FIOx SET (FIO0SET to FIO4SET - 0x2009

C018 to 0x2009 C098) This register is used to produce a HIGH level output at the port pins configured as GPIO in an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins. Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing 1 to the corresponding bit in the FIOxSET has no effect. Reading the FIOxSET register returns the value of this register, as determined by previous writes to FIOxSET and FIOxCLR (or FIOxPIN as noted above). This value does not reflect the effect of any outside world influence on the I/O pins. Table 103. Fast GPIO port Direction contro l byte and half-word accessible register length (bits) & access Reset value PORTn Register Address & Name FIOxDIR0 Fast GPIO Port x Direction control register 0. Bit 0 in FIOxDIR0 register corresponds to pin Px.0 … bit 7 to pin Px.7. 8 (byte) R/W 0x00 FIO0DIR0 - 0x2009 C000 FIO1DIR0 - 0x2009 C020 FIO2DIR0 - 0x2009 C040 FIO3DIR0 - 0x2009 C060 FIO4DIR0 - 0x2009 C080 FIOxDIR1 Fast GPIO Port x Direction control register 1. Bit 0 in FIOxDIR1 register corresponds to pin Px.8 … bit 7 to pin Px.15. 8 (byte) R/W 0x00 FIO0DIR1 - 0x2009 C001 FIO1DIR1 - 0x2009 C021 FIO2DIR1 - 0x2009 C041 FIO3DIR1 - 0x2009 C061 FIO4DIR1 - 0x2009 C081 FIO0DIR2 Fast GPIO Port x Direction control register 2. Bit 0 in FIOxDIR2 register corresponds to pin Px.16 … bit 7 to pin Px.23. 8 (byte) R/W 0x00 FIO0DIR2 - 0x2009 C002 FIO1DIR2 - 0x2009 C022 FIO2DIR2 - 0x2009 C042 FIO3DIR2 - 0x2009 C062 FIO4DIR2 - 0x2009 C082 FIOxDIR3 Fast GPIO Port x Direction control register 3. Bit 0 in FIOxDIR3 register corresponds to pin Px.24 … bit 7 to pin Px.31. 8 (byte) R/W 0x00 FIO0DIR3 - 0x2009 C003 FIO1DIR3 - 0x2009 C023 FIO2DIR3 - 0x2009 C043 FIO3DIR3 - 0x2009 C063 FIO4DIR3 - 0x2009 C083 FIOxDIRL Fast GPIO Port x Direction control Lower half-word register. Bit 0 in FIOxDIRL register corresponds to pin Px.0 … bit 15 to pin Px.15. 16 (half-word) R/W 0x0000 FIO0DIRL - 0x2009 C000 FIO1DIRL - 0x2009 C020 FIO2DIRL - 0x2009 C040 FIO3DIRL - 0x2009 C060 FIO4DIRL - 0x2009 C080 FIOxDIRU Fast GPIO Port x Direction control Upper half-word register. Bit 0 in FIOxDIRU register corresponds to Px.16 … bit 15 to Px.31. 16 (half-word) R/W 0x0000 FIO0DIRU - 0x2009 C002 FIO1DIRU - 0x2009 C022 FIO2DIRU - 0x2009 C042 FIO3DIRU - 0x2009 C062 FIO4DIRU - 0x2009 C082

UM10360_1 © NXP B.V. 2010. All rights reserved. the FIOxMASK register (see Section 9–5.5). additional registers allow easier and faster access to the physical port pins. Table 104. Fast GPIO port output Set register (FIO0SET to FIO4SET - addresses 0x2009 C018 Px.0, bit 31 in FIOxSET controls pin Px.31. 0 Controlled pin output is unchanged. 1 Controlled pin output is set to HIGH. Table 105. Fast GPIO port output Set byte and half-word accessible register description

5.3 GPIO port output Clear register FIOxCLR (FIO0CLR to FIO4CLR-

configured as an input or a secondary function, writing to FIOxCLR has no effect. the FIOxMASK register (see Section 9–5.5). additional registers allow easier and faster access to the physical port pins. Table 106. Fast GPIO port output Clear register (FIO0CLR to FIO4CLR- addresses 0x2009 Px.0, bit 31 controls pin Px.31. 0 Controlled pin output is unchanged. 1 Controlled pin output is set to LOW. Table 107. Fast GPIO port output Clear byte and half-word accessible register description

5.4 GPIO port Pin value register FI OxPIN (FIO0PIN to FIO4PIN- 0x2009

read from the corresponding FIOxPIN register. features of the pin. In that case, the pin value read in the FIOxPIN register is not valid. need to use both the FIOxSET and FIOxCLR registers to obtain the entire written value. This feature should be used carefully in an application since it affects the entire port. the current content of the Fast GPIO port pin value register. Table 108. Fast GPIO port Pin value register (FIO0PIN to FIO4PIN- addresses 0x2009 C014 to to pin Px.0, bit 31 in FIOxCLR corresponds to pin Px.31. 0 Controlled pin output is set to LOW. 1 Controlled pin output is set to HIGH.

5.5 Fast GPIO port Mask re gister FIOxMASK (FIO0MASK to FIO4MASK -

when the FIOxPIN register is read. Table 109. Fast GPIO port Pin value byte an d half-word accessible register description

UM10360_1 © NXP B.V. 2010. All rights reserved. software examples, see Section 9–6. additional registers allow easier and faster access to the physical port pins. Table 110. Fast GPIO port Mask register (FIO0MASK to FIO4MASK - addresses 0x2009 C010

0 Controlled pin is affected by writes to the port’s FIOxSET,

can be read from the FIOxPIN register.

1 Controlled pin is not affected by writes into the port’s

Table 111. Fast GPIO port Mask byte and half-word accessible register description

5.6 GPIO interrupt registers

The following registers configure the pins of Port 0 and Port 2 to generate interrupts.

5.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0x4002 8080)

This read-only register indicates the presence of interrupt pending on all of the GPIO ports that support GPIO interrupts. Only status one bit per port is required.

5.6.2 GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090)

Each bit in these read-write registers enables the rising edge interrupt for the corresponding port 0 pin. Table 112. GPIO overall Interrupt Status regist er (IOIntStatus - address 0x4002 8080) bit Bit Symbol Value Description Reset value 0 P0Int Port 0 GPIO interrupt pending. 0 0 There are no pending interrupts on Port 0. 1 There is at least one pending interrupt on Port 0. 1 - - Reserved. The value read from a reserved bit is not defined. NA 2 P2Int Port 2 GPIO interrupt pending. 0 0 There are no pending interrupts on Port 2. 1 There is at least one pending interrupt on Port 2. 31:2 - - Reserved. The value read from a reserved bit is not defined. NA Table 113. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit Bit Symbol Value Description Reset value 0 P0.0ER Enable rising edge interrupt for P0.0. 0 0 Rising edge interrupt is disabled on P0.0. 1 Rising edge interrupt is enabled on P0.0. 1 P0.1ER Enable rising edge interrupt for P0.1. 0 2 P0.2ER Enable rising edge interrupt for P0.2. 0 3 P0.3ER Enable rising edge interrupt for P0.3. 0 4 P0.4ER [1] Enable rising edge interrupt for P0.4. 0 5 P0.5ER [1] Enable rising edge interrupt for P0.5. 0 6 P0.6ER Enable rising edge interrupt for P0.6. 0 7 P0.7ER Enable rising edge interrupt for P0.7. 0 8 P0.8ER Enable rising edge interrupt for P0.8. 0 9 P0.9ER Enable rising edge interrupt for P0.9. 0 10 P0.10ER Enable rising edge interrupt for P0.10. 0 11 P0.11ER Enable rising edge interrupt for P0.11. 0 14:12 - Reserved NA 15 P0.15ER Enable rising edge interrupt for P0.15. 0 16 P0.16ER Enable rising edge interrupt for P0.16. 0

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 130 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) [1] Not available on 80-pin package.

5.6.3 GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0)

Each bit in these read-write registers enables the rising edge interrupt for the corresponding port 2 pin. 17 P0.17ER Enable rising edge interrupt for P0.17. 0 18 P0.18ER Enable rising edge interrupt for P0.18. 0 19 P0.19ER [1] Enable rising edge interrupt for P0.19. 0 20 P0.20ER [1] Enable rising edge interrupt for P0.20. 0 21 P0.21ER [1] Enable rising edge interrupt for P0.21. 0 22 P0.22ER Enable rising edge interrupt for P0.22. 0 23 P0.23ER [1] Enable rising edge interrupt for P0.23. 0 24 P0.24ER [1] Enable rising edge interrupt for P0.24. 0 25 P0.25ER Enable rising edge interrupt for P0.25. 0 26 P0.26ER Enable rising edge interrupt for P0.26. 0 27 P0.27ER [1] Enable rising edge interrupt for P0.27. 0 28 P0.28ER [1] Enable rising edge interrupt for P0.28. 0 29 P0.29ER Enable rising edge interrupt for P0.29. 0 30 P0.30ER Enable rising edge interrupt for P0.30. 0 31 - Reserved. NA Bit Symbol Value Description Reset value Table 114. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit Bit Symbol Value Description Reset value 0 P2.0ER Enable rising edge interrupt for P2.0. 0 0 Rising edge interrupt is disabled on P2.0. 1 Rising edge interrupt is enabled on P2.0. 1 P2.1ER Enable rising edge interrupt for P2.1. 0 2 P2.2ER Enable rising edge interrupt for P2.2. 0 3 P2.3ER Enable rising edge interrupt for P2.3. 0 4 P2.4ER Enable rising edge interrupt for P2.4. 0 5 P2.5ER Enable rising edge interrupt for P2.5. 0 6 P2.6ER Enable rising edge interrupt for P2.6. 0 7 P2.7ER Enable rising edge interrupt for P2.7. 0 8 P2.8ER Enable rising edge interrupt for P2.8. 0 9 P2.9ER Enable rising edge interrupt for P2.9. 0 10 P2.10ER Enable rising edge interrupt for P2.10. 0 11 P2.11ER [1] Enable rising edge interrupt for P2.11. 0

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 131 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) [1] Not available on 80-pin package.

5.6.4 GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - 0x4002 8094)

Each bit in these read-write registers enables the falling edge interrupt for the corresponding GPIO port 0 pin. 12 P2.12ER [1] Enable rising edge interrupt for P2.12. 0 13 P2.13ER [1] Enable rising edge interrupt for P2.13. 0 31:14 - Reserved. NA Bit Symbol Value Description Reset value Table 115. GPIO Interrupt Enable for port 0 Fa lling Edge (IO0IntEnF - address 0x4002 8094) 0 Falling edge interrupt is disabled on P0.0. 1 Falling edge interrupt is enabled on P0.0.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 132 of 835 NXP Semiconductors UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) [1] Not available on 80-pin package.

5.6.5 GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4)

Each bit in these read-write registers enables the falling edge interrupt for the corresponding GPIO port 2 pin. [1] Not available on 80-pin package. 28 P0.28EF [1] Enable falling edge interrupt for P0.28. 0 29 P0.29EF Enable falling edge interrupt for P0.29. 0 30 P0.30EF Enable falling edge interrupt for P0.30. 0 31 - Reserved. NA Table 116. GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4) bit Bit Symbol Value Description Reset value 0 P2.0EF Enable falling edge interrupt for P2.0 0 0 Falling edge interrupt is disabled on P2.0. 1 Falling edge interrupt is enabled on P2.0. 1 P2.1EF Enable falling edge interrupt for P2.1. 0 2 P2.2EF Enable falling edge interrupt for P2.2. 0 3 P2.3EF Enable falling edge interrupt for P2.3. 0 4 P2.4EF Enable falling edge interrupt for P2.4. 0 5 P2.5EF Enable falling edge interrupt for P2.5. 0 6 P2.6EF Enable falling edge interrupt for P2.6. 0 7 P2.7EF Enable falling edge interrupt for P2.7. 0 8 P2.8EF Enable falling edge interrupt for P2.8. 0 9 P2.9EF Enable falling edge interrupt for P2.9. 0 10 P2.10EF Enable falling edge interrupt for P2.10. 0 11 P2.11EF [1] Enable falling edge interrupt for P2.11. 0 12 P2.12EF [1] Enable falling edge interrupt for P2.12. 0 13 P2.13EF [1] Enable falling edge interrupt for P2.13. 0 31:14 - Reserved. NA

5.6.6 GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR -

Each bit in these read-only registers indicates the rising edge interrupt status for port 0. [1] Not available on 80-pin package. Table 117. GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR - 0x4002 8084) 0 A rising edge has not been detected on P0.0. 1 Interrupt has been generated due to a rising edge on P0.0.

5.6.7 GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR -

Each bit in these read-only registers indicates the rising edge interrupt status for port 2. [1] Not available on 80-pin package.

5.6.8 GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF -

Each bit in these read-only registers indicates the falling edge interrupt status for port 0. Table 118. GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR - 0x4002 80A4) 0 A rising edge has not been detected on P2.0. 1 Interrupt has been generated due to a rising edge on P2.0. Table 119. GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088) 0 A falling edge has not been detected on P0.0. 1 Interrupt has been generated due to a falling edge on P0.0.

5.6.9 GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF -

Each bit in these read-only registers indicates the falling edge interrupt status for port 2. Table 120. GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8) 0 A falling edge has not been detected on P2.0. 1 Interrupt has been generated due to a falling edge on P2.0.

5.6.10 GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)

Table 121. GPIO Interrupt Clear register for po rt 0 (IO0IntClr - 0x4002 808C)) bit description

0 Corresponding bits in IOxIntStatR and IOxIntStatF are

1 Corresponding bits in IOxIntStatR and IOxStatF are cleared.

5.6.11 GPIO Interrupt Clear register for port 0 (IO2IntClr - 0x4002 80AC)

[1] Not available on 80-pin package. Table 122. GPIO Interrupt Clear register for po rt 0 (IO2IntClr - 0x4002 80AC) bit description 1 Corresponding bits in IOxIntStatR and IOxStatF are cleared.

6.1 Example: An instantaneous out put of 0s and 1s on a GPIO port

Solution 1: using 32-bit (word) accessible fast GPIO registers FIO0MASK = 0xFFFF00FF ; FIO0PIN = 0x0000A500; Solution 2: using 16-bit (half-word) accessible fast GPIO registers FIO0MASKL = 0x00FF; FIO0PINL = 0xA500; Solution 3: using 8-bit (byte) accessible fast GPIO registers FIO0PIN1 = 0xA5; 6.2 Writing to FIOSET/FIOCLR vs. FIOPIN Writing to the FIOSET/FIOCLR registers allow a program to easily change a port’s output pin(s) to both high and low levels at the same time. When FIOSET or FIOCLR are used, only pin/bit(s) written with 1 will be changed, while those written as 0 will remain unaffected. Writing to the FIOPIN register enables instantaneous output of a desired value on the parallel GPIO. Data written to the FIOPIN register will affect all pins configured as outputs on that port: zeroes in the value will produce low level pin outputs and ones in the value will produce high level pin outputs. A subset of a port’s pins may be changed by using the FIOMASK register to define which pins are affected. FIOMASK is set up to contain zeroes in bits corresponding to pins that will be changed, and ones for all others. Solution 2 from Section 9–6.1 above illustrates output of 0xA5 on PORT0 pins 15 to 8 while preserving all other PORT0 output pins as they were before.

Power: In the PCONP register ( Table 4–46), set bit PCENET.

Remark: On reset, the Ethernet block is disabled (PCENET = 0).

Pins: Enable Ethernet pins through the PINSEL registers and select their modes

through the PINMODE registers, see Section 8–5.

Wake-up: Activity on the Ethernet port can wake up the microcontroller from

Power-down mode, see Section 4–8.8.

Interrupts: Inte rrupts are enabled in the NVIC using the appropriate Interrupt Set
Initialization: see Section 10–17.2.

reception with Scatter-Gather DMA off-loads many operations from the CPU. bandwidth to the Ethernet function. Table 123. Ethernet acronyms, ab breviations, and definitions

Ethernet standards support: – Supports 10 or 100 Mbps PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. – Flexible transmit and receive frame options. – VLAN frame support.
Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and prefetching.
Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic FCS insertion (CRC) for transmit. – Selectable automatic transmit frame padding. Frame An Ethernet frame consists of destination address, source address, length type field, payload and frame check sequence. Half-word 16-bit entity LAN Local Area Network MAC Media Access Control sublayer MII Media Independent Interface MIIM MII management Octet An 8-bit data entity, used in lieu of "byte" by IEEE 802.3 Packet A frame that is transported across Ethernet; a packet consists of a preamble, a start of frame delimiter and an Ethernet frame. PHY Ethernet Physical Layer RMII Reduced MII Rx Receive TCP/IP Transmission Control Protocol / Internet Protocol. The most common high-level protocol used with Ethernet. Tx Transmit VLAN Virtual LAN WoL Wake-up on LAN Word 32-bit entity

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 141 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision backoff and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter.

Physical interface: – Attachment of external PHY chip through a standard Reduced MII (RMII) interface. – PHY register access is available via the Media Independent Interface Management (MIIM) interface. 4. Architecture and operation Figure 10–16 shows the internal architecture of the Ethernet block. The block diagram for the Ethernet block consists of:
The host registers module containing the registers in the software view and handling AHB accesses to the Ethernet block. The host registers connect to the transmit and receive data path as well as the MAC.
The DMA to AHB interface. This provides an AHB master connection that allows the Ethernet block to access on-chip SRAM for reading of descriptors, writing of status, and reading and writing data buffers.
The Ethernet MAC, which interfaces to the off-chip PHY via an RMII interface.
The transmit data path, including: Fig 16. Ethernet block diagram register interface (AHB slave) DMA interface (AHB master) BUS INTER FACE RECEIVE DMA TRANSMIT DMA RECEIVE BUFFER RECEIVE FILTER TRANSMIT RETRY TRANSMIT FLOW CONTROL ETHE RNET MAC RMII ADAPTER RMII MIIM HOST REGISTERS AHB BUS ETHERNET BLOCK ETHE RNET PHY BUS INTERFACE

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 142 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet – The transmit DMA manager which reads descriptors and data from memory and writes status to memory. – The transmit retry module handling Ethernet retry and abort situations. – The transmit flow control module which can insert Ethernet pause frames.

The receive data path, including: – The receive DMA manager which reads descriptors from memory and writes data and status to memory. – The Ethernet MAC which detects frame types by parsing part of the frame header. – The receive filter which can filter out certain Ethernet frames by applying different filtering schemes. – The receive buffer implementing a delay for receive frames to allow the filter to filter out certain frames before storing them to memory. 5. DMA engine functions The Ethernet block is designed to provide optimized performance via DMA hardware acceleration. Independent scatter/gather DMA engines connected to the AHB bus off-load many data transfers from the CPU. Descriptors, which are stored in memory, contain information about fragments of incoming or outgoing Ethernet frames. A fragment may be an entire frame or a much smaller amount of data. Each descriptor contains a pointer to a memory buffer that holds data associated with a fragment, the size of the fragment buffer, and details of how the fragment will be transmitted or received. Descriptors are stored in arrays in memory, which are located by pointer registers in the Ethernet block. Other registers determine the size of the arrays, point to the next descriptor in each array that will be used by the DMA engine, and point to the next descriptor in each array that will be used by the Ethernet device driver. 6. Overview of DMA operation The DMA engine makes use of a Receive descriptor array and a Transmit descriptor array in memory. All or part of an Ethernet frame may be contained in a memory buffer associated with a descriptor. When transmitting, the transmit DMA engine uses as many descriptors as needed (one or more) to obtain (gather) all of the parts of a frame, and sends them out in sequence. When receiving, the receive DMA engine also uses as many descriptors as needed (one or more) to find places to store (scatter) all of the data in the received frame. The base address registers for the descriptor array, registers indicating the number of descriptor array entries, and descriptor array input/output pointers are contained in the Ethernet block. The descriptor entries and all transmit and receive packet data are stored in memory which is not a part of the Ethernet block. The descriptor entries tell where related frame data is stored in memory, certain aspects of how the data is handled, and the result status of each Ethernet transaction.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 143 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Hardware in the DMA engine controls how data incoming from the Ethernet MAC is saved to memory, causes fragment related status to be saved, and advances the hardware receive pointer for incoming data. Driver software must handle the disposition of received data, changing of descriptor data addresses (to avoid unnecessary data movement), and advancing the software receive pointer. The two pointers create a circular queue in the descriptor array and allow both the DMA hardware and the driver software to know which descriptors (if any) are available for their use, including whether the descriptor array is empty or full. Similarly, driver software must set up pointers to data that will be transmitted by the Ethernet MAC, giving instructions for each fragment of data, and advancing the software transmit pointer for outgoing data. Hardware in the DMA engine reads this information and sends the data to the Ethernet MAC interface when possible, updating the status and advancing the hardware transmit pointer. 7. Ethernet Packet Figure 10–17 illustrates the different fields in an Ethernet packet. A packet consists of a preamble, a start-of-frame delimiter and an Ethernet frame. Fig 17. Ethernet packet fields OPTIONAL VLAN SOURCE ADDRESS DesA oct6 DesA oct1 DesA oct2 DesA oct3 DesA oct4 DesA oct5 SrcA oct6 SrcA oct5 SrcA oct4 SrcA oct3 SrcA oct2 SrcA oct1 LSB oct(0) oct(1) oct(2) oct(3) oct(4) oct(5) oct(6) MSB oct(7) DESTINATION ADDRESS PAYLOAD FCS ETHERNET FRAMEPREAMBLE 7 bytes ethernet packet start-of-frame delimiter 1 byte time LEN TYPE

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 144 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The Ethernet frame consists of the destination address, the source address, an optional VLAN field, the length/type field, the payload and the frame check sequence. Each address consists of 6 bytes where each byte consists of 8 bits. Bits are transferred starting with the least significant bit. 8. Overview

8.1 Partitioning

The Ethernet block and associated device driver software offer the functionality of the Media Access Control (MAC) sublayer of the data link layer in the OSI reference model (see IEEE std 802.3). The MAC sublayer offers the service of transmitting and receiving frames to the next higher protocol level, the MAC client layer, typically the Logical Link Control sublayer. The device driver software implements the interface to the MAC client layer. It sets up registers in the Ethernet block, maintains descriptor arrays pointing to frames in memory and receives results back from the Ethernet block through interrupts. When a frame is transmitted, the software partially sets up the Ethernet frames by providing pointers to the destination address field, source address field, the length/type field, the MAC client data field and optionally the CRC in the frame check sequence field. Preferably concatenation of frame fields should be done by using the scatter/gather functionality of the Ethernet core to avoid unnecessary copying of data. The hardware adds the preamble and start frame delimiter fields and can optionally add the CRC, if requested by software. When a packet is received the hardware strips the preamble and start frame delimiter and passes the rest of the packet - the Ethernet frame - to the device driver, including destination address, source address, length/type field, MAC client data and frame check sequence (FCS). Apart from the MAC, the Ethernet block contains receive and transmit DMA managers that control receive and transmit data streams between the MAC and the AHB interface. Frames are passed via descriptor arrays located in host memory, so that the hardware can process many frames without software/CPU support. Frames can consist of multiple fragments that are accessed with scatter/gather DMA. The DMA managers optimize memory bandwidth using prefetching and buffering. A receive filter block is used to identify received frames that are not addressed to this Ethernet station, so that they can be discarded. The Rx filters include a perfect address filter and a hash filter. Wake-on-LAN power management support makes it possible to wake the system up from a power-down state -a state in which some of the clocks are switched off -when wake-up frames are received over the LAN. Wake-up frames are recognized by the receive filtering modules or by a Magic Frame detection technology. System wake-up occurs by triggering an interrupt. An interrupt logic block raises and masks interrupts and keeps track of the cause of interrupts. The interrupt block sends an interrupt request signal to the host system. Interrupts can be enabled, cleared and set by software.

8.2 Example PHY Devices

Some examples of compatible PHY devices are shown in Table 10–124. Interface (RMII) to the external PHY . (MIIM) of the external PHY . Table 124. Example PHY Devices Table 125. Ethernet RMII pin descriptions ENET_RXD[1:0] Input Receive data, 2 bits. ENET_RX_ER Input Receive error. ENET_CRS Input Carrier sense/data valid. Table 126. Ethernet MIIM pin descriptions

Registers and software interface

10.1 Register map

AHB address space required is 4 kilobytes. all registers are reset to 0 unless stated otherwise in the following register descriptions. Some registers will have unused bits which will return a 0 on a read via the AHB interface. Writing to unused register bits of an otherwise writable register will not have side effects. for controlling DMA transfers, flow control and filtering. reserved addresses or reserved bits has no effect. read-only registers will return a write error on the AHB interface. Table 127. Ethernet register definitions

Ethernet MAC register definitions

This section defines the bits in the individual registers of the Ethernet block register map.

11.1 MAC Configuration Regi ster 1 (MAC1 - 0x5000 0000)

definition is shown in Table 10–128.

11.2 MAC Configuration Regi ster 2 (MAC2 - 0x5000 0004)

definition is shown in Table 10–129. Table 128. MAC Configuration register 1 (MAC1 - address 0x5000 0000) bit description this control bit to the incoming receive stream.

1 PASS ALL RECEIVE

vs. Control). When disabled, the MAC does not pass valid Control frames.

2 RX FLOW CONTROL When enabled (set to ’1’), the MAC acts upon received PAUSE Flow Control

frames. When disabled, received PAUSE Flow Control frames are ignored.

3 TX FLOW CONTROL When enabled (set to ’1’), PAUSE Flow Control frames are allowed to be

transmitted. When disabled, Flow Control frames are blocked.

4 LOOPBACK Setting this bit will cause the MAC Transmit interface to be looped back to the MAC

Receive interface. Clearing this bit results in normal operation. from a reserved bit is not defined.

14 SIMULATION RESET Setting this bit will cause a reset to the random number generator within the

15 SOFT RESET Setting this bit will put all modul es within the MAC in reset except the Host

from a reserved bit is not defined.

UM10360_1 © NXP B.V. 2010. All rights reserved. Table 129. MAC Configuration register 2 (MAC2 - address 0x5000 0004) bit description the MAC operates in Half-Duplex mode. performed. Mismatches are reported in the StatusInfo word for each received frame.

2 HUGE FRAME

3 DELAYED CRC This bit determines the number of by tes, if any, of proprietary header information

by the CRC function) are added. When 0, there is no proprietary header. 4 CRC ENABLE Set this bit to append a CRC to ever y frame whether padding was required or not.

6 VLAN PAD ENABLE Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid

Note: This bit is ignored if PAD / CRC ENABLE is cleared.

7 AUTO DETECT PAD

provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared.

8 PURE PREAMBLE

it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed.

9 LONG PREAMBLE

length preamble as per the Standard. from a reserved bit is not defined.

12 NO BACKOFF When enabled (set to ’1’), the MAC will immediately retransmit following a collision

13 BACK PRESSURE /

further collisions and ensuring transmit packets get sent.

14 EXCESS DEFER When enabled (set to ’1’) the MAC will defer to carrier indefinitely as per the

from a reserved bit is not defined.

11.3 Back-to-Back Inter-Packet-Gap Register (IPGT - 0x5000 0008)

bit definition is shown in Table 10–131.

11.4 Non Back-to-Back Inter-Packet- Gap Register (IPGR - 0x5000 000C)

The Non Back-to-Back Inter-Packet-Gap register (IPGR) has an address of 0x5000 000C. Its bit definition is shown in Table 10–132. Table 130. Pad operation Table 131. Back-to-back Inter-packet-gap regist er (IPGT - address 0x5000 0008) bit description from a reserved bit is not defined. Table 132. Non Back-to-back Inter-packet-gap register (IPGR - address 0x5000 000C) bit description read from a reserved bit is not defined. read from a reserved bit is not defined.

11.5 Collision Window / Retry Register (CLRT - 0x5000 0010)

definition is shown in Table 10–133.

11.6 Maximum Frame Regi ster (MAXF - 0x5000 0014)

11.7 PHY Support Regist er (SUPP - 0x5000 0018)

Unused bits in the PHY support register should be left as zeroes.

11.8 Test Register (TEST - 0x5000 001C)

is shown in Table 10–136. These bits are used for testing purposes only. Table 133. Collision Window / Retry register (CLRT - address 0x5000 0010) bit description a reserved bit is not defined. (55d) represents a 56 byte window following the preamble and SFD. a reserved bit is not defined. restriction is desired, program this 16-bit field. 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected.

11.9 MII Mgmt Configurati on Register (MCFG - 0x5000 0020)

definition of this register is shown in Table 10–137. Table 136. Test register (TEST - address 0x5000 ) bit description

0 SHORTCUT PAUSE

1 TEST PAUSE This bit causes the MAC Control sublayer to inhibit transmissions, just as if a

PAUSE Receive Control frame with a nonzero pause time parameter was received.

2 TEST

system will be sent during backpressure. Table 137. MII Mgmt Configuration register (MCFG - address 0x5000 0020) bit description

0 SCAN INCREMENT Set this bit to cause the MII Management hardware to perform read cycles across a

continuous reads of the same PHY.

1 SUPPRESS

performed. Some PHYs support suppressed preamble. Table 138. Clock select encoding

11.10 MII Mgmt Command Re gister (MCMD - 0x5000 0024)

definition of this register is shown in Table 10–139.

11.11 MII Mgmt Address Re gister (MADR - 0x5000 0028)

of this register is shown in Table 10–140.

11.12 MII Mgmt Write Data Register (MWTD - 0x5000 002C)

0x5000 002C. The bit definition of this register is shown in Table 10–141. Table 139. MII Mgmt Command register (MCMD - address 0x5000 0024) bit description returned in Register MRDD (MII Mgmt Read Data). useful for monitoring Link Fail for example. Table 140. MII Mgmt Address register (MADR - address 0x5000 0028) bit description cycles. Up to 32 registers can be accessed. cycles. Up to 31 PHYs can be addressed (0 is reserved).

11.13 MII Mgmt Read Data Register (MRDD - 0x5000 0030)

0x5000 0030. The bit definition of this register is shown in Table 10–142.

11.14 MII Mgmt Indicators Re gister (MIND - 0x5000 0034)

0x5000 0034. The bit definition of this register is shown in Table 10–143. Here are two examples to access PHY via the MII Management Controller.

Write PHY address and register address to MADR
Wait for busy bit to be cleared in MIND
Write PHY address and register address to MADR

Table 141. MII Mgmt Write Data register (MWTD - address 0x5000 002C) bit description MII Mgmt Address register (MADR). Table 142. MII Mgmt Read Data register (MRDD - address 0x5000 0030) bit description Table 143. MII Mgmt Indica tors register (MIND - address 0x5000 0034) bit description

0 BUSY When ’1’ is returned - indicates MII Mgmt is currently performing an

MII Mgmt Read or Write cycle.

1 SCANNING When ’1’ is returned - indicates a scan operation (continuous MII

Mgmt Read cycles) is in progress.

2 NOT VALID When ’1’ is returned - indicates MII Mgmt Read cycle has not

completed and the Read Data is not yet valid.

3 MII Link Fail When ’1’ is returned - indicates that an MII Mgmt link fail has

Wait for busy bit to be cleared in MIND

11.15 Station Address 0 Re gister (SA0 - 0x5000 0040)

this register is shown in Table 10–144. frames. For the ordering of the octets in the packet please refer to Figure 10–17.

11.16 Station Address 1 Re gister (SA1 - 0x5000 0044)

frames. For the ordering of the octets in the packet please refer to Figure 10–17.

11.17 Station Address 2 Re gister (SA2 - 0x5000 0048)

Table 144. Station Address register (SA0 - address 0x5000 0040) bit description Table 145. Station Address register (SA1 - address 0x5000 0044) bit description Table 146. Station Address register (SA2 - address 0x5000 0048) bit description

Control register definitions

12.1 Command Register (Command - 0x5000 0100)

definition is shown in Table 10–147. All bits can be written and read. The Tx/RxReset bits are write-only, reading will return a 0.

12.2 Status Register (Status - 0x5000 0104)

definition is shown in Table 10–148. Table 147. Command register (Command - address 0x5000 0100) bit description

3 RegReset When a ’1’ is written, all datapaths and the host registers are

reset. The MAC needs to be reset separately.

6 PassRuntFrame When set to ’1’, passes r unt frames smaller than 64 bytes to

received are written to memory. frames in full duplex and continuous preamble in half duplex. one during Ethernet initialization. See Section 10–17.2. Table 148. Status register (Status - address 0x5000 0104) bit description

It is enabled and the Rx/TxEnable bit is set in the Command register or it just got disabled while still transmitting or receiving a frame.
Also, for the transmit channel, the transmit queue is not empty i.e. ProduceIndex != ConsumeIndex.
Also, for the receive channel, the receive queue is not full i.e. ProduceIndex != ConsumeIndex - 1. The status transitions from active to inactive if the channel is disabled by a software reset of the Rx/TxEnable bit in the Command register and the channel has committed the status and data of the current frame to memory. The status also transitions to inactive if the transmit queue is empty or if the receive queue is full and status and data have been committed to memory.

12.3 Receive Descriptor Base Addr ess Register (RxDescriptor -

0x5000 0108) The Receive Descriptor base address register (RxDescriptor) has an address of 0x5000 0108. Its bit definition is shown in Table 10–149. The receive descriptor base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of descriptors.

12.4 Receive Status Base Address Register (RxStatus - 0x5000 010C)

The receive descriptor base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of descriptors. The receive status base address is a byte address aligned to a double word boundary i.e. LSB 2:0 are fixed to “000”.

12.5 Receive Number of D escriptors Register (RxDescriptor - 0x5000 0110)

The Receive Number of Descriptors register (RxDescriptorNumber) has an address of 0x5000 0110. Its bit definition is shown in Table 10–151. Table 149. Receive Descriptor Base Address register (RxDescriptor - address 0x5000 0108) Table 150. receive Status Base Address regi ster (RxStatus - address 0x5000 010C) bit 2:0 - Fixed to ’000’ - 31:3 RxStatus MSBs of receive status base address. 0x0

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 158 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The receive number of descriptors register defines the number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors should match the number of statuses. The register uses minus one encoding i.e. if the array has 8 elements, the value in the register should be 7.

12.6 Receive Produce Index Regist er (RxProduceIndex - 0x5000 0114)

The Receive Produce Index register (RxProduceIndex) is a read-only register with an address of 0x5000 0114. Its bit definition is shown in Table 10–152. The receive produce index register defines the descriptor that is going to be filled next by the hardware receive process. After a frame has been received, hardware increments the index. The value is wrapped to 0 once the value of RxDescriptorNumber has been reached. If the RxProduceIndex equals RxConsumeIndex - 1, the array is full and any further frames being received will cause a buffer overrun error.

12.7 Receive Consume Index Regist er (RxConsumeIndex - 0x5000 0118)

The Receive consume index register (RxConsumeIndex) has an address of 0x5000 0118. Its bit definition is shown in Table 10–153 The receive consume register defines the descriptor that is going to be processed next by the software receive driver. The receive array is empty as long as RxProduceIndex equals RxConsumeIndex. As soon as the array is not empty, software can process the frame pointed to by RxConsumeIndex. After a frame has been processed by software, software should increment the RxConsumeIndex. The value must be wrapped to 0 once the value Table 151. Receive Number of Descriptors regist er (RxDescriptor - address 0x5000 0110) bit 15:0 RxDescriptorNumber Number of descri ptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded. 0x0 31:16 - Unused 0x0 Table 152. Receive Produce Index register (RxProduceIndex - address 0x5000 0114) bit 15:0 RxProduceIndex Index of the descriptor that is going to be filled next by the receive datapath. 0x0 31:16 - Unused 0x0 Table 153. Receive Consume Index register (RxConsumeIndex - address 0x5000 0118) bit 15:0 RxConsumeIndex Index of the descriptor that is going to be processed next by the receive 31:16 - Unused 0x0

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 159 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet of RxDescriptorNumber has been reached. If the RxProduceIndex equals RxConsumeIndex - 1, the array is full and any further frames being received will cause a buffer overrun error.

12.8 Transmit Descriptor Base A ddress Register (TxDescriptor -

0x5000 011C) The Transmit Descriptor base address register (TxDescriptor) has an address of 0x5000 011C. Its bit definition is shown in Table 10–154. The transmit descriptor base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of descriptors.

12.9 Transmit Status Base Address Register (TxStatus - 0x5000 0120)

The Transmit Status base address register (TxStatus) has an address of 0x5000 0120. Its bit definition is shown in Table 10–155. The transmit status base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of statuses.

12.10 Transmit Number of Descripto rs Register (TxDescriptorNumber -

0x5000 0124) The Transmit Number of Descriptors register (TxDescriptorNumber) has an address of 0x5000 0124. Its bit definition is shown in Table 10–156. Table 154. Transmit Descriptor Base Address register (TxDescriptor - address 0x5000 011C) Table 155. Transmit Status Base Address register (TxStatus - address 0x5000 0120) bit 1:0 - Fixed to ’00’ - 31:2 TxStatus MSBs of transmit status base address. 0x0 Table 156. Transmit Number of Descriptors register (TxDescriptorNumber - address

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 160 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The transmit number of descriptors register defines the number of descriptors in the descriptor array for which TxDescriptor is the base address. The number of descriptors should match the number of statuses. The register uses minus one encoding i.e. if the array has 8 elements, the value in the register should be 7.

12.11 Transmit Produce Index Regi ster (TxProduceIndex - 0x5000 0128)

The Transmit Produce Index register (TxProduceIndex) has an address of 0x5000 0128. Its bit definition is shown in Table 10–157. The transmit produce index register defines the descriptor that is going to be filled next by the software transmit driver. The transmit descriptor array is empty as long as TxProduceIndex equals TxConsumeIndex. If the transmit hardware is enabled, it will start transmitting frames as soon as the descriptor array is not empty. After a frame has been processed by software, it should increment the TxProduceIndex. The value must be wrapped to 0 once the value of TxDescriptorNumber has been reached. If the TxProduceIndex equals TxConsumeIndex - 1 the descriptor array is full and software should stop producing new descriptors until hardware has transmitted some frames and updated the TxConsumeIndex.

12.12 Transmit Consume Index Regi ster (TxConsumeIndex - 0x5000 012C)

The Transmit Consume Index register (TxConsumeIndex) is a read-only register with an address of 0x5000 012C. Its bit definition is shown in Table 10–158. The transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. After a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is empty and the transmit channel will stop transmitting until software produces new descriptors.

12.13 Transmit Status Vector 0 Register (TSV0 - 0x5000 0158)

The Transmit Status Vector 0 register (TSV0) is a read-only register with an address of 0x5000 0158. The transmit status vector registers store the most recent transmit status returned by the MAC. Since the status vector consists of more than 4 bytes, status is Table 157. Transmit Produce Index register (TxProduceIndex - address 0x5000 0128) bit 15:0 TxProduceIndex Index of the descriptor that is going to be filled next by the transmit software driver. 0x0 31:16 - Unused 0x0 Table 158. Transmit Consume Index register (TxConsumeIndex - address 0x5000 012C) bit 15:0 TxConsumeIndex Index of the descriptor that is going to be transmitted next by the transmit datapath. 0x0 31:16 - Unused 0x0

12.14 Transmit Status Vector 1 Register (TSV1 - 0x5000 015C)

Table 159. Transmit Status Vector 0 register (TSV0 - address 0x5000 0158) bit description

0 CRC error The attached CRC in the packet did not match the

1 Length check error Indicates the frame length field does not match the actual

number of data items and is not a type field.

2 Length out of range [1] Indicates that frame type/length field was larger than

6 Packet Defer Packet was deferred for at least one attempt, but less than

7 Excessive Defer Packet was deferred in excess of 6071 nibble times in

100 Mbps or 24287 bit times in 10 Mbps mode.

8 Excessive Collision Packet was aborted due to exceeding of maximum allowed

10 Giant Byte count in frame was greater than can be represented

in the transmit byte count field in TSV1.

29 Pause The frame was a control frame with a valid PAUSE

30 Backpressure Carrier-sense method backpressure was previously

31 VLAN Frame’s length/type field contained 0x8100 which is the

12.15 Receive Status Vector Register (RSV - 0x5000 0160)

receive processes are halted. lists the bit definitions of the RSV register. Table 160. Transmit Status Vector 1 register (TSV1 - address 0x5000 015C) bit description Table 161. Receive Status Vector register (RSV - address 0x5000 0160) bit description

16 Packet previously

17 RXDV event

enough to be a valid packet.

18 Carrier event

a carrier event was detected.

19 Receive code

20 CRC error The attached CRC in the packet did not match the

21 Length check error Indicates the frame length field does not match the actual

number of data items and is not a type field.

22 Length out of range [1] Indicates that frame type/length field was larger than

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 163 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet [1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame.

12.16 Flow Control Counter Register (FlowControlCounter - 0x5000 0170)

The Flow Control Counter register (FlowControlCounter) has an address of 0x5000 0170. Table 10–162 lists the bit definitions of the register.

12.17 Flow Control Status Register (FlowControlStatus - 0x5000 0174)

The Flow Control Status register (FlowControlStatus) is a read-only register with an address of 0x5000 8174. Table 10–163 lists the bit definitions of the register.

26 Dribble Nibble Indicates that after the end of packet another 1-7 bits were

received. A single nibble, called dribble nibble, is formed but not sent out. 27 Control frame The frame was a control frame. 0

28 PAUSE The frame was a control frame with a valid PAUSE

opcode.

29 Unsupported Opcode The current frame was recognized as a Control Frame but

contains an unknown opcode.

30 VLAN Frame’s length/type field contained 0x8100 which is the

VLAN protocol identifier. 31 - Unused 0x0 Table 162. Flow Control Counter register (FlowControlCounter - address 0x5000 0170) bit 15:0 MirrorCounter In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame. 0x0 31:16 PauseTimer In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles. 0x0 Table 163. Flow Control Status register (FlowControlStatus - address 0x5000 8174) bit 15:0 MirrorCounterCurrent In full duplex mode this register represents the current value of the datapath’s mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register. 0x0 31:16 - Unused 0x0

13.1 Receive Filter C ontrol Register (RxFilterCtrl - 0x5000 0200)

The Receive Filter Control register (RxFilterCtrl) has an address of 0x5000 0200. Table 10–164 lists the definition of the individual bits in the register.

13.2 Receive Filter WoL Status Regist er (RxFilterWoLStatus - 0x5000 0204)

The Receive Filter Wake-up on LAN Status register (RxFilterWoLStatus) is a read-only register with an address of 0x5000 0204. Table 10–165 lists the definition of the individual bits in the register. Table 164. Receive Filter Control register (RxF ilterCtrl - address 0x5000 0200) bit description

3 AcceptUnicastHashEn When set to ’1’, un icast frames that pass the imperfect

4 AcceptMulticastHashEn When set to ’1’, multicast frames that pass the

imperfect hash filter are accepted.

5 AcceptPerfectEn When set to ’1’, the frames with a destination address

station address are accepted.

12 MagicPacketEnWoL When set to ’1’, the result of the magic packet filter will

generate a WoL interrupt when there is a match.

13 RxFilterEnWoL When set to ’1’, the result of the perfect address

generate a WoL interrupt when there is a match. Table 165. Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit 0 AcceptUnicastWoL When the value is ’1’, a unicast frames caused WoL. 0 1 AcceptBroadcastWoL When the value is ’1 ’, a broadcast frame caused WoL. 0 2 AcceptMulticastWoL When the value is ’1’, a multicast frame caused WoL. 0

3 AcceptUnicastHashWoL When the value is ’1’, a unicast frame that passes the

imperfect hash filter caused WoL.

4 AcceptMulticastHashWoL When the value is ’1’, a multicast frame that passes the

imperfect hash filter caused WoL.

5 AcceptPerfectWoL When the value is ’1’, the perfect address matching filter

caused WoL.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 165 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The bits in this register record the cause for a WoL. Bits in RxFilterWoLStatus can be cleared by writing the RxFilterWoLClear register.

13.3 Receive Filter WoL Cl ear Register (RxFilterWoLClear - 0x5000 0208)

The Receive Filter Wake-up on LAN Clear register (RxFilterWoLClear) is a write-only register with an address of 0x5000 0208. Table 10–166 lists the definition of the individual bits in the register. The bits in this register are write-only; writing resets the corresponding bits in the RxFilterWoLStatus register.

13.4 Hash Filter Table LSBs Regi ster (HashFilterL - 0x5000 0210)

The Hash Filter table LSBs register (HashFilterL) has an address of 0x5000 0210. Table 10–167 lists the bit definitions of the register. Details of Hash filter table use can be found in Section 10–17.10 “Receive filtering” on page 196. 6 - Unused 0x0 7 RxFilterWoL When the value is ’1’, the receive filter caused WoL. 0

8 MagicPacketWoL When the value is ’1’, the magic packet filter caused

WoL. 31:9 - Unused 0x0 Table 166. Receive Filter WoL Clear register (RxFilterWoLClear - address 0x5000 0208) bit

0 AcceptUnicastWoLClr When a ’1’ is written to one of these bits (0 to 5), the

corresponding status bit in the RxFilterWoLStatus register is cleared.

1 AcceptBroadcastWoLClr 0

2 AcceptMulticastWoLClr 0

3 AcceptUnicastHashWoLClr 0

4 AcceptMulticastHashWoLClr 0

5 AcceptPerfectWoLClr 0

7 RxFilterWoLClr When a ’1’ is written to one of these bits (7 and/or 8),

the corresponding status bit in the RxFilterWoLStatus register is cleared.

8 MagicPacketWoLClr 0

31:9 - Unused 0x0 Table 167. Hash Filter Table LSBs register (HashFilterL - address 0x5000 0210) bit 31:0 HashFilterL Bits 31:0 of the imperfect filter hash table for receive filtering. 0x0

13.5 Hash Filter Table MSBs Re gister (HashFilterH - 0x5000 0214)

The Hash Filter table MSBs register (HashFilterH) has an address of 0x5000 0214. found in Section 10–17.10 “Receive filtering” on page 196.

Module control register definitions

14.1 Interrupt Status Regist er (IntStatus - 0x5000 0FE0)

interrupts if there are wake-up events while clocks are disabled. Table 168. Hash Filter MSBs register (HashFi lterH - address 0x5000 0214) bit description Table 169. Interrupt Status register (IntStatus - address 0x5000 0FE0) bit description set when there is a nonfatal overrun error.

1 RxErrorInt Interrupt trigger on receive errors: AlignmentError, RangeError,

LengthError, SymbolError, CRCError or NoDescriptor or Overrun.

2 RxFinishedInt Interrupt triggered when all receive descriptors have been

ProduceIndex == ConsumeIndex.

3 RxDoneInt Interrupt triggered when a receive descriptor has been processed

while the Interrupt bit in the Control field of the descriptor was set. set when there is a nonfatal underrun error.

5 TxErrorInt Interrupt trigger on transmit errors: LateCollision,

6 TxFinishedInt Interrupt triggered when all transmit descriptors have been

ProduceIndex == ConsumeIndex.

7 TxDoneInt Interrupt triggered when a descriptor has been transmitted while

the Interrupt bit in the Control field of the descriptor was set.

12 SoftInt Interrupt triggered by software writing a 1 to the SoftintSet bit in

13 WakeupInt Interrupt triggered by a Wake-up event detected by the receive

14.2 Interrupt Enable Regist er (IntEnable - 0x5000 0FE4)

enable register bit definition is shown in Table 10–170.

14.3 Interrupt Clear Regist er (IntClear - 0x5000 0FE8)

0x5000 0FE8. The interrupt clear register bit definition is shown in Table 10–171. Table 170. Interrupt Enable re gister (intEnable - address 0x5000 0FE4) bit description

0 RxOverrunIntEn Enable for interrupt trigger on receive buffer overrun or

descriptor underrun situations.

2 RxFinishedIntEn Enable for interrupt triggered when all receive descriptors have

ProduceIndex == ConsumeIndex.

3 RxDoneIntEn Enable for interrupt triggered when a receive descriptor has

4 TxUnderrunIntEn Enable for interrupt trigger on transmit buffer or descriptor

6 TxFinishedIntEn Enable for interrupt triggered when all transmit descriptors

where ProduceIndex == ConsumeIndex.

7 TxDoneIntEn Enable for interrupt triggered when a descriptor has been

12 SoftIntEn Enable for interrupt triggered by the SoftInt bit in the IntStatus

13 WakeupIntEn Enable for interrupt triggered by a Wake-up event detected by

14.4 Interrupt Set Regist er (IntSet - 0x5000 0FEC)

The Interrupt Set register (IntSet) is a write-only register with an address of 0x5000 0FEC. The interrupt set register bit definition is shown in Table 10–172. corresponding bit in the status register. Writing a 0 will not affect the interrupt status. Table 171. Interrupt Clear register (IntClear - address 0x5000 0FE8) bit description

0 RxOverrunIntClr Writing a ’1’ to one of these bits clears (0 to 7) the

1 RxErrorIntClr 0

2 RxFinishedIntClr 0

3 RxDoneIntClr 0

4 TxUnderrunIntClr 0

5 TxErrorIntClr 0

6 TxFinishedIntClr 0

7 TxDoneIntClr 0

12 SoftIntClr Writing a ’1’ to one of these bits (12 and/or 13) clears the

13 WakeupIntClr 0

Table 172. Interrupt Set re gister (IntSet - address 0x5000 0FEC) bit description

0 RxOverrunIntSet Writing a ’1’ to one of these bits (0 to 7) sets the

1 RxErrorIntSet 0

2 RxFinishedIntSet 0

3 RxDoneIntSet 0

4 TxUnderrunIntSet 0

5 TxErrorIntSet 0

6 TxFinishedIntSet 0

7 TxDoneIntSet 0

12 SoftIntSet Writing a ’1’ to one of these bits (12 and/or 13) sets the

13 WakeupIntSet 0

14.5 Power-Down Register (PowerDown - 0x5000 0FF4)

bit definition of the register is listed in Table 10–173. except for accesses to the Power-Down register. Table 173. Power-Down register (PowerDown - address 0x5000 0FF4) bit description

31 PowerDownMACAHB If true, all AHB accesses will return a read/write error,

except accesses to the Power-Down register.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 170 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 15. Descriptor and status formats This section defines the descriptor format for the transmit and receive scatter/gather DMA engines. Each Ethernet frame can consist of one or more fragments. Each fragment corresponds to a single descriptor. The DMA managers in the Ethernet block scatter (for receive) and gather (for transmit) multiple fragments for a single Ethernet frame.

15.1 Receive descript ors and statuses

Figure 10–18 depicts the layout of the receive descriptors in memory. Receive descriptors are stored in an array in memory. The base address of the array is stored in the RxDescriptor register, and should be aligned on a 4 byte address boundary. The number of descriptors in the array is stored in the RxDescriptorNumber register using a minus one encoding style e.g. if the array has 8 elements the register value should be 7. Parallel to the descriptors there is an array of statuses. For each element of the descriptor array there is an associated status field in the status array. The base address of the status array is stored in the RxStatus register, and must be aligned on an 8 byte address boundary. During operation (when the receive data path is enabled) the RxDescriptor, RxStatus and RxDescriptorNumber registers should not be modified. Two registers, RxConsumeIndex and RxProduceIndex, define the descriptor locations that will be used next by hardware and software. Both registers act as counters starting at 0 and wrapping when they reach the value of RxDescriptorNumber. The RxProduceIndex contains the index of the descriptor that is going to be filled with the next frame being Fig 18. Receive descriptor memory layout StatusInfo StatusHashCRC StatusInfo StatusHashCRC StatusInfo StatusHashCRC StatusInfo StatusHashCRC StatusInfo StatusHashCRC StatusInfo StatusHashCRC PACKET CONTROL PACKET CONTROL PACKET CONTROL PACKET CONTROL PACKET CONTROL PACKET CONTROL RxStatus RxDescriptorNumber RxDescriptor DATA BUFFER DATA BUFFER DATA BUFFER DATA BUFFER DATA BUFFER DATA BUFFER

UM10360_1 © NXP B.V. 2010. All rights reserved. pointer to the data buffer for storing receive data (Packet) and a control word (Control). with respect to the descriptor address as defined in Table 10–174. Table 10–176 lists the fields in the receive status elements from the status array. Table 174. Receive D escriptor Fields Packet 0x0 4 Base address of the data buffer for storing receive data. Control 0x4 4 Control information, see Table 10–175. Table 175. Receive Descriptor Control Word bytes the size field should be equal to 7.

31 Interrupt If true generate an RxDone interru pt when the data in this frame or frame

Table 176. Receive Status Fields StatusInfo 0x0 4 Receive status return flags, see Table 10–178. the source address hash CRC.

UM10360_1 © NXP B.V. 2010. All rights reserved. definitions in the StatusInfo word. Table 177. Receive Status HashCRC Word 8:0 SAHashCRC Hash CRC calculated from the source address. 24:16 DAHashCRC Hash CRC calculated from the destination address. Table 178. Receive status information word 8 bytes the RxSize value will be 7.

18 ControlFrame Indicates this is a control frame for flow control, either a pause frame or a

frame with an unsupported opcode. 19 VLAN Indicates a VLAN frame. the Command register is set, the whole frame will be passed to memory. 21 Multicast Set when a multicast frame is received. 22 Broadcast Set when a broadcast frame is received. 23 CRCError The received frame had a CRC error. 24 SymbolError The PHY reports a bit error over the PHY interface during reception.

25 LengthError The frame length field value in the frame specifies a valid length, but does

not match the actual data length.

26 RangeError

[1] The received packet exceeds the maximum packet size.

27 AlignmentError An alignment error is flagged when dribble bits are detected and also a

28 Overrun Receive overrun. The adapter can not accept the data stream.

29 NoDescriptor No new Rx descriptor is available and the frame is too long for the buffer

size in the current receive descriptor. 30 LastFlag When set to 1, indicates this descriptor is for the last fragment of a frame. If the frame consists of a single fragment, this bit is also set to 1.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 173 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet [1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. For multi-fragment frames, the value of the AlignmentError, RangeError, LengthError, SymbolError and CRCError bits in all but the last fragment in the frame will be 0; likewise the value of the FailFilter, Multicast, Broadcast, VLAN and ControlFrame bits is undefined. The status of the last fragment in the frame will copy the value for these bits from the MAC. All fragment statuses will have valid LastFrag, RxSize, Error, Overrun and NoDescriptor bits.

15.2 Transmit descriptors and statuses

Figure 10–19 depicts the layout of the transmit descriptors in memory. Transmit descriptors are stored in an array in memory. The lowest address of the transmit descriptor array is stored in the TxDescriptor register, and must be aligned on a 4 byte address boundary. The number of descriptors in the array is stored in the TxDescriptorNumber register using a minus one encoding style i.e. if the array has 8 elements the register value should be 7. Parallel to the descriptors there is an array of statuses. For each element of the descriptor array there is an associated status field in the status array. The base address of the status array is stored in the TxStatus register, and must be aligned on a 4 byte address boundary. During operation (when the transmit data path is enabled) the TxDescriptor, TxStatus, and TxDescriptorNumber registers should not be modified. Fig 19. Transmit descriptor memory layout StatusInfo StatusInfo StatusInfo StatusInfo StatusInfo StatusInfo PACKET CONTROL PACKET CONTROL PACKET CONTROL PACKET CONTROL PACKET CONTROL PACKET CONTROL TxStatus TxDescriptorNumber TxDescriptor DATA BUFFER DATA BUFFER DATA BUFFER DATA BUFFER DATA BUFFER DATA BUFFER

UM10360_1 © NXP B.V. 2010. All rights reserved. contains the index of the next descriptor that is going to be filled by the software driver. the hardware. When TxProduceIndex == TxConsumeIndex, the transmit buffer is empty. hardware has transmitted one or more frames to free up descriptors. pointer to the data buffer containing transmit data (Packet) and a control word (Control). Table 10–181 shows the one field transmit status. Table 179. Transmit descriptor fields Packet 0x0 4 Base address of the data buffer containing transmit data. Control 0x4 4 Control information, see Table 10–180. Table 180. Transmit descriptor control word is -1 encoded e.g. a buffer of 8 bytes is encoded as the Size value 7. prevents transmission of more than the maximum frame length (MAXF[15:0]). 28 Pad If true, pad short frames to 64 bytes. 29 CRC If true, append a hardware CRC to the frame.

30 Last If true, indicates that this is the descriptor for the last fragment in the transmit

frame. If false, the fragment from the next descriptor should be appended.

31 Interrupt If true, a TxDone interrupt will be generated when the data in this frame or

Table 181. Transmit status fields StatusInfo 0x0 4 Transmit status return flags, see Table 10–182.

UM10360_1 © NXP B.V. 2010. All rights reserved. the transmission. Table 10–182 lists the bit definitions in the StatusInfo word. MAC. All fragment statuses will have valid Error, NoDescriptor and Underrun bits.

Ethernet block functional description

control, receive filtering, etc.

16.1 Overview

PHY connected through the RMII interface. arrays as well as the receiver fragment buffers. communication with the target, if debug mode is being used. Table 182. Transmit status information word 25 Defer This packet incurred deferral, because the medium was occupied. This is not an error unless excessive deferral occurs.

26 ExcessiveDefer This packet incurred deferral beyond the maximum deferral limit and

27 ExcessiveCollision Indicates this packet exceeded the maximum collision limit and was

28 LateCollision An Out of window Collision was seen, causing packet abort.

29 Underrun A Tx underrun occurred due to the adapter not producing transmit

30 NoDescriptor The transmit stream was interrupted because a descriptor was not

Underrun, LateCollision, ExcessiveCollision, and ExcessiveDefer.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 176 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet To transmit a packet the software driver has to set up the appropriate Control registers and a descriptor to point to the packet data buffer before transferring the packet to hardware by incrementing the TxProduceIndex register. After transmission, hardware will increment TxConsumeIndex and optionally generate an interrupt. The hardware will receive packets from the PHY and apply filtering as configured by the software driver. While receiving a packet the hardware will read a descriptor from memory to find the location of the associated receiver data buffer. Receive data is written in the data buffer and receive status is returned in the receive descriptor status word. Optionally an interrupt can be generated to notify software that a packet has been received. Note that the DMA manager will prefetch and buffer up to three descriptors.

16.2 AHB interface

The registers of the Ethernet block connect to an AHB slave interface to allow access to the registers from the CPU. The AHB interface has a 32-bit data path, which supports only word accesses and has an address aperture of 4 kB. Table 10–127 lists the registers of the Ethernet block. All AHB write accesses to registers are posted except for accesses to the IntSet, IntClear and IntEnable registers. AHB write operations are executed in order. If the PowerDown bit of the PowerDown register is set, all AHB read and write accesses will return a read or write error except for accesses to the PowerDown register. Bus Errors The Ethernet block generates errors for several conditions:

The AHB interface will return a read error when there is an AHB read access to a write-only register; likewise a write error is returned when there is an AHB write access to the read-only register. An AHB read or write error will be returned on AHB read or write accesses to reserved registers. These errors are propagated back to the CPU. Registers defined as read-only and write-only are identified in Table 10–127.
If the PowerDown bit is set all accesses to AHB registers will result in an error response except for accesses to the PowerDown register. 17. Interrupts The Ethernet block has a single interrupt request output to the CPU (via the NVIC). The interrupt service routine must read the IntStatus register to determine the origin of the interrupt. All interrupt statuses can be set by software writing to the IntSet register; statuses can be cleared by software writing to the IntClear register. The transmit and receive data paths can only set interrupt statuses, they cannot clear statuses. The SoftInt interrupt cannot be set by hardware and can be used by software for test purposes.

17.1 Direct Memory Access (DMA)

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 177 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The Ethernet block includes two DMA managers. The DMA managers make it possible to transfer frames directly to and from memory with little support from the processor and without the need to trigger an interrupt for each frame. The DMA managers work with arrays of frame descriptors and statuses that are stored in memory. The descriptors and statuses act as an interface between the Ethernet hardware and the device driver software. There is one descriptor array for receive frames and one descriptor array for transmit frames. Using buffering for frame descriptors, the memory traffic and memory bandwidth utilization of descriptors can be kept small. Each frame descriptor contains two 32-bit fields: the first field is a pointer to a data buffer containing a frame or a fragment, whereas the second field is a control word related to that frame or fragment. The software driver must write the base addresses of the descriptor and status arrays in the TxDescriptor/RxDescriptor and TxStatus/RxStatus registers. The number of descriptors/statuses in each array must be written in the TxDescriptorNumber/RxDescriptorNumber registers. The number of descriptors in an array corresponds to the number of statuses in the associated status array. Transmit descriptor arrays, receive descriptor arrays and transmit status arrays must be aligned on a 4 byte (32bit)address boundary, while the receive status array must be aligned on a 8 byte (64bit) address boundary. Ownership of descriptors Both device driver software and Ethernet hardware can read and write the descriptor arrays at the same time in order to produce and consume descriptors. A descriptor is "owned" either by the device driver or by the Ethernet hardware. Only the owner of a descriptor reads or writes its value. Typically, the sequence of use and ownership of descriptors and statuses is as follows: a descriptor is owned and set up by the device driver; ownership of the descriptor/status is passed by the device driver to the Ethernet block, which reads the descriptor and writes information to the status field; the Ethernet block passes ownership of the descriptor back to the device driver, which uses the status information and then recycles the descriptor to be used for another frame. Software must pre-allocate the memory used to hold the descriptor arrays. Software can hand over ownership of descriptors and statuses to the hardware by incrementing (and wrapping if on the array boundary) the TxProduceIndex/RxConsumeIndex registers. Hardware hands over descriptors and status to software by updating the TxConsumeIndex/ RxProduceIndex registers. After handing over a descriptor to the receive and transmit DMA hardware, device driver software should not modify the descriptor or reclaim the descriptor by decrementing the TxProduceIndex/ RxConsumeIndex registers because descriptors may have been prefetched by the hardware. In this case the device driver software will have to wait until the frame has been transmitted or the device driver has to soft-reset the transmit and/or receive data paths which will also reset the descriptor arrays. Sequential order with wrap-around When descriptors are read from and statuses are written to the arrays, this is done in sequential order with wrap-around. Sequential order means that when the Ethernet block has finished reading/writing a descriptor/status, the next descriptor/status it reads/writes is

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 178 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet the one at the next higher, adjacent memory address. Wrap around means that when the Ethernet block has finished reading/writing the last descriptor/status of the array (with the highest memory address), the next descriptor/status it reads/writes is the first descriptor/status of the array at the base address of the array. Full and Empty state of descriptor arrays The descriptor arrays can be empty, partially full or full. A descriptor array is empty when all descriptors are owned by the producer. A descriptor array is partially full if both producer and consumer own part of the descriptors and both are busy processing those descriptors. A descriptor array is full when all descriptors (except one) are owned by the consumer, so that the producer has no more room to process frames. Ownership of descriptors is indicated with the use of a consume index and a produce index. The produce index is the first element of the array owned by the producer. It is also the index of the array element that is next going to be used by the producer of frames (it may already be busy using it and subsequent elements). The consume index is the first element of the array that is owned by the consumer. It is also the number of the array element next to be consumed by the consumer of frames (it and subsequent elements may already be in the process of being consumed). If the consume index and the produce index are equal, the descriptor array is empty and all array elements are owned by the producer. If the consume index equals the produce index plus one, then the array is full and all array elements (except the one at the produce index) are owned by the consumer. With a full descriptor array, still one array element is kept empty, to be able to easily distinguish the full or empty state by looking at the value of the produce index and consume index. An array must have at least 2 elements to be able to indicate a full descriptor array with a produce index of value 0 and a consume index of value 1. The wrap around of the arrays is taken into account when determining if a descriptor array is full, so a produce index that indicates the last element in the array and a consume index that indicates the first element in the array, also means the descriptor array is full. When the produce index and the consume index are unequal and the consume index is not the produce index plus one (with wrap around taken into account), then the descriptor array is partially full and both the consumer and producer own enough descriptors to be able to operate actively on the descriptor array. Interrupt bit The descriptors have an Interrupt bit, which is programmed by software. When the Ethernet block is processing a descriptor and finds this bit set, it will allow triggering an interrupt (after committing status to memory) by passing the RxDoneInt or TxDoneInt bits in the IntStatus register to the interrupt output pin. If the Interrupt bit is not set in the descriptor, then the RxDoneInt or TxDoneInt are not set and no interrupt is triggered (note that the corresponding bits in IntEnable must also be set to trigger interrupts). This offers flexible ways of managing the descriptor arrays. For instance, the device driver could add 10 frames to the Tx descriptor array, and set the Interrupt bit in descriptor number 5 in the descriptor array. This would invoke the interrupt service routine before the transmit descriptor array is completely exhausted. The device driver could add another batch of frames to the descriptor array, without interrupting continuous transmission of frames. Frame fragments For maximum flexibility in frame storage, frames can be split up into multiple frame fragments with fragments located in different places in memory. In this case one descriptor is used for each frame fragment. So, a descriptor can point to a single frame or

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 179 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit frames are gathered from multiple fragments in memory and receive frames can be scattered to multiple fragments in memory. By stringing together fragments it is possible to create large frames from small memory areas. Another use of fragments is to be able to locate a frame header and frame payload in different places and to concatenate them without copy operations in the device driver. For transmissions, the Last bit in the descriptor Control field indicates if the fragment is the last in a frame; for receive frames, the LastFrag bit in the StatusInfo field of the status words indicates if the fragment is the last in the frame. If the Last(Frag) bit is 0 the next descriptor belongs to the same Ethernet frame, If the Last(Frag) bit is 1 the next descriptor is a new Ethernet frame.

17.2 Initialization

After reset, the Ethernet software driver needs to initialize the Ethernet block. During initialization the software needs to:

Remove the soft reset condition from the MAC
Configure the PHY via the MIIM interface of the MAC. Remark: it is important to configure the PHY and insure that reference clocks (ENET_REF_CLK signal in RMII mode, or both ENET_RX_CLK and ENET_TX_CLK signals in MII mode) are present at the external pins and connected to the EMAC module (selecting the appropriate pins using the PINSEL registers) prior to continuing with Ethernet configuration. Otherwise the CPU can become locked and no further functionality will be possible. This will cause JTAG lose communication with the target, if debug mode is being used.
Select RMII mode
Configure the transmit and receive DMA engines, including the descriptor arrays
Configure the host registers (MAC1,MAC2 etc.) in the MAC
Enable the receive and transmit data paths Depending on the PHY , the software needs to initialize registers in the PHY via the MII Management interface. The software can read and write PHY registers by programming the MCFG, MCMD, MADR registers of the MAC. Write data should be written to the MWTD register; read data and status information can be read from the MRDD and MIND registers. The Ethernet block supports RMII PHYs. During initialization software must select RMII mode by programming the Command register. Before switching to RMII mode the default soft reset (MAC1 register bit 15) has to be de-asserted. The phy_ref_clk must be running and internally connected during this operation. Transmit and receive DMA engines should be initialized by the device driver by allocating the descriptor and status arrays in memory. Transmit and receive functions have their own dedicated descriptor and status arrays. The base addresses of these arrays need to be programmed in the TxDescriptor/TxStatus and RxDescriptor/RxStatus registers. The number of descriptors in an array matches the number of statuses in an array.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 180 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Please note that the transmit descriptors, receive descriptors and receive statuses are 8 bytes each while the transmit statuses are 4 bytes each. All descriptor arrays and transmit statuses need to be aligned on 4 byte boundaries; receive status arrays need to be aligned on 8 byte boundaries. The number of descriptors in the descriptor arrays needs to be written to the TxDescriptorNumber/RxDescriptorNumber registers using a -1 encoding i.e. the value in the registers is the number of descriptors minus one e.g. if the descriptor array has 4 descriptors the value of the number of descriptors register should be 3. After setting up the descriptor arrays, frame buffers need to be allocated for the receive descriptors before enabling the receive data path. The Packet field of the receive descriptors needs to be filled with the base address of the frame buffer of that descriptor. Amongst others the Control field in the receive descriptor needs to contain the size of the data buffer using -1 encoding. The receive data path has a configurable filtering function for discarding/ignoring specific Ethernet frames. The filtering function should also be configured during initialization. After an assertion of the hardware reset, the soft reset bit in the MAC will be asserted. The soft reset condition must be removed before the Ethernet block can be enabled. Enabling of the receive function is located in two places. The receive DMA manager needs to be enabled and the receive data path of the MAC needs to be enabled. To prevent overflow in the receive DMA engine the receive DMA engine should be enabled by setting the RxEnable bit in the Command register before enabling the receive data path in the MAC by setting the RECEIVE ENABLE bit in the MAC1 register. The transmit DMA engine can be enabled at any time by setting the TxEnable bit in the Command register. Before enabling the data paths, several options can be programmed in the MAC, such as automatic flow control, transmit to receive loop-back for verification, full/half duplex modes, etc. Base addresses of descriptor arrays and descriptor array sizes cannot be modified without a (soft) reset of the receive and transmit data paths.

17.3 Transmit process

This section outlines the transmission process. Device driver sets up descriptors and data If the descriptor array is full the device driver should wait for the descriptor arrays to become not full before writing to a descriptor in the descriptor array. If the descriptor array is not full, the device driver should use the descriptor numbered TxProduceIndex of the array pointed to by TxDescriptor. The Packet pointer in the descriptor is set to point to a data frame or frame fragment to be transmitted. The Size field in the Command field of the descriptor should be set to the number of bytes in the fragment buffer, -1 encoded. Additional control information can be indicated in the Control field in the descriptor (bits Interrupt, Last, CRC, Pad).

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 181 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet After writing the descriptor the descriptor needs to be handed over to the hardware by incrementing (and possibly wrapping) the TxProduceIndex register. If the transmit data path is disabled, the device driver should not forget to enable the transmit data path by setting the TxEnable bit in the Command register. When there is a multi-fragment transmission for fragments other than the last, the Last bit in the descriptor must be set to 0; for the last fragment the Last bit must be set to 1. To trigger an interrupt when the frame has been transmitted and transmission status has been committed to memory, set the Interrupt bit in the descriptor Control field to 1. To have the hardware add a CRC in the frame sequence control field of this Ethernet frame, set the CRC bit in the descriptor. This should be done if the CRC has not already been added by software. To enable automatic padding of small frames to the minimum required frame size, set the Pad bit in the Control field of the descriptor to 1. In typical applications bits CRC and Pad are both set to 1. The device driver can set up interrupts using the IntEnable register to wait for a signal of completion from the hardware or can periodically inspect (poll) the progress of transmission. It can also add new frames at the end of the descriptor array, while hardware consumes descriptors at the start of the array. The device driver can stop the transmit process by resetting the TxEnable bit in the Command register to 0. The transmission will not stop immediately; frames already being transmitted will be transmitted completely and the status will be committed to memory before deactivating the data path. The status of the transmit data path can be monitored by the device driver reading the TxStatus bit in the Status register. As soon as the transmit data path is enabled and the corresponding TxConsumeIndex and TxProduceIndex are not equal i.e. the hardware still needs to process frames from the descriptor array, the TxStatus bit in the Status register will return to 1 (active). Tx DMA manager reads the Tx descriptor array When the TxEnable bit is set, the Tx DMA manager reads the descriptors from memory at the address determined by TxDescriptor and TxConsumeIndex. The number of descriptors requested is determined by the total number of descriptors owned by the hardware: TxProduceIndex - TxConsumeIndex. Block transferring descriptors minimizes memory loading. Read data returned from memory is buffered and consumed as needed. Tx DMA manager transmits data After reading the descriptor the transmit DMA engine reads the associated frame data from memory and transmits the frame. After transfer completion, the Tx DMA manager writes status information back to the StatusInfo and StatusHashCRC words of the status field. The value of the TxConsumeIndex is only updated after status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. The Tx DMA manager continues to transmit frames until the descriptor array is empty. If the transmit descriptor array is empty the TxStatus bit in the Status register will return to 0 (inactive). If the descriptor array is empty the Ethernet hardware will set the TxFinishedInt bit of the IntStatus register. The transmit data path will still be enabled. The Tx DMA manager inspects the Last bit of the descriptor Control field when loading the descriptor. If the Last bit is 0, this indicates that the frame consists of multiple fragments. The Tx DMA manager gathers all the fragments from the host memory, visiting a string of

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 182 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet frame descriptors, and sends them out as one Ethernet frame on the Ethernet connection. When the Tx DMA manager finds a descriptor with the Last bit in the Control field set to 1, this indicates the last fragment of the frame and thus the end of the frame is found. Update ConsumeIndex Each time the Tx DMA manager commits a status word to memory it completes the transmission of a descriptor and it increments the TxConsumeIndex (taking wrap around into account) to hand the descriptor back to the device driver software. Software can re-use the descriptor for new transmissions after hardware has handed it back. The device driver software can keep track of the progress of the DMA manager by reading the TxConsumeIndex register to see how far along the transmit process is. When the Tx descriptor array is emptied completely, the TxConsumeIndex register retains its last value. Write transmission status After the frame has been transmitted over the RMII bus, the StatusInfo word of the frame descriptor is updated by the DMA manager. If the descriptor is for the last fragment of a frame (or for the whole frame if there are no fragments), then depending on the success or failure of the frame transmission, error flags (Error, LateCollision, ExcessiveCollision, Underrun, ExcessiveDefer, Defer) are set in the status. The CollisionCount field is set to the number of collisions the frame incurred, up to the Retransmission Maximum programmed in the Collision window/retry register of the MAC. Statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the Tx DMA manager. Even if the descriptor is for a frame fragment other than the last fragment, the error flags are returned via the AHB interface. If the Ethernet block detects a transmission error during transmission of a (multi-fragment) frame, all remaining fragments of the frame are still read via the AHB interface. After an error, the remaining transmit data is discarded by the Ethernet block. If there are errors during transmission of a multi-fragment frame the error statuses will be repeated until the last fragment of the frame. Statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the Tx DMA manager. These may include error information if the error is detected early enough. The status for the last fragment in the frame will only be written after the transmission has completed on the Ethernet connection. Thus, the status for the last fragment will always reflect any error that occurred anywhere in the frame. The status of the last frame transmission can also be inspected by reading the TSV0 and TSV1 registers. These registers do not report statuses on a fragment basis and do not store information of previously sent frames. They are provided primarily for debug purposes, because the communication between driver software and the Ethernet block takes place through the frame descriptors. The status registers are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted. Transmission error handling If an error occurs during the transmit process, the Tx DMA manager will report the error via the transmission StatusInfo word written in the Status array and the IntStatus interrupt status register.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 183 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The transmission can generate several types of errors: LateCollision, ExcessiveCollision, ExcessiveDefer, Underrun, and NoDescriptor. All have corresponding bits in the transmission StatusInfo word. In addition to the separate bits in the StatusInfo word, LateCollision, ExcessiveCollision, and ExcessiveDefer are ORed together into the Error bit of the Status. Errors are also propagated to the IntStatus register; the TxError bit in the IntStatus register is set in the case of a LateCollision, ExcessiveCollision, ExcessiveDefer, or NoDescriptor error; Underrun errors are reported in the TxUnderrun bit of the IntStatus register. Underrun errors can have three causes:

The next fragment in a multi-fragment transmission is not available. This is a nonfatal error. A NoDescriptor status will be returned on the previous fragment and the TxError bit in IntStatus will be set.
The transmission fragment data is not available when the Ethernet block has already started sending the frame. This is a nonfatal error. An Underrun status will be returned on transfer and the TxError bit in IntStatus will be set.
The flow of transmission statuses stalls and a new status has to be written while a previous status still waits to be transferred across the memory interface. This is a fatal error which can only be resolved by a soft reset of the hardware. The first and second situations are nonfatal and the device driver has to re-send the frame or have upper software layers re-send the frame. In the third case the hardware is in an undefined state and needs to be soft reset by setting the TxReset bit in the Command register. After reporting a LateCollision, ExcessiveCollision, ExcessiveDefer or Underrun error, the transmission of the erroneous frame will be aborted, remaining transmission data and frame fragments will be discarded and transmission will continue with the next frame in the descriptor array. Device drivers should catch the transmission errors and take action. Transmit triggers interrupts The transmit data path can generate four different interrupt types:
If the Interrupt bit in the descriptor Control field is set, the Tx DMA will set the TxDoneInt bit in the IntStatus register after sending the fragment and committing the associated transmission status to memory. Even if a descriptor (fragment) is not the last in a multi-fragment frame the Interrupt bit in the descriptor can be used to generate an interrupt.
If the descriptor array is empty while the Ethernet hardware is enabled the hardware will set the TxFinishedInt bit of the IntStatus register.
If the AHB interface does not consume the transmission statuses at a sufficiently high bandwidth the transmission may underrun in which case the TxUnderrun bit will be set in the IntStatus register. This is a fatal error which requires a soft reset of the transmission queue.

In the case of a transmission error (LateCollision, ExcessiveCollision, or ExcessiveDefer) or a multi-fragment frame where the device driver did provide the initial fragments but did not provide the rest of the fragments (NoDescriptor) or in the case of a nonfatal overrun, the hardware will set the TxErrorInt bit of the IntStatus register. All of the above interrupts can be enabled and disabled by setting or resetting the corresponding bits in the IntEnable register. Enabling or disabling does not affect the IntStatus register contents, only the propagation of the interrupt status to the CPU (via the NVIC). The interrupts, either of individual frames or of the whole list, are a good means of communication between the DMA manager and the device driver, triggering the device driver to inspect the status words of descriptors that have been processed. Transmit example Figure 10–20 illustrates the transmit process in an example transmitting uses a frame header of 8 bytes and a frame payload of 12 bytes. After reset the values of the DMA registers will be zero. During initialization the device driver will allocate the descriptor and status array in memory. In this example, an array of four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address Fig 20. Transmit example memory and registers StatusInfo StatusInfo StatusInfo StatusInfo Packet 0x20081314 TxStatus 0x200811F8 TxDescriptor 0x200810EC 0x200810EC 0x200810F0 0x200810F4 0x200810F8 0x200810FC 0x20081100 0x20081104 0x20081108 0x200811F8 0x200811FC 0x20081200 0x20081204 Packet 0x20081411 Packet 0x20081419 Packet 0x20081324 descriptor array descriptor 0descriptor 1descriptor 2descriptor 3 descriptor array fragment buffers TxProduceIndex TxConsumeIndex TxDescriptorNumber = 3 status 1 status 0statu s 3 statu s 2 status array status array PACKET 1 HEADER (8 bytes) PACKET 0 PAYLOAD (12 bytes) PACKET 0 HEADER (8 bytes) 00 7ControlCONTROL 00 7ControlCONTROL 11 3ControlCONTROL 00 7ControlCONTROL 0x20081314 0x2008131B 0x20081411 0x20081419 0x2008141C 0x20081324 0x2008132B

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 185 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet boundary. Since the number of descriptors matches the number of statuses the status array consists of four elements; the array is 4x1x4 bytes and aligned on a 4 byte address boundary. The device driver writes the base address of the descriptor array (0x2008 10EC) to the TxDescriptor register and the base address of the status array (0x2008 11F8) to the TxStatus register. The device driver writes the number of descriptors and statuses minus 1(3) to the TxDescriptorNumber register. The descriptors and statuses in the arrays need not be initialized, yet. At this point, the transmit data path may be enabled by setting the TxEnable bit in the Command register. If the transmit data path is enabled while there are no further frames to send the TxFinishedInt interrupt flag will be set. To reduce the processor interrupt load only the desired interrupts can be enabled by setting the relevant bits in the IntEnable register. Now suppose application software wants to transmit a frame of 12 bytes using a TCP/IP protocol (in real applications frames will be larger than 12 bytes). The TCP/IP stack will add a header to the frame. The frame header need not be immediately in front of the payload data in memory. The device driver can program the Tx DMA to collect header and payload data. To do so, the device driver will program the first descriptor to point at the frame header; the Last flag in the descriptor will be set to false/0 to indicate a multi-fragment transmission. The device driver will program the next descriptor to point at the actual payload data. The maximum size of a payload buffer is 2 kB so a single descriptor suffices to describe the payload buffer. For the sake of the example though the payload is distributed across two descriptors. After the first descriptor in the array describing the header, the second descriptor in the array describes the initial 8 bytes of the payload; the third descriptor in the array describes the remaining 4 bytes of the frame. In the third descriptor the Last bit in the Control word is set to true/1 to indicate it is the last descriptor in the frame. In this example the Interrupt bit in the descriptor Control field is set in the last fragment of the frame in order to trigger an interrupt after the transmission completed. The Size field in the descriptor’s Control word is set to the number of bytes in the fragment buffer, -1 encoded. Note that in real device drivers, the payload will typically only be split across multiple descriptors if it is more than 2 kB. Also note that transmission payload data is forwarded to the hardware without the device driver copying it (zero copy device driver). After setting up the descriptors for the transaction the device driver increments the TxProduceIndex register by 3 since three descriptors have been programmed. If the transmit data path was not enabled during initialization the device driver needs to enable the data path now. If the transmit data path is enabled the Ethernet block will start transmitting the frame as soon as it detects the TxProduceIndex is not equal to TxConsumeIndex - both were zero after reset. The Tx DMA will start reading the descriptors from memory. The memory system will return the descriptors and the Ethernet block will accept them one by one while reading the transmit data fragments. As soon as transmission read data is returned from memory, the Ethernet block will try to start transmission on the Ethernet connection via the RMII interface.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 186 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet After transmitting each fragment of the frame the Tx DMA will write the status of the fragment’s transmission. Statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the Tx DMA manager. The status for the last fragment in the frame will only be written after the transmission has completed on the Ethernet connection. Since the Interrupt bit in the descriptor of the last fragment is set, after committing the status of the last fragment to memory the Ethernet block will trigger a TxDoneInt interrupt, which triggers the device driver to inspect the status information. In this example the device driver cannot add new descriptors as long as the Ethernet block has not incremented the TxConsumeIndex because the descriptor array is full (even though one descriptor is not programmed yet). Only after the hardware commits the status for the first fragment to memory and the TxConsumeIndex is set to 1 by the DMA manager can the device driver program the next (the fourth) descriptor. The fourth descriptor can already be programmed before completely transmitting the first frame. In this example the hardware adds the CRC to the frame. If the device driver software adds the CRC, the CRC trailer can be considered another frame fragment which can be added by doing another gather DMA. Each data byte is transmitted across the RMII interface as four 2-bit values. The Ethernet block adds the preamble, frame delimiter leader, and the CRC trailer if hardware CRC is enabled. Once transmission on the RMII interface commences the transmission cannot be interrupted without generating an underrun error, which is why descriptors and data read commands are issued as soon as possible and pipelined. Using an RMII PHY , the data communication between the Ethernet block and the PHY is communicated at 50 MHz. In 10 Mbps mode data will only be transmitted once every 10 clock cycles.

17.4 Receive process

This section outlines the receive process including the activities in the device driver software. Device driver sets up descriptors After initializing the receive descriptor and status arrays to receive frames from the Ethernet connection, the receive data path should be enabled in the MAC1 register and the Control register. During initialization, each Packet pointer in the descriptors is set to point to a data fragment buffer. The size of the buffer is stored in the Size bits of the Control field of the descriptor. Additionally, the Control field in the descriptor has an Interrupt bit. The Interrupt bit allows generation of an interrupt after a fragment buffer has been filled and its status has been committed to memory. After the initialization and enabling of the receive data path, all descriptors are owned by the receive hardware and should not be modified by the software unless hardware hands over the descriptor by incrementing the RxProduceIndex, indicating that a frame has been received. The device driver is allowed to modify the descriptors after a (soft) reset of the receive data path.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 187 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Rx DMA manager reads Rx descriptor arrays When the RxEnable bit in the Command register is set, the Rx DMA manager reads the descriptors from memory at the address determined by RxDescriptor and RxProduceIndex. The Ethernet block will start reading descriptors even before actual receive data arrives on the RMII interface (descriptor prefetching). The block size of the descriptors to be read is determined by the total number of descriptors owned by the hardware: RxConsumeIndex - RxProduceIndex - 1. Block transferring of descriptors minimizes memory load. Read data returned from memory is buffered and consumed as needed. RX DMA manager receives data After reading the descriptor, the receive DMA engine waits for the MAC to return receive data from the RMII interface that passes the receive filter. Receive frames that do not match the filtering criteria are not passed to memory. Once a frame passes the receive filter, the data is written in the fragment buffer associated with the descriptor. The Rx DMA does not write beyond the size of the buffer. When a frame is received that is larger than a descriptor’s fragment buffer, the frame will be written to multiple fragment buffers of consecutive descriptors. In the case of a multi-fragment reception, all but the last fragment in the frame will return a status where the LastFrag bit is set to 0. Only on the last fragment of a frame the LastFrag bit in the status will be set to 1. If a fragment buffer is the last of a frame, the buffer may not be filled completely. The first receive data of the next frame will be written to the fragment buffer of the next descriptor. After receiving a fragment, the Rx DMA manager writes status information back to the StatusInfo and StatusHashCRC words of the status. The Ethernet block writes the size in bytes of a descriptor’s fragment buffer in the RxSize field of the Status word. The value of the RxProduceIndex is only updated after the fragment data and the fragment status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. The Rx DMA manager continues to receive frames until the descriptor array is full. If the descriptor array is full, the Ethernet hardware will set the RxFinishedInt bit of the IntStatus register. The receive data path will still be enabled. If the receive descriptor array is full any new receive data will generate an overflow error and interrupt. Update ProduceIndex Each time the Rx DMA manager commits a data fragment and the associated status word to memory, it completes the reception of a descriptor and increments the RxProduceIndex (taking wrap around into account) in order to hand the descriptor back to the device driver software. Software can re-use the descriptor for new receptions by handing it back to hardware when the receive data has been processed. The device driver software can keep track of the progress of the DMA manager by reading the RxProduceIndex register to see how far along the receive process is. When the Rx descriptor array is emptied completely, the RxProduceIndex retains its last value. Write reception status After the frame has been received from the RMII bus, the StatusInfo and StatusHashCRC words of the frame descriptor are updated by the DMA manager.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 188 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet If the descriptor is for the last fragment of a frame (or for the whole frame if there are no fragments), then depending on the success or failure of the frame reception, error flags (Error, NoDescriptor, Overrun, AlignmentError, RangeError, LengthError, SymbolError, or CRCError) are set in StatusInfo. The RxSize field is set to the number of bytes actually written to the fragment buffer, -1 encoded. For fragments not being the last in the frame the RxSize will match the size of the buffer. The hash CRCs of the destination and source addresses of a packet are calculated once for all the fragments belonging to the same packet and then stored in every StatusHashCRC word of the statuses associated with the corresponding fragments. If the reception reports an error, any remaining data in the receive frame is discarded and the LastFrag bit will be set in the receive status field, so the error flags in all but the last fragment of a frame will always be 0. The status of the last received frame can also be inspected by reading the RSV register. The register does not report statuses on a fragment basis and does not store information of previously received frames. RSV is provided primarily for debug purposes, because the communication between driver software and the Ethernet block takes place through the frame descriptors. Reception error handling When an error occurs during the receive process, the Rx DMA manager will report the error via the receive StatusInfo written in the Status array and the IntStatus interrupt status register. The receive process can generate several types of errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError, Overrun, and NoDescriptor. All have corresponding bits in the receive StatusInfo. In addition to the separate bits in the StatusInfo, AlignmentError, RangeError, LengthError, SymbolError, and CRCError are ORed together into the Error bit of the StatusInfo. Errors are also propagated to the IntStatus register; the RxError bit in the IntStatus register is set if there is an AlignmentError, RangeError, LengthError, SymbolError, CRCError, or NoDescriptor error; nonfatal overrun errors are reported in the RxError bit of the IntStatus register; fatal Overrun errors are report in the RxOverrun bit of the IntStatus register. On fatal overrun errors, the Rx data path needs to be soft reset by setting the RxReset bit in the Command register. Overrun errors can have three causes:

In the case of a multi-fragment reception, the next descriptor may be missing. In this case the NoDescriptor field is set in the status word of the previous descriptor and the RxError in the IntStatus register is set. This error is nonfatal.
The data flow on the receiver data interface stalls, corrupting the packet. In this case the overrun bit in the status word is set and the RxError bit in the IntStatus register is set. This error is nonfatal.
The flow of reception statuses stalls and a new status has to be written while a previous status still waits to be transferred across the memory interface. This error will corrupt the hardware state and requires the hardware to be soft reset. The error is detected and sets the Overrun bit in the IntStatus register. The first overrun situation will result in an incomplete frame with a NoDescriptor status and the RxError bit in IntStatus set. Software should discard the partially received frame. In the second overrun situation the frame data will be corrupt which results in the Overrun status bit being set in the Status word while the IntError interrupt bit is set. In the third case

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 189 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet receive errors cannot be reported in the receiver Status arrays which corrupts the hardware state; the errors will still be reported in the IntStatus register’s Overrun bit. The RxReset bit in the Command register should be used to soft reset the hardware. Device drivers should catch the above receive errors and take action. Receive triggers interrupts The receive data path can generate four different interrupt types:

If the Interrupt bit in the descriptor Control field is set, the Rx DMA will set the RxDoneInt bit in the IntStatus register after receiving a fragment and committing the associated data and status to memory. Even if a descriptor (fragment) is not the last in a multi-fragment frame, the Interrupt bit in the descriptor can be used to generate an interrupt.
If the descriptor array is full while the Ethernet hardware is enabled, the hardware will set the RxFinishedInt bit of the IntStatus register.
If the AHB interface does not consume receive statuses at a sufficiently high bandwidth, the receive status process may overrun, in which case the RxOverrun bit will be set in the IntStatus register.
If there is a receive error (AlignmentError, RangeError, LengthError, SymbolError, or CRCError), or a multi-fragment frame where the device driver did provide descriptors for the initial fragments but did not provide the descriptors for the rest of the fragments, or if a nonfatal data Overrun occurred, the hardware will set the RxErrorInt bit of the IntStatus register. All of the above interrupts can be enabled and disabled by setting or resetting the corresponding bits in the IntEnable register. Enabling or disabling does not affect the IntStatus register contents, only the propagation of the interrupt status to the CPU (via the NVIC). The interrupts, either of individual frames or of the whole list, are a good means of communication between the DMA manager and the device driver, triggering the device driver to inspect the status words of descriptors that have been processed. Device driver processes receive data As a response to status (e.g. RxDoneInt) interrupts or polling of the RxProduceIndex, the device driver can read the descriptors that have been handed over to it by the hardware (RxProduceIndex - RxConsumeIndex). The device driver should inspect the status words in the status array to check for multi-fragment receptions and receive errors. The device driver can forward receive data and status to upper software layers. After processing of data and status, the descriptors, statuses and data buffers may be recycled and handed back to hardware by incrementing the RxConsumeIndex. Receive example Figure 10–21 illustrates the receive process in an example receiving a frame of 19 bytes.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 190 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet After reset, the values of the DMA registers will be zero. During initialization, the device driver will allocate the descriptor and status array in memory. In this example, an array of four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address boundary. Since the number of descriptors matches the number of statuses, the status array consists of four elements; the array is 4x2x4 bytes and aligned on a 8 byte address boundary. The device driver writes the base address of the descriptor array (0x2008 10EC) in the RxDescriptor register, and the base address of the status array (0x2008 11F8) in the RxStatus register. The device driver writes the number of descriptors and statuses minus 1 (3) in the RxDescriptorNumber register. The descriptors and statuses in the arrays need not be initialized yet. After allocating the descriptors, a fragment buffer needs to be allocated for each of the descriptors. Each fragment buffer can be between 1 byte and 2 k bytes. The base address of the fragment buffer is stored in the Packet field of the descriptors. The number of bytes in the fragment buffer is stored in the Size field of the descriptor Control word. The Interrupt field in the Control word of the descriptor can be set to generate an interrupt as soon as the descriptor has been filled by the receive process. In this example the fragment buffers are 8 bytes, so the value of the Size field in the Control word of the descriptor is set to 7. Note that in this example, the fragment buffers are actually a Fig 21. Receive Example Memory and Registers PACKET 0x20081409 RxStatus 0x200811F8 RxDescriptor 0x200810EC 0x200810EC 0x200810F0 0x200810F4 0x200810F8 0x200810FC 0x20081100 0x20081104 0x20081108 0x200811F8 0x20081200 0x20081208 0x20081210 PACKET 0x20081411 PACKET 0x20081419 PACKET 0x20081325 descriptor array De script or 0Descriptor 1Descriptor 2Descriptor 3 descriptor array fragment buffers RxProduceIndex RxConsumeIndex RxDescriptorNumber = 3 Status 1 Status 0Status 3 Status 2 status array status array FRAGMENT 1 BUFFER (8 bytes) FRAGMENT 0 BUFFER (8 bytes) FRAGMENT 2 BUFFER (3 bytes) FRAGMENT 3 BUFFER (8 bytes) 17CONTROL

17 CONTROL

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 191 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet continuous memory space; even when a frame is distributed over multiple fragments it will typically be in a linear, continuous memory space; when the descriptors wrap at the end of the descriptor array the frame will not be in a continuous memory space. The device driver should enable the receive process by writing a 1 to the RxEnable bit of the Command register, after which the MAC needs to be enabled by writing a 1 to the ‘RECEIVE ENABLE’ bit of the MAC1 configuration register. The Ethernet block will now start receiving Ethernet frames. To reduce the processor interrupt load, some interrupts can be disabled by setting the relevant bits in the IntEnable register. After the Rx DMA manager is enabled, it will start issuing descriptor read commands. In this example the number of descriptors is 4. Initially the RxProduceIndex and RxConsumeIndex are 0. Since the descriptor array is considered full if RxProduceIndex == RxConsumeIndex - 1, the Rx DMA manager can only read (RxConsumeIndex - RxProduceIndex - 1 =) 3 descriptors; note the wrapping. After enabling the receive function in the MAC, data reception will begin starting at the next frame i.e. if the receive function is enabled while the RMII interface is halfway through receiving a frame, the frame will be discarded and reception will start at the next frame. The Ethernet block will strip the preamble and start of frame delimiter from the frame. If the frame passes the receive filtering, the Rx DMA manager will start writing the frame to the first fragment buffer. Suppose the frame is 19 bytes long. Due to the buffer sizes specified in this example, the frame will be distributed over three fragment buffers. After writing the initial 8 bytes in the first fragment buffer, the status for the first fragment buffer will be written and the Rx DMA will continue filling the second fragment buffer. Since this is a multi-fragment receive, the status of the first fragment will have a 0 for the LastFrag bit in the StatusInfo word; the RxSize field will be set to 7 (8, -1 encoded). After writing the 8 bytes in the second fragment the Rx DMA will continue writing the third fragment. The status of the second fragment will be like the status of the first fragment: LastFrag = 0, RxSize = 7. After writing the three bytes in the third fragment buffer, the end of the frame has been reached and the status of the third fragment is written. The third fragment’s status will have the LastFrag bit set to 1 and the RxSize equal to 2 (3, -1 encoded). The next frame received from the RMII interface will be written to the fourth fragment buffer i.e. five bytes of the third buffer will be unused. The Rx DMA manager uses an internal tag protocol in the memory interface to check that the receive data and status have been committed to memory. After the status of the fragments are committed to memory, an RxDoneInt interrupt will be triggered, which activates the device driver to inspect the status information. In this example, all descriptors have the Interrupt bit set in the Control word i.e. all descriptors will generate an interrupt after committing data and status to memory. In this example the receive function cannot read new descriptors as long as the device driver does not increment the RxConsumeIndex, because the descriptor array is full (even though one descriptor is not programmed yet). Only after the device driver has forwarded the receive data to application software, and after the device driver has updated the RxConsumeIndex by incrementing it, will the Ethernet block can continue reading descriptors and receive data. The device driver will probably increment the RxConsumeIndex by 3, since the driver will forward the complete frame consisting of three fragments to the application, and hence free up three descriptors at the same time.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 192 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Each four pairs of bits transferred on the RMII interface are transferred as a byte on the data write interface after being delayed by 128 or 136 cycles for filtering by the receive filter and buffer modules. The Ethernet block removes preamble, frame start delimiter, and CRC from the data and checks the CRC. To limit the buffer NoDescriptor error probability, three descriptors are buffered. The value of the RxProduceIndex is only updated after status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. The software device driver will process the receive data, after which the device driver will update the RxConsumeIndex.

17.5 Transmission retry

If a collision on the Ethernet occurs, it usually takes place during the collision window spanning the first 64 bytes of a frame. If collision is detected, the Ethernet block will retry the transmission. For this purpose, the first 64 bytes of a frame are buffered, so that this data can be used during the retry. A transmission retry within the first 64 bytes in a frame is fully transparent to the application and device driver software. When a collision occurs outside of the 64 byte collision window, a LateCollision error is triggered, and the transmission is aborted. After a LateCollision error, the remaining data in the transmit frame will be discarded. The Ethernet block will set the Error and LateCollision bits in the frame’s status fields. The TxError bit in the IntStatus register will be set. If the corresponding bit in the IntEnable register is set, the TxError bit in the IntStatus register will be propagated to the CPU (via the NVIC). The device driver software should catch the interrupt and take appropriate actions. The ‘RETRANSMISSION MAXIMUM’ field of the CLRT register can be used to configure the maximum number of retries before aborting the transmission.

17.6 Status hash CRC calculations

For each received frame, the Ethernet block is able to detect the destination address and source address and from them calculate the corresponding hash CRCs. To perform the computation, the Ethernet block features two internal blocks: one is a controller synchronized with the beginning and the end of each frame, the second block is the CRC calculator. When a new frame is detected, internal signaling notifies the controller.The controller starts counting the incoming bytes of the frame, which correspond to the destination address bytes. When the sixth (and last) byte is counted, the controller notifies the calculator to store the corresponding 32-bit CRC into a first inner register. Then the controller repeats counting the next incoming bytes, in order to get synchronized with the source address. When the last byte of the source address is encountered, the controller again notifies the CRC calculator, which freezes until the next new frame. When the calculator receives this second notification, it stores the present 32-bit CRC into a second inner register. Then the CRCs remain frozen in their own registers until new notifications arise. The destination address and source address hash CRCs being written in the StatusHashCRC word are the nine most significant bits of the 32-bit CRCs as calculated by the CRC calculator.

17.7 Duplex modes

The Ethernet block can operate in full duplex and half duplex mode. Half or full duplex mode needs to be configured by the device driver software during initialization. For a full duplex connection the FullDuplex bit of the Command register needs to be set to 1 and the FULL-DUPLEX bit of the MAC2 configuration register needs to be set to 1; for half duplex the same bits need to be set to 0. 17.8 IEE 802.3/Clause 31 flow control Overview For full duplex connections, the Ethernet block supports IEEE 802.3/clause 31 flow control using pause frames. This type of flow control may be used in full-duplex point-to-point connections. Flow control allows a receiver to stall a transmitter e.g. when the receive buffers are (almost) full. For this purpose, the receiving side sends a pause frame to the transmitting side. Pause frames use units of 512 bit times corresponding to 128 rx_clk/tx_clk cycles. Receive flow control In full-duplex mode, the Ethernet block will suspend its transmissions when the it receives a pause frame. Rx flow control is initiated by the receiving side of the transmission. It is enabled by setting the ‘RX FLOW CONTROL’ bit in the MAC1 configuration register. If the RX FLOW CONTROL’ bit is zero, then the Ethernet block ignores received pause control frames. When a pause frame is received on the Rx side of the Ethernet block, transmission on the Tx side will be interrupted after the currently transmitting frame has completed, for an amount of time as indicated in the received pause frame. The transmit data path will stop transmitting data for the number of 512 bit slot times encoded in the pause-timer field of the received pause control frame. By default the received pause control frames are not forwarded to the device driver. To forward the receive flow control frames to the device driver, set the ‘PASS ALL RECEIVE FRAMES’ bit in the MAC1 configuration register. Transmit flow control If case device drivers need to stall the receive data e.g. because software buffers are full, the Ethernet block can transmit pause control frames. Transmit flow control needs to be initiated by the device driver software; there is no IEEE 802.3/31 flow control initiated by hardware, such as the DMA managers. With software flow control, the device driver can detect a situation in which the process of receiving frames needs to be interrupted by sending out Tx pause frames. Note that due to Ethernet delays, a few frames can still be received before the flow control takes effect and the receive stream stops. Transmit flow control is activated by writing 1 to the TxFlowControl bit of the Command register. When the Ethernet block operates in full duplex mode, this will result in transmission of IEEE 802.3/31 pause frames. The flow control continues until a 0 is written to TxFlowControl bit of the Command register.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 194 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet If the MAC is operating in full-duplex mode, then setting the TxFlowControl bit of the Command register will start a pause frame transmission. The value inserted into the pause-timer value field of transmitted pause frames is programmed via the PauseTimer[15:0] bits in the FlowControlCounter register. When the TxFlowControl bit is de-asserted, another pause frame having a pause-timer value of 0x0000 is automatically sent to abort flow control and resume transmission. When flow control be in force for an extended time, a sequence of pause frames must be transmitted. This is supported with a mirror counter mechanism. To enable mirror counting, a nonzero value is written to the MirrorCounter[15:0] bits in the FlowControlCounter register. When the TxFlowControl bit is asserted, a pause frame is transmitted. After sending the pause frame, an internal mirror counter is initialized to zero. The internal mirror counter starts incrementing one every 512 bit-slot times. When the internal mirror counter reaches the MirrorCounter value, another pause frame is transmitted with pause-timer value equal to the PauseTimer field from the FlowControlCounter register, the internal mirror counter is reset to zero and restarts counting. The register MirrorCounter[15:0] is usually set to a smaller value than register PauseTimer[15:0] to ensure an early expiration of the mirror counter, allowing time to send a new pause frame before the transmission on the other side can resume. By continuing to send pause frames before the transmitting side finishes counting the pause timer, the pause can be extended as long as TxFlowControl is asserted. This continues until TxFlowControl is de-asserted when a final pause frame having a pause-timer value of 0x0000 is automatically sent to abort flow control and resume transmission. To disable the mirror counter mechanism, write the value 0 to MirrorCounter field in the FlowControlCounter register. When using the mirror counter mechanism, account for time-of-flight delays, frame transmission time, queuing delays, crystal frequency tolerances, and response time delays by programming the MirrorCounter conservatively, typically about 80% of the PauseTimer value. If the software device driver sets the MirrorCounter field of the FlowControlCounter register to zero, the Ethernet block will only send one pause control frame. After sending the pause frame an internal pause counter is initialized at zero; the internal pause counter is incremented by one every 512 bit-slot times. Once the internal pause counter reaches the value of the PauseTimer register, the TxFlowControl bit in the Command register will be reset. The software device driver can poll the TxFlowControl bit to detect when the pause completes. The value of the internal counter in the flow control module can be read out via the FlowControlStatus register. If the MirrorCounter is nonzero, the FlowControlStatus register will return the value of the internal mirror counter; if the MirrorCounter is zero the FlowControlStatus register will return the value of the internal pause counter value. The device driver is allowed to dynamically modify the MirrorCounter register value and switch between zero MirrorCounter and nonzero MirrorCounter modes. Transmit flow control is enabled via the ‘TX FLOW CONTROL’ bit in the MAC1 configuration register. If the ‘TX FLOW CONTROL’ bit is zero, then the MAC will not transmit pause control frames, software must not initiate pause frame transmissions, and the TxFlowControl bit in the Command register should be zero. Transmit flow control example Figure 10–22 illustrates the transmit flow control.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 195 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet In this example, a frame is received while transmitting another frame (full duplex.) The device driver detects that some buffer might overrun and enables the transmit flow control by programming the PauseTimer and MirrorCounter fields of the FlowControlCounter register, after which it enables the transmit flow control by setting the TxFlowControl bit in the Command register. As a response to the enabling of the flow control a pause control frame will be sent after the currently transmitting frame has been transmitted. When the pause frame transmission completes the internal mirror counter will start counting bit slots; as soon as the counter reaches the value in the MirrorCounter field another pause frame is transmitted. While counting the transmit data path will continue normal transmissions. As soon as software disables transmit flow control a zero pause control frame is transmitted to resume the receive process.

17.9 Half-Duplex mode backpressure

When in half-duplex mode, backpressure can be generated to stall receive packets by sending continuous preamble that basically jams any other transmissions on the Ethernet medium. When the Ethernet block operates in half duplex mode, asserting the TxFlowControl bit in the Command register will result in applying continuous preamble on the Ethernet wire, effectively blocking traffic from any other Ethernet station on the same segment. In half duplex mode, when the TxFlowControl bit goes high, continuous preamble is sent until TxFlowControl is de-asserted. If the medium is idle, the Ethernet block begins transmitting preamble, which raises carrier sense causing all other stations to defer. In the event the transmitting of preamble causes a collision, the backpressure ‘rides through’ the collision. The colliding station backs off and then defers to the backpressure. If during backpressure, the user wishes to send a frame, the backpressure is interrupted, the frame sent and then the backpressure resumed. If TxFlowControl is asserted for longer than 3.3 ms in 10 Mbps mode or 0.33 ms in 100 Mbps mode, backpressure will cease sending preamble for several byte times to avoid the jabber limit. Fig 22. Transmit Flow Control MirrorCounter (1/515 bit slots) 4000 150 300 200 450 35025050 100 500 PauseTimer MirrorCounter TxFlowCtl clear TxFlowCtl pause control frame transmission pause control frame transmission pause control frame transmission normal transimisson normal receive normal transmission normal receiveRMII receive RMII transmit device driver register writes pause in effect

17.10 Receive filtering

Features of receive filtering The Ethernet MAC has several receive packet filtering functions that can be configured from the software driver:

Perfect address filter: allows packets with a perfectly matching station address to be identified and passed to the software driver.
Hash table filter: allows imperfect filtering of packets based on the station address.
Unicast/multicast/broadcast filtering: allows passing of all unicast, multicast, and/or broadcast packets.
Magic packet filter: detection of magic packets to generate a Wake-on-LAN interrupt. The filtering functions can be logically combined to create complex filtering functions. Furthermore, the Ethernet block can pass or reject runt packets smaller than 64 bytes; a promiscuous mode allows all packets to be passed to software. Overview The Ethernet block has the capability to filter out receive frames by analyzing the Ethernet destination address in the frame. This capability greatly reduces the load on the host system, because Ethernet frames that are addressed to other stations would otherwise need to be inspected and rejected by the device driver software, using up bandwidth, memory space, and host CPU time. Address filtering can be implemented using the perfect address filter or the (imperfect) hash filter. The latter produces a 6-bit hash code which can be used as an index into a 64 entry programmable hash table. Figure 10–23 depicts a functional view of the receive filter. At the top of the diagram the Ethernet receive frame enters the filters. Each filter is controlled by signals from control registers; each filter produces a ‘Ready’ output and a ‘Match’ output. If ‘Ready’ is 0 then the Match value is ‘don’t care’; if a filter finishes filtering then it will assert its Ready output; if the filter finds a matching frame it will assert the Match output along with the Ready output. The results of the filters are combined by logic functions into a single RxAbort output. If the RxAbort output is asserted, the frame does not need to be received. In order to reduce memory traffic, the receive data path has a buffer of 68 bytes. The Ethernet MAC will only start writing a frame to memory after 68byte delays. If the RxAbort signal is asserted during the initial 68 bytes of the frame, the frame can be discarded and removed from the buffer and not stored to memory at all, not using up receive descriptors, etc. If the RxAbort signal is asserted after the initial 68 bytes in a frame (probably due to reception of a Magic Packet), part of the frame is already written to memory and the Ethernet MAC will stop writing further data in the frame to memory; the FailFilter bit in the status word of the frame will be set to indicate that the software device driver can discard the frame immediately.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 197 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet Unicast, broadcast and multicast Generic filtering based on the type of frame (unicast, multicast or broadcast) can be programmed using the AcceptUnicastEn, AcceptMulticastEn, or AcceptBroadcastEn bits of the RxFilterCtrl register. Setting the AcceptUnicast, AcceptMulticast, and AcceptBroadcast bits causes all frames of types unicast, multicast and broadcast, respectively, to be accepted, ignoring the Ethernet destination address in the frame. To program promiscuous mode, i.e. to accept all frames, set all 3 bits to 1. Perfect address match When a frame with a unicast destination address is received, a perfect filter compares the destination address with the 6 byte station address programmed in the station address registers SA0, SA1, SA2. If the AcceptPerfectEn bit in the RxFilterCtrl register is set to 1, and the address matches, the frame is accepted. Imperfect hash filtering An imperfect filter is available, based on a hash mechanism. This filter applies a hash function to the destination address and uses the hash to access a table that indicates if the frame should be accepted. The advantage of this type of filter is that a small table can cover any possible address. The disadvantage is that the filtering is imperfect, i.e. sometimes frames are accepted that should have been discarded. Fig 23. Receive filter block diagram IMPERFECT HASH FILTER AcceptUnicastEn AcceptMulticastEn AcceptMulticastHashEn AcceptUnicastHashEn HashFilter PERFECT ADDRESS FILTER packet CRC OK? HFReady HFM atch PA R eady PAMatch RxAbortFReady FMatch RxFilterEnWoL RxFilterWoL StationAddress AcceptPerfectEn

Hash function: – The standard Ethernet cyclic redundancy check (CRC) function is calculated from the 6 byte destination address in the Ethernet frame (this CRC is calculated anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of the 32-bit CRC result are taken to form the hash. The 6-bit hash is used to access the hash table: it is used as an index in the 64-bit HashFilter register that has been programmed with accept values. If the selected accept value is 1, the frame is accepted. – The device driver can initialize the hash filter table by writing to the registers HashFilterL and HashfilterH. HashFilterL contains bits 0 through 31 of the table and HashFilterH contains bit 32 through 63 of the table. So, hash value 0 corresponds to bit 0 of the HashfilterL register and hash value 63 corresponds to bit 31 of the HashFilterH register.
Multicast and unicast – The imperfect hash filter can be applied to multicast addresses, by setting the AcceptMulticastHashEn bit in the RxFilter register to 1. – The same imperfect hash filter that is available for multicast addresses can also be used for unicast addresses. This is useful to be able to respond to a multitude of unicast addresses without enabling all unicast addresses. The hash filter can be applied to unicast addresses by setting the AcceptUnicastHashEn bit in the RxFilter register to 1. Enabling and disabling filtering The filters as defined in the sections above can be bypassed by setting the PassRxFilter bit in the Command register. When the PassRxFilter bit is set, all receive frames will be passed to memory. In this case the device driver software has to implement all filtering functionality in software. Setting the PassRxFilter bit does not affect the runt frame filtering as defined in the next section. Runt frames A frame with less than 64 bytes (or 68 bytes for VLAN frames) is shorter than the minimum Ethernet frame size and therefore considered erroneous; they might be collision fragments. The receive data path automatically filters and discards these runt frames without writing them to memory and using a receive descriptor. When a runt frame has a correct CRC there is a possibility that it is intended to be useful. The device driver can receive the runt frames with correct CRC by setting the PassRuntFrame bit of the Command register to 1.

17.11 Power management

The Ethernet block supports power management by means of clock switching. All clocks in the Ethernet core can be switched off. If Wake-up on LAN is needed, the rx_clk should not be switched off.

17.12 Wake-up on LAN

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 199 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet The Ethernet block supports power management with remote wake-up over LAN. The host system can be powered down, even including part of the Ethernet block itself, while the Ethernet block continues to listen to packets on the LAN. Appropriately formed packets can be received and recognized by the Ethernet block and used to trigger the host system to wake up from its power-down state. Wake-up of the system takes effect through an interrupt. When a wake-up event is detected, the WakeupInt bit in the IntStatus register is set. The interrupt status will trigger an interrupt if the corresponding WakeupIntEn bit in the IntEnable register is set. This interrupt should be used by system power management logic to wake up the system. While in a power-down state the packet that generates a Wake-up on LAN event is lost. There are two ways in which Ethernet packets can trigger wake-up events: generic Wake-up on LAN and Magic Packet. Magic Packet filtering uses an additional filter for Magic Packet detection. In both cases a Wake-up on LAN event is only triggered if the triggering packet has a valid CRC. Figure 10–23 shows the generation of the wake-up signal. The RxFilterWoLStatus register can be read by the software to inspect the reason for a Wake-up event. Before going to power-down the power management software should clear the register by writing the RxFilterWolClear register. NOTE: when entering in power-down mode, a receive frame might be not entirely stored into the Rx buffer. In this situation, after turning exiting power-down mode, the next receive frame is corrupted due to the data of the previous frame being added in front of the last received frame. Software drivers have to reset the receive data path just after exiting power-down mode. The following subsections describe the two Wake-up on LAN mechanisms. Filtering for WoL The receive filter functionality can be used to generate Wake-up on LAN events. If the RxFilterEnWoL bit of the RxFilterCtrl register is set, the receive filter will set the WakeupInt bit of the IntStatus register if a frame is received that passes the filter. The interrupt will only be generated if the CRC of the frame is correct. Magic Packet WoL The Ethernet block supports wake-up using Magic Packet technology (see ‘Magic Packet technology’, Advanced Micro Devices). A Magic Packet is a specially formed packet solely intended for wake-up purposes. This packet can be received, analyzed and recognized by the Ethernet block and used to trigger a wake-up event. A Magic Packet is a packet that contains in its data portion the station address repeated 16 times with no breaks or interruptions, preceded by 6 Magic Packet synchronization bytes with the value 0xFF. Other data may be surrounding the Magic Packet pattern in the data portion of the packet. The whole packet must be a well-formed Ethernet frame. The magic packet detection unit analyzes the Ethernet packets, extracts the packet address and checks the payload for the Magic Packet pattern. The address from the packet is used for matching the pattern (not the address in the SA0/1/2 registers.) A magic

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 200 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet packet only sets the wake-up interrupt status bit if the packet passes the receive filter as illustrated in Figure 10–23: the result of the receive filter is ANDed with the magic packet filter result to produce the result. Magic Packet filtering is enabled by setting the MagicPacketEnWoL bit of the RxFilterCtrl register. Note that when doing Magic Packet WoL, the RxFilterEnWoL bit in the RxFilterCtrl register should be 0. Setting the RxFilterEnWoL bit to 1 would accept all packets for a matching address, not just the Magic Packets i.e. WoL using Magic Packets is more strict. When a magic packet is detected, apart from the WakeupInt bit in the IntStatus register, the MagicPacketWoL bit is set in the RxFilterWoLStatus register. Software can reset the bit writing a 1 to the corresponding bit of the RxFilterWoLClear register. Example: An example of a Magic Packet with station address 0x11 0x22 0x33 0x44 0x55 0x66 is the following (MISC indicates miscellaneous additional data bytes in the packet): FF FF FF FF FF FF 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 <MISC> <CRC>

17.13 Enabling and disabling receive and transmit

Enabling and disabling reception After reset, the receive function of the Ethernet block is disabled. The receive function can be enabled by the device driver setting the RxEnable bit in the Command register and the “RECEIVE ENABLE’ bit in the MAC1 configuration register (in that order). The status of the receive data path can be monitored by the device driver by reading the RxStatus bit of the Status register. Figure 10–24 illustrates the state machine for the generation of the RxStatus bit.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 201 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet After a reset, the state machine is in the INACTIVE state. As soon as the RxEnable bit is set in the Command register, the state machine transitions to the ACTIVE state. As soon as the RxEnable bit is cleared, the state machine returns to the INACTIVE state. If the receive data path is busy receiving a packet while the receive data path gets disabled, the packet will be received completely, stored to memory along with its status before returning to the INACTIVE state. Also if the Receive descriptor array is full, the state machine will return to the INACTIVE state. For the state machine in Figure 10–24, a soft reset is like a hardware reset assertion, i.e. after a soft reset the receive data path is inactive until the data path is re-enabled. Enabling and disabling transmission After reset, the transmit function of the Ethernet block is disabled. The Tx transmit data path can be enabled by the device driver setting the TxEnable bit in the Command register to 1. The status of the transmit data paths can be monitored by the device driver reading the TxStatus bit of the Status register. Figure 10–25 illustrates the state machine for the generation of the TxStatus bit. Fig 24. Receive Active/Inactive state machine ACTIVE RxStatus = 1 INACTIVE RxStatus = 0 RxEnable = 1 RxEnable = 0 and not busy receiving OR RxProduceIndex = RxConsumeIndex - 1 reset xxxxxxxxxxxxxxxxxx

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 202 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet After reset, the state machine is in the INACTIVE state. As soon as the TxEnable bit is set in the Command register and the Produce and Consume indices are not equal, the state machine transitions to the ACTIVE state. As soon as the TxEnable bit is cleared and the transmit data path has completed all pending transmissions, including committing the transmission status to memory, the state machine returns to the INACTIVE state. The state machine will also return to the INACTIVE state if the Produce and Consume indices are equal again i.e. all frames have been transmitted. For the state machine in Figure 10–25, a soft reset is like a hardware reset assertion, i.e. after a soft reset the transmit data path is inactive until the data path is re-enabled.

17.14 Transmission padding and CRC

In the case of a frame of less than 60 bytes (or 64 bytes for VLAN frames), the Ethernet block can pad the frame to 64 or 68 bytes including a 4 bytes CRC Frame Check Sequence (FCS). Padding is affected by the value of the ‘AUTO DETECT PAD ENABLE’ (ADPEN), ‘VLAN PAD ENABLE’ (VLPEN) and ‘PAD/CRC ENABLE’ (PADEN) bits of the MAC2 configuration register, as well as the Override and Pad bits from the transmit descriptor Control word. CRC generation is affected by the ‘CRC ENABLE’ (CRCE) and ‘DELAYED CRC’ (DCRC) bits of the MAC2 configuration register, and the Override and CRC bits from the transmit descriptor Control word. The effective pad enable (EPADEN) is equal to the ‘PAD/CRC ENABLE’ bit from the MAC2 register if the Override bit in the descriptor is 0. If the Override bit is 1, then EPADEN will be taken from the descriptor Pad bit. Likewise the effective CRC enable (ECRCE) equals CRCE if the Override bit is 0, otherwise it equal the CRC bit from the descriptor. If padding is required and enabled, a CRC will always be appended to the padded frames. A CRC will only be appended to the non-padded frames if ECRCE is set. If EPADEN is 0, the frame will not be padded and no CRC will be added unless ECRCE is set. Fig 25. Transmit Active/I nactive state machine ACTIVE TxStatus = 1 INACTIVE TxStatus = 0 TxEnable = 1 AND TxProduceIndex <> TxConsumeIndex TxEnable = 0 and not busy transmitting OR TxProduceIndex = TxConsumeIndex reset xxxxxxxxxxxxxxxxxxxxxx

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 203 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet If EPADEN is 1, then small frames will be padded and a CRC will always be added to the padded frames. In this case if ADPEN and VLPEN are both 0, then the frames will be padded to 60 bytes and a CRC will be added creating 64 bytes frames; if VLPEN is 1, the frames will be padded to 64 bytes and a CRC will be added creating 68 bytes frames; if ADPEN is 1, while VLPEN is 0 VLAN frames will be padded to 64 bytes, non VLAN frames will be padded to 60 bytes, and a CRC will be added to padded frames, creating 64 or 68 bytes padded frames. If CRC generation is enabled, CRC generation can be delayed by four bytes by setting the DELAYED CRC bit in the MAC2 register, in order to skip proprietary header information.

17.15 Huge frames and frame length checking

The ‘HUGE FRAME ENABLE’ bit in the MAC2 configuration register can be set to 1 to enable transmission and reception of frames of any length. Huge frame transmission can be enabled on a per frame basis by setting the Override and Huge bits in the transmit descriptor Control word. When enabling huge frames, the Ethernet block will not check frame lengths and report frame length errors (RangeError and LengthError). If huge frames are enabled, the received byte count in the RSV register may be invalid because the frame may exceed the maximum size; the RxSize fields from the receive status arrays will be valid. Frame lengths are checked by comparing the length/type field of the frame to the actual number of bytes in the frame. A LengthError is reported by setting the corresponding bit in the receive StatusInfo word. The MAXF register allows the device driver to specify the maximum number of bytes in a frame. The Ethernet block will compare the actual receive frame to the MAXF value and report a RangeError in the receive StatusInfo word if the frame is larger.

17.16 Statistics counters

Generally, Ethernet applications maintain many counters that track Ethernet traffic statistics. There are a number of standards specifying such counters, such as IEEE std 802.3 / clause 30. Other standards are RFC 2665 and RFC 2233. The approach taken here is that by default all counters are implemented in software. With the help of the StatusInfo field in frame statuses, many of the important statistics events listed in the standards can be counted by software.

17.17 MAC status vectors

Transmit and receive status information as detected by the MAC are available in registers TSV0, TSV1 and RSV so that software can poll them. These registers are normally of limited use because the communication between driver software and the Ethernet block takes place primarily through frame descriptors. Statistical events can be counted by software in the device driver. However, for debug purposes the transmit and receive status vectors are made visible. They are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted.

17.18 Reset

The Ethernet block has a hard reset input which is connected to the chip reset, as well as several soft resets which can be activated by setting the appropriate bit(s) in registers. All registers in the Ethernet block have a value of 0 after a hard reset, unless otherwise specified. Hard reset After a hard reset, all registers will be set to their default value. Soft reset Parts of the Ethernet block can be soft reset by setting bits in the Command register and the MAC1 configuration register.The MAC1 register has six different reset bits:

SOFT RESET: Setting this bit will put all modules in the MAC in reset, except for the MAC registers (at addresses 0x000 to 0x0FC). The value of the soft reset after a hardware reset assertion is 1, i.e. the soft reset needs to be cleared after a hardware reset.
SIMULATION RESET: Resets the random number generator in the Transmit Function. The value after a hardware reset assertion is 0.
RESET MCS/Rx: Setting this bit will reset the MAC Control Sublayer (pause frame logic) and the receive function in the MAC. The value after a hardware reset assertion is 0.
RESET Rx: Setting this bit will reset the receive function in the MAC. The value after a hardware reset assertion is 0.
RESET MCS/Tx: Setting this bit will reset the MAC Control Sublayer (pause frame logic) and the transmit function in the MAC. The value after a hardware reset assertion is 0.
RESET Tx: Setting this bit will reset the transmit function of the MAC. The value after a hardware reset assertion is 0. The above reset bits must be cleared by software. The Command register has three different reset bits:
TxReset: Writing a ‘1’ to the TxReset bit will reset the transmit data path, excluding the MAC portions, including all (read-only) registers in the transmit data path, as well as the TxProduceIndex register in the host registers module. A soft reset of the transmit data path will abort all AHB transactions of the transmit data path. The reset bit will be cleared autonomously by the Ethernet block. A soft reset of the Tx data path will clear the TxStatus bit in the Status register.
RxReset: Writing a ‘1’ to the RxReset bit will reset the receive data path, excluding the MAC portions, including all (read-only) registers in the receive data path, as well as the RxConsumeIndex register in the host registers module. A soft reset of the receive data path will abort all AHB transactions of the receive data path. The reset bit will be cleared autonomously by the Ethernet block. A soft reset of the Rx data path will clear the RxStatus bit in the Status register.

RegReset: Resets all of the data paths and registers in the host registers module, excluding the registers in the MAC. A soft reset of the registers will also abort all AHB transactions of the transmit and receive data path. The reset bit will be cleared autonomously by the Ethernet block. To do a full soft reset of the Ethernet block, device driver software must:
Set the ‘SOFT RESET’ bit in the MAC1 register to 1.
Set the RegReset bit in the Command register, this bit clears automatically.
Re-initialize the MAC registers (0x000 to 0x0FC).
Reset the ‘SOFT RESET’ bit in the MAC1 register to 0. To reset just the transmit data path, the device driver software has to:
Set the ‘RESET MCS/Tx’ bit in the MAC1 register to 1.
Disable the Tx DMA managers by setting the TxEnable bits in the Command register to 0.
Set the TxReset bit in the Command register, this bit clears automatically.
Reset the ‘RESET MCS/Tx’ bit in the MAC1 register to 0. To reset just the receive data path, the device driver software has to:
Disable the receive function by resetting the ‘RECEIVE ENABLE’ bit in the MAC1 configuration register and resetting of the RxEnable bit of the Command register.
Set the ‘RESET MCS/Rx’ bit in the MAC1 register to 1.
Set the RxReset bit in the Command register, this bit clears automatically.
Reset the ‘RESET MCS/Rx’ bit in the MAC1 register to 0.

17.19 Ethernet errors

The Ethernet block generates errors for the following conditions:

A reception can cause an error: AlignmentError, RangeError, LengthError, SymbolError, CRCError, NoDescriptor, or Overrun. These are reported back in the receive StatusInfo and in the interrupt status register (IntStatus).
A transmission can cause an error: LateCollision, ExcessiveCollision, ExcessiveDefer, NoDescriptor, or Underrun. These are reported back in the transmission StatusInfo and in the interrupt status register (IntStatus).

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 206 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 18. AHB bandwidth The Ethernet block is connected to an AHB bus which must carry all of the data and control information associated with all Ethernet traffic in addition to the CPU accesses required to operate the Ethernet block and deal with message contents.

18.1 DMA access

By making some assumptions, the bandwidth needed for each type of AHB transfer can be calculated and added in order to find the overall bandwidth requirement. The flexibility of the descriptors used in the Ethernet block allows the possibility of defining memory buffers in a range of sizes. In order to analyze bus bandwidth requirements, some assumptions must be made about these buffers. The "worst case" is not addressed since that would involve all descriptors pointing to single byte buffers, with most of the memory occupied in holding descriptors and very little data. It can easily be shown that the AHB cannot handle the huge amount of bus traffic that would be caused by such a degenerate (and illogical) case. For this analysis, an Ethernet packet is assumed to consist of a 64 byte frame. Continuous traffic is assumed on both the transmit and receive channels. This analysis does not reflect the flow of Ethernet traffic over time, which would include inter-packet gaps in both the transmit and receive channels that reduce the bandwidth requirements over a larger time frame. Types of DMA access and their bandwidth requirements The interface to an external Ethernet PHY is via RMII. RMII operates at 50 MHz, transferring a byte in 4 clock cycles. The data transfer rate is 12.5 Mbps. The Ethernet block initiates DMA accesses for the following cases:

Tx descriptor read: – Transmit descriptors occupy 2 words (8 bytes) of memory and are read once for each use of a descriptor. – Two word read happens once every 64 bytes (16 words) of transmitted data. – This gives 1/8th of the data rate, which = 1.5625 Mbps.
Rx descriptor read: – Receive descriptors occupy 2 words (8 bytes) of memory and are read once for each use of a descriptor. – Two word read happens once every 64 bytes (16 words) of received data. – This gives 1/8th of the data rate, which = 1.5625 Mbps.
Tx status write: – Transmit status occupies 1 word (4 bytes) of memory and is written once for each use of a descriptor. – One word write happens once every 64 bytes (16 words) of transmitted data. – This gives 1/16th of the data rate, which = 0.7813 Mbps.

Rx status write: – Receive status occupies 2 words (8 bytes) of memory and is written once for each use of a descriptor. – Two word write happens once every 64 bytes (16 words) of received data. – This gives 1/8 of the data rate, which = 1.5625 Mbps.
Tx data read: – Data transmitted in an Ethernet frame, the size is variable. – Basic Ethernet rate = 12.5 Mbps.
Rx data write: – Data to be received in an Ethernet frame, the size is variable. – Basic Ethernet rate = 12.5 Mbps. This gives a total rate of 30.5 Mbps for the traffic generated by the Ethernet DMA function.

18.2 Types of CPU access

Accesses that mirror each of the DMA access types: – All or part of status values must be read, and all or part of descriptors need to be written after each use, transmitted data must be stored in the memory by the CPU, and eventually received data must be retrieved from the memory by the CPU. – This gives roughly the same or slightly lower rate as the combined DMA functions, which = 30.5 Mbps.
Access to registers in the Ethernet block: – The CPU must read the RxProduceIndex, TxConsumeIndex, and IntStatus registers, and both read and write the RxConsumeIndex and TxProduceIndex registers. – 7 word read/writes once every 64 bytes (16 words) of transmitted and received data. – This gives 7/16 of the data rate, which = 5.4688 Mbps. This gives a total rate of 36 Mbps for the traffic generated by the Ethernet DMA function.

18.3 Overall bandwidth

Overall traffic on the AHB is the sum of DMA access rates and CPU access rates, which comes to approximately 66.5 MB/s. The peak bandwidth requirement can be somewhat higher due to the use of small memory buffers, in order to hold often used addresses (e.g. the station address) for example. Driver software can determine how to build frames in an efficient manner that does not overutilize the AHB. The bandwidth available on the AHB bus depends on the system clock frequency. As an example, assume that the system clock is set at 60 MHz. All or nearly all of bus accesses related to the Ethernet will be word transfers. The raw AHB bandwidth can be approximated as 4 bytes per two system clocks, which equals 2 times the system clock rate. With a 60 MHz system clock, the bandwidth is 120 MB/s, giving about 55% utilization

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 208 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet for Ethernet traffic during simultaneous transmit and receive operations. This shows that it is not necessary to use the maximum CPU frequency for the Ethernet to work with plenty of bandwidth headroom.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 209 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet 19. CRC calculation The calculation is used for several purposes:

Generation the FCS at the end of the Ethernet frame.
Generation of the hash table index for the hash table filtering.
Generation of the destination and source address hash CRCs. The C pseudocode function below calculates the CRC on a frame taking the frame (without FCS) and the number of bytes in the frame as arguments. The function returns the CRC as a 32-bit integer. int crc_calc(char frame_no_fcs[], int frame_len) { int i; // iterator int j; // another iterator char byte; // current byte int crc; // CRC result int q0, q1, q2, q3; // temporary variables crc = 0xFFFFFFFF; for (i = 0; i < frame_len; i++) { byte = *frame_no_fcs++; q3 = 0x04C11DB7; } else { q3 = 0x00000000; q2 = 0x09823B6E; } else { q2 = 0x00000000; q1 = 0x130476DC; } else { q1 = 0x00000000; q0 = 0x2608EDB8; } else { q0 = 0x00000000; crc = (crc << 4) ^ q3 ^ q2 ^ q1 ^ q0; byte >>= 4; return crc; For FCS calculation, this function is passed a pointer to the first byte of the frame and the length of the frame without the FCS.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 210 of 835 NXP Semiconductors UM10360 Chapter 10: LPC17xx Ethernet For hash filtering, this function is passed a pointer to the destination address part of the frame and the CRC is only calculated on the 6 address bytes. The hash filter uses bits [28:23] for indexing the 64-bits { HashFilterH, HashFilterL } vector. If the corresponding bit is set the packet is passed, otherwise it is rejected by the hash filter. For obtaining the destination and source address hash CRCs, this function calculates first both the 32-bit CRCs, then the nine most significant bits from each 32-bit CRC are extracted, concatenated, and written in every StatusHashCRC word of every fragment status.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 211 of 835 1. How to read this chapter This chapter describes the USB controller which is present on all LPC17xx devices except the LPC1767. On some LPC17xx family devices, the USB controller can also be configured for Host or OTG operation. 2. Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set bit PCUSB. Remark: On reset, the USB block is disabled (PCUSB = 0). 2. Clock: The USB block can be used with a dedicated USB PLL (PLL1) to obtain the USB clock or with the Main PLL (PLL0). See Section 4–6.1. 3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to PINMODE5 (Section 8–5). 4. Wake-up: Activity on the USB bus port can wake up the microcontroller from Power-down mode, see Section 4–8.8. 5. Interrupts: Inte rrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 6. Initialization: see Section 11–13. 3. Introduction The Universal Serial Bus (USB) is a four-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The host schedules transactions in 1 ms frames. Each frame contains a Start-Of-Frame (SOF) marker and transactions that transfer data to or from device endpoints. Each device can have a maximum of 16 logical or 32 physical endpoints. There are four types of transfers defined for the endpoints. Control transfers are used to configure the device. Interrupt transfers are used for periodic data transfer. Bulk transfers are used when the rate of transfer is not critical. Isochronous transfers have guaranteed delivery time but no error correction. For more information on the Universal Serial Bus, see the USB Implementers Forum website. The USB device controller on the LPC17xx enables full-speed (12 Mb/s) data exchange with a USB host controller. UM10360 Chapter 11: LPC17xx USB device controller Rev. 01 — 4 January 2010 User manual

Fully compliant with the USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint maximum packet size selection (up to USB maximum specification) by software at run time.
Supports SoftConnect and GoodLink features.
Supports DMA transfers on all non-control endpoints.
Allows dynamic switching between CPU controlled and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints. 5. Fixed endpoint configuration Table 11–184 shows the supported endpoint configurations. Endpoints are realized and configured at run time using the Endpoint realization registers, documented in Section 11–10.4 “Endpoint realization registers”.

Table 183. USB related acronyms, abbreviation s, and definitions used in this chapter

6.1 Analog transceiver

The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX sends/receives the bi-directional D+ and D- signals of the USB bus.

6.2 Serial Interface Engine (SIE)

The SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. It handles transfer of data between the endpoint buffers in EP_RAM and the USB bus. The functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address recognition, and handshake evaluation/generation.

6.3 Endpoint RAM (EP_RAM)

Each endpoint buffer is implemented as an SRAM based FIFO. The SRAM dedicated for this purpose is called the EP_RAM. Each realized endpoint has a reserved space in the EP_RAM. The total EP_RAM space required depends on the number of realized endpoints, the maximum packet size of the endpoint, and whether the endpoint supports double buffering.

6.4 EP_RAM access control

The EP_RAM Access Control logic handles transfer of data from/to the EP_RAM and the three sources that can access it: the CPU (via the Register Interface), the SIE, and the DMA Engine. Fig 26. USB device controller block diagram register interface (AHB slave) DMA interface (AHB master) EP_RAM (4K) EP_RAM ACCESS CONTROL REGISTER INTERFACE SERIAL INTERFACE ENGINE DMA ENGINE USB DEVICE BLOCK USB ATX BUS MASTER INTERFACE AHB BUS VBUS USB_CONNECT USB_D+ USB_D- USB_UP_LED

6.5 DMA engine and bus master interface

When enabled for an endpoint, the DMA Engine transfers data between RAM on the AHB bus and the endpoint’s buffer in EP_RAM. A single DMA channel is shared between all endpoints. When transferring data, the DMA Engine functions as a master on the AHB bus through the bus master interface.

6.6 Register interface

The Register Interface allows the CPU to control the operation of the USB Device Controller. It also provides a way to write transmit data to the controller and read receive data from the controller.

6.7 SoftConnect

The connection to the USB is accomplished by bringing D+ (for a full-speed device) HIGH through a 1.5 kOhm pull-up resistor. The SoftConnect feature can be used to allow software to finish its initialization sequence before deciding to establish connection to the USB. Re-initialization of the USB bus connection can also be performed without having to unplug the cable. To use the SoftConnect feature, the CONNECT signal should control an external switch that connects the 1.5 kOhm resistor between D+ and +3.3V. Software can then control the CONNECT signal by writing to the CON bit using the SIE Set Device Status command.

6.8 GoodLink

Good USB connection indication is provided through GoodLink technology. When the device is successfully enumerated and configured, the LED indicator will be permanently ON. During suspend, the LED will be OFF. This feature provides a user-friendly indicator on the status of the USB device. It is a useful field diagnostics tool to isolate faulty equipment. To use the GoodLink feature the UP_LED signal should control an LED. The UP_LED signal is controlled using the SIE Configure Device command. 7. Operational overview Transactions on the USB bus transfer data between device endpoints and the host. The direction of a transaction is defined with respect to the host. OUT transactions transfer data from the host to the device. IN transactions transfer data from the device to the host. All transactions are initiated by the host controller. For an OUT transaction, the USB ATX receives the bi-directional D+ and D- signals of the USB bus. The Serial Interface Engine (SIE) receives the serial data from the ATX and converts it into a parallel data stream. The parallel data is written to the corresponding endpoint buffer in the EP_RAM. For IN transactions, the SIE reads the parallel data from the endpoint buffer in EP_RAM, converts it into serial data, and transmits it onto the USB bus using the USB ATX.

Clocking and power management

9.1 Power requirements

A device in the non-configured state shou ld draw a maximum of 100 mA from the bus.
A configured device can draw only up to wh at is specified in the Max Power field of

the configuration descriptor. The maximum value is 500 mA.

A suspended device can draw a maximum of 2.5 mA.

9.2 Clocks

Table 185. USB external interface USB_CONNECT O SoftConnect control signal. USB_UP_LED O GoodLink LED control signal. USB_D+ I/O Positive differential data. USB_D- I/O Negative differential data.

9.3 Power management support

clock and usbclk when not in use. usbclk input to the device controller is automatically disabled, helping to conserve power. USBClkCtrl and USBClkSt registers are provided. enabled until DEV_CLK_EN is cleared by software. last DMA access, the AHB master clock is automatically disabled to help conserve power. DEV_CLK_ON and AHB_CLK_ON will be cleared when the corresponding clock turns off. can be read from the USBIntSt register. assertion of USB_NEED_CLK causes the chip to wake up from Power-down mode. Table 186. USB device controller clock sources

9.4 Remote wake-up

all the clocks to the device controller have to be enabled using the USBClkCtrl register. Table 11–187 shows the USB Device Controller registers directly accessible by the CPU. Table 187. USB device register map

UM10360_1 © NXP B.V. 2010. All rights reserved. [1] Reset value reflects the data stored in used bits only. It does not include reserved bits content. [2] Reading WO register will return an invalid value.

10.1 Clock control registers

10.1.1 USB Clock Control register (USBClkCtrl - 0x5000 CFF4)

register (see Section 13–8.6) when the USB is used in OTG configuration. Table 188. USBClkCtrl register (USBClkC trl - address 0x5000 CFF4) bit description read from a reserved bit is not defined. read from a reserved bit is not defined.

10.1.2 USB Clock Status register (USBClkSt - 0x5000 CFF8)

provided that the USBClkCtrl bits are not disturbed. USBClkSt is a read-only register.

10.2 Device interrupt registers

10.2.1 USB Interrupt Status register (USBIntSt - 0x5000 C1C0)

4 AHB_CLK_EN AHB clock enable 0

read from a reserved bit is not defined. Table 189. USB Clock Status register (USB ClkSt - address 0x5000 CFF8) bit description read from a reserved bit is not defined. read from a reserved bit is not defined. read from a reserved bit is not defined. Table 190. USB Interrupt Status register (U SBIntSt - address 0x5000 C1C0) bit description read from a reserved bit is not defined.

10.2.2 USB Device Interrupt Status register (USBDevIntSt - 0x5000 C200)

1 indicates the presence of the interrupt. USBDevIntSt is a read-only register. PLL and invoking the Power-down mode. This bit is read-only. read from a reserved bit is not defined. Controller does not see the ORed output of the USB interrupt lines. Table 191. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit allocation Table 192. USB Device Interrupt Status register (U SBDevIntSt - address 0x5000 C200) bit description the corresponding endpoint interrupt will be routed to this bit. not set, the corresponding endpoint interrupt will be routed to this bit. 3 DEV_STAT Set when USB Bus reset, USB suspend change or Connect change event occurs.

7 TxENDPKT The number of data bytes transferred to the endpoint buffer equals the number of bytes

programmed in the TxPacket length register (USBTxPLen).

10.2.3 USB Device Interrupt Enable register (USBDevIntEn - 0x5000 C204)

USBDevIntPri. USBDevIntEn is a read/write register.

10.2.4 USB Device Interrupt Clear register (USBDevIntClr - 0x5000 C208)

endpoint interrupts in USBEpIntSt should be cleared. USBDevIntClr is a write-only register. register (USBMaxPSize) is updated and the corresponding operation is completed. reserved bit is not defined. Table 193. USB Device Interrupt Enable register (USBDevIntEn - address 0x5000 C204) bit allocation Table 194. USB Device Interrupt Enable register (USBDevIntEn - address 0x5000 C204) bit description

1 An interrupt will be generated when the corresponding bit in the Device

interrupt line by changing the value of USBDevIntPri. Table 195. USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit allocation

10.2.5 USB Device Interrupt Set register (USBDevIntSet - 0x5000 C20C)

USBDevIntSet is a write-only register.

10.2.6 USB Device Interrupt Priority register (USBDevIntPri - 0x5000 C22C)

interrupt will be routed to USB_INT_REQ_HP. USBDevIntPri is a write-only register. Table 196. USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit description 1 The corresponding bit in USBDevIntSt ( Section 11–10.2.2) is cleared. Table 197. USB Device Interrupt Set register (USBDevIntSet - address 0x5000 C20C) bit allocation Table 198. USB Device Interrupt Set register (USBDevIntSet - address 0x5000 C20C) bit description

10.3 Endpoint interrupt registers

used in Slave mode operation.

10.3.1 USB Endpoint Interrupt Status register (USBEpIntSt - 0x5000 C230)

Table 199. USB Device Interrupt Priority register (USBDevIntPri - address 0x5000 C22C) bit description 1 FRAME interrupt is routed to USB_INT_REQ_HP. 1 EP_FAST interrupt is routed to USB_INT_REQ_HP . reserved bit is not defined. Table 200. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit allocation Table 201. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit description

10.3.2 USB Endpoint Interrupt Enable register (USBEpIntEn - 0x5000 C234)

endpoint. USBEpIntEn is a read/write register. Table 202. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit allocation

10.3.3 USB Endpoint Interrupt Clear register (USBEpIntClr - 0x5000 C238)

corresponding bit in USBEpIntSt is cleared.

When clearing interrupts using USBEpIntClr, software should wait for CDFULL to be set to ensure the corresponding interrupt has been cleared before proceeding.
While setting multiple bits in USBEpIntClr simultaneously is possible, it is not recommended; only the status of the endpoint corresponding to the least significant interrupt bit cleared will be available at the end of the operation.
Alternatively, the SIE Select Endpoint/Clear Interrupt command can be directly invoked using the SIE command registers, but using USBEpIntClr is recommended because of its ease of use. Each physical endpoint has its own reserved bit in this register. The bit field definition is the same as that of USBEpIntSt shown in Table 11–200 . USBEpIntClr is a write-only register. Bit 7 6 5 4 3 2 1 0 Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX

Table 203. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0x5000 C234) bit description

0 The corresponding bit in USBDMARSt is set when an interrupt occurs

1 The corresponding bit in USBEpIntSt is set when an interrupt

occurs for this endpoint. Implies Slave mode for this endpoint. Table 204. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0x5000 C238) bit allocation

10.3.4 USB Endpoint Interrupt Set register (USBEpIntSet - 0x5000 C23C)

10.3.5 USB Endpoint Interrupt Priority register (USBEpIntPri - 0x5000 C240)

to the USB_INT_REQ_HP or USB_INT_REQ_LP interrupt line. USBEpIntPri is a write-only register. Table 205. USB Endpoint Interrupt Clear register (U SBEpIntClr - address 0x5000 C238) bit description

1 Clears the corresponding bit in U SBEpIntSt, by executing the SIE

Select Endpoint/Clear Interrupt command for this endpoint. Table 206. USB Endpoint Interrupt Set register (USBEpIntSet - address 0x5000 C23C) bit allocation Table 207. USB Endpoint Interrupt Set register (USBEpIntSet - address 0x5000 C23C) bit description 1 Sets the corresponding bit in USBEpIntSt. Table 208. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit allocation

10.4 Endpoint realization registers

The registers in this group allow realization and configuration of endpoints at run time.

10.4.1 EP RAM requirements

where dbstatus = 1 for a single buffered endpoint and 2 for double a buffered endpoint. 4096 bytes (4 kB, 1 kwords).

10.4.2 USB Realize Endpoint register (USBReEp - 0x5000 C244)

Writing one to a bit in this register causes the corresponding endpoint to be realized. reset occurs. USBReEp is a read/write register. Table 209. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit description

0 The corresponding interrupt is routed to the EP_SLOW bit of

1 The corresponding interrupt is routed to the EP_FAST bit of

UM10360_1 © NXP B.V. 2010. All rights reserved. space for the realized endpoints, see Section 11–10.4.1. Table 210. USB Realize Endpoint register (USBReEp - address 0x5000 C244) bit allocation Table 211. USB Realize Endpoint register (USBReEp - address 0x5000 C244) bit description 1 Control endpoint EP0 is realized. 1 Control endpoint EP1 is realized. 1 Endpoint EPxx is realized.

10.4.3 USB Endpoint Index register (USBEpIn - 0x5000 C248)

will set the array element pointed to by USBEpIn. USBEpIn is a write-only register.

10.4.4 USB MaxPacketSize register (USBMaxPSize - 0x5000 C24C)

indexing is shown in Figure 11–27. USBMaxPSize is a read/write register. [1] Reset value for EP0 and EP1. All other endpoints have a reset value of 0x0.

10.5 USB transfer registers

Table 212. USB Endpoint Index register (USBEpIn - address 0x5000 C248) bit description a reserved bit is not defined. Table 213. USB MaxPacketSize register (USBMax PSize - address 0x5000 C24C) bit description reserved bit is not defined.

10.5.1 USB Receive Data register (USBRxData - 0x5000 C218)

10.5.2 USB Receive Packet Length register (USBRxPLen - 0x5000 C220)

USBRxData register. USBRxPLen is a read-only register.

10.5.3 USB Transmit Data register (USBTxData - 0x5000 C21C)

USBTxData. USBTxData is a write-only register. Table 214. USB Receive Data register (USBRxData - address 0x5000 C218) bit description Table 215. USB Receive Packet Le ngth register (USBRxPlen - address 0x5000 C220) bit description packet is received. In this case DV bit will not be set for the packet. read from a reserved bit is not defined. Table 216. USB Transmit Data register (USBTxData - address 0x5000 C21C) bit description

10.5.4 USB Transmit Packet Length register (USBTxPLen - 0x5000 C224)

10.5.5 USB Control register (USBCtrl - 0x5000 C228)

reading and writing them. USBCtrl is a read/write register.

10.6 SIE command code registers

Table 217. USB Transmit Packet Length register (USBTxPLen - address 0x5000 C224) bit description 9:0 PKT_LNGTH - The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. read from a reserved bit is not defined. Table 218. USB Control register (USBCtrl - address 0x5000 C228) bit description of the current packet is read from USBRxData. value read from a reserved bit is not defined.

10.6.1 USB Command Code register (USBCmdCode - 0x5000 C210)

Section 11–12 for details. USBCmdCode is a write-only register.

10.6.2 USB Command Data register (USBCmdData - 0x5000 C214)

for details. USBCmdData is a read-only register.

10.7 DMA registers

10.7.1 USB DMA Request Status register (USBDMARSt - 0x5000 C250)

control endpoints (EP0 and EP1). USBDMARSt is a read-only register. Table 219. USB Command Code register (USBCm dCode - address 0x5000 C210) bit description read from a reserved bit is not defined. read from a reserved bit is not defined. Table 220. USB Command Data register (USBCmdData - address 0x5000 C214) bit description a reserved bit is not defined. Table 221. USB DMA Request Status register (USBDMARSt - address 0x5000 C250) bit allocation

10.7.2 USB DMA Request Clear register (USBDMARClr - 0x5000 C254)

register. Writing zero has no effect. bit using this register while the endpoint is enabled for DMA operation. USBDMARClr is a write-only register. The USBDMARClr bit allocation is identical to the USBDMARSt register (Table 11–221).

10.7.3 USB DMA Request Set register (USBDMARSet - 0x5000 C258)

Writing one to a bit in this register sets the corresponding bit in the USBDMARSt register. Table 222. USB DMA Request Status register (U SBDMARSt - address 0x5000 C250) bit description

0 EP0 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit

1 EP1 0 Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit

0 DMA not requested by endpoint xx. 1 DMA requested by endpoint xx. Table 223. USB DMA Request Clear register (US BDMARClr - address 0x5000 C254) bit description

0 EP0 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0

1 EP1 0 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit

1 Clear the corresponding bit in USBDMARSt.

UM10360_1 © NXP B.V. 2010. All rights reserved. endpoint buffer before an IN token packet is received from the host. USBDMARSet is a write-only register. The USBDMARSet bit allocation is identical to the USBDMARSt register (Table 11–221).

10.7.4 USB UDCA Head register (USBUDCAH - 0x5000 C280)

UDCA and DMA descriptors. USBUDCAH is a read/write register.

10.7.5 USB EP DMA Status register (USBEpDMASt - 0x5000 C284)

this register. USBEpDMASt is a read-only register. Table 224. USB DMA Request Set register (US BDMARSet - address 0x5000 C258) bit description

0 EP0 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit

1 EP1 0 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must

1 Set the corresponding bit in USBDMARSt. Table 225. USB UDCA Head register (USBU DCAH - address 0x5000 C280) bit description Table 226. USB EP DMA Status register (USBEpDMASt - address 0x5000 C284) bit description

0 EP0_DMA_ENABLE 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and

the EP0_DMA_ENABLE bit must be 0).

1 EP1_DMA_ENABLE 0 Control endpoint IN (DMA cannot be enabled for this endpoint and

the EP1_DMA_ENABLE bit must be 0). 0 The DMA for endpoint EPxx is disabled. 1 The DMA for endpoint EPxx is enabled.

10.7.6 USB EP DMA Enable register (USBEpDMAEn - 0x5000 C288)

EP0 and EP1. USBEpDMAEn is a write-only register.

10.7.7 USB EP DMA Disable register (USBEpDMADis - 0x5000 C28C)

the corresponding bit is cleared by hardware. USBEpDMADis is a write-only register.

10.7.8 USB DMA Interrupt Status register (USBDMAIntSt - 0x5000 C290)

status register are set. USBDMAIntSt is a read-only register. Table 227. USB EP DMA Enable register (USBEpDMAEn - address 0x5000 C288) bit description the EP0_DMA_ENABLE bit value must be 0).

1 EP1_DMA_ENABLE 0 Control endpoint IN (DMA cannot be enabled for this endpoint and the

EP1_DMA_ENABLE bit must be 0). 1 Enable the DMA operation for endpoint EPxx. Table 228. USB EP DMA Disable register (USBEpDMADis - address 0x5000 C28C) bit description

0 EP0_DMA_DISABLE 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and

the EP0_DMA_DISABLE bit value must be 0).

1 EP1_DMA_DISABLE 0 Control endpoint IN (DMA ca nnot be enabled for this endpoint and the

EP1_DMA_DISABLE bit value must be 0). 1 Disable the DMA operation for endpoint EPxx. Table 229. USB DMA Interrupt Status register (U SBDMAIntSt - address 0x5000 C290) bit description 0 All bits in the USBEoTIntSt register are 0. 1 At least one bit in the USBEoTIntSt is set. 0 All bits in the USBNDDRIntSt register are 0. 1 At least one bit in the USBNDDRIntSt is set.

10.7.9 USB DMA Interrupt Enable register (USBDMAIntEn - 0x5000 C294)

10.7.10 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0x5000 C2A0)

this register. The cause of the interrupt is recorded in the DD_status field of the descriptor. USBEoTIntSt is a read-only register.

10.7.11 USB End of Transfer Interrupt Clear register (USBEoTIntClr - 0x5000 C2A4)

register. Writing zero has no effect. USBEoTIntClr is a write-only register. 0 All bits in the USBSysErrIntSt register are 0. 1 At least one bit in the USBSysErrIntSt is set. from a reserved bit is not defined. Table 230. USB DMA Interrupt Enable register (U SBDMAIntEn - address 0x5000 C294) bit description 0 The End of Transfer Interrupt is disabled. 1 The End of Transfer Interrupt is enabled. 0 The New DD Request Interrupt is disabled. 1 The New DD Request Interrupt is enabled. 0 The System Error Interrupt is disabled. 1 The System Error Interrupt is enabled. from a reserved bit is not defined. Table 231. USB End of Transfer Interrupt Status register (USBEoTIntSt - address 0x5000 C2A0s) bit description 0 There is no End of Transfer interrupt request for endpoint xx. 1 There is an End of Transfer Interrupt request for endpoint xx.

10.7.12 USB End of Transfer Interrupt Set register (USBEoTIntSet - 0x5000 C2A8)

Writing one to a bit in this register sets the corresponding bit in the USBEoTIntSt register. Writing zero has no effect. USBEoTIntSet is a write-only register.

10.7.13 USB New DD Request Interrupt Stat us register (USBNDDRIntSt - 0x5000

DD is detected for the corresponding endpoint. USBNDDRIntSt is a read-only register.

10.7.14 USB New DD Request Interrupt Clear register (USBNDDRIntClr - 0x5000

10.7.15 USB New DD Request Interrupt Se t register (USBNDDRIntSet - 0x5000

Table 232. USB End of Transfer Inte rrupt Clear register (USBEoTIntClr - address 0x5000 C2A4) bit description 1 Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. Table 233. USB End of Transfer Interrupt Set register (USBEoTIntSet - address 0x5000 C2A8) bit description 1 Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register. Table 234. USB New DD Request Interrupt Status register (USBNDDRIntSt - address 0x5000 C2AC) bit description 0 There is no new DD interrupt request for endpoint xx. 1 There is a new DD interrupt request for endpoint xx. Table 235. USB New DD Request Interrupt Clear register (USBNDDRIntClr - address 0x5000 C2B0) bit description 1 Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.

10.7.16 USB System Error Interrupt Status register (USBSysErrIntSt - 0x5000 C2B8)

10.7.17 USB System Error Interrupt Clear register (USBSysErrIntClr - 0x5000 C2BC)

10.7.18 USB System Error Interrupt Set register (USBSysErrIntSet - 0x5000 C2C0)

register. Writing zero has no effect. USBSysErrIntSet is a write-only register. . For isochronous endpoints, a frame interrupt is generated every 1 ms. Table 236. USB New DD Request Interrupt Set register (USBNDDRIntSet - address 0x5000 C2B4) bit description 1 Set the EPxx new DD interrupt request in the USBNDDRIntSt register. Table 237. USB System Error Interrupt Status register (USBSysErrIntSt - address 0x5000 C2B8) bit description 0 There is no System Error Interrupt request for endpoint xx. 1 There is a System Error Interrupt request for endpoint xx. Table 238. USB System Error Interrupt Clear register (USBSysErrIntClr - address 0x5000 C2BC) bit description 1 Clear the EPxx System E rror Interrupt request in the USBSysErrIntSt register. Table 239. USB System Error Interrupt Set register (U SBSysErrIntSet - address 0x5000 C2C0) bit description 1 Set the EPxx System Error Interrupt r equest in the USBSysErrIntSt register.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 240 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller The interrupt handling is different for Slave and DMA mode. Slave mode If an interrupt event occurs on an endpoint and the endpoint interrupt is enabled in the USBEpIntEn register, the corresponding status bit in the USBEpIntSt is set. For non-isochronous endpoints, all endpoint interrupt events are divided into two types by the corresponding USBEpIntPri[n] registers: fast endpoint interrupt events and slow endpoint interrupt events. All fast endpoint interrupt events are ORed and routed to bit EP_FAST in the USBDevIntSt register. All slow endpoint interrupt events are ORed and routed to the EP_SLOW bit in USBDevIntSt. For isochronous endpoints, the FRAME bit in USBDevIntSt is set every 1 ms. The USBDevIntSt register holds the status of all endpoint interrupt events as well as the status of various other interrupts (see Section 11–10.2.2 ). By default, all interrupts (if enabled in USBDevIntEn) are routed to the USB_INT_REQ_LP bit in the USBIntSt register to request low priority interrupt handling. However, the USBDevIntPri register can route either the FRAME or the EP_FAST bit to the USB_INT_REQ_HP bit in the USBIntSt register. Only one of the EP_FAST and FRAME interrupt events can be routed to the USB_INT_REQ_HP bit. If routing both bits to USB_INT_REQ_HP is attempted, both interrupt events are routed to USB_INT_REQ_LP. Slow endpoint interrupt events are always routed directly to the USB_INT_REQ_LP bit for low priority interrupt handling by software. The final interrupt signal to the NVIC is gated by the EN_USB_INTS bit in the USBIntSt register. The USB interrupts are routed to the NVIC only if EN_USB_INTS is set. DMA mode If an interrupt event occurs on a non-control endpoint and the endpoint interrupt is not enabled in the USBEpIntEn register, the corresponding status bit in the USBDMARSt is set by hardware. This serves as a flag for the DMA engine to transfer data if DMA transfer is enabled for the corresponding endpoint in the USBEpDMASt register. Three types of interrupts can occur for each endpoint for data transfers in DMA mode: End of transfer interrupt, new DD request interrupt, and system error interrupt. These interrupt events set a bit for each endpoint in the respective registers USBEoTIntSt, USBNDDRIntSt, and USBSysErrIntSt. The End of transfer interrupts from all endpoints are then Ored and routed to the EOT bit in USBDMAIntSt. Likewise, all New DD request interrupts and system error interrupt events are routed to the NDDR and ERR bits respectively in the USBDMAStInt register. The EOT, NDDR, and ERR bits (if enabled in USBDMAIntEn) are ORed to set the USB_INT_REQ_DMA bit in the USBIntSt register. If the EN_USB_INTS bit is set in USBIntSt, the interrupt is routed to the NVIC.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 241 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller For simplicity, USBDevIntEn and USBDMAIntEn are not shown. Fig 28. Interrupt event handling USB_INT_REQ_HP USB_INT_REQ_LP USB_INT_REQ_DMA EN_USB_INTS to NVIC ... ... ... ... ... ... FRAME EP_FAST EP_SLOW USBDevIntPri[0] USBDevIntPri[1]USBEpIntPri[n] USBEpIntSt USBDMARSt to DMA engine interrupt event on EPn n n ... ... ... USBEoTIntST USBNDDRIntSt USBSysErrIntSt EOT NDDR ERR USBDevIntSt USBIntSt USBEpIntEn[n] from other Endpoints USBDMAIntSt Slave mode DMA Mode ERR_INT

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 242 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller 12. Serial interface engine command description The functions and registers of the Serial Interface Engine (SIE) are accessed using commands, which consist of a command code followed by optional data bytes (read or write action). The USBCmdCode (Table 11–219) and USBCmdData (Table 11–220) registers are used for these accesses. A complete access consists of two phases: 1. Command phase: the USBCmdCode register is written with the CMD_PHASE field set to the value 0x05 (Command), and the CMD_CODE field set to the desired command code. On completion of the command, the CCEMPTY bit of USBDevIntSt is set. 2. Data phase (optional): for writes, the USBCmdCode register is written with the CMD_PHASE field set to the value 0x01 (Write), and the CMD_WDATA field set with the desired write data. On completion of the write, the CCEMPTY bit of USBDevIntSt is set. For reads, USBCmdCode register is written with the CMD_PHASE field set to the value 0x02 (Read), and the CMD_CODE field set with command code the read corresponds to. On completion of the read, the CDFULL bit of USBDevInSt will be set, indicating the data is available for reading in the USBCmdData register. In the case of multi-byte registers, the least significant byte is accessed first. An overview of the available commands is given in Table 11–240 Here is an example of the Read Current Frame Number command (reading 2 bytes): USBDevIntClr = 0x30; // Clear both CCEMPTY & CDFULL USBCmdCode = 0x00F50500; // CMD_CODE=0xF5, CMD_PHASE=0x05(Command) while (!(USBDevIntSt & 0x10)); // Wait for CCEMPTY. USBDevIntClr = 0x10; // Clear CCEMPTY interrupt bit. USBCmdCode = 0x00F50200; // CMD_CODE=0xF5, CMD_PHASE=0x02(Read) while (!(USBDevIntSt & 0x20)); // Wait for CDFULL. USBDevIntClr = 0x20; // Clear CDFULL. CurFrameNum = USBCmdData; // Read Frame number LSB byte. USBCmdCode = 0x00F50200; // CMD_CODE=0xF5, CMD_PHASE=0x02(Read) while (!(USBDevIntSt & 0x20)); // Wait for CDFULL. Temp = USBCmdData; // Read Frame number MSB byte USBDevIntClr = 0x20; // Clear CDFULL interrupt bit. CurFrameNum = CurFrameNum | (Temp << 8); Here is an example of the Set Address command (writing 1 byte): USBDevIntClr = 0x10; // Clear CCEMPTY. USBCmdCode = 0x00D00500; // CMD_CODE=0xD0, CMD_PHASE=0x05(Command) while (!(USBDevIntSt & 0x10)); // Wait for CCEMPTY. USBDevIntClr = 0x10; // Clear CCEMPTY. USBCmdCode = 0x008A0100; // CMD_WDATA=0x8A(DEV_EN=1, DEV_ADDR=0xA), // CMD_PHASE=0x01(Write) while (!(USBDevIntSt & 0x10)); // Wait for CCEMPTY. USBDevIntClr = 0x10; // Clear CCEMPTY.

12.1 Set Address (Command: 0xD 0, Data: write 1 byte)

12.2 Configure Device (Command: 0xD8, Data: write 1 byte)

respond even if the device is not configured, in the default state. Table 240. SIE command code table Table 241. Set Address command bit description 7 DEV_EN Device Enable. After a bus reset this bit is set to 1. 0: Device will not respond to any packets. 1: Device will respond to packets for function address DEV_ADDR.

12.3 Set Mode (Command: 0xF 3, Data: write 1 byte)

[1] This bit should be reset to 0 if the DMA is enabled for any of the Interrupt OUT endpoints. [2] This bit should be reset to 0 if the DMA is enabled for any of the Bulk OUT endpoints.

12.4 Read Current Frame Number (Com mand: 0xF5, Data: read 1 or 2

only interested in the lower 8 bits of the frame number, only the first byte needs to be read. Table 242. Configure Device command bit description driven LOW if the device is not in the suspended state (SUS=0). from a reserved bit is not defined. Table 243. Set Mode command bit description

0 USB_NEED_CLK is functional; the 48 MHz clock can be stopped when the

device enters suspend state.

1 USB_NEED_CLK is fixed to 1; the 48 MHz clock cannot be stopped when the

device enters suspend state. 0 Only successful transactions generate an interrupt. 1 Both successful and NAKed IN transactions generate interrupts. 0 Only successful transactions generate an interrupt. 1 Both successful and NAKed OUT transactions generate interrupts. 0 Only successful transactions generate an interrupt. 1 Both successful and NAKed IN transactions generate interrupts.

4 INAK_IO

0 Only successful transactions generate an interrupt. 1 Both successful and NAKed OUT transactions generate interrupts. 0 Only successful transactions generate an interrupt. 1 Both successful and NAKed IN transactions generate interrupts.

6 INAK_BO

0 Only successful transactions generate an interrupt. 1 Both successful and NAKed OUT transactions generate interrupts. from a reserved bit is not defined.

In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF.
In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device.

12.5 Read Test Register (Comma nd: 0xFD, Data: read 2 bytes)

and AHB slave clock) are running.

12.6 Set Device Status (Command: 0xFE, Data: write 1 byte)

The Set Device Status command sets bits in the Device Status Register. Table 244. Set Device Status command bit description 0 Writing a 0 will make the CONNECT pin go HIGH. 1 Writing a 1 will make the CONNECT pin go LOW. 0 This bit is cleared when read.

1 This bit is set when the device’s pull-up resistor is disconnected because V

disappeared. The DEV_STAT interrupt is generated when this bit is 1. 2 SUS Suspend: The Suspend bit represents the current suspend state. writing a 0 has no effect. Writing a 1 to this bit has no effect. 0 This bit is reset to 0 on any activity.

1 This bit is set to 1 when the device hasn’t seen any activity on its upstream port

The device goes into the suspended state.
The device is disconnected.
The device receives resume signalling on its upstream port. This bit is cleared when read. 0 SUS bit not changed. 1 SUS bit changed. At the same time a DEV_STAT interrupt is generated.

12.7 Get Device Status (Command: 0xFE, Data: read 1 byte)

12.8 Get Error Code (Command: 0xFF, Data: read 1 byte)

the last error code that occurred. The 4 least significant bits form the error code.

Device is unconfigured.
Will respond to address 0.
Control endpoint will be in the Stalled state.
All endpoints are unrealized except control endpoints EP0 and EP1.
Data toggling is reset for all endpoints.
All buffers are cleared.
There is no change to the endpoint interrupt status.
DEV_STAT interrupt is generated. Note: Bus resets are ignored when the device is not connected (CON=0). 0 This bit is cleared when read. 1 This bit is set when the device receives a bus reset. A DEV_STAT interrupt is generated. 7:5 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

12.9 Read Error Status (Command: 0xFB, Data: read 1 byte)

ERR_INT bit of USBDevIntSt is set. The error bits are cleared after reading this register.

12.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional))

number. In the case of a single buffered endpoint the B_2_FULL bit is not valid. Table 245. Get Error Code command bit description 0011 Unexpected Packet - any packet sequence violation from the specification. 1000 Error in End of Packet. 1100 Sent Empty Packet (ISO Endpoints only). 1111 Wr ong Toggle Bit in Data PID, ignored data. 4 EA - The Error Active bit will be reset once this register is read. from a reserved bit is not defined. Table 246. Read Error Status command bit description

12.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1

They clear the bit corresponding to the endpoint in the USBEpIntSt register.
In case of a control OUT endpoint, they clear the STP and PO bits in the corresponding Select Endpoint Register.
Reading one byte is obligatory.

Table 247. Select Endpoint command bit description 0 FE Full/Empty. This bit indicates the full or empty status of the endpoint buffer(s). reflects the status of B_1_FULL. 0 For an IN endpoint, at least one write endpoint buffer is empty. 1 For an OUT endpoint, at least one endpoint read buffer is full. 0 The selected endpoint is not stalled. 1 The selected endpoint is stalled.

2 STP SETUP bit: the value of this bit is updated after each successfully received

packet (i.e. an ACKed package on that particular physical endpoint).

0 The STP bit is cleared by doing a Select Endpoint/Clear Interrupt on this

1 The last received packet for the selected endpoint was a SETUP packet. 0 The PO bit is cleared by the ‘Select Endpoint/Clear Interrupt’ command. 1 The previously received packet was over-written by a SETUP packet. to an empty IN buffer, the device returns NAK.

0 The EPN bit is reset after the device has sent an ACK after an OUT packet or

when the device has seen an ACK after sending an IN packet.

1 The EPN bit is set when a NAK is sent and the interrupt on NAK feature is

from a reserved bit is not defined.

12.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte

endpoint number in hex. Not all bits can be set for all types of endpoints.

12.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional))

buffer is cleared, new packets will be accepted. by a SETUP packet. The Packet over-written bit is used only in control transfers. Table 248. Set Endpoint Status command bit description stalled by the Set Endpoint Status command, it is also re-initialized. 0 The endpoint is unstalled. from a reserved bit is not defined. 0 Interrupt endpoint is in the Toggle mode. place without data toggle bit. 0 Unstalls both control endpoints.

1 Stall both control endpoints, unless the STP bit is set in the Select Endpoint

12.14 Validate Buffer (C ommand: 0xFA, Data: none)

command. This tells hardware that the buffer is ready for sending on the USB bus. Hardware will send the contents of the buffer when the next IN token packet is received.

USB device controller initialization
Enable the device controller by setting the PCUSB bit of PCONP.
Configure and enable the PLL and Clock Dividers to provide 48 MHz for usbclk and
Enable the device contro ller clocks by setting DEV_CLK_EN and AHB_CLK_EN bits
Enable the USB pin functions by writing to the corresponding PINSEL register.
Disable the pull-ups and pull-downs on the V BUS pin using the corresponding

resistor enabled” mode. See Section 8–4 “Pin mode select register values”. Table 249. Clear Buffer command bit description 0 The previously received packet is intact. 1 The previously received packet was over-written by a later SETUP packet. a reserved bit is not defined.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 251 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller 6. Set USBEpIn and USBMaxPSize registers for EP0 and EP1, and wait until the EP_RLZED bit in USBDevIntSt is set so that EP0 and EP1 are realized. 7. Enable endpoint interrupts (Slave mode): – Clear all endpoint interrupts using USBEpIntClr. – Clear any device interrupts using USBDevIntClr. – Enable Slave mode for the desired endpoints by setting the corresponding bits in USBEpIntEn. – Set the priority of each enabled interrupt using USBEpIntPri. – Configure the desired interrupt mode using the SIE Set Mode command. – Enable device interrupts using USBDevIntEn (normally DEV_STAT, EP_SLOW, and possibly EP_FAST). 8. Configure the DMA (DMA mode): – Disable DMA operation for all endpoints using USBEpDMADis. – Clear any pending DMA requests using USBDMARClr. – Clear all DMA interrupts using USBEoTIntClr, USBNDDRIntClr, and USBSysErrIntClr. – Prepare the UDCA in system memory. – Write the desired address for the UDCA to USBUDCAH (for example 0x7FD0 0000). – Enable the desired endpoints for DMA operation using USBEpDMAEn. – Set EOT, DDR, and ERR bits in USBDMAIntEn. 9. Install USB interrupt handler in the NVIC by writing its address to the appropriate vector table location and enabling the USB interrupt in the NVIC. 10. Set default USB address to 0x0 and DEV_EN to 1 using the SIE Set Address command. A bus reset will also cause this to happen. 11. Set CON bit to 1 to make CONNECT ac tive using the SIE Set Device Status command. The configuration of the endpoints varies depending on the software application. By default, all the endpoints are disabled except control endpoints EP0 and EP1. Additional endpoints are enabled and configured by software after a SET_CONFIGURATION or SET_INTERFACE device request is received from the host. 14. Slave mode operation In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the Register Interface.

14.1 Interrupt generation

In slave mode, data packet transfer between RAM and an endpoint buffer can be initiated in response to an endpoint interrupt. Endpoint interrupts are enabled using the USBEpIntEn register, and are observable in the USBEpIntSt register.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 252 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller All non-isochronous OUT endpoints generate an endpoint interrupt when they receive a packet without an error. All non-isochronous IN endpoints generate an interrupt when a packet is successfully transmitted, or when a NAK handshake is sent on the bus and the interrupt on NAK feature is enabled. For Isochronous endpoints, transfer of data is done when the FRAME interrupt (in USBDevIntSt) occurs.

14.2 Data transfer for OUT endpoints

When the software wants to read the data from an endpoint buffer it should set the RD_EN bit and program LOG_ENDPOINT with the desired endpoint number in the USBCtrl register. The control logic will fetch the packet length to the USBRxPLen register, and set the PKT_RDY bit (Table 11–215 Software can now start reading the data from the USBRxData register (Table 11–214). When the end of packet is reached, the RD_EN bit is cleared, and the RxENDPKT bit is set in the USBDevSt register. Software now issues a Clear Buffer (refer to Table 11–249) command. The endpoint is now ready to accept the next packet. For OUT isochronous endpoints, the next packet will be received irrespective of whether the buffer has been cleared. Any data not read from the buffer before the end of the frame is lost. See Section 11–16 “Double buffered endpoint operation” for more details. If the software clears RD_EN before the entire packet is read, reading is terminated, and the data remains in the endpoint’s buffer. When RD_EN is set again for this endpoint, the data will be read from the beginning.

14.3 Data transfer for IN endpoints

When writing data to an endpoint buffer, WR_EN (Section 11–10.5.5 “USB Control register (USBCtrl - 0x5000 C228) ”) is set and software writes to the number of bytes it is going to send in the packet to the USBTxPLen register (Section 11–10.5.4). It can then write data continuously in the USBTxData register. When the number of bytes programmed in USBTxPLen have been written to USBTxData, the WR_EN bit is cleared, and the TxENDPKT bit is set in the USBDevIntSt register. Software issues a Validate Buffer (Section 11–12.14 “Validate Buffer (Command: 0xFA, Data: none)”) command. The endpoint is now ready to send the packet. For IN isochronous endpoints, the data in the buffer will be sent only if the buffer is validated before the next FRAME interrupt occurs; otherwise, an empty packet will be sent in the next frame. If the software clears WR_EN before the entire packet is written, writing will start again from the beginning the next time WR_EN is set for this endpoint. Both RD_EN and WR_EN can be high at the same time for the same logical endpoint. Interleaved read and write operation is possible. 15. DMA operation In DMA mode, the DMA transfers data between RAM and the endpoint buffer. The following sections discuss DMA mode operation. Background information is given in sections Section 11–15.2 “USB device communication area” and Section 11–15.3 “Triggering the DMA engine”. The fields of the DMA Descriptor are described in Section

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 253 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller 11–15.4 “The DMA descriptor”. The last three sections describe DMA operation: Section 11–15.5 “Non-isochronous endpoint operation”, Section 11–15.6 “Isochronous endpoint operation”, and Section 11–15.7 “Auto Length Transfer Extraction (ATLE) mode operation”.

15.1 Transfer terminology

Within this section three types of transfers are mentioned: 1. USB transfers – transfer of data over th e USB bus. The USB 2.0 specification refers to these simply as transfers. Within this section they are referred to as USB transfers to distinguish them from DMA transfers. A USB transfer is composed of transactions. Each transaction is composed of packets. 2. DMA transfers – the transfer of data between an endpoint buffer and system memory (RAM). 3. Packet transfers – in this section, a packet transfer refers to the transfer of a packet of data between an endpoint buffer and system memory (RAM). A DMA transfer is composed of one or more packet transfers.

15.2 USB device communication area

The CPU and DMA controller communicate through a common area of memory, called the USB Device Communication Area, or UDCA. The UDCA is a 32-word array of DMA Descriptor Pointers (DDPs), each of which corresponds to a physical endpoint. Each DDP points to the start address of a DMA Descriptor, if one is defined for the endpoint. DDPs for unrealized endpoints and endpoints disabled for DMA operation are ignored and can be set to a NULL (0x0) value. The start address of the UDCA is stored in the USBUDCAH register. The UDCA can reside at any 128-byte boundary of RAM that is accessible to both the CPU and DMA controller. Figure 11–29 illustrates the UDCA and its relationship to the UDCA Head (USBUDCAH) register and DMA Descriptors.

15.3 Triggering the DMA engine

An endpoint raises a DMA request when Slave mode is disabled by setting the corresponding bit in the USBEpIntEn register to 0 (Section 11–10.3.2) and an endpoint interrupt occurs (see Section 11–10.7.1 “USB DMA Request Status register (USBDMARSt - 0x5000 C250) ”). A DMA transfer for an endpoint starts when the endpoint is enabled for DMA operation in USBEpDMASt, the corresponding bit in USBDMARSt is set, and a valid DD is found for the endpoint. All endpoints share a single DMA channel to minimize hardware overhead. If more than one DMA request is active in USBDMARSt, the endpoint with the lowest physical endpoint number is processed first. In DMA mode, the bits corresponding to Interrupt on NAK for Bulk OUT and Interrupt OUT endpoints (INAK_BO and INAK_IO) should be set to 0 using the SIE Set Mode command (Section 11–12.3).

15.4 The DMA descriptor

DMA transfers are described by a data structure called the DMA Descriptor (DD). DDs are placed in RAM. These descriptors can be located anywhere in on-chip RAM at word-aligned addresses. DDs for non-isochronous endpoints are four words long. DDs for isochronous endpoints are five words long. The parameters associated with a DMA transfer are:

The start address of the DMA buffer Fig 29. UDCA Head register and DMA Descriptors UDCA HEAD REGISTER DDP-EP2 DD-EP2-a NULL NULL Next_DD_pointer

0 NULL

Next_DD_pointer DD-EP2-c Next_DD_pointer DD-EP16-a Next_DD_pointer DD-EP16-b Next_DD_pointer UDCA

The length of the DMA buffer
The start address of the next DMA descriptor
Control information
Count information (number of bytes transferred)
Status information Table 11–250 lists the DMA descriptor fields. [1] Write-only in ATLE mode Legend: R - Read; W - Write; I - Initialize

15.4.1 Next_DD_pointer

Pointer to the memory location from where the next DMA descriptor will be fetched. Table 250. DMA descriptor

0 R R/W 31:0 Next_DD_pointer

1 R R/W 1:0 DMA_mode (00 -Normal; 01 - ATLE)

R R/W 2 Next_DD_valid (1 - valid; 0 - invalid) --3 R eserved R R/W 4 Isochronous_endpoint (1 - isochronous; 0 - non-isochronous) R R/W 15:5 Max_packet_size R/W[1] R/W 31:16 DMA_buffer_length This value is specified in bytes for non-isochronous endpoints and in number of packets for isochronous endpoints.

2 R/W R/W 31:0 DMA_buffer_start_addr

3 R/W R/I 0 DD_retired (To be initialized to 0)

W R/I 4:1 DD_status (To be initialized to 0000): 0000 - NotServiced 0001 - BeingServiced 0010 - NormalCompletion 0011 - DataUnderrun (short packet) 1000 - DataOverrun 1001 - SystemError W R/I 5 Packet_valid (To be initialized to 0) W R/I 6 LS_byte_extracted (ATLE mode) (To be initialized to 0) W R/I 7 MS_byte_extracted (ATLE mode) (To be initialized to 0) R W 13:8 Message_length_position (ATLE mode) - - 15:14 Reserved R/W R/I 31:16 Present_DMA_count (To be initialized to 0)

4 R/W R/W 31:0 Isochronous_packetsize_memory_address

15.4.2 DMA_mode

Specifies the DMA mode of operation. Two modes have been defined: Normal and Automatic Transfer Length Extraction (ATLE) mode. In normal mode, software initializes the DMA_buffer_length for OUT endpoints. In ATLE mode, the DMA_buffer_length is extracted from the incoming data. See Section 11–15.7 “Auto Length Transfer Extraction (ATLE) mode operation” on page 261 for more details.

15.4.3 Next_DD_valid

This bit indicates whether the software has prepared the next DMA descriptor. If set, the DMA engine fetches the new descriptor when it is finished with the current one.

15.4.4 Isochronous_endpoint

When set, this bit indicates that the descriptor belongs to an isochronous endpoint. Hence 5 words have to be read when fetching it.

15.4.5 Max_packet_size

The maximum packet size of the endpoint. This parameter is used while transferring the data for IN endpoints from the memory. It is used for OUT endpoints to detect the short packet. This is applicable to non-isochronous endpoints only. This field should be set to the same MPS value that is assigned for the endpoint using the USBMaxPSize register.

15.4.6 DMA_buffer_length

This indicates the depth of the DMA buffer allocated for transferring the data. The DMA engine will stop using this descriptor when this limit is reached and will look for the next descriptor. In Normal mode operation, software sets this value for both IN and OUT endpoints. In ATLE mode operation, software sets this value for IN endpoints only. For OUT endpoints, hardware sets this value using the extracted length of the data stream. For isochronous endpoints, DMA_buffer_length is specified in number of packets, for non-isochronous endpoints in bytes.

15.4.7 DMA_buffer_start_addr

The address where the data is read from or written to. This field is updated each time the DMA engine finishes transferring a packet.

15.4.8 DD_retired

This bit is set by hardware when the DMA engine finishes the current descriptor. This happens when the end of the buffer is reached, a short packet is transferred (non-isochronous endpoints), or an error condition is detected.

15.4.9 DD_status

The status of the DMA transfer is encoded in this field. The following codes are defined:

NotServiced - No packet has been transferred yet.
BeingServiced - At least one packet is transferred.
NormalCompletion - The DD is retired because the end of the buffer is reached and there were no errors. The DD_retired bit is also set.

DataUnderrun - Before reaching the end of the DMA buffer, the USB transfer is terminated because a short packet is received. The DD_retired bit is also set.
DataOverrun - The end of the DMA buffer is reached in the middle of a packet transfer. This is an error situation. The DD_retired bit is set. The present DMA count field is equal to the value of DMA_buffer_length. The packet must be re-transmitted from the endpoint buffer in another DMA transfer. The corresponding EPxx_DMA_ENABLE bit in USBEpDMASt is cleared.
SystemError - The DMA transfer being serviced is terminated because of an error on the AHB bus. The DD_retired bit is not set in this case. The corresponding EPxx_DMA_ENABLE in USBEpDMASt is cleared. Since a system error can happen while updating the DD, the DD fields in RAM may be unreliable.

15.4.10 Packet_valid

This bit is used for isochronous endpoints. It indicates whether the last packet transferred to the memory is received with errors or not. This bit is set if the packet is valid, i.e., it was received without errors. See Section 11–15.6 “Isochronous endpoint operation” on page 259 for isochronous endpoint operation. This bit is unnecessary for non-isochronous endpoints because a DMA request is generated only for packets without errors, and thus Packet_valid will always be set when the request is generated.

15.4.11 LS_byte_extracted

Used in ATLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of the transfer length has been extracted. The extracted size is reflected in the DMA_buffer_length field, bits 23:16.

15.4.12 MS_byte_extracted

Used in ATLE mode. When set, this bit indicates that the Most Significant Byte (MSB) of the transfer size has been extracted. The size extracted is reflected in the DMA_buffer_length field, bits 31:24. Extraction stops when LS_Byte_extracted and MS_byte_extracted bits are set.

15.4.13 Present_DMA_count

The number of bytes transferred by the DMA engine. The DMA engine updates this field after completing each packet transfer. For isochronous endpoints, Present_DMA_count is the number of packets transferred; for non-isochronous endpoints, Present_DMA_count is the number of bytes.

15.4.14 Message_length_position

Used in ATLE mode. This field gives the offset of the message length position embedded in the incoming data packets. This is applicable only for OUT endpoints. Offset 0 indicates that the message length starts from the first byte of the first packet.

15.4.15 Isochronous_packetsize_memory_address

The memory buffer address where the packet size information along with the frame number has to be transferred or fetched. See Figure 11–30. This is applicable to isochronous endpoints only.

15.5 Non-isochronous endpoint operation

15.5.1 Setting up DMA transfers

Software prepares the DMA Descriptors (DDs) for those physical endpoints to be enabled for DMA transfer. These DDs are present in on-chip RAM. The start address of the first DD is programmed into the DMA Description pointer (DDP) location for the corresponding endpoint in the UDCA. Software then sets the EPxx_DMA_ENABLE bit for this endpoint in the USBEpDMAEn register (Section 11–10.7.6 ).The DMA_mode bit field in the descriptor is set to ‘00’ for normal mode operation. All other DD fields are initialized as specified in Table 11–250. DMA operation is not supported for physical endpoints 0 and 1 (default control endpoints).

15.5.2 Finding DMA Descriptor

When there is a trigger for a DMA transfer for an endpoint, the DMA engine will first determine whether a new descriptor has to the fetched or not. A new descriptor does not have to be fetched if the last packet transferred was for the same endpoint and the DD is not yet in the retired state. An internal flag called DMA_PROCEED is used to identify this condition (see Section 11–15.5.4 “ Optimizing descriptor fetch” on page 258). If a new descriptor has to be read, the DMA engine will calculate the location of the DDP for this endpoint and will fetch the start address of the DD from this location. A DD start address at location zero is considered invalid. In this case the NDDR interrupt is raised. All other word-aligned addresses are considered valid. When the DD is fetched, the DD status word (word 3) is read first and the status of the DD_retired bit is checked. If not set, DDP points to a valid DD. If DD_retired is set, the DMA engine will read the control word (word 1) of the DD. If Next_DD_valid bit is set, the DMA engine will fetch the Next_DD_pointer field (word 0) of the DD and load it to the DDP. The new DDP is written to the UDCA area. The full DD (4 words) will then be fetched from the address in the DDP. The DD will give the details of the DMA transfer to be done. The DMA engine will load its hardware resources with the information fetched from the DD (start address, DMA count etc.). If Next_DD_valid is not set and DD_retired bit is set, the DMA engine raises the NDDR interrupt for this endpoint and clears the corresponding EPxx_DMA_ENABLE bit.

15.5.3 Transferring the data

For OUT endpoints, the current packet is read from the EP_RAM by the DMA Engine and transferred to on-chip RAM memory locations starting from DMA_buffer_start_addr. For IN endpoints, the data is fetched from on-chip RAM at DMA_buffer_start_addr and written to the EP_RAM. The DMA_buffer_start_addr and Present_DMA_count fields are updated after each packet is transferred.

15.5.4 Optimizing descriptor fetch

A DMA transfer normally involves multiple packet transfers. Hardware will not re-fetch a new DD from memory unless the endpoint changes. To indicate an ongoing multi-packet transfer, hardware sets an internal flag called DMA_PROCEED.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 259 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller The DMA_PROCEED flag is cleared after the required number of bytes specified in the DMA_buffer_length field is transferred. It is also cleared when the software writes into the USBEpDMADis register. The ability to clear the DMA_PROCEED flag allows software to to force the DD to be re-fetched for the next packet transfer. Writing all zeros into the USBEpDMADis register clears the DMA_PROCEED flag without disabling DMA operation for any endpoint.

15.5.5 Ending the packet transfer

On completing a packet transfer, the DMA engine writes back the DD with updated status information to the same memory location from where it was read. The DMA_buffer_start_addr, Present_DMA_count, and the DD_status fields in the DD are updated. A DD can have the following types of completion: Normal completion - If the current packet is fully transferred and the Present_DMA_count field equals the DMA_buffer_length, the DD has completed normally. The DD will be written back to memory with DD_retired set and DD_status set to NormalCompletion. The EOT interrupt is raised for this endpoint. USB transfer end completion - If the current packet is fully transferred and its size is less than the Max_packet_size field, and the end of the DMA buffer is still not reached, the USB transfer end completion occurs. The DD will be written back to the memory with DD_retired set and DD_Status set to the DataUnderrun completion code. The EOT interrupt is raised for this endpoint. Error completion - If the current packet is partially transferred i.e. the end of the DMA buffer is reached in the middle of the packet transfer, an error situation occurs. The DD is written back with DD_retired set and DD_status set to the DataOverrun status code. The EOT interrupt is raised for this endpoint and the corresponding bit in USBEpDMASt register is cleared. The packet will be re-sent from the endpoint buffer to memory when the corresponding EPxx_DMA_ENABLE bit is set again using the USBEpDMAEn register.

15.5.6 No_Packet DD

For an IN transfer, if the system does not have any data to send for a while, it can respond to an NDDR interrupt by programming a No_Packet DD. This is done by setting both the Max_packet_size and DMA_buffer_length fields in the DD to 0. On processing a No_Packet DD, the DMA engine clears the DMA request bit in USBDMARSt corresponding to the endpoint without transferring a packet. The DD is retired with a status code of NormalCompletion. This can be repeated as often as necessary. The device will respond to IN token packets on the USB bus with a NAK until a DD with a data packet is programmed and the DMA transfers the packet into the endpoint buffer.

15.6 Isochronous endpoint operation

For isochronous endpoints, the packet size can vary for each packet. There is one packet per isochronous endpoint for each frame.

15.6.1 Setting up DMA transfers

Software sets the isochronous endpoint bit to 1 in the DD, and programs the initial value of the Isochronous_packetsize_memory_address field. All other fields are initialized the same as for non-isochronous endpoints.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 260 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller For isochronous endpoints, the DMA_buffer_length and Present_DMA_count fields are in frames rather than bytes.

15.6.2 Finding the DMA Descriptor

Finding the descriptors is done in the same way as that for a non-isochronous endpoint. A DMA request will be placed for DMA-enabled isochronous endpoints on every FRAME interrupt. On processing the request, the DMA engine will fetch the descriptor and if Isochronous_endpoint is set, will fetch the Isochronous_packetsize_memory_address from the fifth word of the DD.

15.6.3 Transferring the Data

The data is transferred to or from the memory location DMA_buffer_start_addr. After the end of the packet transfer the Present_DMA_count value is incremented by 1. The isochronous packet size is stored in memory as shown in Figure 11–30. Each word in the packet size memory shown is divided into fields: Frame_number (bits 31 to 17), Packet_valid (bit 16), and Packet_length (bits 15 to 0). The space allocated for the packet size memory for a given DD should be DMA_buffer_length words in size – one word for each packet to transfer. OUT endpoints At the completion of each frame, the packet size is written to the address location in Isochronous_packet_size_memory_address, and Isochronous_packet_size_memory_address is incremented by 4. IN endpoints Only the Packet_length field of the isochronous packet size word is used. For each frame, an isochronous data packet of size specified by this field is transferred from the USB device to the host, and Isochronous_packet_size_memory_address is incremented by 4 at the end of the packet transfer. If Packet_length is zero, an empty packet will be sent by the USB device.

15.6.4 DMA descriptor completion

DDs for isochronous endpoints can only end with a status code of NormalCompletion since there is no short packet on Isochronous endpoints, and the USB transfer continues indefinitely until a SystemError occurs. There is no DataOverrun detection for isochronous endpoints.

15.6.5 Isochronous OUT Endpoint Operation Example

Assume that an isochronous endpoint is programmed for the transfer of 10 frames and that the transfer begins when the frame number is 21. After transferring four frames with packet sizes of 10,15, 8 and 20 bytes without errors, the descriptor and memory map appear as shown in Figure 11–30 The_total_number_of_bytes_transferred = 0x0A + 0x0F + 0x08 + 0x14 = 0x35. The Packet_valid bit (bit 16) of all the words in the packet length memory is set to 1.

15.7 Auto Length Transfer Extr action (ATLE) mode operation

Some host drivers such as NDIS (Network Driver Interface Specification) host drivers are capable of concatenating small USB transfers (delta transfers) to form a single large USB transfer. For OUT USB transfers, the device hardware has to break up this concatenated transfer back into the original delta transfers and transfer them to separate DMA buffers. This is achieved by setting the DMA mode to Auto Transfer Length Extraction (ATLE) mode in the DMA descriptor. ATLE mode is supported for Bulk endpoints only. OUT transfers in ATLE mode Fig 30. Isochronous OUT endpoint operation example DMA_modeNext_DD_ValidIsochronous_endpointMax_packet_sizeDMA_buffer_length 01631 after 4 packets 150x60000010 0x80000035 0x000A0010 0x4 0x0 FULL EMPTY data memory packet size memory 0x60000000 0x80000000 0010x00x000A Next_DD_Pointer NULL DMA_buffer_start_addr Isocronous_packetsize_memory_address DD_RetiredDD_StatusPacket_ValidATLE settingsPresent_DMA_Count 0x0 0NANA0x0 Packet_Lengthframe_ number Packet_Valid 00x1- -

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 263 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller In ATLE mode, the last buffer length to be transferred always ends with a short or empty packet indicating the end of the USB transfer. If the concatenated transfer lengths are such that the USB transfer ends on a MaxPacketSize packet boundary, the (NDIS) host will send an empty packet to mark the end of the USB transfer. IN transfers in ATLE mode For IN USB transfers from the device to the host, DMA_buffer_length is set by the device software as in normal mode. In ATLE mode, the device concatenates data from multiple DDs to form a single USB transfer. If a DD is retired in the middle of a packet (packet size is less than MaxPacketSize), the next DD referenced by Next_DD_pointer is fetched, and the remaining bytes to form a packet of MaxPacketSize are transferred from the next DD’s buffer. If the next DD is not programmed (i.e. Next_DD_valid field in DD is 0), and the DMA buffer length for the current DD has completed before the MaxPacketSize packet boundary, then the available bytes from current DD are sent as a short packet on USB, which marks the end of the USB transfer for the host. If the last buffer length completes on a MaxPacketSize packet boundary, the device software must program the next DD with DMA_buffer_length field 0, so that an empty packet is sent by the device to mark the end of the USB transfer for the host.

15.7.1 Setting up the DMA transfer

For OUT endpoints, the host hardware needs to set the field Message_length_position in the DD. This indicates the start location of the message length in the incoming data packets. Also the device software has to set the DMA_buffer_length field to 0 for OUT endpoints because this field is updated by the device hardware after the extraction of the buffer length. For IN endpoints, descriptors are set in the same way as in normal mode operation. Since a single packet can be split between two DDs, software should always keep two DDs ready, except for the last DMA transfer which ends with a short or empty packet.

15.7.2 Finding the DMA Descriptor

DMA descriptors are found in the same way as the normal mode operation.

15.7.3 Transferring the Data

If the LS_byte_extracted or MS_byte_extracted bit in the status field is not set, the hardware will extract the transfer length from the data stream and program DMA_buffer_length. Once the extraction is complete both the LS_byte_extracted and MS_byte_extracted bits will be set. IN endpoints The DMA transfer proceeds as in normal mode and continues until the number of bytes transferred equals the DMA_buffer_length.

15.7.4 Ending the packet transfer

The DMA engine proceeds with the transfer until the number of bytes specified in the field DMA_buffer_length is transferred to or from on-chip RAM. Then the EOT interrupt will be generated. If this happens in the middle of the packet, the linked DD will get loaded and the remaining part of the packet gets transferred to or from the address pointed by the new DD. OUT endpoints If the linked DD is not valid and the packet is partially transferred to memory, the DD ends with DataOverrun status code set, and the DMA will be disabled for this endpoint. Otherwise DD_status will be updated with the NormalCompletion status code. IN endpoints If the linked DD is not valid and the packet is partially transferred to USB, the DD ends with a status code of NormalCompletion in the DD_status field. This situation corresponds to the end of the USB transfer, and the packet will be sent as a short packet. Also, when the linked DD is valid and buffer length is 0, an empty packet will be sent to indicate the end of the USB transfer. 16. Double buffered endpoint operation The Bulk and Isochronous endpoints of the USB Device Controller are double buffered to increase data throughput. When a double-buffered endpoint is realized, enough space for both endpoint buffers is automatically allocated in the EP_RAM. See Section 11–10.4.1. For the following discussion, the endpoint buffer currently accessible to the CPU or DMA engine for reading or writing is said to be the active buffer.

16.1 Bulk endpoints

For Bulk endpoints, the active endpoint buffer is switched by the SIE Clear Buffer or Validate Buffer commands. The following example illustrates how double buffering works for a Bulk OUT endpoint in Slave mode: Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty, and that the active buffer is B_1. 1. The host sends a data packet to the endpoint. The device hardware puts the packet into B_1, and generates an endpoint interrupt. 2. Software clears the endpoint interrupt and begins reading the packet data from B_1. While B_1 is still being read, the host sends a second packet, which device hardware places in B_2, and generates an endpoint interrupt. 3. Software is still reading from B_1 when the host attempts to send a third packet. Since both B_1 and B_2 are full, the device hardware responds with a NAK. 4. Software finishes reading the first pack et from B_1 and sends a SIE Clear Buffer command to free B_1 to receive another packet. B_2 becomes the active buffer.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 265 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller 5. Software sends the SIE Select Endpoint command to read the Select Endpoint Register and test the FE bit. Software finds that the active buffer (B_2) has data (FE=1). Software clears the endpoint interrupt and begins reading the contents of B_2. 6. The host re-sends the third packet which device hardware places in B_1. An endpoint interrupt is generated. 7. Software finishes reading the second packet from B_2 and sends a SIE Clear Buffer command to free B_2 to receive another packet. B_1 becomes the active buffer. Software waits for the next endpoint interrupt to occur (it already has been generated back in step 6). 8. Software responds to the endpoint interrup t by clearing it and begins reading the third packet from B_1. 9. Software finishes reading the third packet from B_1 and sends a SIE Clear Buffer command to free B_1 to receive another packet. B_2 becomes the active buffer. 10. Software tests the FE bit and finds that the active buffer (B_2) is empty (FE=0). 11. Both B_1 and B_2 are empty. Software waits for the next endpoint interrupt to occur. The active buffer is now B_2. The next data packet sent by the host will be placed in B_2. The following example illustrates how double buffering works for a Bulk IN endpoint in Slave mode: Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty and that the active buffer is B_1. The interrupt on NAK feature is enabled. 1. The host requests a data packet by sending an IN token packet. The device responds with a NAK and generates an endpoint interrupt. 2. Software clears the endpoint interrupt. The device has three packets to send. Software fills B_1 with the first packet and sends a SIE Validate Buffer command. The active buffer is switched to B_2. 3. Software sends the SIE Select Endpoint command to read the Select Endpoint Register and test the FE bit. It finds that B_2 is empty (FE=0) and fills B_2 with the second packet. Software sends a SIE Validate Buffer command, and the active buffer is switched to B_1. 4. Software waits for the en dpoint interrupt to occur. 5. The device successfully sends the packet in B_1 and clears the buffer. An endpoint interrupt occurs. 6. Software clears the endpoint interrupt. Software fills B_1 with the third packet and validates it using the SIE Validate Buffer command. The active buffer is switched to B_2. 7. The device successfully sends the second packet from B_2 and generates an endpoint interrupt. 8. Software has no more packets to se nd, so it simply clears the interrupt. 9. The device successfully sends the third packet from B_1 and generates an endpoint interrupt. 10. Software has no more packets to send, so it simply clears the interrupt.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 266 of 835 NXP Semiconductors UM10360 Chapter 11: LPC17xx USB device controller 11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written by software will go into B_2. In DMA mode, switching of the active buffer is handled automatically in hardware. For Bulk IN endpoints, proactively filling an endpoint buffer to take advantage of the double buffering can be accomplished by manually starting a packet transfer using the USBDMARSet register.

16.2 Isochronous endpoints

For isochronous endpoints, the active data buffer is switched by hardware when the FRAME interrupt occurs. The SIE Clear Buffer and Validate Buffer commands do not cause the active buffer to be switched. Double buffering allows the software to make full use of the frame interval writing or reading a packet to or from the active buffer, while the packet in the other buffer is being sent or received on the bus. For an OUT isochronous endpoint, any data not read from the active buffer before the end of the frame is lost when it switches. For an IN isochronous endpoint, if the active buffer is not validated before the end of the frame, an empty packet is sent on the bus when the active buffer is switched, and its contents will be overwritten when it becomes active again.

Power: In the PCONP register ( Table 4–46), set bit PCUSB.

Remark: On reset, the USB block is disabled (PCUSB = 0).

Clock: The USB block can be used with a dedicated USB PLL (PLL1) to obtain the

USB clock or with the Main PLL (PLL0). See Section 4–6.1.

Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to
Wake-up: Activity on the USB bus port can wake up the microcontroller from

Power-down mode, see Section 4–8.8.

Interrupts: Inte rrupts are enabled in the NVIC using the appropriate Interrupt Set
Initialization: see Section 13–11.

I2C interface controls the external OTG ATX. configuration of the devices. All transactions are initiated by the host controller. The host controller enables data exchange with various USB devices attached to the bus. interface complies to the OHCI specification. Table 251. USB (OHCI) related acronyms and abbreviations used in this chapter

3.1 Features

OHCI compliant.
OpenHCI specifies the operation and interface of the USB Host Controller and SW Driver – USBOperational: Process Lists and generate SOF Tokens. – USBReset: Forces reset signaling on the bus, SOF disabled. – USBSuspend: Monitor USB for wake-up activity. – USBResume: Forces resume signaling on the bus.
The Host Controller has four USB states visible to the SW Driver.
HCCA register points to Interrupt and Isochronous Descriptors List.
ControlHeadED and BulkHeadED registers point to Control and Bulk Descriptors List.

3.2 Architecture

The architecture of the USB host controller is shown below in Figure 12–32. The USB interface is controlled by the OTG controller. It has one USB port.

4.1 Pin description

4.1.1 USB host usage note

port, see the USB OTG chapter, Section 13–7. writing a 1 to the PCUSB bit in the PCONP register, see Table 4–46.

4.2 Software interface

specification. The register map is shown in the next subsection.

4.2.1 Register map

Table 252. USB Host port pins Table 253. USB Host register address definitions specification that is implemented by the Host Controller. hardware interrupts by setting the appropriate bits. in turn disable that event leading to hardware interrupt. or interrupt endpoint descriptor.

4.2.2 USB Host Register Definitions

Refer to the OHCI specification document on the Compaq website for register definitions. descriptor of the control list. descriptor of the bulk list. descriptor of the bulk list. descriptor added to the ‘Done’ queue. 8-byte LS packet before EOF. characteristics of the root hub. characteristics of the Root Hub. represents the hub status change field. and zz (0x00) is a unique revision number. Table 253. USB Host register address definitions …continued

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 271 of 835 1. How to read this chapter The USB OTG controller is available in the LPC1768, LPC1766, LPC1765, LPC1758, LPC1756, and LPC1754. On these devices, the USB controller can be configured for device, Host, or OTG operation. 2. Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set bit PCUSB. Remark: On reset, the USB block is disabled (PCUSB = 0). 2. Clock: The USB clock can generated using the dedicated USB PLL (PLL1) or with the Main PLL (PLL0). See Section 4–6.1. 3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to PINMODE5 (Section 8–5). 4. Wake-up: Activity on the USB bus port can wake up the microcontroller from Power-down mode (see Section 13–10.2 and Section 4–8.8). 5. Interrupts: Inte rrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 6. Initialization: see Section 13–11. 3. Introduction This chapter describes the OTG and I2C portions of the USB 2.0 OTG dual role device controller which integrates the (OHCI) host controller, device controller, and I2C. The I2C interface that is part of the USB block is intended to control an external OTG transceiver, and is not the same as the I2C peripherals described in Section 19–1. USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The specification and more information on USB OTG can be found on the USB Implementers Forum web site. 4. Features

Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a.
Hardware support for Host Negotiation Protocol (HNP).
Includes a programmable timer required for HNP and SRP .
Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev. 1.0. UM10360 Chapter 13: LPC17xx USB OTG controller Rev. 01 — 4 January 2010 User manual

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 272 of 835 NXP Semiconductors UM10360 Chapter 13: LPC17xx USB OTG controller 5. Architecture The architecture of the USB OTG controller is shown below in the block diagram. The host, device, OTG, and I2C controllers can be programmed through the register interface. The OTG controller enables dynamic switching between host and device roles through the HNP protocol. One port may be connected to an external OTG transceiver to support an OTG connection. The communication between the register interface and an external OTG transceiver is handled through an I 2C interface and through the external OTG transceiver interrupt signal. For USB connections that use the device or host controller only (not OTG), the ports use an embedded USB Analog Transceiver (ATX). 6. Modes of operation The OTG controller is capable of operating in the following modes:

Host mode (see Figure 13–34)
Device mode (see Figure 13–35)
OTG mode (see Figure 13–36) Fig 33. USB OTG controller block diagram REGISTER INTERFACE BUS MASTER INTERFACE USB ATX DMA interface (AHB master) register interface (AHB slave) AHB bus I2C CONTROLLER DEVICE CONTROLLER HOST CONTROLLER EP_RAM OTG CONTROLLER ATX CONTROL LOGIC/ PORT MUX USB port OTG TRANSCEIVER USB OTG BLOCK

7.1 Connecting the USB port to an external OTG transceiver

Table 254. USB OTG port pins

7.2 Connecting USB as a host

The USB port is connected as host using an embedded USB transceiver. There is no OTG functionality on the port.

7.3 Connecting USB as device

The USB port is connected as device. There is no OTG functionality on the USB port. Fig 35. USB host port configuration USB_UP_LED USB_D+ USB_D− USB_PWRD 15 kΩ 15 kΩLPC176x USB-A connector 33 Ω 33 Ω graphicID VDD USB_OVRCR USB_PPWR LM3526-L ENA IN 5 V FLAGA OUTA VDD VBUS VSS Fig 36. USB device port configuration LPC176x USB-B connector 33 Ω 33 Ω graphicID USB_UP_LED USB_CONNECT VDD VDD USB_D+ USB_D− VBUS VBUS VSS

8.1 USB Interrupt Status Re gister (USBIntSt - 0x5000 C1C0)

determine their status with a single read operation. Table 255. USB OTG and I 2C register address definitions Table 256. USB Interrupt Status register - (U SBIntSt - address 0x5000 C1C0) bit description

8.2 OTG Interrupt Status Register (OTGIntSt - 0x5000 C100)

handoff sequence. See Section 13–9 for more information on when these bits are set.

8.3 OTG Interrupt Enable Register (OTGIntEn - 0x5000 C104)

interrupt line in the USBIntSt register. The bit allocation and reset value of OTGIntEn is the same as OTGIntSt.

8.4 OTG Interrupt Set Register (OTGIntSet - 0x5000 C20C)

Writing a one to a bit in this register will set the corresponding bit in the OTGIntSt register. Writing a zero has no effect. The bit allocation of OTGIntSet is the same as in OTGIntSt. Table 257. OTG Interrupt Status register (OTGIntSt - address 0x5000 C100) bit description needs to disable the D+ pull-up resistor. 3 HNP_SUCCESS HNP succeeded.

8.5 OTG Interrupt Clear Regist er (OTGIntClr - 0x5000 C10C)

8.6 OTG Status and Control Re gister (OTGStCtrl - 0x5000 C110)

functions mapped to port U1 and U2.

Monoshot mode: an interrupt is generated at the end of TIMEOUT_CNT (see Section

OTGIntSt, and the timer will be disabled.

Free running mode: an interrupt is generated at the end of TIMEOUT_CNT (see

Table 258. OTG Status Control register (OTGStCtrl - address 0x5000 C110) bit description HNP succeeds. See Section 13–9. Bit 1 is reserved. 4 TMR_MODE Timer mode selection. cleared, TMR_CNT is reset to 0. 6 TMR_RST Timer reset. Writing one to this bit resets TMR_CNT to 0. restart the timer when the timer is enabled.

8 B_HNP_TRACK Enable HNP tracking for B-device (peripheral), see

HNP_SUCCESS or HNP_FAILURE is set.

9 A_HNP_TRACK Enable HNP tracking for A-device (host), see

HNP_SUCCESS or HNP_FAILURE is set.

8.7 OTG Timer Register (OTGTmr - 0x5000 C114)

8.8 OTG Clock Control Register (OTGClkCtrl - 0x5000 CFF4)

This register controls the clocking of the OTG controller. Whenever software wants to access the registers, the corresponding clock control bit needs to be set. The software does not have to repeat this exercise for every register access, provided that the corresponding OTGClkCtrl bits are already set.

10 PU_REMOVED When the B-device changes its role from peripheral to

host, software sets this bit when it removes the D+ pull-up, see Section 13–9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set. 15:11 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 31:16 TMR_CNT Current timer count value. 0x0 Table 259. OTG Timer register (OTGTmr - address 0x5000 C114) bit description bits. The value read from a reserved bit is not defined. Table 260. OTG clock control register (OTG_clock_control - address 0x5000 CFF4) bit Bit Symbol Value Description Reset Value

0 HOST_CLK_EN Host clock enable 0

0 Disable the Host clock. 1 Enable the Host clock.

1 DEV_CLK_EN Device clock enable 0

0 Disable the Device clock. 1 Enable the Device clock.

2 I2C_CLK_EN I

0 Disable the I 2C clock. 1 Enable the I 2C clock.

3 OTG_CLK_EN OTG clock enable 0

0 Disable the OTG clock. 1 Enable the OTG clock.

8.9 OTG Clock Status Regist er (OTGClkSt - 0x5000 CFF8)

This register holds the clock availability status. When enabling a clock via OTGClkCtrl, software should poll the corresponding bit in this register. If it is set, then software can go ahead with the register access. Software does not have to repeat this exercise for every access, provided that the OTGClkCtrl bits are not disturbed.

8.10 I 2C Receive Register (I2C_RX - 0x5000 C300)

This register is the top byte of the receive FIFO. The receive FIFO is 4 bytes deep. The Rx FIFO is flushed by a hard reset or by a soft reset (I2C_CTL bit 7). Reading an empty FIFO gives unpredictable data results.

4 AHB_CLK_EN AHB master clock enable 0

0 Disable the AHB clock. 1 Enable the AHB clock. 31:5 - NA Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Bit Symbol Value Description Reset Value Table 261. OTG clock status register (OTGClkSt - address 0x5000 CFF8) bit description 0 Host clock is not available. 0 Device clock is not available. 1 Device clock is available.

2 I2C_CLK_ON I

0I 2C clock is not available. 0 OTG clock is not available. 0 AHB clock is not available. reserved bit is not defined.

8.11 I 2C Transmit Register (I2C_TX - 0x5000 C300)

This register is the top byte of the transmit FIFO. The transmit FIFO is 4 bytes deep. occurs (I2C_STS bit 3). Data writes to a full FIFO are ignored. the last byte of a master-receive operation is not acknowledged.

8.12 I 2C Status Register (I2C_STS - 0x5000 C304)

I2C_CTL register and routed to the I2C_USB_INT bit in USBIntSt. Table 262. I 2C Receive register (I2C_RX - address 0x5000 C300) bit description Table 263. I 2C Transmit register (I2C_TX - address 0x5000 C300) bit description value read from a reserved bit is not defined. Table 264. I 2C status register (I2C_STS - address 0x5000 C304) bit description the status register. It is unaffected by slave transactions. 0 Transaction has not completed. 0 No arbitration failure on last transmission. 1 Arbitration failure occurred on last transmission.

UM10360_1 © NXP B.V. 2010. All rights reserved. is written to the master TX FIFO. 0 Last transmission received an acknowledge. 1 Last transmission did not receive an acknowledge. SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO. 0 Master transmitter does not need data. 1 Master transmitter needs data. cleared when a byte is written to the slave Tx FIFO. 0 Slave transmitter does not need data. 1 Slave transmitter needs data.

0 RX FIFO is not full

1 RX FIFO is full

and is cleared when the RX FIFO contains valid data.

1 RX FIFO is empty

cleared when the TX FIFO is not full.

8.13 I 2C Control Register (I2C_CTL - 0x5000 C308)

The I2C_CTL register is used to enable interrupts and reset the I2C state machine. Enabled interrupts cause the USB_I2C_INT interrupt output line to be asserted when set. and is cleared when the TX FIFO contains valid data. 0 TX FIFO contains valid data. 31:12 - NA Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Table 265. I 2C Control register (I2C_CTL - address 0x5000 C308) bit description 0 Disable the TDI interrupt. that transmitted byte was not acknowledged. 0 Disable the DRMI interrupt. 1 Enable the DRMI interrupt. so the SCL line is being held low. 0 Disable the DRSI interrupt. 1 Enable the DRSI interrupt. indicate that the receive FIFO cannot accept any more data.

8.14 I 2C Clock High Register (I2C_CLKHI - 0x5000 C30C)

high period of the slower I2C serial clock, SCL.

8.15 I 2C Clock Low Register (I2C_CLKLO - 0x5000 C310)

low period of the slower I2C serial clock, SCL.

8.16 Interrupt handling

data is available in the receive FIFO (i.e. not empty). to indicate that the more data can be written to the transmit FIFO. Note that this is not full. and do this without polling the status register. NOT modified by a soft reset.

1 Reset the I

2C to idle state. Self clearing. reserved bit is not defined. Table 266. I 2C_CLKHI register (I2C_CLKHI - address 0x5000 C30C) bit description clocks the serial clock (SCL) will be high. Table 267. I 2C_CLKLO register (I2C_CLKLO - address 0x5000 C310) bit description clocks the serial clock (SCL) will be low.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 284 of 835 NXP Semiconductors UM10360 Chapter 13: LPC17xx USB OTG controller I2C related interrupts are set in the I2C_STS register and routed, if enabled by I2C_CTL, to the USB_I2C_INT bit. For more details on the interrupts created by device controller, see the USB device chapter. For interrupts created by the host controllers, see the OHCI specification. The EN_USB_INTS bit in the USBIntSt register enables the routing of any of the USB related interrupts to the NVIC controller (see Figure 13–37). Remark: During the HNP switching between host and device with the OTG stack active, an action may raise several levels of interrupts. It is advised to let the OTG stack initiate any actions based on interrupts and ignore device and host level interrupts. This means that during HNP switching, the OTG stack provides the communication to the host and device controllers. 9. HNP support This section describes the hardware support for the Host Negotiation Protocol (HNP) provided by the OTG controller. When two dual-role OTG devices are connected to each other, the plug inserted into the mini-AB receptacle determines the default role of each device. The device with the mini-A plug inserted becomes the default Host (A-device), and the device with the mini-B plug inserted becomes the default Peripheral (B-device). Once connected, the default Host (A-device) and the default Peripheral (B-device) can switch Host and Peripheral roles using HNP . The context of the OTG controller operation is shown in Figure 13–38 . Each controller (Host, Device, or OTG) communicates with its software stack through a set of status and control registers and interrupts. In addition, the OTG software stack communicates with the external OTG transceiver through the I2C interface and the external transceiver interrupt signal. Fig 37. USB OTG interrupt handling USB_INT_REQ_HP USB_INT_REQ_LP USB_INT_REQ_DMA EN_USB_INTS to NVIC USB_HOST_INT USB_OTG_INT USB_I2C_INT USB_NEED_CLOCK USBIntSt USB DEVICE INTERRUPTS USB HOST INTERRUPTS OTGIntSt TMR REMOVE_PU HNP_SUCCESS HNP_FAILURE USB I2C INTERRUPTS

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 285 of 835 NXP Semiconductors UM10360 Chapter 13: LPC17xx USB OTG controller The OTG software stack is responsible for implementing the HNP state machines as described in the On-The-Go Supplement to the USB 2.0 Specification. The OTG controller hardware provides support for some of the state transitions in the HNP state machines as described in the following subsections. The USB state machines, the HNP switching, and the communications between the USB controllers are described in more detail in the following documentation:

USB OHCI specification
USB OTG supplement, version 1.2
USB 2.0 specification
ISP1302 data sheet and user manual

9.1 B-device: peripheral to host switching

In this case, the default role of the OTG controller is peripheral (B-device), and it switches roles from Peripheral to Host. The On-The-Go Supplement defines the behavior of a dual-role B-device during HNP using a state machine diagram. The OTG software stack is responsible for implementing all of the states in the Dual-Role B-Device State Diagram. The OTG controller hardware provides support for the state transitions between the states b_peripheral, b_wait_acon, and b_host in the Dual-Role B-Device state diagram. Setting B_HNP_TRACK in the OTGStCtrl register enables hardware support for the B-device switching from peripheral to host. The hardware actions after setting this bit are shown in Figure 13–39. Fig 38. USB OTG controller with software stack HOST CONTROLLER MUX OHCI STACK OTG STACK DEVICE STACK USB BUS ISP1302 OTG CONTROLLER DEVICE CONTROLLER I2C CONTROLLER

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 286 of 835 NXP Semiconductors UM10360 Chapter 13: LPC17xx USB OTG controller Figure 13–40 shows the actions that the OTG software stack should take in response to the hardware actions setting REMOVE_PU, HNP_SUCCESS, AND HNP_FAILURE. The relationship of the software actions to the Dual-Role B-Device states is also shown. B-device states are in bold font with a circle around them. Fig 39. Hardware support for B-device switchin g from peripheral state to host state idle set HNP_SUCCESS set PORT_FUNC[0] drive J on internal host controller port and SE0 on U1 wait 25 μs for bus to settle disconnect device controller from U1 set REMOVE_PU bus suspended ? set HNP_FAILURE, clear B_HNP_TRACK, clear PU_REMOVED reconnect port U1 to the device controller reconnect port U1 to the device controller connect U1 to host controller clear B_HNP_TRACK clear PU_REMOVED PU_REMOVED set? PU_REMOVED set? bus reset/resume detected? connect from A-device detected? bus reset/resume detected? SE0 sent by host? B_HNP_TRACK = 0 no yes yes no no yes yes no B_HNP_TRACK = 1 ? no no no yes

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 287 of 835 NXP Semiconductors UM10360 Chapter 13: LPC17xx USB OTG controller Note that only the subset of B-device HNP states and state transitions supported by hardware are shown. Software is responsible for implementing all of the HNP states. Figure 13–40 may appear to imply that the interrupt bits such as REMOVE_PU should be polled, but this is not necessary if the corresponding interrupt is enabled. Following are code examples that show how the actions in Figure 13–40 are accomplished. The examples assume that ISP1302 is being used as the external OTG transceiver. Remove D+ pull-up /* Remove D+ pull-up through ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x007; // Send OTG Control (Clear) register address OTG_I2C_TX = 0x201; // Clear DP_PULLUP bit, send STOP condition Fig 40. State transitions implemente d in software during B-device switching from peripheral to host REMOVE_PU set? HNP_FAILURE set? HNP_SUCCESS set? b_peripheral when host sends SET_FEATURE with b_hnp_enable, set B_HNP_TRACK remove D+ pull-up, set PU_REMOVED b_peripheral add D+ pull-up b_wait_acon b_host no yes go to go to go to yes no no yes

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 288 of 835 NXP Semiconductors UM10360 Chapter 13: LPC17xx USB OTG controller /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Add D+ pull-up /* Add D+ pull-up through ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x006; // Send OTG Control (Set) register address OTG_I2C_TX = 0x201; // Set DP_PULLUP bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI;

9.2 A-device: host to pe ripheral HNP switching

In this case, the role of the OTG controller is host (A-device), and the A-device switches roles from host to peripheral. The On-The-Go Supplement defines the behavior of a dual-role A-device during HNP using a state machine diagram. The OTG software stack is responsible for implementing all of the states in the Dual-Role A-Device State Diagram. The OTG controller hardware provides support for the state transitions between a_host, a_suspend, a_wait_vfall, and a_peripheral in the Dual-Role A-Device state diagram. Setting A_HNP_TRACK in the OTGStCtrl register enables hardware support for switching the A-device from the host state to the device state. The hardware actions after setting this bit are shown in Figure 13–41.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 289 of 835 NXP Semiconductors UM10360 Chapter 13: LPC17xx USB OTG controller Figure 13–42 shows the actions that the OTG software stack should take in response to the hardware actions setting TMR, HNP_SUCCESS, and HNP_FAILURE. The relationship of the software actions to the Dual-Role A-Device states is also shown. A-device states are shown in bold font with a circle around them. Fig 41. Hardware support for A-device switchin g from host state to peripheral state disconnect host controller from U1 set HNP_FAILURE, clear A_HNP_TRACK clear A_HNP_TRACK set HNP_SUCCESS connect device to U1 by clearing PORT_FUNC[0] bus reset detected? OTG timer expired? (TMR =1 ) resume detected? connnect host controller back to U1 no no no yes yesyes yes yes idle A_HNP_TRACK = 0 bus suspended ? resume detected ? no no A_HNP_TRACK = 1 ? no

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 290 of 835 NXP Semiconductors UM10360 Chapter 13: LPC17xx USB OTG controller Note that only the subset of A-device HNP states and state transitions supported by hardware are shown. Software is responsible for implementing all of the HNP states. Figure 13–42 may appear to imply that the interrupt bits such as TMR should be polled, but this is not necessary if the corresponding interrupt is enabled. Following are code examples that show how the actions in Figure 13–42 are accomplished. The examples assume that ISP1302 is being used as the external OTG transceiver. Fig 42. State transitions implemented in software during A-device switching from host to peripheral HNP_SUCCESS set? HNP_FAILURE set?TMR set? a_host when host sends SET_FEATURE with a_hnp_enable, set A_HNP_TRACK stop the OTG timer a_suspend a_host a_wait_vfall go to a_peripheral go to go to yes yes yes set BDIS_ACON_EN in external OTG transceiver load and enable OTG timer clear BDIS_ACON_EN bit in external OTG transceiver clear BDIS_ACON_EN bit in external OTG transceiver discharge VBUS stop OTG timer suspend host on port 1 go to no no no

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 291 of 835 NXP Semiconductors UM10360 Chapter 13: LPC17xx USB OTG controller Set BDIS_ACON_EN in external OTG transceiver /* Set BDIS_ACON_EN in ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x004; // Send Mode Control 1 (Set) register address OTG_I2C_TX = 0x210; // Set BDIS_ACON_EN bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Clear BDIS_ACON_EN in external OTG transceiver /* Set BDIS_ACON_EN in ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x005; // Send Mode Control 1 (Clear) register address OTG_I2C_TX = 0x210; // Clear BDIS_ACON_EN bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Discharge VBUS /* Clear the VBUS_DRV bit in ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x007; // Send OTG Control (Clear) register address OTG_I2C_TX = 0x220; // Clear VBUS_DRV bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; /* Set the VBUS_DISCHRG bit in ISP1302 */ OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0 OTG_I2C_TX = 0x006; // Send OTG Control (Set) register address OTG_I2C_TX = 0x240; // Set VBUS_DISCHRG bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI;

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 292 of 835 NXP Semiconductors UM10360 Chapter 13: LPC17xx USB OTG controller Load and enable OTG timer /* The following assumes that the OTG timer has previously been */ /* configured for a time scale of 1 ms (TMR_SCALE = “10”) */ /* and monoshot mode (TMR_MODE = 0) */ /* Load the timeout value to implement the a_aidl_bdis_tmr timer */ /* the minimum value is 200 ms */ OTG_TIMER = 200; /* Enable the timer */ OTG_STAT_CTRL |= TMR_EN; Stop OTG timer /* Disable the timer – causes TMR_CNT to be reset to 0 */ OTG_STAT_CTRL &= ~TMR_EN; /* Clear TMR interrupt */ OTG_INT_CLR = TMR; Suspend host on port 1 /* Write to PortSuspendStatus bit to suspend host port 1 – */ /* this example demonstrates the low-level action software needs to take. */ /* The host stack code where this is done will be somewhat more involved. */ HC_RH_PORT_STAT1 = PSS; 10. Clocking and power management The OTG controller clocking is shown in Figure 13–43. A clock switch controls each clock with the exception of ahb_slave_clk. When the enable of the clock switch is asserted, its clock output is turned on and its CLK_ON output is asserted. The CLK_ON signals are observable in the OTGClkSt register. To conserve power, the clocks to the Device, Host, OTG, and I 2C controllers can be disabled when not in use by clearing the respective CLK_EN bit in the OTGClkCtrl register. When the entire USB block is not in use, all of its clocks can be disabled by clearing the PCUSB bit in the PCONP register. When software wishes to access registers in one of the controllers, it should first ensure that the respective controller’s 48 MHz clock is enabled by setting its CLK_EN bit in the OTGClkCtrl register and then poll the corresponding CLK_ON bit in OTGClkSt until set. Once set, the controller’s clock will remain enabled until CLK_EN is cleared by software. Accessing the register of a controller when its 48 MHz clock is not enabled will result in a data abort exception.

10.1 Device clock request signals

The Device controller has two clock request signals, dev_need_clk and dev_dma_need_clk. When asserted, these signals turn on the device’s 48 MHz clock and ahb_master_clk respectively. The dev_need_clk signal is asserted while the device is not in the suspend state, or if the device is in the suspend state and activity is detected on the USB bus. The dev_need_clk signal is de-asserted if a disconnect is detected (CON bit is cleared in the SIE Get Device Status register – Section 11–10.6). This signal allows DEV_CLK_EN to be cleared during normal operation when software does not need to access the Device controller registers – the Device will continue to function normally and automatically shut off its clock when it is suspended or disconnected. Fig 43. Clocking and power control CLOCK SWITCHUSB CLOCK DIVIDER REGISTER INTERFACE DEVICE CONTROLLER HOST CONTROLLER OTG CONTROLLER I2C CONTROLLER AHB_CLK_ON ahb_slave_clk ahb_master_clk DEV_CLK_ON HOST_CLK_ON OTG_CLK_ON I2C_CLK_ON DEV_CLK_EN HOST_CLK_EN OTG_CLK_EN I2C_CLK_EN dev_dma_need_clk host_dma_need_clk dev_need_clk host_need_clk AHB_CLK_EN ahb_need_clk PCUSB cclk usbclk (48 MHz) EN CLOCK SWITCH EN CLOCK SWITCH EN EN CLOCK SWITCH CLOCK SWITCH EN USB_NEED_CLK

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 294 of 835 NXP Semiconductors UM10360 Chapter 13: LPC17xx USB OTG controller The dev_dma_need_clk signal is asserted on any Device controller DMA access to memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA throughput is not affected by any latency associated with re-enabling ahb_master_clk. 2 ms after the last DMA access, dev_dma_need_clk is de-asserted to help conserve power. This signal allows AHB_CLK_EN to be cleared during normal operation.

10.1.1 Host clock request signals

The Host controller has two clock request signals, host_need_clk and host_dma_need_clk. When asserted, these signals turn on the host’s 48 MHz clock and ahb_master_clk respectively. The host_need_clk signal is asserted while the Host controller functional state is not UsbSuspend, or if the functional state is UsbSuspend and resume signaling or a disconnect is detected on the USB bus. This signal allows HOST_CLK_EN to be cleared during normal operation when software does not need to access the Host controller registers – the Host will continue to function normally and automatically shut off its clock when it goes into the UsbSuspend state. The host_dma_need_clk signal is asserted on any Host controller DMA access to memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA throughput is not affected by any latency associated with re-enabling ahb_master_clk. 2 ms after the last DMA access, host_dma_need_clk is de-asserted to help conserve power. This signal allows AHB_CLK_EN to be cleared during normal operation.

10.2 Power-down mode support

The LPC17xx can be configured to wake up from Power-down mode on any USB bus activity. When the chip is in Power-down mode and the USB interrupt is enabled, the assertion of USB_NEED_CLK causes the chip to wake up from Power-down mode. Before Power-down mode can be entered when the USB activity interrupt is enabled, USB_NEED_CLK must be de-asserted. This is accomplished by clearing all of the CLK_EN bits in OTGClkCtrl and putting the Host controller into the UsbSuspend functional state. If it is necessary to wait for either of the dma_need_clk signals or the dev_need_clk to be de-asserted, the status of USB_NEED_CLK can be polled in the USBIntSt register to determine when they have all been de-asserted. 11. USB OTG controller initialization The LPC17xx OTG device controller initialization includes the following steps: 1. Enable the device controller by setting the PCUSB bit of PCONP. 2. Configure and enable the USB PLL (PLL1) or Main PLL (PLL0) to provide 48 MHz for usbclk and the desired frequency for cclk. For correct operation of synchronization logic in the device controller, the minimum cclk frequency is 18 MHz. For the procedure for determining the PLL setting and configuration, see Section 4–5.11 “Procedure for determining PLL0 settings” or Section 4–6.9 “Procedure for determining PLL1 settings”. 3. Enable the desired controller clocks by setting their respective CLK_EN bits in the USBClkCtrl register. Poll the corresponding CLK_ON bits in the USBClkSt register until they are set.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 295 of 835 NXP Semiconductors UM10360 Chapter 13: LPC17xx USB OTG controller 4. Enable the desired USB pin functions by writing to the corresponding PINSEL registers. 5. Follow the appropriate steps in Section 11–13 “USB device controller initialization” to initialize the device controller. 6. Follow the guidelines given in the OpenHC I specification for initializing the host controller.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 296 of 835 1. Basic configuration The UART0/2/3 peripherals are configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set bits PCUART0/2/3. Remark: On reset, UART0 is enabled (PCUART0 = 1), and UART2/3 are disabled (PCUART2/3 = 0). 2. Peripheral clock: In the PCLKSEL0 register (Table 4–40), select PCLK_UART0; in the PCLKSEL1 register (Table 4–41), select PCLK_UART2/3. 3. Baud rate: In register U0/2/3LCR ( Table 14–278), set bit DLAB =1. This enables access to registers DLL (Table 14–272) and DLM (Table 14–273) for setting the baud rate. Also, if needed, set the fractional baud rate in the fractional divider register (Table 14–284). 4. UART FIFO: Use bit FIFO enable (bit 0) in register U0/2/3FCR ( Table 14–277) to enable FIFO. 5. Pins: Select UART pins through the PI NSEL registers and pin modes through the PINMODE registers (Section 8–5). Remark: UART receive pins should not have pull-down resistors enabled. 6. Interrupts: To enable UA RT interrupts set bit DLAB =0 in register U0/2/3LCR (Table 14–278). This enables access to U0/2/3IER (Table 14–274). Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 7. DMA: UART0/2/3 transmit and receiv e functions can operate with the GPDMA controller (see Table 31–544). 2. Features

Data sizes of 5, 6, 7, and 8 bits.
Parity generation and checking: odd, even mark, space or none.
One or two stop bits.
16 byte Receive and Transmit FIFOs.
Built-in baud rate generator, including a fractional rate divider for great versatility.
Supports DMA for both transmit and receive.
Auto-baud capability
Break generation and detection.
Multiprocessor addressing mode.
IrDA mode to support infrared communication.
Support for software flow control. UM10360 Chapter 14: LPC17xx UART0/2/3 Rev. 01 — 4 January 2010 User manual

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 297 of 835 NXP Semiconductors UM10360 Chapter 14: LPC17xx UART0/2/3 3. Pin description 4. Register description Each UART contains registers as shown in Table 14–269. The Divisor Latch Access Bit (DLAB) is contained in UnLCR7 and enables access to the Divisor Latches. Table 268: UARTn Pin description Pin Type Description RXD0, RXD2, RXD3 Input Serial Input. Serial receive data. TXD0, TXD2, TXD3 Output Serial Output. Serial transmit data.

UM10360_1 © NXP B.V. 2010. All rights reserved. [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. Table 269. UART0/2/3 Register Map transmitted is written here. baud rate from the fractional rate divider. baud rate from the fractional rate divider. enable bits for the 7 potential UART interrupts. formatting and break generation. receive status, including line errors. for use with software flow control.

14.4.1 UARTn Receiver Buffer Regi ster (U0RBR - 0x4000 C000, U2RBR -

0x4009 8000, U3RBR - 0x4009 C000 when DLAB = 0) The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes. The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the UnRBR. The UnRBR is always read-only. Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e. the one that will be read in the next read from the RBR), the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the U0LSR register, and then to read a byte from the UnRBR.

4.2 UARTn Transmit Holding Regi ster (U0THR - 0x4000 C000, U2THR -

0x4009 8000, U3THR - 0x4009 C000 when DLAB = 0) The UnTHR is the top byte of the UARTn TX FIFO. The top byte is the newest character in the TX FIFO and can be written via the bus interface. The LSB represents the first bit to transmit. The Divisor Latch Access Bit (DLAB) in UnLCR must be zero in order to access the UnTHR. The UnTHR is always write-only.

4.3 UARTn Divisor Latch LSB regist er (U0DLL - 0x4000 C000, U2DLL -

0x4009 8000, U3DLL - 0x4009 C000 when DLAB = 1) and UARTn Divisor Latch MSB register (U0DLM - 0x4000 C004, U2DLL - 0x4009 8004, U3DLL - 0x4009 C004 when DLAB = 1) The UARTn Divisor Latch is part of the UARTn Baud Rate Generator and holds the value used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce the baud rate clock, which must be 16× the desired baud rate. The UnDLL and UnDLM registers together form a 16-bit divisor where UnDLL contains the lower 8 bits of the divisor and UnDLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed. The Divisor Latch Access Bit (DLAB) in Table 270: UARTn Receiver Buffer Register (U0R BR - address 0x4000 C000, U2RBR - 0x4009 8000, U3RBR -

04009 C000 when DLAB = 0) bit description

Bit Symbol Description Reset Value 7:0 RBR The UARTn Receiver Buffer Register contai ns the oldest received byte in the UARTn Rx FIFO. Undefined 31:8 - Reserved, the value read from a reserved bit is not defined. NA Table 271: UARTn Transmit Holding Register (U0THR - address 0x4000 C000, U2THR - 0x4009 8000, U3THR - 0x4009 C000 when DLAB = 0) bit description Bit Symbol Description Reset Value 7:0 THR Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. NA 31:8 - Reserved, user software should not write ones to reserved bits. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 300 of 835 NXP Semiconductors UM10360 Chapter 14: LPC17xx UART0/2/3 UnLCR must be one in order to access the UARTn Divisor Latches. Details on how to select the right value for U1DLL and U1DLM can be found later in this chapter, see Section 14–4.12.

4.4 UARTn Interrupt Enable Register (U0IER - 0 x4000 C004, U2IER -

0x4009 8004, U3IER - 0x4009 C004 when DLAB = 0) The UnIER is used to enable the three UARTn interrupt sources. Table 272: UARTn Divisor Latch LS B register (U0DLL - address 0x4000 C000, U2DLL - 0x4009 8000, U3DLL - 0x4009 C000 when DLAB = 1) bit description Bit Symbol Description Reset Value 7:0 DLLSB The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn. 0x01 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 273: UARTn Divisor Latch MSB register (U0DLM - address 0x4000 C004, U2DLM - 0x4009 8004, U3DLM - 0x4009 C004 when DLAB = 1) bit description Bit Symbol Description Reset Value 7:0 DLMSB The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn. 0x00 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 274: UARTn Interrupt Enable Register (U0IER - address 0x4000 C004, U2IER - 0x4009 8004, U3IER - 0x4009 C004 when DLAB = 0) bit description Bit Symbol Value Description Reset Value

0 RBR Interrupt

Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. 0 Disable the RDA interrupts. 1 Enable the RDA interrupts.

1 THRE Interrupt

Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. 0 Disable the THRE interrupts. 1 Enable the THRE interrupts.

2 RX Line Status

Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. 0 Disable the RX line status interrupts. 1 Enable the RX line status interrupts. 7:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 8 ABEOIntEn Enables the end of auto-baud interrupt. 0 0 Disable end of auto-baud Interrupt. 1 Enable end of auto-baud Interrupt.

4.5 UARTn Interrupt Identification Regi ster (U0IIR - 0x4000 C008, U2IIR -

0x4009 8008, U3IIR - 0x4009 C008) The UnIIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an UnIIR access. If an interrupt occurs during an UnIIR access, the interrupt is recorded for the next UnIIR access. Bit UnIIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud condition. The auto-baud interrupt conditions are cleared by setting the corresponding Clear bits in the Auto-baud Control Register. If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of interrupt and handling as described in Table 14–276. Given the status of UnIIR[3:0], an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. The UnIIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine. 9 ABTOIntEn Enables the auto-baud time-out interrupt. 0 0 Disable auto-baud time-out Interrupt. 1 Enable auto-baud time-out Interrupt. 31:10 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 274: UARTn Interrupt Enable Register (U0IER - address 0x4000 C004, U2IER - 0x4009 8004, U3IER - 0x4009 C004 when DLAB = 0) bit description Bit Symbol Value Description Reset Value Table 275: UARTn Interrupt Identification Register (U 0IIR - address 0x4000 C008, U2IIR - 0x4009 8008, U3IIR - 0x4009 C008) bit description Bit Symbol Value Description Reset Value 0 IntStatus Interrupt status. Note that U1IIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1]. 0 At least one interrupt is pending. 1 No interrupt is pending. 3:1 IntId Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111). 011 1 - Receive Line Status (RLS). 010 2a - Receive Data Available (RDA). 110 2b - Character Time -out Indicator (CTI). 001 3 - THRE Interrupt 5:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 7:6 FIFO Enable Copies of UnFCR[0]. 0 8 ABEOInt End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. 9 ABTOInt Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. 31:10 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 302 of 835 NXP Semiconductors UM10360 Chapter 14: LPC17xx UART0/2/3 The UARTn RLS interrupt (UnIIR[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UARTn Rx input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI). The UARTn Rx error condition that set the interrupt can be observed via U0LSR[4:1]. The interrupt is cleared upon an UnLSR read. The UARTn RDA interrupt (UnIIR[3:1] = 010) shares the second level priority with the CTI interrupt (UnIIR[3:1] = 110). The RDA is activated when the UARTn Rx FIFO reaches the trigger level defined in UnFCR[7:6] and is reset when the UARTn Rx FIFO depth falls below the trigger level. When the RDA interrupt goes active, the CPU can read a block of data defined by the trigger level. The CTI interrupt (UnIIR[3:1] = 110) is a second level interrupt and is set when the UARTn Rx FIFO contains at least one character and no UARTn Rx FIFO activity has occurred in 3.5 to 4.5 character times. Any UARTn Rx FIFO activity (read or write of UARTn RSR) will clear the interrupt. This interrupt is intended to flush the UARTn RBR after a message has been received that is not a multiple of the trigger level size. For example, if a peripheral wished to send a 105 character message and the trigger level was 10 characters, the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters. [2] For details see Section 14–4.8 “UARTn Line Status Register (U0LSR - 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014)” [3] For details see Section 14–14.4.1 “UARTn Receiver Buffer Register (U0RBR - 0x4000 C000, U2RBR - 0x4009 8000, U3RBR - 0x4009 C000 when DLAB = 0)” [4] For details see Section 14–4.5 “UARTn Interrupt Identification Register (U0IIR - 0x4000 C008, U2IIR - 0x4009 8008, U3IIR - 0x4009 C008)” and Section 14–4.2 “UARTn Transmit Holding Register (U0THR - 0x4000 C000, U2THR - 0x4009 8000, U3THR - 0x4009 C000 when DLAB = 0)” The UARTn THRE interrupt (UnIIR[3:1] = 001) is a third level interrupt and is activated when the UARTn THR FIFO is empty provided certain initialization conditions have been met. These initialization conditions are intended to give the UARTn THR FIFO a chance to Table 276: UARTn Interrupt Handling U0IIR[3:0] value[1] Priority Interrupt Type Interrupt Source Interrupt Reset 0001 - None None -

0110 Highest RX Line

OE[2] or PE[2] or FE[2] or BI[2] UnLSR Read[2]

0100 Second RX Data

Rx data available or trigger level reached in FIFO (UnFCR0=1) UnRBR Read[3] or UARTn FIFO drops below trigger level

1100 Second Character

Minimum of one character in the Rx FIFO and no character input or removed during a time period depending on how many characters are in FIFO and what the trigger level is set at (3.5 to 4.5 character times). The exact time will be: [(word length) × 7 - 2] × 8 + [(trigger level - number of characters) × 8 + 1] RCLKs UnRBR Read[3]

0010 Third THRE THRE [2] UnIIR Read (if source of

interrupt) or THR write[4]

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 303 of 835 NXP Semiconductors UM10360 Chapter 14: LPC17xx UART0/2/3 fill up with data to eliminate many THRE interrupts from occurring at system start-up. The initialization conditions implement a one character delay minus the stop bit whenever THRE = 1 and there have not been at least two characters in the UnTHR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to UnTHR without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the UARTn THR FIFO has held two or more characters at one time and currently, the UnTHR is empty. The THRE interrupt is reset when a UnTHR write occurs or a read of the UnIIR occurs and the THRE is the highest interrupt (UnIIR[3:1] = 001).

4.6 UARTn FIFO Control Register (U0FCR - 0x4000 C008, U2FCR -

0x4009 8008, U3FCR - 0x4009 C008) The write-only UnFCR controls the operation of the UARTn Rx and TX FIFOs.

4.6.1 DMA Operation

The user can optionally operate the UART transmit and/or receive using DMA. The DMA mode is determined by the DMA Mode Select bit in the FCR register. This bit only has an affect when the FIFOs are enabled via the FIFO Enable bit in the FCR register. UART receiver DMA In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO level becoming equal to or greater than trigger level, or if a character timeout occurs. See the description of the RX Trigger Level above. The receiver DMA request is cleared by the DMA controller. Table 277: UARTn FIFO Control Register (U0FCR - address 0x4000 C008, U2FCR - 0x4009 8008, U3FCR - 0x4007 C008) bit description Bit Symbol Value Description Reset Value 0 FIFO Enable 0 UARTn FIFOs are disabled. Must not be used in the application. 0 1 Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs.

1 RX FIFO

0 No impact on either of UARTn FIFOs. 0

1 Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the

pointer logic. This bit is self-clearing. 2T X F I F O Reset 0 No impact on either of UARTn FIFOs. 0

1 Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the

pointer logic. This bit is self-clearing.

3 DMA Mode

When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 14–4.6.1 5:4 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 7:6 RX Trigger Level These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.

00 Trigger level 0 (1 character or 0x01)

01 Trigger level 1 (4 characters or 0x04)

10 Trigger level 2 (8 characters or 0x08)

11 Trigger level 3 (14 characters or 0x0E)

31:8 - Reserved, user software should not write ones to reserved bits. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 304 of 835 NXP Semiconductors UM10360 Chapter 14: LPC17xx UART0/2/3 UART transmitter DMA In DMA mode, the transmitter DMA request is asserted on the event of the transmitter FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA controller.

4.7 UARTn Line Control Register (U0LCR - 0x4000 C00C, U2LCR -

0x4009 800C, U3LCR - 0x4009 C00C) The UnLCR determines the format of the data character that is to be transmitted or received.

4.8 UARTn Line Status Register (U0LSR - 0x4000 C014, U2LSR -

0x4009 8014, U3LSR - 0x4009 C014) The UnLSR is a read-only register that provides status information on the UARTn TX and RX blocks. Table 278: UARTn Line Control Register (U0LCR - address 0x4000 C00C, U2LCR - 0x4009 800C, U3LCR - 0x4009 C00C) bit description Bit Symbol Value Description Reset Value 1:0 Word Length Select 00 5-bit character length 0 01 6-bit character length 10 7-bit character length 11 8-bit character length 2 Stop Bit Select 0 1 stop bit. 0 1 2 stop bits (1.5 if UnLCR[1:0]=00). 3 Parity Enable 0 Disable parity generation and checking. 0 1 Enable parity generation and checking. 5:4 Parity Select 00 Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 01 Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 10 Forced "1" stick parity. 11 Forced "0" stick parity. 6 Break Control 0 Disable break transmission. 0 1 Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high.

7 Divisor Latch

Access Bit (DLAB) 0 Disable access to Divisor Latches. 0 1 Enable access to Divisor Latches. 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 305 of 835 NXP Semiconductors UM10360 Chapter 14: LPC17xx UART0/2/3 Table 279: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014) bit description Bit Symbol Value Description Reset Value

0 Receiver Data

Ready (RDR) UnLSR0 is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. 0 The UARTn receiver FIFO is empty. 1 The UARTn receiver FIFO is not empty.

1 Overrun Error

(OE) The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR1. UnLSR1 is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. 0 Overrun error status is inactive. 1 Overrun error status is active.

2 Parity Error (PE) When the parity bit of a received character is in the wrong state, a parity error

occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. 0 Parity error status is inactive. 1 Parity error status is active.

3 Framing Error

(FE) When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR0. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. 0 Framing error status is inactive. 1 Framing error status is active.

4 Break Interrupt

(BI) When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. 0 Break interrupt status is inactive. 1 Break interrupt status is active.

5 Transmitter

Empty (THRE)) THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. 0 UnTHR contains valid data. 1 UnTHR is empty.

6 Transmitter

Empty (TEMT) TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. 0 UnTHR and/or the UnTSR contains valid data. 1 UnTHR and the UnTSR are empty.

4.9 UARTn Scratch Pad Register (U0SCR - 0x4000 C01C, U2SCR -

0x4009 801C U3SCR - 0x4009 C01C) The UnSCR has no effect on the UARTn operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the UnSCR has occurred.

4.10 UARTn Auto-baud Control Regi ster (U0ACR - 0x4000 C020, U2ACR -

0x4009 8020, U3ACR - 0x4009 C020) The UARTn Auto-baud Control Register (UnACR) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user’s discretion.

7 Error in RX FIFO

(RXFE) UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. 0 UnRBR contains no UARTn RX errors or UnFCR[0]=0. 1 UARTn RBR contains at least one UARTn RX error. 31:8 - Reserved, the value read from a reserved bit is not defined. NA Table 279: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014) bit description Bit Symbol Value Description Reset Value Table 280: UARTn Scratch Pad Register (U0SCR - address 0x4000 C01C, U2SCR - 0x4009 801C, U3SCR - 0x4009 C01C) bit description Bit Symbol Description Reset Value 7:0 Pad A readable, writable byte. 0x00 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 281: UARTn Auto-bau d Control Register (U0ACR - address 0x4000 C020, U2ACR - 0x4009 8020, U3ACR - 0x4009 C020) bit description Bit Symbol Value Description Reset value 0 Start This bit is automatically cleared after auto-baud completion. 0 0 Auto-baud stop (auto-baud is not running). 1 Auto-baud start (auto-baud is running) . Auto-baud run bit. This bit is automatically cleared after auto-baud completion. 1 Mode Auto-baud mode select bit. 0 0 Mode 0. 1 Mode 1. 2 AutoRestart 0 No restart. 0

1 Restart in case of time-out (counter restarts at next UARTn Rx falling edge) 0

7:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

14.4.10.1 Auto-baud

The UARTn auto-baud function can be used to measure the incoming baud-rate based on the “AT” protocol (Hayes command). If enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers UnDLM and UnDLL accordingly. Remark: the fractional rate divider is not connected during auto-baud operations, and therefore should not be used when the auto-baud feature is needed. Auto-baud is started by setting the UnACR Start bit. Auto-baud can be stopped by clearing the UnACR Start bit. The Start bit will clear once auto-baud has finished and reading the bit will return the status of auto-baud (pending/finished). Two auto-baud measuring modes are available which can be selected by the UnACR Mode bit. In mode 0 the baud-rate is measured on two subsequent falling edges of the UARTn Rx pin (the falling edge of the start bit and the falling edge of the least significant bit). In mode 1 the baud-rate is measured between the falling edge and the subsequent rising edge of the UARTn Rx pin (the length of the start bit). The UnACR AutoRestart bit can be used to automatically restart baud-rate measurement if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate measurement will restart at the next falling edge of the UARTn Rx pin. The auto-baud function can generate two interrupts.

The UnIIR ABTOInt interrupt will get set if the interrupt is enabled (UnIER ABToIntEn is set and the auto-baud rate measurement counter overflows).
The UnIIR ABEOInt interrupt will get set if the interrupt is enabled (UnIER ABEOIntEn is set and the auto-baud has completed successfully). The auto-baud interrupts have to be cleared by setting the corresponding UnACR ABTOIntClr and ABEOIntEn bits. Typically the fractional baud-rate generator is disabled (DIVADDVAL = 0) during auto-baud. However, if the fractional baud-rate generator is enabled (DIVADDVAL > 0), it is going to impact the measuring of UARTn Rx pin baud-rate, but the value of the UnFDR register is not going to be modified after rate measurement. Also, when auto-baud is used, any write to UnDLM and UnDLL registers should be done before UnACR register write. The minimum and the maximum baud rates supported by UARTn are function of pclk, number of data bits, stop bits and parity bits. 8 ABEOIntClr End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. 9 ABTOIntClr Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact. 31:10 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 281: UARTn Auto-bau d Control Register (U0ACR - address 0x4000 C020, U2ACR - 0x4009 8020, U3ACR - 0x4009 C020) bit description Bit Symbol Value Description Reset value

14.4.10.2 Auto-baud modes

When the software is expecting an “AT” command, it configures the UARTn with the expected character format and sets the UnACR Start bit. The initial values in the divisor latches UnDLM and UnDLM don‘t care. Because of the “A” or “a” ASCII coding (”A" = 0x41, “a” = 0x61), the UARTn Rx pin sensed start bit and the LSB of the expected character are delimited by two falling edges. When the UnACR Start bit is set, the auto-baud protocol will execute the following phases: 1. On UnACR Start bit setting, the baud rate measurement counter is reset and the UARTn UnRSR is reset. The UnRSR baud rate is switch to the highest rate. 2. A falling edge on UARTn Rx pin triggers the beginning of the start bit. The rate measuring counter will start counting pclk cycles optionally pre-scaled by the fractional baud-rate generator. 3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with the frequency of the (fractional baud-rate pre-scaled) UARTn input clock, guaranteeing the start bit is stored in the UnRSR. 4. During the receipt of the start bit (and the character LSB for mode = 0) the rate counter will continue incrementing with the pre-scaled UARTn input clock (pclk). 5. If Mode = 0 then the rate counter will stop on next falling edge of the UARTn Rx pin. If Mode = 1 then the rate counter will stop on the next rising edge of the UARTn Rx pin. 6. The rate counter is loaded into UnDLM/ UnDLL and the baud-rate will be switched to normal operation. After setting the UnDLM/UnDLL the end of auto-baud interrupt UnIIR ABEOInt will be set, if enabled. The UnRSR will now continue receiving the remaining bits of the “A/a” character. ratemin 2P× CLK 16 2 15× PCLK

4.11 UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009

8024, U3ICR - 0x4009 C024) The IrDA Control Register enables and configures the IrDA mode on each UART. The value of UnICR should not be changed while transmitting or receiving data, or data loss or corruption may occur. a. Mode 0 (start bit and LSB are used for auto-baud) b. Mode 1 (only start bit is used for auto-baud) Fig 44. Auto-baud a) mode 0 and b) mode 1 waveform UARTn RX start bit LSB of 'A' or 'a' U0ACR start rate counter start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop 'A' (0x41) or 'a' (0x61) 16 cycles 16 cycles 16xbaud_rate UARTn RX start bit LSB of 'A' or 'a' rate counter 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop U1ACR start 16 cycles 16xbaud_rate Table 282: UARTn IrDA Control Register (U0ICR - 0x4 000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) bit Bit Symbol Value Description Reset value 0 IrDAEn 0 IrDA mode on UARTn is dis abled, UARTn acts as a standard UART. 0 1 IrDA mode on UARTn is enabled. 1 IrDAInv When 1, the serial input is inverted. This has no effect on the serial output. When 0, the serial input is not inverted.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 310 of 835 NXP Semiconductors UM10360 Chapter 14: LPC17xx UART0/2/3 The PulseDiv bits in UnICR are used to select the pulse width when the fixed pulse width mode is used in IrDA mode (IrDAEn = 1 and FixPulseEn = 1). The value of these bits should be set so that the resulting pulse width is at least 1.63 µs. Table 14–283 shows the possible pulse widths.

4.12 UARTn Fractional Divider Regist er (U0FDR - 0x4000 C028, U2FDR -

0x4009 8028, U3FDR - 0x4009 C028) The UART0/2/3 Fractional Divider Register (U0/2/3FDR) controls the clock pre-scaler for the baud rate generation and can be read and written at the user’s discretion. This pre-scaler takes the APB clock and generates an output clock according to the specified fractional requirements. Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of the DLL register must be greater than 2. 2 FixPulseEn When 1, enabled IrDA fixed pulse width mode. 0 5:3 PulseDiv Configures the pulse when FixPulseEn = 1. See text below for details. 0 31:6 - NA Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Table 282: UARTn IrDA Control Register (U0ICR - 0x4 000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) bit Bit Symbol Value Description Reset value Table 283: IrDA Pulse Width FixPulseEn PulseDiv IrDA Transmitter Pulse width (µs) 0 x 3 / (16 × baud rate) 10 2 × TPCLK 11 4 × TPCLK 12 8 × TPCLK 13 1 6 × TPCLK 14 3 2 × TPCLK 15 6 4 × TPCLK 1 6 128 × TPCLK 1 7 256 × TPCLK Table 284: UARTn Fractional Divider Register (U 0FDR - address 0x4000 C028, U2FDR - 0x4009 8028, U3FDR - 0x4009 C028) bit description Bit Function Value Description Reset value 3:0 DIVADDVAL 0 Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. 7:4 MULVAL 1 Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. 31:8 - NA Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 311 of 835 NXP Semiconductors UM10360 Chapter 14: LPC17xx UART0/2/3 This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART0/2/3 disabled making sure that UART0/2/3 is fully software and hardware compatible with UARTs not equipped with this feature. UART0/2/3 baud rate can be calculated as (n = 0/2/3): (2) Where PCLK is the peripheral clock, U0/2/3DLM and U0/2/3DLL are the standard UART0/2/3 baud rate divider registers, and DIVADDVAL and MULVAL are UART0/2/3 fractional baud rate generator specific parameters. The value of MULVAL and DIVADDVAL should comply to the following conditions: 1. 1 ≤ MULVAL ≤ 15 2. 0 ≤ DIVADDVAL ≤ 14 3. DIVADDVAL < MULVAL The value of the U0/2/3FDR should not be modified while transmitting/receiving data or data may be lost or corrupted. If the U0/2/3FDR register value does not comply to these two requests, then the fractional divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled, and the clock will not be divided.

4.12.1 Baud rate calculation

UARTn can operate with or without using the Fractional Divider. In real-life applications it is likely that the desired baud rate can be achieved using several different Fractional Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL, MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a relative error of less than 1.1% from the desired one. UARTn baudrate PCLK 16 256 UnDLM× UnDLL+()× 1 DivAddVal ⎛⎞×

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 312 of 835 NXP Semiconductors UM10360 Chapter 14: LPC17xx UART0/2/3 Fig 45. Algorithm for setting UART dividers PCLK, BR Calculating UART baudrate (BR) DL est = PCLK/(16 x BR) DLest is an integer? DIVADDVAL = 0 MULVAL = 1 Tr ue FR est = 1.5 DL est = Int(PCLK/(16 x BR x FR est)) 1.1 < FR est < 1.9? Pick another FR est from the range [1.1, 1.9] FRest = PCLK/(16 x BR x DL est) DIVADDVAL = table(FRest ) MULVAL = table(FR est ) DLM = DLest [15:8] DLL = DLest [7:0] End False Tr ue False

4.12.1.2 Example 2: PCLK = 12 MHz, BR = 115200

equivalent to DIVADDVAL = 5 and MULVAL = 8. DIVADDVAL = 5, and MULVAL = 8. According to Equation 14–2 the UART rate is 115384. This rate has a relative error of 0.16% from the originally specified 115200.

4.13 UARTn Transmit Enable Regist er (U0TER - 0x4000 C030, U2TER -

becomes 0, UARTn transmission will stop. Table 285. Fractional Divider setting look-up table

4.14 UARTn FIFO Level register (U0FIFOLVL - 0x4000 C058, U2FIFOLVL -

level status. Both the transmit and receive FIFO levels are present in this register. The architecture of the UARTs 0, 2 and 3 are shown below in the block diagram. The UARTn receiver block, UnRX, monitors the serial input line, RXDn, for valid input. to await access by the CPU or host via the generic host interface. divided down clock is a 16x oversample clock, NBAUDOUT. reserved bit is not defined.

7 TXEN When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as

can set this bit again when it receives an XON (DC1) character. Table 287. UARTn FIFO Level register (U0FIFOLVL - 0x4000 C058, U2FIFOLVL - 0x4009 8058, U3FIFOLVL - 0x4009 3:0 RXFIFILVL Reflects the current level of the UART receiver FIFO. 11:8 TXFIFOLVL Reflects the current level of the UART transmitter FIFO.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 315 of 835 NXP Semiconductors UM10360 Chapter 14: LPC17xx UART0/2/3 The interrupt interface contains registers UnIER and UnIIR. The interrupt interface receives several one clock wide enables from the UnTX and UnRX blocks. Status information from the UnTX and UnRX is stored in the UnLSR. Control information for the UnTX and UnRX is stored in the UnLCR. Fig 46. UART0, 2 and 3 block diagram Transmitter Shift Register Transmitter Holding Register Transmitter FIFO Transmitter Receiver Shift Register Receiver Buffer Register Receiver FIFO Receiver TX_DMA_REQ TX_DMA_CLR RX_DMA_REQ RX_DMA_CLR Baud Rate Generator Fractional Rate Divider Main Divider (DLM, DLL) Transmitter DMA Interface Receiver DMA Interface PCLK Line Control & Status FIFO Control & Status Un_TXD Un_RXD Un_OERS485, IrDA, & Auto-baud UARTn interrupt Interrupt Control & Status

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 316 of 835 1. Basic configuration The UART1 peripheral is configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set bits PCUART1. Remark: On reset, UART1 is enabled (PCUART1 = 1). 2. Peripheral clock: In the PCLKSEL0 register (Table 4–40 ), select PCLK_UART1. 3. Baud rate: In register U1LCR ( Table 15–298), set bit DLAB =1. This enables access to registers DLL (Table 15–292) and DLM (Table 15–293) for setting the baud rate. Also, if needed, set the fractional baud rate in the fractional divider register (Table 15–305). 4. UART FIFO: Use bit FIFO enable (bit 0) in register U0FCR ( Table 15–297) to enable FIFO. 5. Pins: Select UART pins through PINSEL registers and pin modes through the PINMODE registers (Section 8–5). Remark: UART receive pins should not have pull-down resistors enabled. 6. Interrupts: To enable UA RT interrupts set bit DLAB =0 in register U1LCR (Table 15–298). This enables access to U1IER (Table 15–294). Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 7. DMA: UART1 transmit and receive functions can operated with the GPDMA controller (see Table 31–544). 2. Features

Full modem control handshaking available
Data sizes of 5, 6, 7, and 8 bits.
Parity generation and checking: odd, even mark, space or none.
One or two stop bits.
16 byte Receive and Transmit FIFOs.
Built-in baud rate generator, including a fractional rate divider for great versatility.
Supports DMA for both transmit and receive.
Auto-baud capability
Break generation and detection.
Multiprocessor addressing mode.
RS-485 support. UM10360 Chapter 15: LPC17xx UART1 Rev. 01 — 4 January 2010 User manual

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 317 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 3. Pin description Table 288: UART1 Pin Description Pin Type Description RXD1 Input Serial Input. Serial receive data. TXD1 Output Serial Output. Serial transmit data. CTS1 Input Clear To Send. Active low signal indicates if the external modem is ready to accept transmitted data via TXD1 from the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is stored in U1MSR[4]. State change information is stored in U1MSR[0] and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1). Clear to send. CTS1 is an asynchronous, active low modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the Modem Status Register (MSR) indicates that CTS1 has changed states since the last read from the MSR. If the modem status interrupt is enabled when CTS1 changes levels and the auto-cts mode is not enabled, an interrupt is generated. CTS1 is also used in the auto-cts mode to control the transmitter. DCD1 Input Data Carrier Detect. Active low signal indicates if the external modem has established a communication link with the UART1 and data may be exchanged. In normal operation of the modem interface (U1MCR[4]=0), the complement value of this signal is stored in U1MSR[7]. State change information is stored in U1MSR3 and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1). DSR1 Input Data Set Ready. Active low signal indicates if the external modem is ready to establish a communications link with the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is stored in U1MSR[5]. State change information is stored in U1MSR[1] and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1). DTR1 Output Data Terminal Ready. Active low signal indicates that the UART1 is ready to establish connection with external modem. The complement value of this signal is stored in U1MCR[0]. The DTR pin can also be used as an RS-485/EIA-485 output enable signal. RI1 Input Ring Indicator. Active low signal indicates that a telephone ringing signal has been detected by the modem. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is stored in U1MSR[6]. State change information is stored in U1MSR[2] and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1). RTS1 Output Request To Send. Active low signal indicates that the UART1 would like to transmit data to the external modem. The complement value of this signal is stored in U1MCR[1]. In auto-rts mode, RTS1 is used to control the transmitter FIFO threshold logic. Request to send. RTS1 is an active low signal informing the modem or data set that the UART is ready to receive data. RTS1 is set to the active (low) level by setting the RTS modem control register bit and is set to the inactive (high) level either as a result of a system reset or during loop-back mode operations or by clearing bit 1 (RTS) of the MCR. In the auto-rts mode, RTS1 is controlled by the transmitter FIFO threshold logic. The RTS pin can also be used as an RS-485/EIA-485 output enable signal.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 318 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 4. Register description UART1 contains registers organized as shown in Table 15–289. The Divisor Latch Access Bit (DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches. [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. Table 289: UART1 register map Name Description Access Reset Value[1] Address U1RBR (when DLAB =0) Receiver Buffer Register. Contains the next received character to be read. RO NA 0x4001 0000 (when DLAB=0) U1THR (when DLAB =0) Transmit Holding Register. The next character to be transmitted is written here. WO NA 0x4001 0000 (when DLAB=0) U1DLL (when DLAB =1) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. R/W 0x01 0x4001 0000 (when DLAB=1) U1DLM (when DLAB =1) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. R/W 0x00 0x4001 0004 (when DLAB=1) U1IER (when DLAB =0) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. R/W 0x00 0x4001 0004 (when DLAB=0) U1IIR Interrupt ID Register. Identifies which interrupt(s) are pending. RO 0x01 0x4001 0008 U1FCR FIFO Control Register. Controls UART1 FIFO usage and modes. WO 0x00 0x4001 0008 U1LCR Line Control Register. Contains controls for frame formatting and break generation. R/W 0x00 0x4001 000C U1MCR Modem Control Register. Contains controls for flow control handshaking and loopback mode. R/W 0x00 0x4001 0010 U1LSR Line Status Register. Contains flags for transmit and receive status, including line errors. RO 0x60 0x4001 0014 U1MSR Modem Status Register. Contains handshake signal status flags. RO 0x00 0x4001 0018 U1SCR Scratch Pad Register. 8-bit temporary storage for software. R/W 0x00 0x4001 001C U1ACR Auto-baud Control Register. Contains controls for the auto-baud feature. R/W 0x00 0x4001 0020 U1FDR Fractional Divider Register. Generates a clock input for the baud rate divider. R/W 0x10 0x4001 0028 U1TER Transmit Enable Register. Turns off UART transmitter for use with software flow control. R/W 0x80 0x4001 0030 U1RS485CTRL RS-485/EIA-485 Control. Cont ains controls to configure various aspects of RS-485/EIA-485 modes. R/W 0x00 0x4001 004C U1ADRMATCH RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. R/W 0x00 0x4001 0050 U1RS485DLY RS-485/EIA-485 direction control delay. R/W 0x00 0x4001 0054 U1FIFOLVL FIFO Level register. Provides t he current fill levels of the transmit and receive FIFOs. RO 0x00 0x4001 0058

4.1 UART1 Receiver Buffer Regist er (U1RBR - 0x4001 0000, when

DLAB = 0) The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes. The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the U1RBR. The U1RBR is always read-only. Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e. the one that will be read in the next read from the RBR), the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the U1LSR register, and then to read a byte from the U1RBR.

4.2 UART1 Transmitter Holding Regi ster (U1THR - 0x4001 0000 when

DLAB = 0) The write-only U1THR is the top byte of the UART1 TX FIFO. The top byte is the newest character in the TX FIFO and can be written via the bus interface. The LSB represents the first bit to transmit. The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the U1THR. The U1THR is write-only.

4.3 UART1 Divisor Latch LSB and MSB Registers (U1DLL - 0x4001 0000

and U1DLM - 0x4001 0004, when DLAB = 1) The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce the baud rate clock, which must be 16x the desired baud rate. The U1DLL and U1DLM registers together form a 16-bit divisor where U1DLL contains the lower 8 bits of the divisor and U1DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in U1LCR must be one in order to access the UART1 Divisor Latches. Details on how to select the right value for U1DLL and U1DLM can be found later in this chapter, see Section 15–4.16. Table 290: UART1 Receiver Buffer Register (U1RBR - address 0x4001 0000 when DLAB = 0) bit description Bit Symbol Description Reset Value 7:0 RBR The UART1 Receiver Buffer Register contai ns the oldest received byte in the UART1 RX FIFO. undefined 31:8 - Reserved, the value read from a reserved bit is not defined. NA Table 291: UART1 Transmitter Holding Register (U1THR - address 0x4001 0000 when DLAB = 0) bit description Bit Symbol Description Reset Value 7:0 THR Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. NA 31:8 - Reserved, user software should not write ones to reserved bits. NA

4.4 UART1 Interrupt Enable Regi ster (U1IER - 0x4001 0004, when

DLAB = 0) The U1IER is used to enable the four UART1 interrupt sources. Table 292: UART1 Divisor Latch LSB Register (U1DLL - address 0x4001 0000 when DLAB = 1) bit description Bit Symbol Description Reset Value 7:0 DLLSB The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1. 0x01 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 293: UART1 Divisor Latch MSB Register (U1DLM - address 0x4001 0004 when DLAB = 1) bit description Bit Symbol Description Reset Value 7:0 DLMSB The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1. 0x00 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 294: UART1 Interrupt Enable Register (U1IER - address 0x4001 0004 when DLAB = 0) bit description Bit Symbol Value Description Reset Value 0R B R Interrupt Enable enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt. 0 Disable the RDA interrupts. 1 Enable the RDA interrupts. 1T H R E Interrupt Enable enables the THRE interrupt for UART1. The status of this interrupt can be read from U1LSR[5]. 0 Disable the THRE interrupts. 1 Enable the THRE interrupts.

2 RX Line

enables the UART1 RX line status interrupts. The status of this interrupt can be read from U1LSR[4:1]. 0 Disable the RX line status interrupts. 1 Enable the RX line status interrupts.

3 Modem

enables the modem interrupt. The status of this interrupt can be read from U1MSR[3:0]. 0 0 Disable the modem interrupt. 1 Enable the modem interrupt. 6:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 7C T S Interrupt Enable If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (U1IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the U1IER[3] bit in the U1IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the U1IER[3] and U1IER[7] bits are set. 0 Disable the CTS interrupt. 1 Enable the CTS interrupt.

4.5 UART1 Interrupt Identifica tion Register (U1IIR - 0x4001 0008)

The U1IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an U1IIR access. If an interrupt occurs during an U1IIR access, the interrupt is recorded for the next U1IIR access. Bit U1IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud condition. The auto-baud interrupt conditions are cleared by setting the corresponding Clear bits in the Auto-baud Control Register. If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of interrupt and handling as described in Table 15–296. Given the status of U1IIR[3:0], an 8 ABEOIntEn Enables the end of auto-baud interrupt. 0 0 Disable end of auto-baud Interrupt. 1 Enable end of auto-baud Interrupt. 9 ABTOIntEn Enables the auto-baud time-out interrupt. 0 0 Disable auto-baud time-out Interrupt. 1 Enable auto-baud time-out Interrupt. 31:10 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 294: UART1 Interrupt Enable Register (U1IER - address 0x4001 0004 when DLAB = 0) bit description Bit Symbol Value Description Reset Value Table 295: UART1 Interrupt Identi fication Register (U1IIR - address 0x4001 0008) bit description Bit Symbol Value Description Reset Value 0 IntStatus Interrupt status. Note that U1IIR[0] is active low. The pending interrupt can be determined by evaluating U1IIR[3:1]. 0 At least one interrupt is pending. 1 No interrupt is pending. 3:1 IntId Interrupt identification. U1IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of U1IER[3:1] not listed below are reserved (100,101,111). 011 1 - Receive Line Status (RLS). 010 2a - Receive Data Available (RDA). 110 2b - Character Time-out Indicator (CTI). 001 3 - THRE Interrupt. 000 4 - Modem Interrupt. 5:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 7:6 FIFO Enable Copies of U1FCR[0]. 0 8 ABEOInt End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. 9 ABTOInt Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. 31:10 - Reserved, the value read from a reserved bit is not defined. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 322 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. The U1IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine. The UART1 RLS interrupt (U1IIR[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART1RX input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART1 Rx error condition that set the interrupt can be observed via U1LSR[4:1]. The interrupt is cleared upon an U1LSR read. The UART1 RDA interrupt (U1IIR[3:1] = 010) shares the second level priority with the CTI interrupt (U1IIR[3:1] = 110). The RDA is activated when the UART1 Rx FIFO reaches the trigger level defined in U1FCR7:6 and is reset when the UART1 Rx FIFO depth falls below the trigger level. When the RDA interrupt goes active, the CPU can read a block of data defined by the trigger level. The CTI interrupt (U1IIR[3:1] = 110) is a second level interrupt and is set when the UART1 Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in 3.5 to 4.5 character times. Any UART1 Rx FIFO activity (read or write of UART1 RSR) will clear the interrupt. This interrupt is intended to flush the UART1 RBR after a message has been received that is not a multiple of the trigger level size. For example, if a peripheral wished to send a 105 character message and the trigger level was 10 characters, the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters. [2] For details see Section 15–4.10 “UART1 Line Status Register (U1LSR - 0x4001 0014)” [3] For details see Section 15–4.1 “UART1 Receiver Buffer Register (U1RBR - 0x4001 0000, when DLAB = 0)” [4] For details see Section 15–4.5 “UART1 Interrupt Identification Register (U1IIR - 0x4001 0008)” and Section 15–4.2 “UART1 Transmitter Holding Register (U1THR - 0x4001 0000 when DLAB = 0)” Table 296: UART1 Interrupt Handling U1IIR[3:0] value[1] Priority Interrupt Type Interrupt Source Interrupt Reset 0001 - None None - OE[2] or PE[2] or FE[2] or BI[2] U1LSR Read[2] Rx data available or trigger level reached in FIFO (U1FCR0=1) U1RBR Read[3] or UART1 FIFO drops below trigger level Minimum of one character in the RX FIFO and no character input or removed during a time period depending on how many characters are in FIFO and what the trigger level is set at (3.5 to 4.5 character times). The exact time will be: [(word length) × 7 - 2] × 8 + [(trigger level - number of characters) × 8 + 1] RCLKs U1RBR Read[3]

0010 Third THRE THRE [2] U1IIR Read[4] (if source of

interrupt) or THR write

0000 Fourth Modem

CTS or DSR or RI or DCD MSR Read

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 323 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 The UART1 THRE interrupt (U1IIR[3:1] = 001) is a third level interrupt and is activated when the UART1 THR FIFO is empty provided certain initialization conditions have been met. These initialization conditions are intended to give the UART1 THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up. The initialization conditions implement a one character delay minus the stop bit whenever THRE = 1 and there have not been at least two characters in the U1THR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to U1THR without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the UART1 THR FIFO has held two or more characters at one time and currently, the U1THR is empty. The THRE interrupt is reset when a U1THR write occurs or a read of the U1IIR occurs and the THRE is the highest interrupt (U1IIR[3:1] = 001). It is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem input RI will generate a modem interrupt. The source of the modem interrupt can be determined by examining U1MSR[3:0]. A U1MSR read will clear the modem interrupt.

4.6 UART1 FIFO Control Register (U1FCR - 0x4001 0008)

The write-only U1FCR controls the operation of the UART1 RX and TX FIFOs. The user can optionally operate the UART transmit and/or receive using DMA. The DMA mode is determined by the DMA Mode Select bit in the FCR register. This bit only has an affect when the FIFOs are enabled via the FIFO Enable bit in the FCR register. Table 297: UART1 FIFO Control Register (U1FCR - address 0x4001 0008) bit description Bit Symbol Value Description Reset Value 0 FIFO Enable 0 UART1 FIFOs are disabled. Must not be used in the application. 0 1 Active high enable for both UART1 Rx and TX FIFOs and U1FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs. 0 No impact on either of UART1 FIFOs. 0

1 Writing a logic 1 to U1FCR[1] will clear all bytes in UART1 Rx FIFO, reset the

pointer logic. This bit is self-clearing.

2 TX FIFO

0 No impact on either of UART1 FIFOs. 0

1 Writing a logic 1 to U1FCR[2] will clear all bytes in UART1 TX FIFO, reset the

pointer logic. This bit is self-clearing. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 15–4.6.1 5:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 7:6 RX Trigger Level These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated. 00 Trigger level 0 (1 character or 0x01). 01 Trigger level 1 (4 characters or 0x04). 10 Trigger level 2 (8 characters or 0x08). 11 Trigger level 3 (14 characters or 0x0E). 31:8 - Reserved, user software should not write ones to reserved bits. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 324 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 UART receiver DMA In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO level becoming equal to or greater than trigger level, or if a character timeout occurs. See the description of the RX Trigger Level above. The receiver DMA request is cleared by the DMA controller. UART transmitter DMA In DMA mode, the transmitter DMA request is asserted on the event of the transmitter FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA controller.

4.7 UART1 Line Control Regi ster (U1LCR - 0x4001 000C)

The U1LCR determines the format of the data character that is to be transmitted or received.

4.8 UART1 Modem Control Re gister (U1MCR - 0x4001 0010)

The U1MCR enables the modem loopback mode and controls the modem output signals. Table 298: UART1 Line Control Register (U1LCR - address 0x4001 000C) bit description Bit Symbol Value Description Reset Value 1:0 Word Length Select 00 5-bit character length. 0 01 6-bit character length. 10 7-bit character length. 11 8-bit character length. 2 Stop Bit Select 0 1 stop bit. 0 1 2 stop bits (1.5 if U1LCR[1:0]=00). 3 Parity Enable 0 Disable parity generation and checking. 0 1 Enable parity generation and checking. 5:4 Parity Select 00 Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 01 Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 10 Forced "1" stick parity. 11 Forced "0" stick parity. 6 Break Control 0 Disable break transmission. 0 1 Enable break transmission. Output pin UART1 TXD is forced to logic 0 when U1LCR[6] is active high. Access Bit (DLAB) 0 Disable access to Divisor Latches. 0 1 Enable access to Divisor Latches. 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

4.9 Auto-flow control

If auto-RTS mode is enabled the UART1‘s receiver FIFO hardware controls the RTS1 output of the UART1. If the auto-CTS mode is enabled the UART1‘s U1TSR hardware will only start transmitting if the CTS1 input signal is asserted.

15.4.9.1 Auto-RTS

The auto-RTS function is enabled by setting the RTSen bit. Auto-RTS data flow control originates in the U1RBR module and is linked to the programmed receiver FIFO trigger level. If auto-RTS is enabled, the data-flow is controlled as follows: When the receiver FIFO level reaches the programmed trigger level, RTS1 is de-asserted (to a high value). It is possible that the sending UART sends an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it might not recognize the de-assertion of RTS1 until after it has begun sending the additional byte. RTS1 is automatically reasserted (to a low value) once the receiver FIFO has reached the previous trigger level. The re-assertion of RTS1 signals to the sending UART to continue transmitting data. Table 299: UART1 Modem Control Register (U 1MCR - address 0x4001 0010) bit description Bit Symbol Value Description Reset value 0 DTR Control Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active. 1 RTS Control Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. 3-2 - NA Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

4 Loopback

The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the U1MSR will be driven by the lower 4 bits of the U1MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of U1MCR. 0 Disable modem loopback mode. 1 Enable modem loopback mode. 5 - NA Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 6 RTSen 0 Disable auto-rts flow control. 0 1 Enable auto-rts flow control. 7 CTSen 0 Disable auto-cts flow control. 0 1 Enable auto-cts flow control. 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 326 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 If Auto-RTS mode is disabled, the RTSen bit controls the RTS1 output of the UART1. If Auto-RTS mode is enabled, hardware controls the RTS1 output, and the actual value of RTS1 will be copied in the RTS Control bit of the UART1. As long as Auto-RTS is enabled, the value of the RTS Control bit is read-only for software. Example: Suppose the UART1 operating in ‘550 mode has trigger level in U1FCR set to 0x2 then if Auto-RTS is enabled the UART1 will de-assert the RTS1 output as soon as the receive FIFO contains 8 bytes (Table 15–297 on page 323). The RTS1 output will be reasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes.

15.4.9.2 Auto-CTS

The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled the transmitter circuitry in the U1TSR module checks CTS1 input before sending the next data byte. When CTS1 is active (low), the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS1 must be released before the middle of the last stop bit that is currently being sent. In Auto-CTS mode a change of the CTS1 signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set, Delta CTS bit in the U1MSR will be set though. Table 15–300 lists the conditions for generating a Modem Status interrupt. Fig 47. Auto-RTS Functional Timing start byte N stop start bits0..7 stop start bits0..7 stop N-1 N N-1 N-1N-2 N-2 M+2 M+1 M M-1 UART1 Rx RTS1 pin UART1 Rx FIFO level UART1 Rx FIFO read ~~ ~ ~ ~ ~ ~ Table 300: Modem status interrupt generation Enable Modem Status Interrupt (U1ER[3]) CTSen (U1MCR[7]) CTS Interrupt Enable (U1IER[7]) Delta CTS (U1MSR[0]) Delta DCD or Trailing Edge RI or Delta DSR (U1MSR[3] or U1MSR[2] or U1MSR[1]) Modem Status Interrupt 0x x x x N o 10 x 0 0 N o 10 x 1 x Y es 10 x x 1 Y es 11 0 x 0 N o 11 0 x 1 Y es 11 1 0 0 N o 11 1 1 x Y es 11 1 x 1 Y es

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 327 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 The auto-CTS function reduces interrupts to the host system. When flow control is enabled, a CTS1 state change does not trigger host interrupts because the device automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error can result. Figure 15–48 illustrates the Auto-CTS functional timing. While starting transmission of the initial character the CTS1 signal is asserted. Transmission will stall as soon as the pending transmission has completed. The UART will continue transmitting a 1 bit as long as CTS1 is de-asserted (high). As soon as CTS1 gets de-asserted transmission resumes and a start bit is sent followed by the data bits of the next character.

4.10 UART1 Line Status Re gister (U1LSR - 0x4001 0014)

The U1LSR is a read-only register that provides status information on the UART1 TX and RX blocks. Fig 48. Auto-CTS Functional Timing UART1 TX CTS1 pin ~~~ stop Table 301: UART1 Line Status Register (U1LSR - address 0x4001 0014) bit description Bit Symbol Value Description Reset Value 0R e c e i v e r D a t a Ready (RDR) U1LSR[0] is set when the U1RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty. 0 The UART1 receiver FIFO is empty. 1 The UART1 receiver FIFO is not empty. (OE) The overrun error condition is set as soon as it occurs. An U1LSR read clears U1LSR[1]. U1LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost. 0 Overrun error status is inactive. 1 Overrun error status is active. occurs. An U1LSR read clears U1LSR[2]. Time of parity error detection is dependent on U1FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO. 0 Parity error status is inactive. 1 Parity error status is active.

4.11 UART1 Modem Status Re gister (U1MSR - 0x4001 0018)

The U1MSR is a read-only register that provides status information on the modem input signals. U1MSR[3:0] is cleared on U1MSR read. Note that modem signals have no direct effect on UART1 operation, they facilitate software implementation of modem signal operations. (FE) When the stop bit of a received character is a logic 0, a framing error occurs. An U1LSR read clears U1LSR[3]. The time of the framing error detection is dependent on U1FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO. 0 Framing error status is inactive. 1 Framing error status is active. (BI) When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An U1LSR read clears this status bit. The time of break detection is dependent on U1FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO. 0 Break interrupt status is inactive. 1 Break interrupt status is active. Empty (THRE) THRE is set immediately upon detection of an empty UART1 THR and is cleared on a U1THR write. 0 U1THR contains valid data. 1 U1THR is empty. Empty (TEMT) TEMT is set when both U1THR and U1TSR are empty; TEMT is cleared when either the U1TSR or the U1THR contain valid data. 0 U1THR and/or the U1TSR contains valid data. 1 U1THR and the U1TSR are empty. (RXFE) U1LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the U1RBR. This bit is cleared when the U1LSR register is read and there are no subsequent errors in the UART1 FIFO. 0 U1RBR contains no UART1 RX errors or U1FCR[0]=0. 1 UART1 RBR contains at least one UART1 RX error. 31:8 - Reserved, the value read from a reserved bit is not defined. NA Table 301: UART1 Line Status Register (U1LSR - address 0x4001 0014) bit description Bit Symbol Value Description Reset Value Table 302: UART1 Modem Status Register (U1MSR - address 0x4001 0018) bit description Bit Symbol Value Description Reset Value 0 Delta CTS Set upon state change of input CTS. Cleared on an U1MSR read. 0 0 No change detected on modem input, CTS. 1 State change detected on modem input, CTS.

4.12 UART1 Scratch Pad Regi ster (U1SCR - 0x4001 001C)

The U1SCR has no effect on the UART1 operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the U1SCR has occurred.

4.13 UART1 Auto-baud Control Re gister (U1ACR - 0x4001 0020)

The UART1 Auto-baud Control Register (U1ACR) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user’s discretion. 1 Delta DSR Set upon state change of input DSR. Cleared on an U1MSR read. 0 0 No change detected on modem input, DSR. 1 State change detected on modem input, DSR. 2 Trailing Edge RI Set upon low to high transition of input RI. Cleared on an U1MSR read. 0 0 No change detected on modem input, RI. 1 Low-to-high transition detected on RI. 3 Delta DCD Set upon state change of input DCD. Cleared on an U1MSR read. 0 0 No change detected on modem input, DCD. 1 State change detected on modem input, DCD. 4 CTS Clear To Send State. Complement of input signal CTS. This bit is connected to U1MCR[1] in modem loopback mode. 5 DSR Data Set Ready State. Complement of input signal DSR. This bit is connected to U1MCR[0] in modem loopback mode. 6 RI Ring Indicator State. Complement of input RI. This bit is connected to U1MCR[2] in modem loopback mode. 7 DCD Data Carrier Detect State. Complement of input DCD. This bit is connected to U1MCR[3] in modem loopback mode. 31:8 - Reserved, the value read from a reserved bit is not defined. NA Table 302: UART1 Modem Status Register (U1MSR - address 0x4001 0018) bit description Bit Symbol Value Description Reset Value Table 303: UART1 Scratch Pad Register (U1SCR - address 0x4001 0014) bit description Bit Symbol Description Reset Value 7:0 Pad A readable, writable byte. 0x00 Table 304: Auto-baud Control Register (U1ACR - address 0x4001 0020) bit description Bit Symbol Value Description Reset value 0 Start This bit is automatically cleared after auto-baud completion. 0 0 Auto-baud stop (auto-baud is not running). 1 Auto-baud start (auto-baud is running) . Auto-baud run bit. This bit is automatically cleared after auto-baud completion. 1 Mode Auto-baud mode select bit. 0 0 Mode 0. 1 Mode 1.

4.14 Auto-baud

The UART1 auto-baud function can be used to measure the incoming baud-rate based on the “AT” protocol (Hayes command). If enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers U1DLM and U1DLL accordingly. Remark: the fractional rate divider is not connected during auto-baud operations, and therefore should not be used when the auto-baud feature is needed. Auto-baud is started by setting the U1ACR Start bit. Auto-baud can be stopped by clearing the U1ACR Start bit. The Start bit will clear once auto-baud has finished and reading the bit will return the status of auto-baud (pending/finished). Two auto-baud measuring modes are available which can be selected by the U1ACR Mode bit. In mode 0 the baud-rate is measured on two subsequent falling edges of the UART1 Rx pin (the falling edge of the start bit and the falling edge of the least significant bit). In mode 1 the baud-rate is measured between the falling edge and the subsequent rising edge of the UART1 Rx pin (the length of the start bit). The U1ACR AutoRestart bit can be used to automatically restart baud-rate measurement if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate measurement will restart at the next falling edge of the UART1 Rx pin. The auto-baud function can generate two interrupts.

The U1IIR ABTOInt interrupt will get set if the interrupt is enabled (U1IER ABToIntEn is set and the auto-baud rate measurement counter overflows).
The U1IIR ABEOInt interrupt will get set if the interrupt is enabled (U1IER ABEOIntEn is set and the auto-baud has completed successfully). The auto-baud interrupts have to be cleared by setting the corresponding U1ACR ABTOIntClr and ABEOIntEn bits. Typically the fractional baud-rate generator is disabled (DIVADDVAL = 0) during auto-baud. However, if the fractional baud-rate generator is enabled (DIVADDVAL > 0), it is going to impact the measuring of UART1 Rx pin baud-rate, but the value of the U1FDR

2 AutoRestart 0 No restart 0

1 Restart in case of time-out (counter restarts at next UART1 Rx falling edge) 0

7:3 - NA Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 8 ABEOIntClr End of auto-baud interrupt clear bit (write-only accessible). 0 0 Writing a 0 has no impact. 1 Writing a 1 will clear the corresponding interrupt in the U1IIR. 9 ABTOIntClr Auto-baud time-out interrupt clear bit (write-only accessible). 0 0 Writing a 0 has no impact. 1 Writing a 1 will clear the corresponding interrupt in the U1IIR. 31:10 - NA Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Table 304: Auto-baud Control Register (U1ACR - address 0x4001 0020) bit description Bit Symbol Value Description Reset value

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 331 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 register is not going to be modified after rate measurement. Also, when auto-baud is used, any write to U1DLM and U1DLL registers should be done before U1ACR register write. The minimum and the maximum baud rates supported by UART1 are function of pclk, number of data bits, stop bits and parity bits. (3)

4.15 Auto-baud modes

When the software is expecting an “AT” command, it configures the UART1 with the expected character format and sets the U1ACR Start bit. The initial values in the divisor latches U1DLM and U1DLM don‘t care. Because of the “A” or “a” ASCII coding (”A" = 0x41, “a” = 0x61), the UART1 Rx pin sensed start bit and the LSB of the expected character are delimited by two falling edges. When the U1ACR Start bit is set, the auto-baud protocol will execute the following phases: 1. On U1ACR Start bit setting, the baud-rate measurement counter is reset and the UART1 U1RSR is reset. The U1RSR baud rate is switch to the highest rate. 2. A falling edge on UART1 Rx pin triggers the beginning of the start bit. The rate measuring counter will start counting pclk cycles optionally pre-scaled by the fractional baud-rate generator. 3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with the frequency of the (fractional baud-rate pre-scaled) UART1 input clock, guaranteeing the start bit is stored in the U1RSR. 4. During the receipt of the start bit (and the character LSB for mode = 0) the rate counter will continue incrementing with the pre-scaled UART1 input clock (pclk). 5. If Mode = 0 then the rate counter will stop on next falling edge of the UART1 Rx pin. If Mode = 1 then the rate counter will stop on the next rising edge of the UART1 Rx pin. 6. The rate counter is loaded into U1DLM/ U1DLL and the baud-rate will be switched to normal operation. After setting the U1DLM/U1DLL the end of auto-baud interrupt U1IIR ABEOInt will be set, if enabled. The U1RSR will now continue receiving the remaining bits of the “A/a” character. ratemin 2P× CLK 16 2 15× PCLK

4.16 UART1 Fractional Divider Register (U1FDR - 0x4001 0028)

The UART1 Fractional Divider Register (U1FDR) controls the clock pre-scaler for the baud rate generation and can be read and written at the user’s discretion. This pre-scaler takes the APB clock and generates an output clock according to the specified fractional requirements. Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of the DLL register must be greater than 2. a. Mode 0 (start bit and LSB are used for auto-baud) b. Mode 1 (only start bit is used for auto-baud) Fig 49. Auto-baud a) mode 0 and b) mode 1 waveform UARTn RX start bit LSB of 'A' or 'a' U0ACR start rate counter start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop 'A' (0x41) or 'a' (0x61) 16 cycles 16 cycles 16xbaud_rate UARTn RX start bit LSB of 'A' or 'a' rate counter 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop U1ACR start 16 cycles 16xbaud_rate

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 333 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART1 disabled making sure that UART1 is fully software and hardware compatible with UARTs not equipped with this feature. UART1 baud rate can be calculated as (n = 1): (4) Where PCLK is the peripheral clock, U1DLM and U1DLL are the standard UART1 baud rate divider registers, and DIVADDVAL and MULVAL are UART1 fractional baud rate generator specific parameters. The value of MULVAL and DIVADDVAL should comply to the following conditions: 1. 1 ≤ MULVAL ≤ 15 2. 0 ≤ DIVADDVAL ≤ 14 3. DIVADDVAL < MULVAL The value of the U1FDR should not be modified while transmitting/receiving data or data may be lost or corrupted. If the U1FDR register value does not comply to these two requests, then the fractional divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled, and the clock will not be divided.

4.16.1 Baud rate calculation

UART1 can operate with or without using the Fractional Divider. In real-life applications it is likely that the desired baud rate can be achieved using several different Fractional Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL, MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a relative error of less than 1.1% from the desired one. Table 305: UART1 Fractional Divider Register (U1FDR - address 0x4001 0028) bit description Bit Function Value Description Reset value 3:0 DIVADDVAL 0 Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. 7:4 MULVAL 1 Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. 31:8 - NA Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. UART1 baudrate PCLK 16 256 U1DLM× U1DLL+()× 1 DivAddVal ⎛⎞×

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 334 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 Fig 50. Algorithm for setting UART dividers PCLK, BR Calculating UART baudrate (BR) DL est = PCLK/(16 x BR) DLest is an integer? DIVADDVAL = 0 MULVAL = 1 Tr ue FR est = 1.5 DL est = Int(PCLK/(16 x BR x FR est)) 1.1 < FR est < 1.9? Pick another FR est from the range [1.1, 1.9] FRest = PCLK/(16 x BR x DL est) DIVADDVAL = table(FRest ) MULVAL = table(FR est ) DLM = DLest [15:8] DLL = DLest [7:0] End False Tr ue False

4.16.1.2 Example 2: PCLK = 12 MHz, BR = 115200

equivalent to DIVADDVAL = 5 and MULVAL = 8. DIVADDVAL = 5, and MULVAL = 8. According to Equation 15–4 the UART rate is 115384. This rate has a relative error of 0.16% from the originally specified 115200.

4.17 UART1 Transmit Enable Register (U1TER - 0x4001 0030)

available. As soon as TxEn becomes 0, UART1 transmission will stop. Table 306. Fractional Divider setting look-up table

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 336 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 Although Table 15–307 describes how to use TxEn bit in order to achieve hardware flow control, it is strongly suggested to let UART1 hardware implemented auto flow control features take care of this, and limit the scope of TxEn to software flow control. U1TER enables implementation of software and hardware flow control. When TXEn=1, UART1 transmitter will keep sending data as long as they are available. As soon as TXEn becomes 0, UART1 transmission will stop. Table 15–307 describes how to use TXEn bit in order to achieve software flow control.

4.18 UART1 RS485 Control regist er (U1RS485CTRL - 0x4001 004C)

The U1RS485CTRL register controls the configuration of the UART in RS-485/EIA-485 mode. Table 307: UART1 Transmit Enable Register (U1TER - address 0x4001 0030) bit description Bit Symbol Description Reset Value 6:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NATable 308: UART1 RS485 Control register (U1RS4 85CTRL - address 0x4001 004C) bit description Bit Symbol Value Description Reset value 0 NMMEN 0 RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. 0 1 RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. 1 RXDIS 0 The receiver is enabled. 0 1 The receiver is disabled. 2 AADEN 0 Auto Address Detect (AAD) is disabled. 0 1 Auto Address Detect (AAD) is enabled.

3 SEL 0 If direction control is enabled (bit DCTRL = 1), pin RTS

is used for direction control. 0 1 If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. 4 DCTRL 0 Disable Auto Direction Control. 0 1 Enable Auto Direction Control.

4.19 UART1 RS-485 Address Match register (U1RS485ADRMATCH -

4.20 UART1 RS-485 Delay value register (U1RS485DLY - 0x4001 0054)

the baud clock. Any delay time from 0 to 255 bit times may be programmed.

4.21 RS-485/EIA-485 modes of operation

The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave. The addressable slave is one of multiple slaves controlled by a single master. bit to ‘1’. For data characters, the parity bit is set to ‘0’. when a received byte causes the UART to set the parity error and generate an interrupt.

0 The direction control pin will be driven to logic ‘0’ when the transmitter has data to

be sent. It will be driven to logic ‘1’ after the last bit of data has been transmitted.

1 The direction control pin will be driven to logic ‘1’ when the transmitter has data to

be sent. It will be driven to logic ‘0’ after the last bit of data has been transmitted. from a reserved bit is not defined. Table 309. UART1 RS-485 Address Match register (U1RS485ADRMATCH - address 0x4001 0050) bit description reserved bit is not defined. Table 310. UART1 RS-485 Delay value register (U 1RS485DLY - address 0x4001 0054) bit description conjunction with an 8-bit counter. reserved bit is not defined.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 338 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received data bytes will be ignored and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated. The processor can then read the address byte and decide whether or not to enable the receiver to accept the following data. While the receiver is ENABLED (RS485CTRL bit 1 =’0’) all received bytes will be accepted and stored in the RXFIFO regardless of whether they are data or address. When an address character is received a parity error interrupt will be generated and the processor can decide whether or not to disable the receiver. RS-485/EIA-485 Auto Address Detection (AAD) mode When both RS485CTRL register bits 0 (9-bit mode enable) and 2 (AAD mode enable) are set, the UART is in auto address detect mode. In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bit value programmed into the RS485ADRMATCH register. If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received byte will be discarded if it is either a data byte OR an address byte which fails to match the RS485ADRMATCH value. When a matching address character is detected it will be pushed onto the RXFIFO along with the parity bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will be cleared by hardware). The receiver will also generate n Rx Data Ready Interrupt. While the receiver is ENABLED (RS485CTRL bit 1 = ‘0’) all bytes received will be accepted and stored in the RXFIFO until an address byte which does not match the RS485ADRMATCH value is received. When this occurs, the receiver will be automatically disabled in hardware (RS485CTRL bit 1 will be set), The received non-matching address character will not be stored in the RXFIFO. RS-485/EIA-485 Auto Direction Control RS485/EIA-485 Mode includes the option of allowing the transmitter to automatically control the state of either the RTS pin or the DTR pin as a direction control output signal. Setting RS485CTRL bit 4 = ‘1’ enables this feature. Direction control, if enabled, will use the RTS pin when RS485CTRL bit 3 = ‘0’. It will use the DTR pin when RS485CTRL bit 3 = ‘1’. When Auto Direction Control is enabled, the selected pin will be asserted (driven low) when the CPU writes data into the TXFIFO. The pin will be de-asserted (driven high) once the last bit of data has been transmitted. See bits 4 and 5 in the RS485CTRL register. The RS485CTRL bit 4 takes precedence over all other mechanisms controlling RTS (or DTR) with the exception of loopback mode. RS485/EIA-485 driver delay time The driver delay time is the delay between the last stop bit leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time can be programmed in the 8-bit RS485DLY register. The delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be programmed.

4.22 UART1 FIFO Level register (U1FIFOLVL - 0x4001 0058)

level status. Both the transmit and receive FIFO levels are present in this register. The architecture of the UART1 is shown below in the block diagram. The UART1 receiver block, U1RX, monitors the serial input line, RXD1, for valid input. to await access by the CPU or host via the generic host interface. divided down clock is a 16x oversample clock, NBAUDOUT. responsible for handshaking between a modem peripheral and the UART1. receives several one clock wide enables from the U1TX and U1RX blocks. for the U1TX and U1RX is stored in the U1LCR. Table 311. UART1 FIFO Level register (U1FIFOLVL - address 0x4001 0058) bit description 3:0 RXFIFILVL Reflects the current level of the UART1 receiver FIFO. 11:8 TXFIFOLVL Reflects the current level of the UART1 transmitter FIFO.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 340 of 835 NXP Semiconductors UM10360 Chapter 15: LPC17xx UART1 Fig 51. UART1 block diagram Transmitter Shift Register Transmitter Holding Register Transmitter FIFO Transmitter Receiver Shift Register Receiver Buffer Register Receiver FIFO Receiver TX_DMA_REQ TX_DMA_CLR RX_DMA_REQ RX_DMA_CLR Baud Rate Generator Fractional Rate Divider Main Divider (DLM, DLL) Modem Control Status Transmitter DMA Interface Receiver DMA Interface PCLK Line Control & Status FIFO Control & Status U1_TXD U1_RXD U1_OE U1_CTS U1_RTS U1_DTR U1_DSR U1_RI U1_DCD RS485, IrDA, & Auto-baud UART1 interrupt Interrupt Control & Status

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 341 of 835 1. Basic configuration The CAN1/2 peripherals are configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set bits PCAN1/2. Remark: On reset, the CAN1/2 blocks are disabled (PCAN1/2 = 0). 2. Peripheral clock: In the PCLKSEL0 register (Table 4–40 ), select PCLK_CAN1, PCLK_CAN2, and, for the acceptance filter, PCLK_ACF. Note that these must all be the same value. Remark: If CAN baud rates above 100 kbit/s (see Table 16–323) are needed, do not select the IRC as the clock source (see Table 4–17). 3. Wake-up: CAN controllers ar e able to wake up the microcontroller from Power-down mode, see Section 4–8.8. 4. Pins: Select CAN1/2 pins through the PI NSEL registers and their pin modes through the PINMODE registers (Section 8–5). 5. Interrupts: CAN interrupts are enabled using the CAN1/2IER registers (Table 16–322). Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 6. CAN controller initialization: see CANMOD register ( Section 16–7.1). 2. CAN controllers Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The CAN Controller is designed to provide a full implementation of the CAN-Protocol according to the CAN Specification Version 2.0B. Microcontrollers with this on-chip CAN controller are used to build powerful local networks by supporting distributed real-time control with a very high level of security. The applications are automotive, industrial environments, and high speed networks as well as low cost multiplex wiring. The result is a strongly reduced wiring harness and enhanced diagnostic and supervisory capabilities. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in various applications. The CAN module consists of two elements: the controller and the Acceptance Filter. All registers and the RAM are accessed as 32-bit words. 3. Features

3.1 General CAN features

Compatible with CAN specification 2.0B, ISO 11898-1.
Multi-master architecture with non destructive bit-wise arbitration. UM10360 Chapter 16: LPC17xx CAN1/2 Rev. 01 — 4 January 2010 User manual

Bus access priority determined by the message identifier (11-bit or 29-bit).
Guaranteed latency time for high priority messages.
Programmable transfer rate (up to 1 Mbit/s).
Multicast and broadcast message facility.
Data length from 0 up to 8 bytes.
Powerful error handling capability.
Non-return-to-zero (NRZ) encoding/decoding with bit stuffing.

3.2 CAN controller features

2 CAN controllers and buses.
Supports 11-bit identifier as well as 29-bit identifier.
Double Receive Buffer and Triple Transmit Buffer.
Programmable Error Warning Limit and Error Counters with read/write access.
Arbitration Lost Capture and Error Code Capture with detailed bit position.
Single Shot Transmission (no re-transmission).
Listen Only Mode (no acknowledge, no active error flags).
Reception of "own" messages (Self Reception Request).

3.3 Acceptance filter features

Fast hardware implemented search algorithm supporting a large number of CAN identifiers.
Global Acceptance Filter recognizes 11-bit and 29-bit Rx Identifiers for all CAN buses.
Allows definition of explicit and groups for 11-bit and 29-bit CAN identifiers.
Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. 4. Pin description 5. CAN controller architecture The CAN Controller is a complete serial interface with both Transmit and Receive Buffers but without Acceptance Filter. CAN Identifier filtering is done for all CAN channels in a separate block (Acceptance Filter). Except for message buffering and acceptance filtering the functionality is similar to the PeliCAN concept. The CAN Controller Block includes interfaces to the following blocks:
APB Interface

Table 312. CAN Pin descriptions RD1, RD2 Input Serial Inputs. From CAN transceivers. TD1, TD2 Output Serial Outputs. To CAN transceivers.

Acceptance Filter
Nested Vectored Interrupt Controller (NVIC)
CAN Transceiver
Common Status Registers

5.1 APB Interface Block (AIB)

The APB Interface Block provides access to all CAN Controller registers.

5.2 Interface Management Logic (IML)

The Interface Management Logic interprets commands from the CPU, controls internal addressing of the CAN Registers and provides interrupts and status information to the CPU.

5.3 Transmit Buffers (TXB)

The TXB represents a Triple Transmit Buffer, which is the interface between the Interface Management Logic (IML) and the Bit Stream Processor (BSP). Each Transmit Buffer is able to store a complete message which can be transmitted over the CAN network. This buffer is written by the CPU and read out by the BSP. Fig 52. CAN controller block diagram INTERFACE MANAGEMENT LOGIC TRANSMIT BUFFERS 1,2 AND 3 RECEIVE BUFFERS 1 AND 2 BIT TIMING LOGIC BIT STREAM PROCESSOR ERROR MANAGEMENT LOGIC CAN CORE BLOCK NVIC APB BUS ACCEPTANCE FILTER COMMON STATUS REGISTER CAN TRANSCEIVER TX RX

5.4 Receive Buffer (RXB)

The Receive Buffer (RXB) represents a CPU accessible Double Receive Buffer. It is located between the CAN Controller Core Block and APB Interface Block and stores all received messages from the CAN Bus line. With the help of this Double Receive Buffer concept the CPU is able to process one message while another message is being received. The global layout of the Receive Buffer is very similar to the Transmit Buffer described earlier. Identifier, Frame Format, Remote Transmission Request bit and Data Length Code have the same meaning as described for the Transmit Buffer. In addition, the Receive Buffer includes an ID Index field (see Section 16–7.9.1 “ ID index field”). The received Data Length Code represents the real transmitted Data Length Code, which may be greater than 8 depending on transmitting CAN node. Nevertheless, the maximum number of received data bytes is 8. This should be taken into account by reading a message from the Receive Buffer. If there is not enough space for a new message within the Receive Buffer, the CAN Controller generates a Data Overrun condition when this message becomes valid and the acceptance test was positive. A message that is partly written into the Receive Buffer (when the Data Overrun situation occurs) is deleted. This situation is signalled to the CPU via the Status Register and the Data Overrun Interrupt, if enabled. Fig 53. Transmit buffer layout for standard and extended frame format configurations TX Frame info unused TX Priority TX Data 4 TX Data 3 TX Data 2 TX Data 1 TX Data 8 TX Data 7 TX Data 6 TX Data 5 unused 31 24 23 16 15 8 7 0 TFS TID TDA TDB Descriptor Field Data Field Standard Frame Format (11-bit Identifier) Frame info unused TX DLC TX Priority TX Data 4 TX Data 3 TX Data 2 TX Data 1 TX Data 8 TX Data 7 TX Data 6 TX Data 5 unused 31 24 23 16 15 8 7 0 TFS TID TDA TDB Descriptor Field Data Field Extended Frame Format (29-bit Identifier) TX DLC TX

5.5 Error Management Logic (EML)

The EML is responsible for the error confinement. It gets error announcements from the BSP and then informs the BSP and IML about error statistics.

5.6 Bit Timing Logic (BTL)

The Bit Timing Logic monitors the serial CAN Bus line and handles the Bus line related bit timing. It synchronizes to the bit stream on the CAN Bus on a "recessive" to "dominant" Bus line transition at the beginning of a message (hard synchronization) and re-synchronizes on further transitions during the reception of a message (soft synchronization). The BTL also provides programmable time segments to compensate for the propagation delay times and phase shifts (e.g. due to oscillator drifts) and to define the sample point and the number of samples to be taken within a bit time.

5.7 Bit Stream Processor (BSP)

The Bit Stream Processor is a sequencer, controlling the data stream between the Transmit Buffer, Receive Buffers and the CAN Bus. It also performs the error detection, arbitration, stuffing and error handling on the CAN Bus.

5.8 CAN controller self-tests

The CAN controller supports two different options for self-tests:

Global Self-Test (setting the self reception request bit in normal Operating Mode)
Local Self-Test (setting the self reception request bit in Self Test Mode) Fig 54. Receive buffer layout for standard and extended frame format configurations RX Frame info unused ID Index RX Data 4 RX Data 3 RX Data 2 RX Data 1 RX Data 8 RX Data 7 RX Data 6 RX Data 5 unused 31 24 23 16 15 10 9 8 7 0 RFS RID RDA RDB Descriptor Field Data Field Standard Frame Format (11-bit Identifier) Frame info unused RX DLC RX Data 4 RX Data 3 RX Data 2 RX Data 1 RX Data 8 RX Data 7 RX Data 6 RX Data 5 31 24 23 16 15 RFS RID RDA RDB Descriptor Field Data Field Extended Frame Format (29-bit Identifier) RX DLC RX unused unused ID Indexunused 10 9 8 7 0 BPM=bypass message

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 346 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Both self-tests are using the ‘Self Reception’ feature of the CAN Controller. With the Self Reception Request, the transmitted message is also received and stored in the receive buffer. Therefore the acceptance filter has to be configured accordingly. As soon as the CAN message is transmitted, a transmit and a receive interrupt are generated, if enabled. Global self test A Global Self-Test can for example be used to verify the chosen configuration of the CAN Controller in a given CAN system. As shown in Figure 16–55, at least one other CAN node, which is acknowledging each CAN message has to be connected to the CAN bus. Initiating a Global Self-Test is similar to a normal CAN transmission. In this case the transmission of a CAN message(s) is initiated by setting Self Reception Request bit (SRR) in conjunction with the selected Message Buffer bits (STB3, STB2, STB1) in the CAN Controller Command register (CANCMR). Local self test The Local Self-Test perfectly fits for single node tests. In this case an acknowledge from other nodes is not needed. As shown in the Figure below, a CAN transceiver with an appropriate CAN bus termination has to be connected to the LPC17xx. The CAN Controller has to be put into the 'Self Test Mode' by setting the STM bit in the CAN Controller Mode register (CANMOD). Hint: Setting the Self Test Mode bit (STM) is possible only when the CAN Controller is in Reset Mode. A message transmission is initiated by setting Self Reception Request bit (SRR) in conjunction with the selected Message Buffer(s) (STB3, STB2, STB1). Fig 55. Global Self-Test (h igh-speed CAN Bus example) Transceiver TX Buffer RX Buffer ack TX BufferTX Buffer CAN Bus LPC17xx Fig 56. Local self test (high-speed CAN Bus example) Transceiver RX Buffer TX BufferTX BufferTX Buffer LPC17xx

Memory map of the CAN block

detailed descriptions follow. Table 313. Memory map of the CAN block 0x4003 8000 - 0x4003 87FF Acceptance Filter RAM. 0x4003 C000 - 0x4003 C017 Acceptance Filter Registers. 0x4004 0000 - 0x4004 000B Central CAN Registers. 0x4004 4000 - 0x4004 405F CAN Controller 1 Registers. 0x4004 8000 - 0x4004 805F CAN Controller 2 Registers. 0x400F C110 - 0x400F C114 CAN Wake and Sleep Registers. Table 314. CAN acceptance filt er and central CAN registers Table 315. CAN1 and CAN2 controller register map

7.1 CAN Mode register (CAN1MOD - 0x4004 4000, CAN2MOD -

Table 316. CAN1 and CAN2 cont roller register summary Table 317. CAN Wake and Sleep registers

UM10360_1 © NXP B.V. 2010. All rights reserved. be used e.g. for software driven bit rate detection and "hot plugging". Table 318. CAN Mode register (CAN1MOD - address 0x40 04 4000, CAN2MOD - address 0x4004 8000) bit description transmission/reception of a message is aborted. CAN bus. The error counters are stopped at the current value. 0 (normal) A transmitted message must be acknowledged to be considered successful. bus using the SRR bit in CANxCMR. 0 (CAN ID) The transmit priority for 3 Transmit Buffers depends on the CAN Identifier. Tx Priority register within the Transmit Buffer. 0 (wake-up) Normal operation. 0 (low active) RD input is active Low (dominant bit = 0). 1 (high active) RD input is active High (dominant bit = 1) -- reverse polarity. 0 (disabled) Normal operation. read from a reserved bit is not defined.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 351 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 [3] A write access to the bits MOD.1 and MOD.2 is possible only if the Reset Mode is entered previously. [4] Transmit Priority Mode is explained in more detail in Section 16–5.3 “Transmit Buffers (TXB)”. [5] The CAN Controller will enter Sleep Mode, if the Sleep Mode bi t is set '1' (sleep), there is no bus activity, and none of the CAN interrupts is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. The CAN Controller will wake up if SM is set LOW (wake-up) or there is bus activity. On wake-up, a Wake-up Interrupt is generated. A sleeping CAN Controller which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits (Bus-Free sequence). Note that setting of SM is not possible in Reset Mode. After clearing of Reset Mode, setting of SM is possible only when Bus-Free is detected again. [6] The LOM and STM bits can only be written if t he RM bit is 1 prior to the write operation.

7.2 CAN Command Register (C AN1CMR - 0x4004 x004, CAN2CMR -

0x4004 8004) Writing to this write-only register initiates an action within the transfer layer of the CAN Controller. Reading this register yields zeroes. At least one internal clock cycle is needed for processing between two commands. Table 319. CAN Command Re gister (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit Bit Symbol Value Function Reset Value RM Set 0[1][2] TR Transmission Request. 0 0 0 (absent) No transmission request. 1 (present) The message, previously writ ten to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 16–5.3 “ Transmit Buffers (TXB)”) 1[1][3] AT Abort Transmission. 0 0 0 (no action) Do not abort the transmission. 1 (present) if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled. 2[4] RRB Release Receive Buffer. 0 0 0 (no action) Do not release the receive buffer. 1 (released) The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s). [5] CDO Clear Data Overrun. 0 0 0 (no action) Do not clear the data overrun bit. 1 (clear) The Data Overrun bit in Status Register(s) is cleared. 4[1][6] SRR Self Reception Request. 0 0 0 (absent) No self reception request. 1 (present) The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 352 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 [1] - Setting the command bits TR and AT simultaneously results in transmitting a message once. No re-transmission will be performed in case of an error or arbitration lost (single shot transmission). - Setting the command bits SRR and TR simultaneously results in sending the transmit message once using the self-reception feature. No re-transmission will be performed in case of an error or arbitration lost. - Setting the command bits TR, AT and SRR simultaneously results in transmitting a message once as described for TR and AT. The moment the Transmit Status bit is set within the Status Register, the internal Transmission Request Bit is cleared automatically. - Setting TR and SRR simultaneously will ignore the set SRR bit. [2] If the Transmission Request or the Self-R eception Request bit was set '1' in a previous command, it cannot be cancelled by resetting the bits. The requested transmission may only be cancelled by setting the Abort Transmission bit. [3] The Abort Transmission bit is used when the CPU requires the suspension of the prev iously requested transmission, e.g. to transmit a more urgent message before. A transmission already in progress is not stopped. In order to see if the original message has been either transmitted successfully or aborted, the Transmission Complete Status bit should be checked. This should be done after the Transmit Buffer Status bit has been set to '1' or a Transmit Interrupt has been generated. [4] After reading the contents of the Receive Buffer, the CPU can release this memory space by setting the Release Receive Buffer bit '1'. This may result in another message becoming immediately available. If there is no other message available, the Receive Interrupt bit is reset. If the RRB command is given, it will take at least 2 internal clock cycles before a new interrupt is generated. [5] This command bit is used to clear the Data Overrun condition si gnalled by the Data Overrun Status bit. As long as the Data Overrun Status bit is set no further Data Overrun Interrupt is generated. [6] Upon Self Reception Request, a message is transmitted and simultan eously received if the Acceptance Filter is set to the corresponding identifier. A receive and a transmit interrupt will indicate correct self reception (see also Self Test Mode in Section 16–7.1 “CAN Mode register (CAN1MOD - 0x4004 4000, CAN2MOD - 0x4004 8000)”).

7.3 CAN Global Status Register (CAN1GSR - 0x4004 x008, CAN2GSR -

0x4004 8008) The content of the Global Status Register reflects the status of the CAN Controller. This register is read-only, except that the Error Counters can be written when the RM bit in the CANMOD register is 1. Bits not listed read as 0 and should be written as 0. 5 STB1 Select Tx Buffer 1. 0 0 0 (not selected) Tx Buffer 1 is not selected for transmission. 1 (selected) Tx Buffer 1 is selected for transmission. 6 STB2 Select Tx Buffer 2. 0 0 0 (not selected) Tx Buffer 2 is not selected for transmission. 1 (selected) Tx Buffer 2 is selected for transmission. 7 STB3 Select Tx Buffer 3. 0 0 0 (not selected) Tx Buffer 3 is not selected for transmission. 1 (selected) Tx Buffer 3 is selected for transmission. 31:8 - Reserved, user software should not write ones to reserved bits. NA Bit Symbol Value Function Reset Value RM Set

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 353 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 [1] After reading all messages and releasing their memory space with the command 'Releas e Receive Buffer,' this bit is cleared. Table 320. CAN Global Status Register (CAN1GSR - address 0x4004 4008, CAN2GSR - address 0x4004 8008) bit Bit Symbol Value Function Reset Value RM Set 0R B S [1] Receive Buffer Status. 0 0 0 (empty) No message is available. 1 (full) At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available. 1D O S [2] Data Overrun Status. 0 0 0 (absent) No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset). 1 (overrun) A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer). 2 TBS Transmit Buffer Status. 1 1 0 (locked) At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s). 1 (released) All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers. 3T C S [3] Transmit Complete Status. 1 x 0 (incomplete) At least one requested transmission has not been successfully completed yet. 1 (complete) All requested transmission(s) has (have) been successfully completed. 4R S [4] Receive Status. 1 0 0 (idle) The CAN controller is idle. 1 (receive) The CAN controller is receiving a message. 5T S [4] Transmit Status. 1 0 0 (idle) The CAN controller is idle. 1 (transmit) The CAN controller is sending a message. 6E S [5] Error Status. 0 0 0 (ok) Both error counters are below the Error Warning Limit. 1 (error) One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register. 7B S [6] Bus Status. 0 0 0 (Bus-On) The CAN Controller is involved in bus activities 1 (Bus-Off) The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255. 15:8 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 23:16 RXERR - The current value of the Rx Error Counter (an 8-bit value). 0 X 31:24 TXERR - The current value of the Tx Error Counter (an 8-bit value). 0 X

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 354 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 [2] If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. [3] The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmi ssion Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully. [4] If both the Receive Status and the Transmit Status bits are '0 ' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits. [5] Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 16–7.7 “CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018)”. [6] Mode bit '1' (present) and an Error Warning Interrupt is generat ed, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. RX error counter The RX Error Counter Register, which is part of the Status Register, reflects the current value of the Receive Error Counter. After hardware reset this register is initialized to 0. In Operating Mode this register appears to the CPU as a read-only memory. A write access to this register is possible only in Reset Mode. If a Bus Off event occurs, the RX Error Counter is initialized to 0. As long as Bus Off is valid, writing to this register has no effect.The Rx Error Counter is determined as follows: RX Error Counter = (CANxGSR AND 0x00FF0000) / 0x00010000 Note that a CPU-forced content change of the RX Error Counter is possible only if the Reset Mode was entered previously. An Error Status change (Status Register), an Error Warning or an Error Passive Interrupt forced by the new register content will not occur until the Reset Mode is cancelled again. TX error counter The TX Error Counter Register, which is part of the Status Register, reflects the current value of the Transmit Error Counter. In Operating Mode this register appears to the CPU as a read-only memory. After hardware reset this register is initialized to 0. A write access to this register is possible only in Reset Mode. If a bus-off event occurs, the TX Error Counter is initialized to 127 to count the minimum protocol-defined time (128 occurrences of the Bus-Free signal). Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. If Bus Off is active, a write access to TXERR in the range of 0 to 254 clears the Bus Off Flag and the controller will wait for one occurrence of 11 consecutive recessive bits (bus free) after clearing of Reset Mode. The Tx error counter is determined as follows: TX Error Counter = (CANxGSR AND 0xFF000000) / 0x01000000 Writing 255 to TXERR allows initiation of a CPU-driven Bus Off event. Note that a CPU-forced content change of the TX Error Counter is possible only if the Reset Mode was entered previously. An Error or Bus Status change (Status Register), an Error

7.4 CAN Interrupt and Capture Register (CAN1ICR - 0x4004 400C,

Receive Interrupt bit. The Interrupt Register appears to the CPU as a read-only memory. Bits 1 through 10 clear when they are read. CANIER is 1, the BEI bit in this register is set, and a CAN interrupt can occur. released to capture a new value. register as appropriate for the application. Table 321. CAN Interrupt and Captur e Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C) stored in the Receive Buffer.

1 TI1 0 (reset)

indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1. Interrupt Enable Register at the time of the change.

3 DOI 0 (reset)

to 1 and the DOIE bit in CANxIER is 1. is detected and the WUIE bit in CANxIER is 1.

5 EPI 0 (reset)

6 ALI 0 (reset)

CAN node becomes a receiver.

7 BEI 0 (reset)

controller detects an error on the bus.

8 IDI 0 (reset)

aborted and the IDIE bit is set in the IER register.

9 TI2 0 (reset)

indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.

10 TI3 0 (reset)

indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.

00011 Start of Frame

00100 SRTR Bit

00101 IDE bit

01100 RTR Bit

01101 Reserved Bit 1

01001 Reserved Bit 0

01011 Data Length Code

01010 Data Field

01000 CRC Sequence

11000 CRC Delimiter

11001 Acknowledge Slot

11011 Acknowledge Delimiter

11010 End of Frame

10010 Intermission

10001 Active Error Flag

10110 Passive Error Flag

10011 Tolerate Dominant Bits

10111 Error Delimiter

11100 Overload flag

21 ERRDIR When the CAN controller detects a bus error, the direction of the current bit is

0 Error occurred during transmitting. 1 Error occurred during receiving.

00 Bit error

01 Form error

10 Stuff error

11 Other error

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 358 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 [1] The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command “Release Receive Buffer” will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared. [2] A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted. [3] Whenever a bus error occurs, the co rresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt. [4] On arbitration lost, the corresponding arbitration lost in terrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again.

7.5 CAN Interrupt Enable Register (CAN1IER - 0x4004 4010, CAN2IER -

0x4004 8010) This read/write register controls whether various events on the CAN controller will result in an interrupt or not. Bits 10:0 in this register correspond 1-to-1 with bits 10:0 in the CANxICR register. If a bit in the CANxIER register is 0 the corresponding interrupt is disabled; if a bit in the CANxIER register is 1 the corresponding source is enabled to trigger an interrupt. 31:24 ALCBIT [4] - Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 arbitration lost in the first bit (MS) of identifier ... 11 arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 arbitration lost in IDE bit 13 arbitration lost in 12th bit of identifier (extended frame only) ... 30 arbitration lost in last bit of identifier (extended frame only) 31 arbitration lost in RTR bit (extended frame only) Table 322. CAN Interrupt Enable Register (CAN1IER - address 0x4004 4010, CAN2IER - address 0x4004 8010) bit 0 RIE Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt. 1 TIE1 Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. 2 EIE Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt.

7.6 CAN Bus Timing Register ( CAN1BTR - 0x4004 4014, CAN2BTR -

0x4004 8014) This register controls how various CAN timings are derived from the APB clock. It defines the values of the Baud Rate Prescaler (BRP) and the Synchronization Jump Width (SJW). Furthermore, it defines the length of the bit period, the location of the sample point and the number of samples to be taken at each sample point. It can be read at any time but can only be written if the RM bit in CANmod is 1. 3 DOIE Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt. 4 WUIE Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested. 5 EPIE Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested. 6 ALIE Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested. 7 BEIE Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt. 8 IDIE ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt. 9 TIE2 Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. 10 TIE3 Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt. 31:11 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 323. CAN Bus Timing Register (CAN1BTR - ad dress 0x4004 4014, CAN2BTR - address 0x4004 8014) bit Bit Symbol Value Function Reset Value RM Set 9:0 BRP Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock. 13:10 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 15:14 SJW The Synchronization Jump Width is (this value plus one) CAN clocks. 0 X 19:16 TESG1 The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks. 1100 X 22:20 TESG2 The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks. 001 X

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 360 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Baud rate prescaler The period of the CAN system clock tSCL is programmable and determines the individual bit timing. The CAN system clock tSCL is calculated using the following equation: (5) Synchronization jump width To compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width tSJW defines the maximum number of clock cycles a certain bit period may be shortened or lengthened by one re-synchronization: (6) Time segment 1 and time segment 2 Time segments TSEG1 and TSEG2 determine the number of clock cycles per bit period and the location of the sample point: (7) (8) (9)

7.7 CAN Error Warning Limit re gister (CAN1EWL - 0x4004 4018,

CAN2EWL - 0x4004 8018) This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be read at any time but can only be written if the RM bit in CANmod is 1.

23 SAM Sampling

0 The bus is sampled once (recommended for high speed buses) 0 X

1 The bus is sampled 3 times (recommended for low to medium speed buses to filter

spikes on the bus-line) 31:24 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Bit Symbol Value Function Reset Value RM Set tSCL tCANsuppliedCLK BRP 1+()×= tSJW tSCL SJW 1+()×= tSYNCSEG tSCL= tTSEG1 tSCL TSEG1 1+()×= tTSEG2 tSCL TSEG2 1+()×=

7.8 CAN Status Register (CAN1SR - 0x4004 401C, CAN2SR -

those relating to transmission reflect the status of each of the 3 Tx Buffers. Table 324. CAN Error Warning Limit register (CAN1EW L - address 0x4004 4018, CAN2EWL - address 0x4004 8018) either of these counter matches this value, the Error Status (ES) bit in CANSR is set. reserved bit is not defined. Table 325. CAN Status Register (CAN1SR - address 0x4 004 401C, CAN2SR - address 0x4004 801C) bit description message is either waiting for transmission or is in transmitting process. CANxTID, CANxTDA, and CANxTDB registers. 0(incomplete) The previously requested transm ission for Tx Buffer 1 is not complete. 0(idle) There is no transmission from Tx Buffer 1. 1(transmit) The CAN Controller is transm itting a message from Tx Buffer 1.

UM10360_1 © NXP B.V. 2010. All rights reserved. lost without this being signalled. is set '1' for this TX buffer. The Transmission Complete Status bit remains '0' until a message is transmitted successfully. message is either waiting for transmission or is in transmitting process. CANxTID, CANxTDA, and CANxTDB registers. 0(incomplete) The previously requested transm ission for Tx Buffer 2 is not complete. 0(idle) There is no transmission from Tx Buffer 2. 1(transmit) The CAN Controller is transm itting a message from Tx Buffer 2. message is either waiting for transmission or is in transmitting process. CANxTID, CANxTDA, and CANxTDB registers. 0(incomplete) The previously requested transm ission for Tx Buffer 3 is not complete. 0(idle) There is no transmission from Tx Buffer 3. 1(transmit) The CAN Controller is transm itting a message from Tx Buffer 3.

7.9 CAN Receive Frame Status re gister (CAN1RFS - 0x4004 4020,

normal operation but can be written for testing purposes if the RM bit in CANxMOD is 1.

7.9.1 ID index field

CAN message was received in acceptance filter bypass mode.

7.10 CAN Receive Identifi er register (CAN1RID - 0x4004 4024, CAN2RID -

details on specific CAN channel register address. Table 326. CAN Receive Frame Status register (CAN1RFS - address 0x4004 4020, CAN2RFS - address 0x4004 8020)

10 BP If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field

reserved bit is not defined. reserved bit is not defined. value identifies the number of data bytes requested to be sent using the same Identifier.

31 FF A 0 in this bit indicates that the current received message included an 11-bit Identifier, while

7.11 CAN Receive Data register A (C AN1RDA - 0x4004 4028, CAN2RDA -

0x4004 8028) This register contains the first 1-4 Data bytes of the current received message. It is read-only in normal operation, but can be written for testing purposes if the RM bit in CANMOD is 1. See Table 16–314 for details on specific CAN channel register address.

7.12 CAN Receive Data register B (C AN1RDB - 0x4004 402C, CAN2RDB -

0x4004 802C) This register contains the 5th through 8th Data bytes of the current received message. It is read-only in normal operation, but can be written for testing purposes if the RM bit in CANMOD is 1. See Table 16–314 for details on specific CAN channel register address. Table 327. CAN Receive Identifier register (CAN1RID - address 0x4004 4024, CAN2RID - address 0x4004 8024) bit Bit Symbol Function Reset Value RM Set 10:0 ID The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they’re called ID29-18. 31:11 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 328. RX Identifier register when FF = 1 from a reserved bit is not defined. Table 329. CAN Receive Data register A (CAN1RDA - ad dress 0x4004 4028, CAN2RDA - address 0x4004 8028) bit Bit Symbol Function Reset Value RM Set 7:0 Data 1 If the DLC field in CANRFS ≥ 0001, this contains the first Data byte of the current received message. 15:8 Data 2 If the DLC field in CANRFS ≥ 0010, this contains the first Data byte of the current received message. 23:16 Data 3 If the DLC field in CANRFS ≥ 0011, this contains the first Data byte of the current received message. 31:24 Data 4 If the DLC field in CANRFS ≥ 0100, this contains the first Data byte of the current received message. Table 330. CAN Receive Data register B (CAN1RDB - ad dress 0x4004 402C, CAN2RDB - address 0x4004 802C) bit Bit Symbol Function Reset Value RM Set 7:0 Data 5 If the DLC field in CANRFS ≥ 0101, this contains the first Data byte of the current received message.

7.13 CAN Transmit Frame Informati on register (CAN1TFI[1/2/3] -

When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the format of the next transmit message for that Tx buffer. Bits not listed read as 0 and should be written as 0. The values for the reserved bits of the CANxTFI register in the Transmit Buffer should be set to the values expected in the Receive Buffer for an easy comparison, when using the Self Reception facility (self test), otherwise they are not defined. The CAN Controller consist of three Transmit Buffers. Each of them has a length of 4 words and is able to store one complete CAN message as shown in Figure 16–53. The buffer layout is subdivided into Descriptor and Data Field where the first word of the Descriptor Field includes the TX Frame Info that describes the Frame Format, the Data Length and whether it is a Remote or Data Frame. In addition, a TX Priority register allows the definition of a certain priority for each transmit message. Depending on the chosen Frame Format, an 11-bit identifier for Standard Frame Format (SFF) or an 29-bit identifier for Extended Frame Format (EFF) follows. Note that unused bits in the TID field have to be defined as 0. The Data Field in TDA and TDB contains up to eight data bytes. 15:8 Data 6 If the DLC field in CANRFS ≥ 0110, this contains the first Data byte of the current received message. 23:16 Data 7 If the DLC field in CANRFS ≥ 0111, this contains the first Data byte of the current received message. 31:24 Data 8 If the DLC field in CANRFS ≥ 1000, this contains the first Data byte of the current received message. Bit Symbol Function Reset Value RM Set Table 331. CAN Transmit Frame Information register (CAN1TFI[1/2/3] - address 0x4004 40[30/40/50], CAN2TFI[1/2/3] - lowest TX Priority value wins the prioritization and is sent first. data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes.

31 FF If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame

7.14 CAN Transmit Identifier register (CAN1TID[1/2/3] -

Table 332. CAN Transfer Identifier register (CAN1TID[1/2/3] - address 0x4004 40[34/44/54], CAN2TID[1/2/3] - address from a reserved bit is not defined.

7.15 CAN Transmit Data re gister A (CAN1TDA[1/2/3] - 0x4004 40[38/48/58],

significant bit of TX Data Byte 1.

7.16 CAN Transmit Data register B ( CAN1TDB[1/2/3] - 0x4004 40[3C/4C/5C],

most significant bit of TX Data Byte 1.

7.17 CAN Sleep Clear regist er (CANSLEEPCLR - 0x400F C110)

“Sleep mode” for more information on the CAN sleep feature. Table 333. Transfer Identifier register when FF = 1 from a reserved bit is not defined. Table 334. CAN Transmit Data register A (CAN1TDA[1/2/3] - address 0x4004 40[38/48/58], CAN2TDA[1/2/3] - address the first Data byte of the next transmit message. the 2nd Data byte of the next transmit message. the 3rd Data byte of the next transmit message. the 4th Data byte of the next transmit message. Table 335. CAN Transmit Data register B (CAN1TDB[1/2/3] - address 0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] - address 5th Data byte of the next transmit message. 6th Data byte of the next transmit message. 7th Data byte of the next transmit message. 8th Data byte of the next transmit message.

7.18 CAN Wake-up Flags register (CANWAKEFLAGS - 0x400F C114)

8.1 Error handling

Table 336. CAN Sleep Clear register (CANSL EEPCLR - address 0x400F C110) bit description reserved bit is not defined. 1 CAN1SLEEP Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1. 2 CAN2SLEEP Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2. reserved bit is not defined. Table 337. CAN Wake-up Flags register (CANWAKEFLAGS - address 0x400F C114) bit description a reserved bit is not defined. 1 CAN1WAKE Wake-up status for CAN channel 1. Write: writing a 1 clears this bit. 2 CAN2WAKE Wake-up status for CAN channel 2. Write: writing a 1 clears this bit. a reserved bit is not defined.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 369 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 recessive bits). Software can monitor this countdown by reading the Tx Error Counter. When this countdown is complete, the CAN Controller clears BS and ES in CANxSR, and sets EI in CANxSR if EIE in IER is 1. The Tx and Rx error counters can be written if RM in CANxMOD is 1. Writing 255 to the Tx Error Counter forces the CAN Controller to Bus-Off state. If Bus-Off (BS in CANxSR) is 1, writing any value 0 through 254 to the Tx Error Counter clears Bus-Off. When software clears RM in CANxMOD thereafter, only one Bus Free condition (11 consecutive recessive bits) is needed before operation resumes.

8.2 Sleep mode

The CAN Controller will enter sleep mode if the SM bit in the CAN Mode register is 1, no CAN interrupt is pending, and there is no activity on the CAN bus. Software can only set SM when RM in the CAN Mode register is 0; it can also set the WUIE bit in the CAN Interrupt Enable register to enable an interrupt on any wake-up condition. The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b) software clearing SM in the CAN Mode register. A sleeping CAN Controller that wakes up in response to bus activity is not able to receive an initial message until after it detects Bus_Free (11 consecutive recessive bits). If an interrupt is pending or the CAN bus is active when software sets SM, the wake-up is immediate. Upon wake-up, software needs to do the following things: 1. Write a 1 to the relevant bit( s) in the CANSLEEPCLR register. 2. Write a 0 to the SM bit in the CAN1MOD and/or CAN2MOD register. 3. Write a 1 to the relevant bit(s) in t he CANWAKEFLAGS register. Failure to perform this step will prevent subsequent entry into Power-down mode. If the LPC17xx is in Deep Sleep or Power-down mode, CAN activity will wake up the device if the CAN activity interrupt is enabled. See Section 4–8 “ Power control”.

8.3 Interrupts

Each CAN Controller produces 3 interrupt requests, Receive, Transmit, and “other status”. The Transmit interrupt is the OR of the Transmit interrupts from the three Tx Buffers. Each Receive and Transmit interrupt request from each controller is assigned its own channel in the NVIC, and can have its own interrupt service routine. The “other status” interrupts from all of the CAN controllers, and the Acceptance Filter LUTerr condition, are ORed into one NVIC channel.

8.4 Transmit priority

If the TPM bit in the CANxMOD register is 0, multiple enabled Tx Buffers contend for the right to send their messages based on the value of their CAN Identifier (TID). If TPM is 1, they contend based on the PRIO fields in bits 7:0 of their CANxTFS registers. In both cases the smallest binary value has priority. If two (or three) transmit-enabled buffers have the same smallest value, the lowest-numbered buffer sends first. The CAN controller selects among multiple enabled Tx Buffers dynamically, just before it sends each message.

Centralized CAN registers

particular status bit from each of the CAN controllers, in its LS bits. All Status registers are read-only and allow byte, half word and word access.

9.1 Central Transmit Status Register (CANTxSR - 0x4004 0000)

9.2 Central Receive Status Re gister (CANRxSR - 0x4004 0004)

Table 338. Central Transit Status Register (CANTxSR - address 0x4004 0000) bit description

1 TS2 When 1, the CAN controller 2 is sendi ng a message (same as TS in the CAN2GSR) 0

reserved bit is not defined.

8 TBS1 When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in

9 TBS2 When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in

reserved bit is not defined.

16 TCS1 When 1, all requested transmissions have been completed successfully by the CAN1

controller (same as TCS in CAN1GSR). controller (same as TCS in CAN2GSR). Table 339. Central Receive Status Register (C ANRxSR - address 0x4004 0004) bit description reserved bit is not defined.

8 RB1 When 1, a received message is available in the CAN1 controller (same as RBS in

9 RB2 When 1, a received message is available in the CAN2 controller (same as RBS in

reserved bit is not defined.

16 DOS1 When 1, a message was lost because the preceding message to CAN1 controller was not

read out quickly enough (same as DOS in CAN1GSR). read out quickly enough (same as DOS in CAN2GSR).

9.3 Central Miscellaneous Status Register (CANMSR - 0x4004 0008)

Global acceptance filter

Standard Identifiers or 512 Extended Identifiers, or a mixture of both types. access to the Configuration Register and the ID Look-up table is handled differently. [1] The whole ID Look-up Table RA M is only word accessible. Filter Off and Bypass Mode. Read access is allowed in all Acceptance Filter Modes. Table 340. Central Miscellaneous Status Register (CANMSR - address 0x4004 0008) bit description

0 E1 When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the

1 E2 When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the

reserved bit is not defined.

8 BS1 When 1, the CAN1 controller is currently involved in bus activities (same as BS in

9 BS2 When 1, the CAN2 controller is currently involved in bus activities (same as BS in

Table 341. Acceptance filter modes and access control

11.1 Acceptance filter Off mode

the Receive Buffers of active CAN Controllers.

11.2 Acceptance filter Bypass mode

Table memory. During this re-configuration, software acceptance filtering has to be used. It is recommended to use the ID ready Interrupt (ID Index) and the Receive Interrupt (RI).

11.3 Acceptance filter Operating mode

Configuration Register is set and the eFCAN = 0.

11.4 FullCAN mode

Sections of the ID look-up table RAM

Message Objects, if enabled are stored. Table 342. Section configuration register settings

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 373 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 13. ID look-up table RAM The Whole ID Look-up Table RAM is only word accessible. A write access is only possible during the Acceptance Filter Off or Bypass Mode. Read access is allowed in all Acceptance Filter Modes. If Standard (11-bit) Identifiers are used in the application, at least one of 3 tables in Acceptance Filter RAM must not be empty. If the optional “FullCAN mode” is enabled, the first table contains Standard identifiers for which reception is to be handled in this mode. The next table contains individual Standard Identifiers and the third contains ranges of Standard Identifiers, for which messages are to be received via the CAN Controllers. The tables of FullCAN and individual Standard Identifiers must be arranged in ascending numerical order, one per halfword, two per word. Since each CAN bus has its own address map, each entry also contains the number of the CAN Controller (001-010) to which it applies. The table of Standard Identifier Ranges contains paired upper and lower (inclusive) bounds, one pair per word. These must also be arranged in ascending numerical order. The disable bits in Standard entries provide a means to turn response, to particular CAN Identifiers or ranges of Identifiers, on and off dynamically. When the Acceptance Filter function is enabled, only the disable bits in Acceptance Filter RAM can be changed by software. Response to a range of Standard addresses can be enabled by writing 32 zero bits to its word in RAM, and turned off by writing 32 one bits (0xFFFF FFFF) to its word in RAM. Only the disable bits are actually changed. Disabled entries must maintain the ascending sequence of Identifiers. If Extended (29-bit) Identifiers are used in the application, at least one of the other two tables in Acceptance Filter RAM must not be empty, one for individual Extended Identifiers and one for ranges of Extended Identifiers. The table of individual Extended Identifiers must be arranged in ascending numerical order. Fig 57. Entry in FullCAN and indivi dual standard identifier tables Fig 58. Entry in standard identifier range table CONTROLLER # IDENTIFIERDIS ABLE NOT USED CONTROLLER LOWER IDENTIFIER BOUND DISABLE NOT USED UPPER IDENTIFIER BOUND DISABLE NOT USEDCONTROLLER 31 29 26 16 10 0

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 374 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 The table of ranges of Extended Identifiers must contain an even number of entries, of the same form as in the individual Extended Identifier table. Like the Individual Extended table, the Extended Range must be arranged in ascending numerical order. The first and second (3rd and 4th …) entries in the table are implicitly paired as an inclusive range of Extended addresses, such that any received address that falls in the inclusive range is received (accepted). Software must maintain the table to consist of such word pairs. There is no facility to receive messages to Extended identifiers using the FullCAN method. Five address registers point to the boundaries between the tables in Acceptance Filter RAM: FullCAN Standard addresses, Standard Individual addresses, Standard address ranges, Extended Individual addresses, and Extended address ranges. These tables must be consecutive in memory. The start of each of the latter four tables is implicitly the end of the preceding table. The end of the Extended range table is given in an End of Tables register. If the start address of a table equals the start of the next table or the End Of Tables register, that table is empty. When the Receive side of a CAN controller has received a complete Identifier, it signals the Acceptance Filter of this fact. The Acceptance Filter responds to this signal, and reads the Controller number, the size of the Identifier, and the Identifier itself from the Controller. It then proceeds to search its RAM to determine whether the message should be received or ignored. If FullCAN mode is enabled and the CAN controller signals that the current message contains a Standard identifier, the Acceptance Filter first searches the table of identifiers for which reception is to be done in FullCAN mode. Otherwise, or if the AF doesn’t find a match in the FullCAN table, it searches its individual Identifier table for the size of Identifier signalled by the CAN controller. If it finds an equal match, the AF signals the CAN controller to retain the message, and provides it with an ID Index value to store in its Receive Frame Status register. If the Acceptance Filter does not find a match in the appropriate individual Identifier table, it then searches the Identifier Range table for the size of Identifier signalled by the CAN controller. If the AF finds a match to a range in the table, it similarly signals the CAN controller to retain the message, and provides it with an ID Index value to store in its Receive Frame Status register. If the Acceptance Filter does not find a match in either the individual or Range table for the size of Identifier received, it signals the CAN controller to discard/ignore the received message. Fig 59. Entry in either extended identifier table CONTROLLER # IDENTIFIER 31 29 28 0

Acceptance filter registers

14.1 Acceptance Filter Mode Register (AFMR - 0x4003 C000)

be used to activate a FullCAN mode enhancement for received 11-bit CAN ID messages. acceptance filtering can be done by software. software, will force the acceptance filter into Off mode. eFCAN bit in the acceptance filter mode register.

14.2 Section configur ation registers

APB addresses for the acceptance filter RAM and do not include the APB base address. filter off and Bypass modes. Read access is allowed in all acceptance filter modes. Table 343. Acceptance Filter Mode Register (AFMR - address 0x4003 C000) bit description are 0, the Acceptance filter operates to screen received CAN Identifiers. from the receiving CAN controllers.

1 The Acceptance Filter itself will take care of receiving and storing messages for

from a reserved bit is not defined.

14.3 Standard Frame Individual St art Address register (SFF_sa -

filter bypass mode or the Acceptance filter off mode.

14.4 Standard Frame Group Start A ddress register (SFF_GRP_sa -

filter bypass mode or the Acceptance filter off mode.

14.5 Extended Frame Start Address register (EFF_sa - 0x4003 C00C)

Table 344. Standard Frame Individual Start Address register (SFF_sa - address 0x4003 C004) bit description reserved bit is not defined. automatically store received messages in Acceptance Filter RAM. reserved bit is not defined. Table 345. Standard Frame Group Start Address register (SFF_GRP_sa - address 0x4003 C008) bit description a reserved bit is not defined. please write zeroes in bits 31:12 and 1:0 of this register. a reserved bit is not defined. reserved bit is not defined. 31:11 and 1:0 of this register. reserved bit is not defined.

14.6 Extended Frame Group Start A ddress register (EFF_GRP_sa -

filter bypass mode or the Acceptance filter off mode.

14.7 End of AF Tables regist er (ENDofTable - 0x4003 C014)

filter bypass mode or the Acceptance filter off mode.

14.8 Status registers

Table 347. Extended Frame Group Start Address register (EFF_GRP_sa - address 0x4003 C010) bit description a reserved bit is not defined. 31:12 and 1:0 of this register. a reserved bit is not defined. Table 348. End of AF Tables register (ENDofTable - address 0x4003 C014) bit description reserved bit is not defined. with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. reserved bit is not defined.

14.9 LUT Error Address regist er (LUTerrAd - 0x4003 C018)

14.10 LUT Error register (LUTerr - 0x4003 C01C)

14.11 Global FullCANInterrupt Enable register (FCANIE - 0x4003 C020)

Acceptance Filter is in the off mode.

14.12 FullCAN Interrupt and Capture re gisters (FCANIC0 - 0x4003 C024 and

For detailed description on these two registers, see Section 16–16.2 “FullCAN interrupts”. Table 349. LUT Error Address register (LUTerrAd - address 0x4003 C018) bit description reserved bit is not defined. Table 350. LUT Error register (LUTerr - address 0x4003 C01C) bit description

0 LUTerr This read-only bit is set to 1 if the Accept ance Filter encounters an error in the content of

request that is connected to the NVIC. Table 351. Global FullCAN En able register (FCANIE - address 0x4003 C020) bit description reserved bit is not defined. Table 352. FullCAN Interrupt and Capture register 0 (FCANIC0 - address 0x4003 C024) bit description

Configuration and search algorithm

with CAN Identifier in each section. (CANRFS) of the according CAN Controller.

15.1 Acceptance filter search algorithm

FullCAN (Standard Frame Fo rmat) Identifier Section
Explicit Standard Frame Format Identifier Section
Group of Standard Frame Format Identifier Section
Explicit Extended Frame Fo rmat Identifier Section
Group of Extended Frame Format Identifier Section

Note: Only activated sections will take part in the screening process. one section, the first match will end the screening process for this identifier. defined in the FullCAN, Explicit and Group of Standard Frame Format Identifier Sections. This example corresponds part with 6 CAN controllers. Table 353. FullCAN Interrupt and Capture register 1 (FCANIC1 - address 0x4003 C028) bit description

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 380 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 The identifier 0x5A of the CAN Controller 1 with the Source CAN Channel SCC = 1, is defined in all three sections. With this configuration incoming CAN messages on CAN Controller 1 with a 0x5A identifier will find a match in the FullCAN section. It is possible to disable the ‘0x5A identifier’ in the FullCAN section. With that, the screening process would be finished with the match in the Explicit Identifier Section. The first group in the Group Identifier Section has been defined in that way, that incoming CAN messages with identifiers of 0x5A up to 0x5F are accepted on CAN Controller 1 with the Source CAN Channel SCC = 1. As stated above, the identifier 0x5A would find a match already in the FullCAN or in the Explicit Identifier section if enabled. The rest of the defined identifiers of this group (0x5B to 0x5F) will find a match in this Group Identifier Section. This way the user can switch dynamically between different filter modes for same identifiers. 16. FullCAN mode The FullCAN mode is based on capabilities provided by the CAN Gateway module used in the LPC2000 family of products. This block uses the Acceptance Filter to provide filtering for both CAN channels. The concept of the CAN Gateway block is mainly based on a BasicCAN functionality. This concept fits perfectly in systems where a gateway is used to transfer messages or message data between different CAN channels. A BasicCAN device is generating a Fig 60. ID Look-up table example ex plaining the search algorithm SCC = 1 SCC = 2 SCC = 1 SCC = 2 SCC = 1 SCC = 3 SCC = 5 SCC = 1 SCC = 2 SCC = 4

0 FullCAN

ID = 0x5A ... ... ID = 0x5A ID = 0x5A ... SCC = 1 SCC = 3 SCC = 5 SCC = 6 SCC = 1 SCC = 2 SCC = 6 ...SCC = 4 Message disable bit ID = 0x5A ... ... ... ... ... ID = 0x5F ... Message disable bit Index 0, 1 Index 2, 3 Index 4, 5 Index 6, 7 Index 8, 9 Index 10, 11 Index 12, 13 Index 14 Index 15

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 381 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 receive interrupt whenever a CAN message is accepted and received. Software has to move the received message out of the receive buffer from the according CAN controller into the user RAM. To cover dashboard like applications where the controller typically receives data from several CAN channels for further processing, the CAN Gateway block was extended by a so-called FullCAN receive function. This additional feature uses an internal message handler to move received FullCAN messages from the receive buffer of the according CAN controller into the FullCAN message object data space of Look-up Table RAM. When FullCAN mode is enabled, the Acceptance Filter itself takes care of receiving and storing messages for selected Standard ID values on selected CAN buses, in the style of “FullCAN” controllers. In order to set this bit and use this mode, two other conditions must be met with respect to the contents of Acceptance Filter RAM and the pointers into it:

The Standard Frame Individual Start Address Register (SFF_sa) must be greater than or equal to the number of IDs for which automatic receive storage is to be done, times two. SFF_sa must be rounded up to a multiple of 4 if necessary.
The EndOfTable register must be less than or equal to 0x800 minus 6 times the SFF_sa value, to allow 12 bytes of message storage for each ID for which automatic receive storage will be done. When these conditions are met and eFCAN is set:
The area between the start of Acceptance Filter RAM and the SFF_sa address, is used for a table of individual Standard IDs and CAN Controller/bus identification, sorted in ascending order and in the same format as in the Individual Standard ID table (see Figure 16–57 “Entry in FullCAN and individual standard identifier tables” on page 373). Entries can be marked as “disabled” as in the other Standard tables. If there are an odd number of “FullCAN” ID’s, at least one entry in this table must be so marked.
The first (SFF_sa)/2 IDindex values are assigned to these automatically-stored ID’s. That is, IDindex values stored in the Rx Frame Status Register, for IDs not handled in this way, are increased by (SFF_sa)/2 compared to the values they would have when eFCAN is 0.
When a Standard ID is received, the Acceptance Filter searches this table before the Standard Individual and Group tables.
When a message is received for a controller and ID in this table, the Acceptance filter reads the received message out of the CAN controller and stores it in Acceptance Filter RAM, starting at (EndOfTable) + its IDindex*12.
The format of such messages is shown in Table 16–354.

16.1 FullCAN message layout

The FF, RTR, and DLC fields are as described in Table 16–326. the FrameInfo byte into the according buffer location with SEM[1:0] = 01. update the semaphore bits by setting SEM[1:0] = 11. Before the CPU begins reading from the message object, it should clear SEM[1:0] = 00. successfully read by the CPU. read from the message are all from the same received message. Table 354. Format of automatically stored Rx messages

0000 SEM

Table 355. FullCAN semaphore operation

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 383 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 Fig 61. Semaphore procedure for reading an auto-stored message read 1 st word SEM == 01? SEM == 11? clear SEM, write back 1 st word read 2 nd and 3 rd words read 1 st word SEM == 00? START most recently read 1 st, 2nd, and 3rd words are from the same message this message has not been received since last check

16.2 FullCAN interrupts

The CAN Gateway Block contains a 2 kB ID Look-up Table RAM. With this size a maximum number of 146 FullCAN objects can be defined if the whole Look-up Table RAM is used for FullCAN objects only. Only the first 64 FullCAN objects can be configured to participate in the interrupt scheme. It is still possible to define more than 64 FullCAN objects. The only difference is, that the remaining FullCAN objects will not provide a FullCAN interrupt. The FullCAN Interrupt Register-set contains interrupt flags (IntPndx) for (pending) FullCAN receive interrupts. As soon as a FullCAN message is received, the according interrupt bit (IntPndx) in the FCAN Interrupt Register gets asserted. In case that the Global FullCAN Interrupt Enable bit is set, the FullCAN Receive Interrupt is passed to the Vectored Interrupt Controller. Application Software has to solve the following: 1. Index/Object number calculation based on the bit position in the FCANIC Interrupt Register for more than one pending interrupt. 2. Interrupt priority handling if more than one FullCA N receive interrupt is pending. The software that covers the interrupt priority handling has to assign a receive interrupt priority to every FullCAN object. If more than one interrupt is pending, then the software has to decide, which received FullCAN object has to be served next. To each FullCAN object a new FullCAN Interrupt Enable bit (FCANIntxEn) is added, so that it is possible to enable or disable FullCAN interrupts for each object individually. The new Message Lost flag (MsgLstx) is introduced to indicate whether more than one FullCAN message has been received since last time this message object was read by the CPU. The Interrupt Enable and the Message Lost bits reside in the existing Look-up Table RAM.

16.2.1 FullCAN message interrupt enable bit

In Figure 16–62 8 FullCAN Identifiers with their Source CAN Channel are defined in the FullCAN, Section. The new introduced FullCAN Message Interrupt enable bit can be used to enable for each FullCAN message an Interrupt.

16.2.2 Message lost bit and CAN channel number

Figure 16–63 is the detailed layout structure of one FullCAN message stored in the FullCAN message object section of the Look-up Table. The new message lost bit (MsgLst) is introduced to indicate whether more than one FullCAN message has been received since last time this message object was read. For more information the CAN Source Channel (SCC) of the received FullCAN message is added to Message Object. Fig 62. FullCAN section example of the ID look-up table Index 0, 1 Index 2, 3 Index 4, 5 Index 6, 7 SCC 11-bit CAN ID 1 2 3 4 5 6 7 8 9 0 11 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 0 11-bit CAN ID SCC 0SCC 11-bit CAN ID 0 11-bit CAN ID SCC 0SCC 11-bit CAN ID 0 11-bit CAN ID SCC 0SCC 11-bit CAN ID New: FullCAN Message Interrupt enable bit New: FullCAN Message Interrupt enable bit Fig 63. FullCAN message object layout 31 0 RX Data 4 RX Data 3 RX Data 2 RX Data 1 RX Data 8 RX Data 7 RX Data 6 RX Data 5 9 781516 102324 Msg_ObjAddr + 0 APB Base + F F RX DLC R T R S E M ID.2 ID.1 Msg_ObjAddr + 4 Msg_ObjAddr + 8 S E M New: FullCAN Message lost bit SCC New: CAN Source Channel un- usedunused unused

16.2.3 Setting the interrupt pending bits (IntPnd 63 to 0)

The interrupt pending bit (IntPndx) gets asserted in case of an accepted FullCAN message and if the interrupt of the according FullCAN Object is enabled (enable bit FCANIntxEn) is set). During the last write access from the data storage of a FullCAN message object the interrupt pending bit of a FullCAN object (IntPndx) gets asserted.

16.2.4 Clearing the interrupt pending bits (IntPnd 63 to 0)

Each of the FullCAN Interrupt Pending requests gets cleared when the semaphore bits of a message object are cleared by Software (ARM CPU).

16.2.5 Setting the message lost bit of a FullCAN message object (MsgLost 63 to 0)

The Message Lost bit of a FullCAN message object gets asserted in case of an accepted FullCAN message and when the FullCAN Interrupt of the same object is asserted already. During the first write access from the data storage of a FullCAN message object the Message Lost bit of a FullCAN object (MsgLostx) gets asserted if the interrupt pending bit is set already.

16.2.6 Clearing the message lost bit of a FullCAN message object (MsgLost 63 to

The Message Lost bit of a FullCAN message object gets cleared when the FullCAN Interrupt of the same object is not asserted. During the first write access from the data storage of a FullCAN message object the Message Lost bit of a FullCAN object (MsgLostx) gets cleared if the interrupt pending bit is not set.

16.3 Set and clear mechanis m of the FullCAN interrupt

Special precaution is needed for the built-in set and clear mechanism of the FullCAN Interrupts. The following text illustrates how the already existing Semaphore Bits (see Section 16–16.1 “FullCAN message layout” for more details) and how the new introduced features (IntPndx, MsgLstx) will behave.

16.3.1 Scenario 1: Normal case, no message lost

Figure 16–64 below shows a typical “normal” scenario in which an accepted FullCAN message is stored in the FullCAN Message Object Section. After storage the message is read out by Software (ARM CPU).

16.3.2 Scenario 2: Message lost

In this scenario a first FullCAN Message is stored and read out by Software (1st Object write and read). In a second course a second message is stored (2nd Object write) but not read out before a third message gets stored (3rd Object write). Since the FullCAN Interrupt of that Object (IntPndx) is already asserted, the Message Lost Signal gets asserted. Fig 64. Normal case, no messages lost 01 11 IntPndx semaphore bits look-up table access MsgLostx message handler access ARM processor access read SEM read read clear SEM read SEM write SEM write write Write ID, SEM Fig 65. Message lost 01 11 01 11 1100 1st Object write 2nd Object write 1st Object read 3rd Object write IntPndx semaphore bits look-up table access MsgLostx message handler access ARM processor access read SEM read read clear SEM read SEM write SEM write write write ID, SEM write SEM write write write ID, SEM write SEM write write write ID, SEM

16.3.3 Scenario 3: Message gets overwritten indicated by Semaphore bits

This scenario is a special case in which the lost message is indicated by the existing semaphore bits. The scenario is entered, if during a Software read of a message object another new message gets stored by the message handler. In this case, the FullCAN Interrupt bit gets set for a second time with the 2nd Object write. 16.3.4 Scenario 3.1: Message gets overwritten indicated by Semaphore bits and Message Lost This scenario is a sub-case to Scenario 3 in which the lost message is indicated by the existing semaphore bits and by Message Lost. Fig 66. Message gets overwritten 01 11 01 1100 00 1st Object write 2nd Object write 2nd Object read1st Object read Interrupt Service Routine IntPndx semaphore bits look-up table access MsgLostx message handler access ARM processor access read SEM read read clear SEM read SEM write SEM write write write ID, SEM write SEM write write write ID, SEM read SEM read read clear SEM

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 389 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 16.3.5 Scenario 3.2: Message gets overwritten indicated by Message Lost This scenario is a sub-case to Scenario 3 in which the lost message is indicated by Message Lost. Fig 67. Message overwritten indicated by semaphore bits and message lost 01 11 01 1100 00 1st Object write 2nd Object write 2nd Object read Interrupt Service Routine IntPndx semaphore bits look-up table access MsgLostx message handler access ARM processor access clear SEM write SEM write write write ID, SEM write SEM write write write ID, SEM read SEM read clear SEM read SEM read read SEM read read 1st Object read

16.3.6 Scenario 4: Clearing Message Lost bit

This scenario is a special case in which the lost message bit of an object gets set during an overwrite of a none read message object (2nd Object write). The subsequent read out of that object by Software (1st Object read) clears the pending Interrupt. The 3rd Object write clears the Message Lost bit. Every “write ID, SEM” clears Message Lost bit if no pending Interrupt of that object is set. Fig 68. Message overwritten indicated by message lost IntPndx semaphore bits look-up table access MsgLostx message handler access ARM processor access write SEM write write write ID, SEM 01 11 01 11 00 1st Object write 2nd Object write 1st Object read Interrupt Service Routine 01 11 3rd Object write write SEM write write write ID, SEM write SEM write write write ID, SEM read SEM read read read SEM clear SEM

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 391 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 17. Examples of acceptance filter tables and ID index values

17.1 Example 1: only on e section is used

SFF_sa < ENDofTable OR SFF_GRP_sa < ENDofTable OR EFF_sa < ENDofTable OR EFF_GRP_sa < ENDofTable The start address of a section is lower than the end address of all programmed CAN identifiers.

17.2 Example 2: all sections are used

SFF_sa < SFF_GRP_sa AND SFF_GRP_sa < EFF_sa AND EFF_sa < EFF_GRP_sa AND EFF_GRP_sa < ENDofTable In cases of a section not being used, the start address has to be set onto the value of the next section start address.

17.3 Example 3: more than one but not all sections are used

If the SFF group is not used, the start address of the SFF Group Section (SFF_GRP_sa register) has to be set to the same value of the next section start address, in this case the start address of the Explicit SFF Section (SFF_sa register). Fig 69. Clearing message lost message handler access ARM processor access 01 11 01 11 1100 1st Object write 2nd Object write 1st Object read 3rd Object write write SEM write write write ID, SEM write SEM write write write ID, SEM write SEM write write write ID, SEM read SEM read read read SEM clear SEM IntPndx semaphore bits look-up table access MsgLostx

17.4 Configuration example 4

Identifiers match the entries in that table.

17.5 Configuration example 5

A Standard Individual table starting at the start of Acceptance Filter RAM and containing 26 Identifiers, followed by:
A Standard Group table containing 12 ranges of Identifiers, followed by:
An Extended Individual table containing 3 Identifiers, followed by:
An Extended Group table containing 2 ranges of Identifiers.

Table 356. Example of Acceptance Filter Tables and ID index Values

17.6 Configuration example 6

The Table below shows which sections and therefore which types of CAN identifiers are used and activated. The ID-Look-up Table configuration of this example is shown in Figure 16–71. Fig 70. Detailed example of acceptance filter tables and ID index values SFF_sa 000 d := 000 h := 0 0000 0000 b explicit SFF table lower_boundary 3 4 upper_boundary lower_boundary 3 lower_boundary 3 5 upper_boundary 6 upper_boundary 26 d 22 23 2524 2 6 34 d 35 d 36 d 38 d 39 d lower_boundary 41 upper_boundary lower_boundary 42 upper_boundary 41 d 42 d group SFF tableexplicit EFF tablegroup EFF table SFF_GRP_sa 52 d := 034 h := 0 0011 0100 b EFF_sa 100 d := 064 h := 0 0110 0100 b EFF_GRP_sa 112 d := 070 h := 0 0111 0000 b ENDofTable 128 d := 080 h := 0 1000 0000 b APB base + address 00d = 00h 04d = 04h 44d = 2Ch 48d = 30h 52d = 34h 84d = 54h 88d = 58h 92d = 5Ch 100d = 64h 104d = 68h 112d = 70h 116d = 74h 120d = 78h 124d = 7Ch column_lower column_upper look-up table RAM ID index #

UM10360_1 © NXP B.V. 2010. All rights reserved. disabled CAN Identifiers can be marked by setting the message disable bit. group with the Index 9 of this section is not used and therefore disabled. register value is set to 0x30. Extended Frame Format Identifiers, the ENDofTable register value is set to 0x40. Table 357. Used ID-Look-up Table sections

17.7 Configuration example 7

the FullCAN section first, before it continues with the rest of enabled sections.e disabled. Table 358. Used ID-Look-up Table sections

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 396 of 835 NXP Semiconductors UM10360 Chapter 16: LPC17xx CAN1/2 FullCAN explicit standard frame format identifier section (11-bit CAN ID) The start address of the FullCAN Explicit Standard Frame Format Identifier section is (automatically) set to 0x00. The end of this section is defined in the SFF_sa register. In the FullCAN ID section only identifiers of FullCAN Object are stored for acceptance filtering. In this section two CAN Identifiers with their Source CAN Channels (SCC) share one 32-bit word. Not used or disabled CAN Identifiers can be marked by setting the message disable bit. The FullCAN Object data for each defined identifier can be found in the FullCAN Message Object section. In case of an identifier match during the acceptance filter process, the received FullCAN message object data is moved from the Receive Buffer of the appropriate CAN Controller into the FullCAN Message Object section. To provide memory space for eight FullCAN, Explicit Standard Frame Format identifiers, the SFF_sa register value is set to 0x10. The identifier with the Index 1 of this section is not used and therefore disabled. Explicit standard frame format identifier section (11-bit CAN ID) The start address of the Explicit Standard Frame Format section is defined in the SFF_sa register with the value of 0x10. The end of this section is defined in the End of Table address register (ENDofTable). In the explicit Standard Frame Format section of the ID Look-up Table two CAN Identifiers with their Source CAN Channel (SCC) share one 32-bit word. Not used or disabled CAN Identifiers can be marked by setting the message disable bit. To provide memory space for eight Explicit Standard Frame Format identifiers, the ENDofTable register value is set to 0x20. FullCAN message object data section The start address of the FullCAN Message Object Data section is defined with the ENDofTable register. The number of enabled FullCAN identifiers is limited to the available memory space in the FullCAN Message Object Data section. Each defined FullCAN Message needs three address lines for the Message Data in the FullCAN Message Object Data section. The FullCAN Message Object section is organized in that way, that each Index number of the FullCAN Identifier section corresponds to a Message Object Number in the FullCAN Message Object section.

17.8 Look-up table prog ramming guidelines

All identifier sections of the ID Look-up Table have to be programmed in such a way, that each active section is organized as a sorted list or table with an increasing order of the Source CAN Channel (SCC) together with CAN Identifier in each section. SCC value equals CAN_controller - 1, i.e., SCC = 0 matches CAN1 and SCC = 1 matches CAN2. In cases, where a syntax error in the ID Look-up Table is encountered, the Look-up Table address of the incorrect line is made available in the Look-up Table Error Address Register (LUTerrAd). The reporting process in the Look-up Table Error Address Register (LUTerrAd) is a “run-time” process. Only those address lines with syntax error are reported, which were passed through the acceptance filtering process. The following general rules for programming the Look-up Table apply: Fig 72. ID Look-up table configuration example (FullCAN activated and enabled) 150SCC 0140SCC 0 ... ... FullCAN Explicit Standard Frame Format Identifier Section Explicit Standard Frame Format Identifier Section SFF_sa = 0x10 FF RTR SEM DLC CAN-ID FullCAN Message Object section Section ENDofTable = SFF_GRP_sa = EFF_sa = EFF_GRP_sa = 0x20 RXDATA 4, 3, 2, 1 RXDATA 8, 7, 6, 5 No Message Data, disabled. No Message Data, disabled. No Message Data, disabled. FF RTR SEM DLC CAN-ID RXDATA 4, 3, 2, 1 RXDATA 8, 7, 6, 5 Message Object Data 0 Message Object Data 1 Message Object Data 2 Index FullCAN Interrupt Enable bit FullCAN Interrupt Enable bit 00SCC 0 Disabled, 11SCC 1 20SCC 1 40SCC 1 60SCC 1 30SCC 0 50SCC 0 70SCC 0 120SCC 0 110SCC 0 130SCC 0 100SCC 0 80SCC 0 90SCC 0 Message Disable bit Message Disable bit MSB ID28 MSB ID28 MSB ID28 MSB ID28 MSB ID28 MSB ID28 MSB ID28 MSB ID28 MSB ID28 MSB ID28 MSB ID28 MSB ID28 MSB ID28 MSB ID28 MSB ID28 MSB ID28 LSB ID18 LSB ID18 LSB ID18 LSB ID18 LSB ID18 LSB ID18 LSB ID18 LSB ID18 LSB ID18 LSB ID18 LSB ID18 LSB ID18 LSB ID18 LSB ID18 LSB ID18 LSB ID18

Each section has to be organized as a sorted list or table with an increasing order of the Source CAN Channel (SCC) in conjunction with the CAN Identifier (there is no exception for disabled identifiers).
The upper and lower bound in a Group of Identifiers definition has to be from the same Source CAN Channel.
To disable a Group of Identifiers the message disable bit has to be set for both, the upper and lower bound.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 399 of 835 1. Basic configuration The SPI is configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set bit PCSPI. Remark: On reset, the SPI is enabled (PCSPI = 1). 2. Clock: In the PCLKSEL0 register ( Table 4–40), set bit PCLK_SPI. In master mode, the clock must be an even number greater than or equal to 8 (see Section 17–7.4). 3. Pins: The SPI pins are conf igured using both PINSEL0 (Table 8–78) and PINSEL1 (Table 8–79), as well as the PINMODE (Section 8–4) register. PINSEL0[31:30] is used to configure the SPI CLK pin. PINSEL1[1:0], PINSEL1[3:2] and PINSEL1[5:4] are used to configure the pins SSEL, MISO and MOSI, respectively. 4. Interrupts: The SPI interrupt flag is enabled using the S0SPINT[0] bit (Section 17–7.7). The SPI interrupt flag must be enabled in the NVIC, see Table 6–50. Remark: SSP0 is intended to be used as an alternative for the SPI interface, which is included as a legacy peripheral. Only one of these peripherals can be used at the any one time. 2. Features

Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex Communication.
SPI master or slave.
Maximum data bit rate of one eighth of the peripheral clock rate.
8 to 16 bits per transfer. 3. SPI overview SPI is a full duplex serial interface. It can handle multiple masters and slaves being connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 to 16 bits of data to the slave, and the slave always sends a byte of data to the master. UM10360 Chapter 17: LPC17xx SPI Rev. 01 — 4 January 2010 User manual

UM10360_1 © NXP B.V. 2010. All rights reserved. guaranteed when CPHA = 1 (the signal can remain active). Table 359. SPI pin description inactive state, or tri-stated. simple general purpose I/O under software control. selected, the slave drives the signal high-impedance. device is a slave, serial data is input on this pin.

UM10360_1 © NXP B.V. 2010. All rights reserved. The data and clock phase relationships are summarized in Table 17–360. master or a slave, and the setting of the CPHA variable. begin the transfer. The transfer ends when the last clock cycle of the transfer is complete. the last clock edge where data is sampled. Table 360. SPI Data To Clock Phase Relationship

6.1 General information

There are five control and status registers for the SPI port. They are described in detail in Section 17–7 “Register description” on page 404. The SPI Control Register (S0SPCR) contains a number of programmable bits used to control the function of the SPI block. The settings for this register must be set up prior to a given data transfer taking place. The SPI Status Register (S0SPSR) contains read-only bits that are used to monitor the status of the SPI interface, including normal functions, and exception conditions. The primary purpose of this register is to detect completion of a data transfer. This is indicated by the SPI Interrupt Flag (SPIF) in the S0SPINT register. The remaining bits in the register are exception condition indicators. These exceptions will be described later in this section. The SPI Data Register (S0SPDR) is used to provide the transmit and receive data bytes. An internal shift register in the SPI block logic is used for the actual transmission and reception of the serial data. Data is written to the SPI Data Register for the transmit case. There is no buffer between the data register and the internal shift register. A write to the data register goes directly into the internal shift register. Therefore, data should only be written to this register when a transmit is not currently in progress. Read data is buffered. When a transfer is complete, the receive data is transferred to a single byte data buffer, where it is later read. A read of the SPI Data Register returns the value of the read data buffer. The SPI Clock Counter Register (S0SPCCR) controls the clock rate when the SPI block is in master mode. This needs to be set prior to a transfer taking place, when the SPI block is a master. This register has no function when the SPI block is a slave. Prior to use, SPI configurations such as the master/slave settings, clock polarity, clock rate, etc. must be set up in the SPI Control Register and SPI Clock Counter Register. The I/Os for this implementation of SPI are standard CMOS I/Os. The open drain SPI option is not implemented in this design. When a device is set up to be a slave, its I/Os are only active when it is selected by the SSEL signal being active.

6.2 Master operation

The following sequence can be followed to set up the SPI prior to its first use as a master. This is typically done during program initialization. 1. Set the SPI Clock Counter Register to the desired clock rate. 2. Set the SPI Control Register to the desired settings for master mode. The following sequence describes how one should process a data transfer with the SPI block when it is set up to be the master. This process assumes that any prior data transfer has already completed. 1. Optionally, verify the SPI setup before starting the transfer. 2. Write the data to transmitted to the SPI Da ta Register. This write starts the SPI data transfer.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 403 of 835 NXP Semiconductors UM10360 Chapter 17: LPC17xx SPI 3. Wait for the SPIF bit in the SPI Status Regi ster to be set to 1. The SPIF bit will be set after the last cycle of the SPI data transfer. 4. Read the SPI Status Register. 5. Read the received data from the SPI Data Register (optional). 6. Go to step 2 if more data is to be transmitted. Note: A read or write of the SPI Data Register is required in order to clear the SPIF status bit. Therefore, if the optional read of the SPI Data Register does not take place, a write to this register is required in order to clear the SPIF status bit.

6.3 Slave operation

The following sequence can be followed to set up the SPI prior to its first use as a slave. This is typically done during program initialization. 1. Set the SPI Control Register to the desired settings for slave mode. The following sequence describes how one should process a data transfer with the SPI block when it is set up to be a slave. This process assumes that any prior data transfer has already completed. It is required that the system clock driving the SPI logic be at least 8X faster than the SPI. 1. Optionally, verify the SPI setup before starting the transfer. 2. Write the data to transmitted to the SPI Da ta Register (optional). Note that this can only be done when a slave SPI transfer is not in progress. 3. Wait for the SPIF bit in the SPI Status Regi ster to be set to 1. The SPIF bit will be set after the last sampling clock edge of the SPI data transfer. 4. Read the SPI Status Register. 5. Read the received data from the SPI Data Register (optional). 6. Go to step 2 if more da ta is to be transferred. Note: A read or write of the SPI Data Register is required in order to clear the SPIF status bit. Therefore, at least one of the optional reads or writes of the SPI Data Register must take place, in order to clear the SPIF status bit.

6.4 Exception conditions

A read overrun occurs when the SPI block internal read buffer contains data that has not been read by the processor, and a new transfer has completed. The read buffer containing valid data is indicated by the SPIF bit in the SPI Interrupt Register being active. When a transfer completes, the SPI block needs to move the received data to the read buffer. If the SPIF bit is active (the read buffer is full), the new receive data will be lost, and the read overrun (ROVR) bit in the SPI Status Register will be activated. Write Collision As stated previously, there is no write buffer between the SPI block bus interface, and the internal shift register. As a result, data must not be written to the SPI Data Register when a SPI data transfer is currently in progress. The time frame where data cannot be written to the SPI Data Register is from when the transfer starts, until after the SPI Status

UM10360_1 © NXP B.V. 2010. All rights reserved. Status Register will be activated. master has selected the device to be a slave. This condition is known as a mode fault. Register, the SSEL signal must always be inactive when the SPI controller is a master. [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

7.1 SPI Control Regist er (S0SPCR - 0x4002 0000)

Table 361. SPI register map can be read from this register. controls the frequency of a master’s SCK0. interrupt flag for the SPI interface.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 405 of 835 NXP Semiconductors UM10360 Chapter 17: LPC17xx SPI Table 362: SPI Control Register (S0SP CR - address 0x4002 0000) bit description Bit Symbol Value Description Reset Value 1:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

2 BitEnable 0 The SPI controller sends and receives 8 bits of data per

transfer.

1 The SPI controller sends and receives the number of bits

selected by bits 11:8.

3 CPHA Clock phase control determines the relationship between the

data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending. 0 Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal. 1 Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active. 4 CPOL Clock polarity control. 0 0 SCK is active high. 1 SCK is active low. 5 MSTR Master mode select. 0 0 The SPI operates in Slave mode. 1 The SPI operates in Master mode.

6 LSBF LSB First controls which direction each byte is shifted when

transferred. 0 SPI data is transferred MSB (bit 7) first. 1 SPI data is transferred LSB (bit 0) first. 7 SPIE Serial peripheral interrupt enable. 0 0 SPI interrupts are inhibited.

1 A hardware interrupt is generated each time the SPIF or MODF

bits are activated. 11:8 BITS When bit 2 of this register is 1, this field controls the number of bits per transfer: 0000 1000 8 bits per transfer 1001 9 bits per transfer 1010 10 bits per transfer 1011 11 bits per transfer 1100 12 bits per transfer 1101 13 bits per transfer 1110 14 bits per transfer 1111 15 bits per transfer 0000 16 bits per transfer 31:12 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

7.2 SPI Status Regist er (S0SPSR - 0x4002 0004)

The S0SPSR register controls the operation of SPI0 as per the configuration bits setting shown in Table 17–363.

7.3 SPI Data Regist er (S0SPDR - 0x4002 0008)

This bi-directional data register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI by writing to this register. Data received by the SPI can be read from this register. When used as a master, a write to this register will start an SPI data transfer. Writes to this register will be blocked when a data transfer starts, or when the SPIF status bit is set, and the SPI Status Register has not been read.

7.4 SPI Clock Counter Regi ster (S0SPCCR - 0x4002 000C)

This register controls the frequency of a master’s SCK. The register indicates the number of SPI peripheral clock cycles that make up an SPI clock. Table 363: SPI Status Register (S0SPSR - address 0x4002 0004) bit description Bit Symbol Description Reset Value 2:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 3 ABRT Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register. 4 MODF Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register. 5 ROVR Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register. 6 WCOL Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register. 7 SPIF SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register. 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 364: SPI Data Register (S0SPDR - address 0x4002 0008) bit description Bit Symbol Description Reset Value 7:0 DataLow SPI Bi-directional data port. 0x00 15:8 DataHigh If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes. 0x00 31:16 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 407 of 835 NXP Semiconductors UM10360 Chapter 17: LPC17xx SPI In Master mode, this register must be an even number greater than or equal to 8. Violations of this can result in unpredictable behavior. The SPI0 SCK rate may be calculated as: PCLK_SPI / SPCCR0 value. The SPI peripheral clock is determined by the PCLKSEL0 register contents for PCLK_SPI as described in Section 4–7.3 In Slave mode, the SPI clock rate provided by the master must not exceed 1/8 of the SPI peripheral clock selected in Section 4–7.3. The content of the S0SPCCR register is not relevant.

7.5 SPI Test Control Register (SPTCR - 0x4002 0010)

Note that the bits in this register are intended for functional verification only. This register should not be used for normal operation.

7.6 SPI Test Status Regi ster (SPTSR - 0x4002 0014)

Note: The bits in this register are intended for functional verification only. This register should not be used for normal operation. This register is a replication of the SPI Status Register. The difference between the registers is that a read of this register will not start the sequence of events required to clear these status bits. A write to this register will set an interrupt if the write data for the respective bit is a 1. Table 365: SPI Clock Counter Register (S0 SPCCR - address 0x4002 000C) bit description Bit Symbol Description Reset Value 7:0 Counter SPI0 Clock counter setting. 0x00 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 366: SPI Test Control Register (SPTCR - address 0x4002 0010) bit description Bit Symbol Description Reset Value 0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 7:1 Test SPI test mode. When 0, the SPI operates normally. When 1, SCK will always be on, independent of master mode select, and data availability setting. 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 367: SPI Test Status Register (SPTSR - address 0x4002 0014) bit description Bit Symbol Description Reset Value 2:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 3 ABRT Slave abort. 0 4 MODF Mode fault. 0 5 ROVR Read overrun. 0

7.7 SPI Interrupt Regist er (S0SPINT - 0x4002 001C)

This register contains the interrupt flag for the SPI0 interface. 6 WCOL Write collision. 0 7 SPIF SPI transfer complete flag. 0 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 367: SPI Test Status Register (SPTSR - address 0x4002 0014) bit description Bit Symbol Description Reset Value Table 368: SPI Interrupt Register (S0SPI NT - address 0x4002 001C) bit description Bit Symbol Description Reset Value 0 SPIF SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software. 7:1 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 409 of 835 NXP Semiconductors UM10360 Chapter 17: LPC17xx SPI 8. Architecture The block diagram of the SPI solution implemented in SPI0 interface is shown in the Figure 17–74. Fig 74. SPI block diagram MOSI_IN MOSI_OUT MISO_IN MISO_OUT OUTPUT ENABLE LOGIC SPI REGISTER INTERFACE SPI Interrupt APB Bus SPI SHIFT REGISTER SCK_OUT_EN MOSI_OUT_EN MISO_OUT_EN SCK_IN SCK_OUT SS_IN SPI STATE CONTROL SPI CLOCK GENERATOR & DETECTOR

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 410 of 835 1. Basic configuration The two SSP interfaces, SSP0 and SSP1 are configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set bit PCSSP0 to enable SSP0 and bit PCSSP1 to enable SSP1. Remark: On reset, both SSP interfaces are enabled (PCSSP0/1 = 1). 2. Clock: In PCLKSEL0 sele ct PCLK_SSP1; in PCLKSEL1 select PCLK_SSP0 (see Section 4–7.3. In master mode, the clock must be scaled down (see Section 18–6.5). 3. Pins: Select the SSP pins th rough the PINSEL registers (Section 8–5) and pin modes through the PINMODE registers (Section 8–4). 4. Interrupts: Interrupts ar e enabled in the SSP0IMSC register for SSP0 and SSP1IMSC register for SSP1 Table 18–376. Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register, see Table 6–50. 5. Initialization: There are two control r egisters for each of the SSP ports to be configured: SSP0CR0 and SSP0CR1 for SSP0, SSP1CR0 and SSP1CR1 for SSP1. See Section 18–6.1 and Section 18–6.2. 6. DMA: The Rx and Tx FIFOs of the SSP in terfaces can be connected to the GPDMA controller (see Section 18–6.10). For GPDMA system connections, see Table 31–544. Remark: SSP0 is intended to be used as an alternative for the SPI interface, which is included as a legacy peripheral. Only one of these peripherals can be used at the any one time. 2. Features

Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire buses.
Synchronous Serial Communication.
Master or slave operation.
8 frame FIFOs for both transmit and receive.
4 to 16 bit data frame.
DMA transfers supported by GPDMA. 3. Description The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. Data transfers are in principle full duplex, with frames of 4 to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice it is often the case that only one of these data flows carries meaningful data. UM10360 Chapter 18: LPC17xx SSP0/1 interface Rev. 01 — 4 January 2010 User manual

5.1 Texas Instruments sync hronous serial frame format

supported by the SSP module. Table 369. SSP pi n descriptions otherwise it is always active-high. SCK1 only switches during a data transfer. not drive it (leaves it in high-impedance state). data from the Master, according to the protocol in use. necessary to prevent more than one slave from responding to a transfer. the master. When the SSPn is a slave, serial data is output on this signal. (leaves it in high-impedance state). to the slave. When the SSPn is a master, it outputs serial data on this signal. When the SSPn is a slave, it clocks in serial data from this signal.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 412 of 835 NXP Semiconductors UM10360 Chapter 18: LPC17xx SSP0/1 interface For device configured as a master in this mode, CLK and FS are forced LOW, and the transmit data line DX is tri-stated whenever the SSP is idle. Once the bottom entry of the transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR pin by the off-chip serial slave device. Both the SSP and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each CLK. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.

5.2 SPI frame format

The SPI interface is a four-wire interface where the SSEL signal behaves as a slave select. The main feature of the SPI format is that the inactive state and phase of the SCK signal are programmable through the CPOL and CPHA bits within the SSPCR0 control register.

5.2.1 Clock Polarity (CPOL) and Phase (CPHA) control

When the CPOL clock polarity control bit is 0, it produces a steady state low value on the SCK pin. If the CPOL clock polarity control bit is 1, a steady state high value is placed on the CLK pin when data is not being transferred. a. Single frame transfer b. Continuous/back-to-back frames transfer Fig 75. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two Frames Transfer CLK FS DX/DR 4 to 16 bits MSB LSB CLK FS DX/DR LSBMSB LSBMSB 4 to 16 bits 4 to 16 bits

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 413 of 835 NXP Semiconductors UM10360 Chapter 18: LPC17xx SSP0/1 interface The CPHA control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the CPHA phase control bit is 0, data is captured on the first clock edge transition. If the CPHA clock phase control bit is 1, data is captured on the second clock edge transition.

5.2.2 SPI format with CPOL=0,CPHA=0

Single and continuous transmission signal sequences for SPI format with CPOL = 0, CPHA = 0 are shown in Figure 18–76 In this configuration, during idle periods:

The CLK signal is forced LOW.
SSEL is forced HIGH.
The transmit MOSI/MISO pad is in high impedance. If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW. This causes slave data to be enabled onto the MISO input line of the master. Master’s MOSI is enabled. One half SCK period later, valid master data is transferred to the MOSI pin. Now that both the master and slave data have been set, the SCK master clock pin goes HIGH after one further half SCK period. The data is now captured on the rising and propagated on the falling edges of the SCK signal. a. Single transfer with CPOL=0 and CPHA=0 b. Continuous transfer with CPOL=0 and CPHA=0 Fig 76. SPI frame format with CPOL=0 and CPHA=0 (a) Single and b) Continuous Transfer) SCK SSEL MOSI MSB LSB QMSB LSB 4 to 16 bits MISO SCK SSEL MOSI MISO 4 to 16 bits 4 to 16 bits MSB LSBMSB LSB QMSB LSB QMSB LSB

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 414 of 835 NXP Semiconductors UM10360 Chapter 18: LPC17xx SSP0/1 interface In the case of a single word transmission, after all bits of the data word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSEL signal must be pulsed HIGH between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK period after the last bit has been captured.

5.2.3 SPI format with CPOL=0,CPHA=1

The transfer signal sequence for SPI format with CPOL = 0, CPHA = 1 is shown in Figure 18–77, which covers both single and continuous transfers. In this configuration, during idle periods:

The CLK signal is forced LOW.
SSEL is forced HIGH.
The transmit MOSI/MISO pad is in high impedance. If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI pin is enabled. After a further one half SCK period, both master and slave valid data is enabled onto their respective transmission lines. At the same time, the SCK is enabled with a rising edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SCK signal. In the case of a single word transfer, after all bits have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured. For continuous back-to-back transfers, the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer.

5.2.4 SPI format with CPOL = 1,CPHA = 0

Single and continuous transmission signal sequences for SPI format with CPOL=1, CPHA=0 are shown in Figure 18–78. Fig 77. SPI frame format with CPOL=0 and CPHA=1 SCK SSEL MOSI Q 4 to 16 bits MISO Q MSB MSB LSB LSB

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 415 of 835 NXP Semiconductors UM10360 Chapter 18: LPC17xx SSP0/1 interface In this configuration, during idle periods:

The CLK signal is forced HIGH.
SSEL is forced HIGH.
The transmit MOSI/MISO pad is in high impedance. If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW, which causes slave data to be immediately transferred onto the MISO line of the master. Master’s MOSI pin is enabled. One half period later, valid master data is transferred to the MOSI line. Now that both the master and slave data have been set, the SCK master clock pin becomes LOW after one further half SCK period. This means that data is captured on the falling edges and be propagated on the rising edges of the SCK signal. In the case of a single word transmission, after all bits of the data word are transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSEL signal must be pulsed HIGH between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK period after the last bit has been captured. a. Single transfer with CPOL=1 and CPHA=0 b. Continuous transfer with CPOL=1 and CPHA=0 Fig 78. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer) SCK SSEL QMSB LSB 4 to 16 bits MISO MOSI MSB LSB SCK SSEL MOSI MISO 4 to 16 bits 4 to 16 bits MSB LSBMSB LSB QMSB LSB QMSB LSB

5.2.5 SPI format with CPOL = 1,CPHA = 1

The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in Figure 18–79, which covers both single and continuous transfers. In this configuration, during idle periods:

The CLK signal is forced HIGH.
SSEL is forced HIGH.
The transmit MOSI/MISO pad is in high impedance. If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI is enabled. After a further one half SCK period, both master and slave data are enabled onto their respective transmission lines. At the same time, the SCK is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SCK signal. After all bits have been transferred, in the case of a single word transmission, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured. For continuous back-to-back transmissions, the SSEL pins remains in its active LOW state, until the final bit of the last word has been captured, and then returns to its idle state as described above. In general, for continuous back-to-back transfers the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer.

5.3 National Semiconductor Microwire frame format

Figure 18–80 shows the Microwire frame format for a single frame. Figure 18–81 shows the same format when back-to-back frames are transmitted. Fig 79. SPI Frame Format with CPOL = 1 and CPHA = 1 SCK SSEL MOSI Q 4 to 16 bits MISO Q MSB MSB LSB LSB

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 417 of 835 NXP Semiconductors UM10360 Chapter 18: LPC17xx SSP0/1 interface Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSP to the off-chip slave device. During this transmission, no incoming data is received by the SSP . After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. In this configuration, during idle periods:

The SK signal is forced LOW.
CS is forced HIGH.
The transmit data line SO is arbitrarily forced LOW. A transmission is triggered by writing a control byte to the transmit FIFO.The falling edge of CS causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SO pin. CS remains LOW for the duration of the frame transmission. The SI pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SK. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSP. Each bit is driven onto SI line on the falling edge of SK. The SSP in turn latches each bit on the rising edge of SK. At the end of the frame, for single transfers, the CS signal is pulled HIGH one clock period after the last bit has been latched in the receive serial shifter, that causes the data to be transferred to the receive FIFO. Note: The off-chip slave device can tristate the receive line either on the falling edge of SK after the LSB has been latched by the receive shiftier, or when the CS pin goes HIGH. For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the CS line is continuously asserted (held LOW) and transmission of data occurs back to back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge SK, after the LSB of the frame has been latched into the SSP . Fig 80. Microwire frame fo rmat (single transfer) SK CS SO 4 to 16 bits output data SI 8-bit control MSB LSB

0 MSB LSB

5.3.1 Setup and hold time requirements on CS with respect to SK in Microwire

In the Microwire mode, the SSP slave samples the first bit of receive data on the rising edge of SK after CS has gone LOW. Masters that drive a free-running SK must ensure that the CS signal has sufficient setup and hold margins with respect to the rising edge of SK. Figure 18–82 illustrates these setup and hold time requirements. With respect to the SK rising edge on which the first bit of receive data is to be sampled by the SSP slave, CS must have a setup of at least two times the period of SK on which the SSP operates. With respect to the SK rising edge previous to this edge, CS must have a hold of at least one SK period. Fig 81. Microwire frame forma t (continuos transfers) SK CS SO SI MSB LSB 4 to 16 bits output data 8-bit control 4 to 16 bits output data MSB LSB0 MSB LSB LSB Fig 82. Microwire frame format setup and hold details SK CS SI tHOLD= tSK tSETUP=2*tSK

UM10360_1 © NXP B.V. 2010. All rights reserved. The register addresses of the SSP controllers addresses are shown in Table 18–370. [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

6.1 SSPn Control Register 0 (SSP0 CR0 - 0x4008 8000, SSP1CR0 - 0x4003

This register controls the basic operation of the SSP controller. Table 370. SSP Re gister Map master/slave and other modes.

6.2 SSPn Control Register 1 (S SP0CR1 - 0x4008 8004, SSP1CR1 -

0x4003 0004) This register controls certain aspects of the operation of the SSP controller. Table 371: SSPn Control Register 0 (SSP0CR0 - address 0x4008 8000, SSP1CR0 - 0x4003 0000) bit description Bit Symbol Value Description Reset Value 3:0 DSS Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. 0000 0011 4-bit transfer 0100 5-bit transfer 0101 6-bit transfer 0110 7-bit transfer 0111 8-bit transfer 1000 9-bit transfer 1001 10-bit transfer 1010 11-bit transfer 1011 12-bit transfer 1100 13-bit transfer 1101 14-bit transfer 1110 15-bit transfer 1111 16-bit transfer 5:4 FRF Frame Format. 00

00 SPI

10 Microwire

11 This combination is not supported and should not be used. 6 CPOL Clock Out Polarity. This bit is only used in SPI mode. 0 0 SSP controller maintains the bus clock low between frames. 1 SSP controller maintains the bus clock high between frames. 7 CPHA Clock Out Phase. This bit is only used in SPI mode. 0

0 SSP controller captures serial data on the first clock transition of

the frame, that is, the transition away from the inter-frame state of the clock line.

1 SSP controller captures serial data on the second clock transition

of the frame, that is, the transition back to the inter-frame state of the clock line. 15:8 SCR Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR × [SCR+1]). 0x00 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

6.3 SSPn Data Register (SSP0 DR - 0x4008 8008, SSP1DR - 0x4003 0008)

Software can write data to be transmitted to this register, and read data that has been received. Table 372: SSPn Control Register 1 (SSP0CR1 - address 0x4008 8004, SSP1CR1 - 0x4003 0004) bit description Bit Symbol Value Description Reset Value 0 LBM Loop Back Mode. 0 0 During normal operation.

1 Serial input is taken from the serial output (MOSI or MISO) rather

than the serial input pin (MISO or MOSI respectively). 1 SSE SSP Enable. 0 0 The SSP controller is disabled.

1 The SSP controller will interact with other devices on the serial

bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit. 2 MS Master/Slave Mode.This bit can only be written when the SSE bit is 0.

0 The SSP controller acts as a master on the bus, driving the

SCLK, MOSI, and SSEL lines and receiving the MISO line.

1 The SSP controller acts as a slav e on the bus, driving MISO line

and receiving SCLK, MOSI, and SSEL lines. 3 SOD Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). 31:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 373: SSPn Data Register (SSP0DR - address 0x4008 8008, SSP1DR - 0x4003 0008) bit Bit Symbol Description Reset Value 15:0 DATA Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s. 0x0000 31:16 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

6.4 SSPn Status Register (S SP0SR - 0x4008 800C, SSP1SR -

0x4003 000C) This read-only register reflects the current status of the SSP controller.

6.5 SSPn Clock Prescale Register (SSP0CPSR - 0x4008 8010, SSP1CPSR

0x4003 0010) This register controls the factor by which the Prescaler divides the SSP peripheral clock SSP_PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in SSPnCR0, to determine the bit clock. Important: the SSPnCPSR value must be properly initialized or the SSP controller will not be able to transmit data correctly. In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the SSP peripheral clock selected in Section 4–7.3. The content of the SSPnCPSR register is not relevant. In master mode, CPSDVSR min = 2 or larger (even numbers only).

6.6 SSPn Interrupt Mask Set/Clear Register (SSP0IMSC - 0x4008 8014,

SSP1IMSC - 0x4003 0014) This register controls whether each of the four possible interrupt conditions in the SSP controller are enabled. Note that ARM uses the word “masked” in the opposite sense from classic computer terminology, in which “masked” meant “disabled”. ARM uses the word “masked” to mean “enabled”. To avoid confusion we will not use the word “masked”. Table 374: SSPn Status Register (SSP0SR - address 0x4008 800C, SSP1SR - 0x4003 000C) bit description Bit Symbol Description Reset Value 0 TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. 1 1 TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1 2 RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. 3 RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. 0 4 BSY Busy. This bit is 0 if the SSPn contro ller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. 31:5 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NATable 375: SSPn Clock Prescale Register (SSP0CPSR - address 0x4008 8010, SSP1CPSR - 0x4003 0010) bit description Bit Symbol Description Reset Value 7:0 CPSDVSR This even value between 2 and 254, by which SSP_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

6.7 SSPn Raw Interrupt Status Re gister (SSP0RIS - 0x4008 8018,

SSP1RIS - 0x4003 0018) This read-only register contains a 1 for each interrupt condition that is asserted, regardless of whether or not the interrupt is enabled in the SSPnIMSC.

6.8 SSPn Masked Interrupt Status Register (SSP0MIS - 0x4008 801C,

SSP1MIS - 0x4003 001C) This read-only register contains a 1 for each interrupt condition that is asserted and enabled in the SSPnIMSC. When an SSP interrupt occurs, the interrupt service routine should read this register to determine the cause(s) of the interrupt. Table 376: SSPn Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4008 8014, SSP1IMSC - 0x4003 0014) bit description Bit Symbol Description Reset Value

0 RORIM Software should set this bit to enable interrupt when a Receive Overrun

occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.

1 RTIM Software should set this bit to enable interrupt when a Receive Timeout

condition occurs. A Receive Timeout occurs when the Rx FIFO is not empty, and no has not been read for a "timeout period".

2 RXIM Software should set this bit to enable interrupt when the Rx FIFO is at

least half full.

3 TXIM Software should set this bit to enable interrupt when the Tx FIFO is at

least half empty. 31:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 377: SSPn Raw Interrupt Status register (SSP0RIS - address 0x4008 8018, SSP1RIS - 0x4003 0018) bit description Bit Symbol Description Reset Value

0 RORRIS This bit is 1 if another frame was completely received while the RxFIFO

was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.

1 RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a

"timeout period". 2 RXRIS This bit is 1 if the Rx FIFO is at least half full. 0 3 TXRIS This bit is 1 if the Tx FIFO is at least half empty. 1 31:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

6.9 SSPn Interrupt Clear Register (SSP0ICR - 0x4008 8020, SSP1ICR -

0x4003 0020) Software can write one or more one(s) to this write-only register, to clear the corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt conditions can be cleared by writing or reading the appropriate FIFO, or disabled by clearing the corresponding bit in SSPnIMSC.

6.10 SSPn DMA Control Regi ster (SSP0DMACR - 0x4008 8024,

SSP1DMACR - 0x4003 0024) The SSPnDMACR register is the DMA control register. It is a read/write register. Table 378: SSPn Masked Interrupt Status register (SSPnMIS -address 0x4008 801C, SSP1MIS - 0x4003 001C) bit description Bit Symbol Description Reset Value

0 RORMIS This bit is 1 if another frame was completely received while the RxFIFO

was full, and this interrupt is enabled.

1 RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a

"timeout period", and this interrupt is enabled.

2 RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is

enabled.

3 TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is

enabled. 31:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 379: SSPn interrupt Clear Register (SSP0ICR - address 0x4008 8020, SSP1ICR - 0x4003 0020) bit description Bit Symbol Description Reset Value

0 RORIC Writing a 1 to this bit clears the “frame was received when RxFIFO was

full” interrupt. NA

1 RTIC Writing a 1 to this bit clears the "Rx FIFO was not empty and has not

been read for a timeout period" interrupt. NA 31:2 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 380: SSPn DMA Control Register (SSP0DMACR - address 0x4008 8024, SSP1DMACR - 0x4003 0024) bit description Bit Symbol Description Reset Value

0 Receive DMA Enable

(RXDMAE) When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled.

1 Transmit DMA Enable

(TXDMAE) When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled 31:2 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 425 of 835 1. Basic configuration The I2C0/1/2 interfaces are configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set bit PCI2C0/1/2. Remark: On reset, all I2C interfaces are enabled (PCI2C0/1/2 = 1). 2. Clock: In PCLKSEL0 sele ct PCLK_I2C0; in PCLKSEL1 select PCLK_I2C1 or PCLK_I2C2 (see Section 4–7.3). 3. Pins: Select I 2C0, I2C1, or I2C2 pins through the PINSEL registers. Select the pin modes for the port pins with I2C1 or I2C2 functions through the PINMODE registers (no pull-up, no pull-down resistors) and the PINMODE_OD registers (open drain) (See Section 8–5). Remark: I2C0 pins SDA0 and SCL0 are open-drain outputs and fully I2C-bus compliant (see Table 7–72). I2C0 can be further configured through the I2CPADCFG register to support Fast Mode Plus (See Table 8–98). Remark: I2C0 is not available in the 80-pin package. Remark: I2C1 and I2C2 pins are not fully I2C-bus compliant open-drain pins but can be configured to be open-drain via the PINMODE and PINMODE_OD registers. The non-compliance is in the I2C-bus ability to turn off power to the device without pulling down the I2C-bus itself. 4. Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 2. Features

Standard I2C compliant bus interfaces may be configured as Master, Slave, or Master/Slave.
Arbitration is handled between simultaneously transmitting masters without corruption of serial data on the bus.
Programmable clock allows adjustment of I2C transfer rates.
Data transfer is bidirectional between masters and slaves.
Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.
Serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer.
Supports Fast Mode Plus (I2C0 only).
Optional recognition of up to 4 distinct slave addresses.
Monitor mode allows observing all I2C-bus traffic, regardless of slave address, without affecting the actual I2C-bus traffic.
The I2C-bus can be used for test and diagnostic purposes. UM10360 Chapter 19: LPC17xx I2C0/1/2 interface Rev. 01 — 4 January 2010 User manual

I2C0 is a standard I2C compliant bus interface with open-drain pins. This interface supports functions described in the I2C specification for speeds up to 1 MHz. This includes multi-master operation and allows powering off this device in a working system while leaving the I2C-bus functional.
I2C1 and I2C2 use standard I/O pins and are intended for use with a single-master I2C-bus and do not support powering off of this device while leaving the I2C-bus functional, and do not support multi-master I2C implementations. 3. Applications Interfaces to external I2C standard parts, such as serial RAMs, LCDs, tone generators, other microcontrollers, etc. 4. Description A typical I2C-bus configuration is shown in Figure 19–83. Depending on the state of the direction bit (R/W), two types of data transfers are possible on the I2C-bus:
Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte, unless the slave device is unable to accept more data.
Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I 2C-bus will not be released. The LPC17xx I2C interfaces are byte oriented and have four operating modes: master transmitter mode, master receiver mode, slave transmitter mode and slave receiver mode. I2C0 complies with the entire I2C specification, supporting the ability to have the LPC17xx powered off and not interfere with other powered devices on the same I2C-bus. I2C1 and I2C2 do not support the ability to have the power to the LPC17xx turned off without interfering with other powered devices on the same I2C-bus. Since I2C1 and I2C2 use standard port pins, internal pull-ups could (in theory) be enabled in order to pull I2C-bus signals high when they are not driven low. However, these internal pull-ups are far weaker than what would normally be used for I2C, so this practice is not recommended. Refer to the “I2C-bus specification and user manual” for information on proper pull-up values for a specific case.

4.1 I 2C FAST Mode Plus

the NXP Semiconductors is now providing. with I2C specifications. The pins must be configured in the I2CPADCFG register for Fast Mode Plus. Table 381. I 2C Pin Description

6.1 Master Transmitter mode

transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. writing a 1 to the SIC bit in the I2CONCLR register. Table 382. I2C0CONSET and I2C1CONSET used to configure Master mode

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 429 of 835 NXP Semiconductors UM10360 Chapter 19: LPC17xx I2C0/1/2 interface When the slave address and R/W bit have been transmitted and an acknowledgment bit has been received, the SI bit is set again, and the possible status codes now are 0x18, 0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xB0 if the slave mode was enabled (by setting AA to 1). The appropriate actions to be taken for each of these status codes are shown in Table 19–399 to Table 19–402.

6.2 Master Receiver mode

In the master receiver mode, data is received from a slave transmitter. The transfer is initiated in the same way as in the master transmitter mode. When the START condition has been transmitted, the interrupt service routine must load the slave address and the data direction bit to the I2C Data register (I2DAT), and then clear the SI bit. In this case, the data direction bit (R/W) should be 1 to indicate a read. When the slave address and data direction bit have been transmitted and an acknowledge bit has been received, the SI bit is set, and the Status Register will show the status code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. For slave mode, the possible status codes are 0x68, 0x78, or 0xB0. For details, refer to Table 19–400. When the LPC17xx needs to acknowledge a received byte, the AA bit needs to be set accordingly prior to clearing the SI bit and initiating the byte read. When the LPC17xx needs to not acknowledge a received byte, the AA bit needs to be cleared prior to clearing the SI bit and initiating the byte read. Note that the last received byte is always followed by a "Not Acknowledge" from the LPC17xx so that the master can signal the slave that the reading sequence is finished and that it needs to issue a STOP or repeated START Command. Once the "Not Acknowledge has been sent and the SI bit is set, the LPC17xx can send either a STOP (STO bit is set) or a repeated START (STA bit is set). Then the SI bit is cleared to initiate the requested operation. Fig 84. Format in the Ma ster Transmitter mode A = Acknowledge (SDA low) A = Not acknowledge (SDA high) S = START condition P = STOP condition S SLAVE ADDRESS RW=0 A DATA A A/A P from Master to Slave from Slave to Master DATA n bytes data transmitted

6.3 Slave Receiver mode

Table 383. I2C0CONSET and I2C1CONSET used to configure Slave mode

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 431 of 835 NXP Semiconductors UM10360 Chapter 19: LPC17xx I2C0/1/2 interface enters slave transmitter mode. After the address and direction bit have been received, the SI bit is set and a valid status code can be read from the Status register (I2STAT). Refer to Table 19–401 for the status codes and actions.

6.4 Slave Transmitter mode

The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via SDA while the serial clock is input through SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. In a given application, I2C may operate as a master and as a slave. In the slave mode, the I2C hardware looks for any of its own slave addresses and the General Call address. If one of these addresses is detected, an interrupt is requested. When the microcontrollers wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the master mode, the I2C interface switches to the slave mode immediately and can detect any of its own slave addresses in the same serial transfer. 7. I 2C implementation and operation Figure 19–89 shows how the on-chip I2C-bus interface is implemented, and the following text describes the individual blocks. Fig 87. Format of Slave Receiver mode A A = Acknowledge (SDA low) A = Not acknowledge (SDA high) S = START condition P = STOP condition Sr = Repeated START condition A A/A n bytes data received from Master to Slave from Slave to Master S SLAVE ADDRESS RW=0 DATA P/SrDATA Fig 88. Format of Slave Transmitter mode DATA A = Acknowledge (SDA low) A = Not acknowledge (SDA high) S = START condition P = STOP condition A DATA n bytes data transmitted from Master to Slave from Slave to Master S SLAVE ADDRESS RW=1 A PA

7.1 Input filters and output stages

Input signals are synchronized with the internal clock, and spikes shorter than three clocks are filtered out. The output for I2C is a special pad designed to conform to the I2C specification. Fig 89. I 2C serial interface block diagram APB BUS STATUS REGISTER I2CnSTAT CONTROL REGISTER and SCL DUTY CYLE REGISTERS I2CnCONSET, I2CnCONCLR, I2CnSCLH, I2CnSCLL ADDRESS REGISTERS MASK and COMPARE SHIFT REGISTER I2CnDAT ACK BIT COUNTER/ ARBITRATION and MONITOR MODE REGISTER I2CnMMCTRL SYNC LOGIC SERIAL CLOCK GENERATOR TIMING and CONTROL LOGIC STATUS DECODER status bus interrupt PCLKINPUT FILTER OUTPUT STAGE SCL INPUT FILTER OUTPUT STAGE SDA I2CnADDR0 to I2CnADDR3 MASK REGISTERS I2CnMASK0 to I2CnMASK3 I2CnDATABUFFER MATCHALL I2CnMMCTRL[3]

7.2 Address Registers, I2ADR0 to I2ADR3

These registers may be loaded with the 7-bit slave address (7 most significant bits) to which the I2C block will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable General Call address (0x00) recognition. When multiple slave addresses are enabled, the actual address received may be read from the I2DAT register at the state where the “own slave address” has just been received. Remark: in the remainder of this chapter, when the phrase “own slave address” is used, it refers to any of the four configured slave addresses after address masking.

7.3 Address mask registers, I2MASK0 to I2MASK3

The four mask registers each contain seven active bits (7:1). Any bit in these registers which is set to ‘1’ will cause an automatic compare on the corresponding bit of the received address when it is compared to the I2ADRn register associated with that mask register. In other words, bits in an I2ADRn register which are masked are not taken into account in determining an address match. When an address-match interrupt occurs, the processor will have to read the data register (I2DAT) to determine which received address actually caused the match.

7.4 Comparator

The comparator compares the received 7-bit slave address with any of the four configured slave addresses in I2ADR0 through I2ADR3 after masking. It also compares the first received 8-bit byte with the General Call address (0x00). If an a match is found, the appropriate status bits are set and an interrupt is requested.

7.5 Shift register, I2DAT

This 8-bit register contains a byte of serial data to be transmitted or a byte which has just been received. Data in I2DAT is always shifted from right to left; the first bit to be transmitted is the MSB (bit 7) and, after a byte has been received, the first bit of received data is located at the MSB of I2DAT. While data is being shifted out, data on the bus is simultaneously being shifted in; I2DAT always contains the last byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in I2DAT.

7.6 Arbitration and synchronization logic

In the master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I2C-bus. If another device on the bus overrules a logic 1 and pulls the SDA line low, arbitration is lost, and the I2C block immediately changes from master transmitter to slave receiver. The I2C block will continue to output clock pulses (on SCL) until transmission of the current serial byte is complete. Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode can only occur while the I2C block is returning a “not acknowledge: (logic 1) to the bus. Arbitration is lost when another device on the bus pulls this signal low. Since this can occur only at the end of a serial byte, the I2C block generates no further clock pulses. Figure 19–90 shows the arbitration procedure.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 434 of 835 NXP Semiconductors UM10360 Chapter 19: LPC17xx I2C0/1/2 interface The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device. If two or more master devices generate clock pulses, the “mark” duration is determined by the device that generates the shortest “marks,” and the “space” duration is determined by the device that generates the longest “spaces”. Figure 19–91 shows the synchronization procedure. A slave may stretch the space duration to slow down the bus master. The space duration may also be stretched for handshaking purposes. This can be done after each bit or after a complete byte transfer. the I2C block will stretch the SCL space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. The serial interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is cleared.

7.7 Serial clock generator

This programmable clock pulse generator provides the SCL clock pulses when the I2C block is in the master transmitter or master receiver mode. It is switched off when the I2C block is in a slave mode. The I2C output clock frequency and duty cycle is programmable (1) Another device transmits serial data. (2) Another device overrules a logic (dotted line) transmitted this I 2C master by pulling the SDA line low. Arbitration is lost, and this I2C enters Slave Receiver mode. (3) This I 2C is in Slave Receiver mode but still generates clock pulses until the current byte has been transmitted. This I2C will not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration. Fig 90. Arbitration procedure (1) Another device pulls the SCL line low before this I 2C has timed a complete high time. The other device effectively determines the (shorter) HIGH period. (2) Another device continues to pull the SCL line low after this I 2C has timed a complete low time and released SCL. The I2C clock generator is forced to wait until SCL goes HIGH. The other device effectively determines the (longer) LOW period. (3) The SCL line is released , and the clock generator begins timing the HIGH time. Fig 91. Serial clock synchronization SDA line SCL line 1234 89 ACK (1) (2)(1) (3) SDA line SCL line (2) (1)(3) high period low period (1)

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 435 of 835 NXP Semiconductors UM10360 Chapter 19: LPC17xx I2C0/1/2 interface via the I2C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH registers for details. The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above.

7.8 Timing and control

The timing and control logic generates the timing and control signals for serial byte handling. This logic block provides the shift pulses for I2DAT, enables the comparator, generates and detects START and STOP conditions, receives and transmits acknowledge bits, controls the master and slave modes, contains interrupt request logic, and monitors the I 2C-bus status.

7.9 Control register, I2CONSET and I2CONCLR

The I2C control register contains bits used to control the following I2C block functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment. The contents of the I2C control register may be read as I2CONSET. Writing to I2CONSET will set bits in the I2C control register that correspond to ones in the value written. Conversely, writing to I2CONCLR will clear bits in the I2C control register that correspond to ones in the value written.

7.10 Status decoder and status register

The status decoder takes all of the internal status bits and compresses them into a 5-bit code. This code is unique for each I2C-bus status. The 5-bit code may be used to generate vector addresses for fast processing of the various service routines. Each service routine processes a particular bus status. There are 26 possible bus states if all four modes of the I 2C block are used. The 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. The three least significant bits of the status register are always zero. If the status code is used as a vector to service routines, then the routines are displaced by eight address locations. Eight bytes of code is sufficient for most of the service routines (see the software example in this section).

UM10360_1 © NXP B.V. 2010. All rights reserved. Each I2C interface contains 16 registers as shown in Table 19–384 below. Table 384. I 2C register map the corresponding bit in the I2C control register. software to determine the next action needed. responds to the General Call address. SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. I2SCLL SCL Duty Cycle Register Low Half Word. responds to the General Call address.

8.1 I 2C Control Set register (I2CONSET: I2C0, I2C0CONSET -

corresponding bit in the I2C control register to be set. Writing a zero has no effect. Reading this register provides the current values of the control and flag bits. responds to the General Call address. responds to the General Call address.

UM10360_1 © NXP B.V. 2010. All rights reserved. addressed” slave state, and the STO bit is forced to “0”. I2C-bus status is lost. The AA flag should be used instead. 0, no START condition or repeated START condition will be generated. the STOP condition, STO is cleared automatically. Table 385. I 2C Control Set register (I2CONSET: I2C0, I2C0CONSET - address 0x4001 C000, value read from a reserved bit is not defined. value read from a reserved bit is not defined.

A matching address defined by regist ers I2ADR0 through I2ADR3, masked by

I2MASK0 though I2MASK3, has been received.

The General Call address has been received while the General Call bit (GC) in I2ADR
A data byte has been received while the I 2C is in the master receiver mode.
A data byte has been received while the I 2C is in the addressed slave receiver mode
A data byte has been received while the I 2C is in the master receiver mode.
A data byte has been received while the I 2C is in the addressed slave receiver mode.

8.2 I 2C Control Clear register (I2CONCLR: I2C0, I2C0CONCLR -

corresponding bit in the I2C control register to be cleared. Writing a zero has no effect. Table 386. I 2C Control Clear register (I2CONCLR: I2C0, I2C0CONCLR - 0x4001 C018; I2C1, from a reserved bit is not defined. 2 AAC Assert acknowledge Clear bit. 3S I C I 2C interrupt Clear bit.

UM10360_1 © NXP B.V. 2010. All rights reserved. I2CONSET register. Writing 0 has no effect. register. Writing 0 has no effect. I2CONSET register. Writing 0 has no effect. I2CONSET register. Writing 0 has no effect.

8.3 I 2C Status register (I2STAT: I2C0, I2C0STAT - 0x4001 C004; I2C1,

Status register is read-only.

8.4 I 2C Data register (I2DAT: I2C0, I2C0DAT - 0x4001 C008; I2C1, I2C1DAT -

byte has been received, the first bit of received data is located at the MSB of I2DAT. from a reserved bit is not defined. 5 STAC START flag Clear bit. 6I 2 E N C I 2C interface Disable bit. from a reserved bit is not defined. Table 387. I 2C Status register (I2STAT: I2C0, I2C0STAT - 0x4001 C004; I2C1, I2C1STAT -

8.5 I 2C Monitor mode control register (I2MMCTRL: I2C0, I2C0MMCTRL -

0x4001 C01C; I2C1, I2C1MMCTRL- 0x4005 C01C; I2C2, I2C2MMCTRL- 0x400A 001C) This register controls the Monitor mode which allows the I2C module to monitor traffic on the I2C-bus without actually participating in traffic or interfering with the I2C-bus. Table 388. I 2C Data register (I2DAT: I2C0, I2C0DAT - 0x4001 C008; I2C1, I2C1DAT - value read from a reserved bit is not defined. Table 389. I 2C Monitor mode control register (I2MMCTRL: I2C0, I2C0MMCTRL - 0x4001 C01C; Bit Symbol Value Description Reset value 0 MM_ENA Monitor mode enable. 0 0 Monitor mode disabled. 1 The I2C module will enter monitor mode. In this mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. 1 ENA_SCL SCL output enable. 0

0 When this bit is cleared to ‘0’, the SCL output will be forced

high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line.

1 When this bit is set, the I2C module may exercise the same

control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can “stretch” the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 442 of 835 NXP Semiconductors UM10360 Chapter 19: LPC17xx I2C0/1/2 interface [1] When the ENA_SCL bit is cleared and the I 2C no longer has the ability to stretch the clock, interrupt response time becomes important. To give the part more time to respond to an I2C interrupt under these conditions, an I2DATA_BUFFER register is used (Section 19–8.6) to hold received data for a full 9-bit word transmission time. Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if the module is NOT in monitor mode).

8.5.1 Interrupt in Monitor mode

All interrupts will occur as normal when the module is in monitor mode. This means that the first interrupt will occur when an address-match is detected (any address received if the MATCH_ALL bit is set, otherwise an address matching one of the four address registers). Subsequent to an address-match detection, interrupts will be generated after each data byte is received for a slave-write transfer, or after each byte that the module believes it has transmitted for a slave-read transfer. In this second case, the data register will actually contain data transmitted by some other slave on the bus which was actually addressed by the master. Following all of these interrupts, the processor may read the data register to see what was actually transmitted on the bus.

8.5.2 Loss of arbitration in Monitor mode

In monitor mode, the I2C module will not be able to respond to a request for information by the bus master or issue an ACK. Some other slave on the bus will respond instead. Software should be aware of the fact that the module is in monitor mode and should not respond to any loss of arbitration state that is detected. 2 MATCH_ALL Select interrupt register match. 0

0 When this bit is cleared, an interrupt will only be generated

when a match occurs to one of the (up-to) four address registers, I2ADR0 through I2ADR3. That is, the module will respond as a normal slave as far as address-recognition is concerned.

1 When this bit is set to ‘1’ and the

I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. 31:3 - Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Bit Symbol Value Description Reset value

8.6 I 2C Data buffer register (I2DATA_BUFFER: I2C0, I2CDATA_BUFFER -

received data is overwritten by new data. bit transmission times to respond to the interrupt and read the data before it is overwritten. I2DAT will not be altered in any way.

8.7 I 2C Slave Address registers (I2ADR0 to 3: I2C0, I2C0ADR[0, 1, 2, 3]-

General Call bit. When this bit is set, the General Call address (0x00) is recognized. four registers will be cleared to this disabled state on reset. Table 390. I 2C Data buffer register (I2DATA_BUFFER: I2C0, I2CDATA_BUFFER - Table 391. I 2C Slave Address registers (I2ADR0 to 3: I2C0, I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C, value read from a reserved bit is not defined.

8.8 I 2C Mask registers (I2MASK0 to 3: I2C0, I2C0MASK[0, 1, 2, 3] -

account in determining an address match. The mask register has no effect on comparison to the General Call address (“0000000”). (I2DAT) to determine which received address actually caused the match.

8.9 I 2C SCL HIGH duty cycle register (I2SCLH: I2C0, I2C0SCLH -

8.10 I 2C SCL Low duty cycle register (I2SCLL: I2C0 - I2C0SCLL:

Table 392. I 2C Mask registers (I2MASK0 to 3: I2C0, I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34, bits read always back as zeroes. Table 393. I 2C SCL HIGH Duty Cycle register (I2SCLH: I2C0, I2C0SCLH - address Table 394. I 2C SCL Low duty cycle register (I2SCLL: I2C0 - I2C0SCLL: 0x4001 C014; I2C1 -

8.11 Selecting the appropriate I 2C data rate and duty cycle

Table 395. Example I 2C clock rates

1 MHz (Fast

Details of I 2C operating modes

Master Transmitter
Master Receiver
Slave Receiver
Slave Transmitter Data transfers in each mode of operation are shown in Figure 19–92, Figure 19–93, Figure 19–94, Figure 19–95, and Figure 19–96. Table 19–396 lists abbreviations used in these figures when describing the I2C operating modes. In Figure 19–92 to Figure 19–96, circles are used to indicate when the serial interrupt flag is set. The numbers in the circles show the status code held in the I2STAT register. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. When a serial interrupt routine is entered, the status code in I2STAT is used to branch to the appropriate service routine. For each status code, the required software action and details of the following serial transfer are given in tables from Table 19–399 to Table 19–403.

Table 396. Abbreviations used to describe an I 2C operation

9.1 Master Transmitter mode

enter a slave mode. STA, STO, and SI must be reset. now test the I2C-bus and generate a START condition as soon as the bus becomes free. before the serial transfer can continue. master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = logic 1). to the master receiver mode by loading I2DAT with SLA+R). Table 397. I2CONSET used to initialize Master Transmitter mode

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 448 of 835 NXP Semiconductors UM10360 Chapter 19: LPC17xx I2C0/1/2 interface Fig 92. Format and states in the Master Transmitter mode DATA A R WSLAS DATAAWSLA to Master receive mode, entry = MR MT to corresponding states in Slave mode A OR AA OR A A other Master continues other Master continues A other Master continues 20H 08H 18H 28H 30H 10H 68H 78H B0H 38H 38H arbitration lost in Slave address or Data byte Not Acknowledge received after a Data byte Not Acknowledge received after the Slave address next transfer started with a Repeated Start condition arbitration lost and addressed as Slave successful transmission to a Slave Receiver from Master to Slave from Slave to Master any number of data bytes and their associated Acknowledge bits n this number (contained in I2STA) corresponds to a defined state of the I2C bus A P P S P

9.2 Master Receiver mode

In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure 19–93). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt service routine must load I2DAT with the 7-bit slave address and the data direction bit (SLA+R). The SI bit in I2CON must then be cleared before the serial transfer can continue. When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in I2STAT are possible. These are 0x40, 0x48, or 0x38 for the master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = 1). The appropriate action to be taken for each of these status codes is detailed in Table 19–400 After a repeated START condition (state 0x10), the I2C block may switch to the master transmitter mode by loading I2DAT with SLA+W.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 450 of 835 NXP Semiconductors UM10360 Chapter 19: LPC17xx I2C0/1/2 interface Fig 93. Format and states in the Master Receiver mode A to Master transmit mode, entry = MT MR to corresponding states in Slave mode ARSLAS RSLAS W AA OR A A P other Master continues other Master continues A other Master continues 48H 40H 58H 10H 68H 78H B0H 38H 38H arbitration lost in Slave address or Acknowledge bit Not Acknowledge received after the Slave address next transfer started with a Repeated Start condition arbitration lost and addressed as Slave successful transmission to a Slave transmitter from Master to Slave from Slave to Master any number of data bytes and their associated Acknowledge bits n this number (contained in I2STA) corresponds to a defined state of the I 2C bus DATAADATA 50H ADATA P 08H

9.3 Slave Receiver mode

registers, and the I2MASK registers must be configured. I2C block is in the master mode (see status 0x68 and 0x78). Table 398. I2CONSET used to initialize Slave Receiver mode

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 452 of 835 NXP Semiconductors UM10360 Chapter 19: LPC17xx I2C0/1/2 interface Fig 94. Format and states in the Slave Receiver mode A A P OR SARSLAS P OR SA A 68H 60H 80H 88H reception of the General Call address and one or more Data bytes arbitration lost as Master and addressed as Slave last data byte received is Not acknowledged arbitration lost as Master and addressed as Slave by General Call reception of the own Slave address and one or more Data bytes all are acknowledged from Master to Slave from Slave to Master any number of data bytes and their associated Acknowledge bits n this number (contained in I2STA) corresponds to a defined state of the I2C bus DATAADATA 80H A0H last data byte is Not acknowledged A P OR SA 70h 90h DATAADATA 90h A0H GENERAL CALL A 98h P OR S A 78h DATA

9.4 Slave Transmitter mode

In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 19–95). Data transfer is initialized as in the slave receiver mode. When I2ADR and I2CON have been initialized, the I2C block waits until it is addressed by its own slave address followed by the data direction bit which must be “1” (R) for the I2C block to operate in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag (SI) is set and a valid status code can be read from I2STAT. This status code is used to vector to a state service routine, and the appropriate action to be taken for each of these status codes is detailed in Table 19–402. The slave transmitter mode may also be entered if arbitration is lost while the I2C block is in the master mode (see state 0xB0). If the AA bit is reset during a transfer, the I2C block will transmit the last byte of the transfer and enter state 0xC0 or 0xC8. The I2C block is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1s as serial data. While AA is reset, the I2C block does not respond to its own slave address or a General Call address. However, the I2C-bus is still monitored, and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate the I2C block from the I2C-bus. Fig 95. Format and states in the Slave Transmitter mode DATA AARSLAS P OR SA A B0H A8H C0H C8H last data byte transmitted. Switched to Not Addressed Slave (AA bit in I2CON = “0”) arbitration lost as Master and addressed as Slave reception of the own Slave address and one or more Data bytes all are acknowledged from Master to Slave from Slave to Master any number of data bytes and their associated Acknowledge bits n this number (contained in I2STA) corresponds to a defined state of the I 2C bus ADATA B8H ALL ONES ADATA P OR S

9.5 Detailed state tables

The following tables show detailed state information for the four I2C operating modes. Table 399. Master Transmitter mode Load SLA+W or X 0 0 X As above. will be switched to MST/REC mode. No I2DAT action or 1 0 0 X Repeated START will be transmitted. No I2DAT action or 1 0 0 X Repeated START will be transmitted. No I2DAT action or 1 0 0 X Repeated START will be transmitted. No I2DAT action or 1 0 0 X Repeated START will be transmitted.

UM10360_1 © NXP B.V. 2010. All rights reserved. Table 402. Slave Transmitter mode transmitted when the bus becomes free. be transmitted when the bus becomes free. transmitted when the bus becomes free. be transmitted when the bus becomes free.

9.6 Miscellaneous states

Table 19–403). These are discussed below.

9.6.1 I2STAT = 0xF8

is not involved in a serial transfer.

9.6.2 I2STAT = 0x00

released (a STOP condition is not transmitted).

9.7 Some special cases

9.7.1 Simultaneous repeated START conditions from two masters

either master since they were both transmitting the same data. Table 403. Miscellaneous States No I2DAT action No I2CON action Wait or proceed current transfer.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 460 of 835 NXP Semiconductors UM10360 Chapter 19: LPC17xx I2C0/1/2 interface If the I2C hardware detects a repeated START condition on the I2C-bus before generating a repeated START condition itself, it will release the bus, and no interrupt request is generated. If another master frees the bus by generating a STOP condition, the I2C block will transmit a normal START condition (state 0x08), and a retry of the total serial data transfer can commence.

9.7.2 Data transfer after loss of arbitration

Arbitration may be lost in the master transmitter and master receiver modes (see Figure 19–90). Loss of arbitration is indicated by the following states in I2STAT; 0x38, 0x68, 0x78, and 0xB0 (see Figure 19–92 and Figure 19–93). If the STA flag in I2CON is set by the routines which service these states, then, if the bus is free again, a START condition (state 0x08) is transmitted without intervention by the CPU, and a retry of the total serial transfer can commence.

9.7.3 Forced access to the I 2C-bus

In some applications, it may be possible for an uncontrolled source to cause a bus hang-up. In such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between SDA and SCL. If an uncontrolled source generates a superfluous START or masks a STOP condition, then the I2C-bus stays busy indefinitely. If the STA flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the I2C-bus is possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP condition is transmitted. The I 2C hardware behaves as if a STOP condition was received and is able to transmit a START condition. The STO flag is cleared by hardware Figure 19–97.

9.7.4 I 2C-bus obstructed by a LOW level on SCL or SDA

An I2C-bus hang-up can occur if either the SDA or SCL line is held LOW by any device on the bus. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is possible, and the problem must be resolved by the device that is pulling the SCL bus line LOW. Typically, the SDA line may be obstructed by another device on the bus that has become out of synchronization with the current bus master by either missing a clock, or by sensing a noise pulse as a clock. In this case, the problem can be solved by transmitting additional clock pulses on the SCL line Figure 19–98. The I2C interface does not include a dedicated timeout timer to detect an obstructed bus, but this can be implemented using another timer in the system. When detected, software can force clocks (up to 9 may be required) on SCL until SDA is released by the offending device. At that point, the slave may still be out of synchronization, so a START should be generated to insure that all I2C peripherals are synchronized.

9.7.5 Bus error

A bus error occurs when a START or STOP condition is detected at an illegal position in the format frame. Examples of illegal positions are during the serial transfer of an address byte, a data bit, or an acknowledge bit.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 461 of 835 NXP Semiconductors UM10360 Chapter 19: LPC17xx I2C0/1/2 interface The I2C hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. When a bus error is detected, the I2C block immediately switches to the not addressed slave mode, releases the SDA and SCL lines, sets the interrupt flag, and loads the status register with 0x00. This status code may be used to vector to a state service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in Table 19–403. Fig 96. Simultaneous repeated START conditions from two masters Fig 97. Forced access to a busy I 2C-bus (1) Unsuccessful attempt to send a START condition. (2) SDA line is released. (3) Successful attempt to send a START condition. State 08H is entered. Fig 98. Recovering from a bus obstruction caused by a LOW level on SDA SLAA WSLAS 18H 08H ADATA 28H08H OTHER MASTER CONTINUES other Master sends repeated START earlier S retry S P SDA line SCL line STA flag STO flag time limit start condition SDA line SCL line (1) (2) (1) (3) STA flag start condition

9.8 I 2C state service routines

This section provides examples of operations that must be performed by various I2C state service routines. This includes:

Initialization of the I2C block after a Reset.
I2C Interrupt Service
The 26 state service routines providing support for all four I2C operating modes.

9.8.1 Initialization

In the initialization example, the I2C block is enabled for both master and slave modes. For each mode, a buffer is used for transmission and reception. The initialization routine performs the following functions:

The I2ADR registers and I2MASK registers are loaded with values to configure the part’s own slave address(es) and the General Call bit (GC)
The I2C interrupt enable and interrupt priority bits are set
The slave mode is enabled by simultaneously setting the I2EN and AA bits in I2CON and the serial clock frequency (for master modes) is defined by loading the I2SCLH and I2SCLL registers. The master routines must be started in the main program. The I2C hardware now begins checking the I2C-bus for its own slave address and General Call. If the General Call or the own slave address is detected, an interrupt is requested and I2STAT is loaded with the appropriate state information.

9.8.2 I 2C interrupt service

When the I2C interrupt is entered, I2STAT contains a status code which identifies one of the 26 state services to be executed.

9.8.3 The state service routines

Each state routine is part of the I2C interrupt routine and handles one of the 26 states.

9.8.4 Adapting state services to an application

The state service examples show the typical actions that must be performed in response to the 26 I2C state codes. If one or more of the four I2C operating modes are not used, the associated state services can be omitted, as long as care is taken that the those states can never occur. In an application, it may be desirable to implement some kind of timeout during I2C operations, in order to trap an inoperative bus or a lost service routine.

10.1 Initialization routine

Example to initialize I2C Interface as a Slave and/or Master. 1. Load the I2ADR registers and I2MASK registers with values to configure the own Slave Address, enable General Call recognition if needed. 2. Enable I 2C interrupt. 3. Write 0x44 to I2CONSET to set the I2EN and AA bits, enabling Slave functions. For Master only functions, write 0x40 to I2CONSET.

10.2 Start Master Transmit function

Begin a Master Transmit operation by setting up the buffer, pointer, and data count, then initiating a START. 1. Initialize Master data counter. 2. Set up the Slave Address to which data will be transmitted, and add the Write bit. 3. Write 0x20 to I2CONSET to set the STA bit. 4. Set up data to be transmitted in Master Transmit buffer. 5. Initialize the Master data counter to ma tch the length of the message being sent. 6. Exit

10.3 Start Master Receive function

Begin a Master Receive operation by setting up the buffer, pointer, and data count, then initiating a START. 1. Initialize Master data counter. 2. Set up the Slave Address to which data will be transmitted, and add the Read bit. 3. Write 0x20 to I2CONSET to set the STA bit. 4. Set up the Master Receive buffer. 5. Initialize the Master data counter to match the length of the message to be received. 6. Exit

10.4 I 2C interrupt routine

Determine the I2C state and which state routine will be used to handle it. 1. Read the I 2C status from I2STA. 2. Use the status value to branch to one of 26 possible state routines.

10.5 Non mode specific states

10.5.1 State: 0x00

Bus Error. Enter not addressed Slave mode and release bus.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 464 of 835 NXP Semiconductors UM10360 Chapter 19: LPC17xx I2C0/1/2 interface 1. Write 0x14 to I2CONSET to set the STO and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit

10.5.2 Master States

State 0x08 and State 0x10 are for both Master Transmit and Master Receive modes. The R/W bit decides whether the next state is within Master Transmit mode or Master Receive mode.

10.5.3 State: 0x08

A START condition has been transmitted. The Slave Address + R/W bit will now be transmitted. 1. Write Slave Address with R/W bit to I2DAT. 2. Write 0x04 to I2CONSET to set the AA bit. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Set up Master Transmit mode data buffer. 5. Set up Master Receive mode data buffer. 6. Initialize Master data counter. 7. Exit

10.5.4 State: 0x10

A repeated START condition has been transmitted. The Slave Address + R/W bit will now be transmitted. 1. Write Slave Address with R/W bit to I2DAT. 2. Write 0x04 to I2CONSET to set the AA bit. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Set up Master Transmit mode data buffer. 5. Set up Master Receive mode data buffer. 6. Initialize Master data counter. 7. Exit

10.6 Master Transmitter states

10.6.1 State: 0x18

Previous state was State 0x08 or State 0x10, Slave Address + Write has been transmitted, ACK has been received. The first data byte will be transmitted. 1. Load I2DAT with first data byte from Master Transmit buffer. 2. Write 0x04 to I2CONSET to set the AA bit. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Increment Master Transmit buffer pointer. 5. Exit

10.6.2 State: 0x20

Slave Address + Write has been transmitted, NOT ACK has been received. A STOP condition will be transmitted. 1. Write 0x14 to I2CONSET to set the STO and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit

10.6.3 State: 0x28

Data has been transmitted, ACK has been received. If the transmitted data was the last data byte then transmit a STOP condition, otherwise transmit the next data byte. 1. Decrement the Master data counter, skip to step 5 if not the last data byte. 2. Write 0x14 to I2CONSET to set the STO and AA bits. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Exit 5. Load I2DAT with next data byte from Master Transmit buffer. 6. Write 0x04 to I2CONSET to set the AA bit. 7. Write 0x08 to I2CONCLR to clear the SI flag. 8. Increment Master Transmit buffer pointer 9. Exit

10.6.4 State: 0x30

Data has been transmitted, NOT ACK received. A STOP condition will be transmitted. 1. Write 0x14 to I2CONSET to set the STO and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit

10.6.5 State: 0x38

Arbitration has been lost during Slave Address + Write or data. The bus has been released and not addressed Slave mode is entered. A new START condition will be transmitted when the bus is free again. 1. Write 0x24 to I2CONSET to set the STA and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit

10.7 Master Receive states

10.7.1 State: 0x40

Previous state was State 08 or State 10. Slave Address + Read has been transmitted, ACK has been received. Data will be received and ACK returned. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag.

10.7.2 State: 0x48

Slave Address + Read has been transmitted, NOT ACK has been received. A STOP condition will be transmitted. 1. Write 0x14 to I2CONSET to set the STO and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit

10.7.3 State: 0x50

Data has been received, ACK has been returned. Data will be read from I2DAT. Additional data will be received. If this is the last data byte then NOT ACK will be returned, otherwise ACK will be returned. 1. Read data byte from I2DAT into Master Receive buffer. 2. Decrement the Master data counter, skip to step 5 if not the last data byte. 3. Write 0x0C to I2CONCLR to clear the SI flag and the AA bit. 4. Exit 5. Write 0x04 to I2CONSET to set the AA bit. 6. Write 0x08 to I2CONCLR to clear the SI flag. 7. Increment Master Receive buffer pointer 8. Exit

10.7.4 State: 0x58

Data has been received, NOT ACK has been returned. Data will be read from I2DAT. A STOP condition will be transmitted. 1. Read data byte from I2DAT into Master Receive buffer. 2. Write 0x14 to I2CONSET to set the STO and AA bits. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Exit

10.8 Slave Receiver states

10.8.1 State: 0x60

Own Slave Address + Write has been received, ACK has been returned. Data will be received and ACK returned. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Set up Slave Receive mode data buffer. 4. Initialize Slave data counter. 5. Exit

10.8.2 State: 0x68

Arbitration has been lost in Slave Address and R/W bit as bus Master. Own Slave Address + Write has been received, ACK has been returned. Data will be received and ACK will be returned. STA is set to restart Master mode after the bus is free again. 1. Write 0x24 to I2CONSET to set the STA and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Set up Slave Receive mode data buffer. 4. Initialize Slave data counter. 5. Exit.

10.8.3 State: 0x70

General Call has been received, ACK has been returned. Data will be received and ACK returned. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Set up Slave Receive mode data buffer. 4. Initialize Slave data counter. 5. Exit

10.8.4 State: 0x78

Arbitration has been lost in Slave Address + R/W bit as bus Master. General Call has been received and ACK has been returned. Data will be received and ACK returned. STA is set to restart Master mode after the bus is free again. 1. Write 0x24 to I2CONSET to set the STA and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Set up Slave Receive mode data buffer. 4. Initialize Slave data counter. 5. Exit

10.8.5 State: 0x80

Previously addressed with own Slave Address. Data has been received and ACK has been returned. Additional data will be read. 1. Read data byte from I2DAT into the Slave Receive buffer. 2. Decrement the Slave data counter, skip to step 5 if not the last data byte. 3. Write 0x0C to I2CONCLR to clear the SI flag and the AA bit. 4. Exit. 5. Write 0x04 to I2CONSET to set the AA bit. 6. Write 0x08 to I2CONCLR to clear the SI flag. 7. Increment Slave Receive buffer pointer. 8. Exit

10.8.6 State: 0x88

Previously addressed with own Slave Address. Data has been received and NOT ACK has been returned. Received data will not be saved. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit

10.8.7 State: 0x90

Previously addressed with General Call. Data has been received, ACK has been returned. Received data will be saved. Only the first data byte will be received with ACK. Additional data will be received with NOT ACK. 1. Read data byte from I2DAT into the Slave Receive buffer. 2. Write 0x0C to I2CONCLR to clear the SI flag and the AA bit. 3. Exit

10.8.8 State: 0x98

Previously addressed with General Call. Data has been received, NOT ACK has been returned. Received data will not be saved. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit

10.8.9 State: 0xA0

A STOP condition or repeated START has been received, while still addressed as a Slave. Data will not be saved. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit

10.9 Slave Transmitter states

10.9.1 State: 0xA8

Own Slave Address + Read has been received, ACK has been returned. Data will be transmitted, ACK bit will be received. 1. Load I2DAT from Slave Transmit buffer with first data byte. 2. Write 0x04 to I2CONSET to set the AA bit. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Set up Slave Transmit mode data buffer. 5. Increment Slave Transmit buffer pointer. 6. Exit

10.9.2 State: 0xB0

Arbitration lost in Slave Address and R/W bit as bus Master. Own Slave Address + Read has been received, ACK has been returned. Data will be transmitted, ACK bit will be received. STA is set to restart Master mode after the bus is free again. 1. Load I2DAT from Slave Transmit buffer with first data byte. 2. Write 0x24 to I2CONSET to set the STA and AA bits. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Set up Slave Transmit mode data buffer. 5. Increment Slave Transmit buffer pointer. 6. Exit

10.9.3 State: 0xB8

Data has been transmitted, ACK has been received. Data will be transmitted, ACK bit will be received. 1. Load I2DAT from Slave Transmit buffer with data byte. 2. Write 0x04 to I2CONSET to set the AA bit. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Increment Slave Transmit buffer pointer. 5. Exit

10.9.4 State: 0xC0

Data has been transmitted, NOT ACK has been received. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit.

10.9.5 State: 0xC8

The last data byte has been transmitted, ACK has been received. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 470 of 835 1. Basic configuration The I2S interface is configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set bit PCI2S. Remark: On reset, the I2S interface is disabled (PCI2S = 0). 2. Clock: In PCLKSEL1 select PCLK_I2S, see Table 4–41. 3. Pins: Select I 2S pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to PINMODE4 (see Section 8–5). 4. Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 5. DMA: The I 2S interface supports two DMA requests, see Table 20–411 and Table 20–412, and Table 31–544. 2. Features The I2S bus provides a standard communication interface for digital audio applications. The I2S bus specification defines a 3-wire serial bus, having one data, one clock, and one word select signal. The basic I2S connection has one master, which is always the master, and one slave. The I2S interface on the LPC17xx provides a separate transmit and receive channel, each of which can operate as either a master or a slave.

The I2S input can operate in both master and slave mode. The I2S output can operate in both master and slave mode, independent of the I2S input.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
Versatile clocking includes independent transmit and receive fractional rate generators, and an ability to use a single clock input or output for a 4-wire mode.
The sampling frequency (fs) can range (in practice) from 16 to 96 kHz. (16, 22.05, 32, 44.1, 48, or 96 kHz) for audio applications.
Separate Master Clock outputs for both transmit and receive channels support a clock up to 512 times the I2S sampling frequency.
Word Select period in master mode is configurable (separately for I2S input and I2S output).
Two 8 word (32 byte) FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected to the General Purpose DMA block.
Controls include reset, stop and mute options separately for I2S input and I2S output. UM10360 Chapter 20: LPC17xx I2S interface Rev. 01 — 4 January 2010 User manual

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 471 of 835 NXP Semiconductors UM10360 Chapter 20: LPC17xx I2S interface 3. Description The I2S performs serial data out via the transmit channel and serial data in via the receive channel. These support the NXP Inter IC Audio format for 8-bit, 16-bit and 32-bit audio data, both for stereo and mono modes. Configuration, data access and control is performed by a APB register set. Data streams are buffered by FIFOs with a depth of 8 words. The I2S receive and transmit stage can operate independently in either slave or master mode. Within the I2S module the difference between these modes lies in the word select (WS) signal which determines the timing of data transmissions. Data words start on the next falling edge of the transmitting clock after a WS change. In stereo mode when WS is low left data is transmitted and right data when WS is high. In mono mode the same data is transmitted twice, once when WS is low and again when WS is high.

In master mode, word select is generated internally with a 9-bit counter. The half period count value of this counter can be set in the control register.
In slave mode, word select is input from the relevant bus pin.
When an I2S bus is active, the word select, receive clock and transmit clock signals are sent continuously by the bus master, while data is sent continuously by the transmitter.
Disabling the I2S can be done with the stop or mute control bits separately for the transmit and receive.
The stop bit will disable accesses by the transmit channel or the receive channel to the FIFOs and will place the transmit channel in mute mode.
The mute control bit will place the transmit channel in mute mode. In mute mode, the transmit channel FIFO operates normally, but the output is discarded and replaced by zeroes. This bit does not affect the receive channel, data reception can occur normally.

UM10360_1 © NXP B.V. 2010. All rights reserved. Table 404. Pin descriptions master and received by the slave. Corresponds to the signal WS in the I2S bus specification. WS = 0 indicates that data is being received by channel 1 (left channel). WS = 1 indicates that data is being received by channel 2 (right channel). receiver. Corresponds to the signal SD in the I2S bus specification. RX_MCLK Output Optional master clock output for the I2S receive function. and received by the slave. Corresponds to the signal WS in the I2S bus specification. WS = 0 indicates that data is being sent to channel 1 (left channel). WS = 1 indicates that data is being sent to channel 2 (right channel). Transmit Data. Serial data, sent MSB first. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S bus specification. TX_MCLK Output Optional master clock output for the I2S transmit function.

UM10360_1 © NXP B.V. 2010. All rights reserved. their functions. Following the table are details for each register. [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

5.1 Digital Audio Output re gister (I2SDAO - 0x400A 8000)

bits in DAO are shown in Table 20–406. Table 405. I 2S register map I2S interrupt request is generated. by specifying the value to divide PCLK by in order to produce MCLK. by specifying the value to divide PCLK by in order to produce MCLK.

10 Reserved, do not use this setting

5.2 Digital Audio Input re gister (I2SDAI - 0x400A 8004)

The I2SDAI register controls the operation of the I2S receive channel. The function of bits in DAI are shown in Table 20–407.

5.3 Transmit FIFO register (I2STXFIFO - 0x400A 8008)

The I2STXFIFO register provides access to the transmit FIFO. The function of bits in I2STXFIFO are shown in Table 20–408.

5.4 Receive FIFO register (I2SRXFIFO - 0x400A 800C)

The I2SRXFIFO register provides access to the receive FIFO. The function of bits in I2SRXFIFO are shown in Table 20–409. 2 mono When 1, data is of monaural format. When 0, the data is in stereo format. 0 3 stop When 1, disables accesses on FIFOs, places the transmit channel in mute mode. 0 4 reset When 1, asynchronously resets the transmit channel and FIFO. 0 5 ws_sel When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 20–7 for a summary of useful combinations for this bit with I2STXMODE. 14:6 ws_halfperiod Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. 0x1F 15 mute When 1, the transmit channel sends only zeroes. 1 31:16 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 406: Digital Audio Output register (I2SDAO - address 0x400A 8000) bit description Bit Symbol Value Description Reset Value Table 407: Digital Audio Input register (I2SDAI - address 0x400A 8004) bit description Bit Symbol Value Description Reset Value 1:0 wordwidth Selects the number of bytes in data as follows: 01 00 8-bit data 01 16-bit data 2 mono When 1, data is of monaural format. When 0, the data is in stereo format. 0 3 stop When 1, disables accesses on FIFOs, places the transmit channel in mute mode. 0 4 reset When 1, asynchronously reset the transmit channel and FIFO. 0 5 ws_sel When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 20–7 for a summary of useful combinations for this bit with I2SRXMODE. 14:6 ws_halfperiod Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. 0x1F 31:15 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 408: Transmit FIFO register (I2STXFIFO - address 0x400A 8008) bit description Bit Symbol Description Reset Value 31:0 I2STXFIFO 8 × 32-bit transmit FIFO. Level = 0

5.5 Status Feedback regist er (I2SSTATE - 0x400A 8010)

The I2SSTATE register provides status information about the I2S interface. The meaning of bits in I2SSTATE are shown in Table 20–410.

5.6 DMA Configuration Regist er 1 (I2SDMA1 - 0x400A 8014)

The I2SDMA1 register controls the operation of DMA request 1. The function of bits in I2SDMA1 are shown in Table 20–411. Refer to the General Purpose DMA Controller chapter for details of DMA operation. Table 409: Receive FIFO register (I2RXFIFO - address 0x400A 800C) bit description Bit Symbol Description Reset Value 31:0 I2SRXFIFO 8 × 32-bit transmit FIFO. level = 0 Table 410: Status Feedback register (I2SSTATE - address 0x400A 8010) bit description Bit Symbol Description Reset Value 0 irq This bit reflects the presence of Receive Interr upt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the I2SIRQ register. 1 dmareq1 This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the I2SDMA1 register. 2 dmareq2 This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the I2SDMA2 register. 7:3 Unused Unused. 0 11:8 rx_level Reflects the current level of the Receive FIFO. 0 15:12 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 19:16 tx_level Reflects the current level of the Transmit FIFO. 0 31:20 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 411: DMA Configuration register 1 (I2S DMA1 - address 0x400A 8014) bit description Bit Symbol Description Reset Value 0 rx_dma1_enable When 1, enables DMA1 for I 2S receive. 0 1 tx_dma1_enable When 1, enables DMA1 for I 2S transmit. 0 7:2 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 11:8 rx_depth_dma1 Set the FIFO level that triggers a receive DMA request on DMA1. 0 15:12 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 19:16 tx_depth_dma1 Set the FIFO level that triggers a transmit DMA request on DMA1. 0 31:20 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

5.7 DMA Configuration Regist er 2 (I2SDMA2 - 0x400A 8018)

The I2SDMA2 register controls the operation of DMA request 2. The function of bits in I2SDMA2 are shown in Table 20–406.

5.8 Interrupt Request Control register (I2SIRQ - 0x400A 801C)

The I2SIRQ register controls the operation of the I2S interrupt request. The function of bits in I2SIRQ are shown in Table 20–406.

5.9 Transmit Clock Rate regi ster (I2STXRATE - 0x400A 8020)

The MCLK rate for the I2S transmitter is determined by the values in the I2STXRATE register. The required I2STXRATE setting depends on the desired audio sample rate desired, the format (stereo/mono) used, and the data size. The transmitter MCLK rate is generated using a fractional rate generator, dividing down the frequency of PCLK_I2S. Values of the numerator (X) and the denominator (Y) must be chosen to produce a frequency twice that desired for the transmitter MCLK, which must be an integer multiple of the transmitter bit clock rate. Fractional rate generators have some aspects that the user should be aware of when choosing settings. These are discussed in Section 20–5.9.1. The equation for the fractional rate generator is: I2STXMCLK = PCLK_I2S * (X/Y) /2 Table 412: DMA Configuration register 2 (I2S DMA2 - address 0x400A 8018) bit description Bit Symbol Description Reset Value 0 rx_dma2_enable When 1, enables DMA1 for I 2S receive. 0 1 tx_dma2_enable When 1, enables DMA1 for I 2S transmit. 0 7:2 Unused Unused. 0 11:8 rx_depth_dma2 Set the FIFO level that triggers a receive DMA request on DMA2. 0 15:12 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 19:16 tx_depth_dma2 Set the FIFO level that triggers a transmit DMA request on DMA2. 0 31:20 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 413: Interrupt Request Control register (I2SIRQ - address 0x400A 801C) bit description Bit Symbol Description Reset Value 0 rx_Irq_enable When 1, enables I2S receive interrupt. 0 1 tx_Irq_enable When 1, enables I2S transmit interrupt. 0 7:2 Unused Unused. 0 11:8 rx_depth_irq Set the FIFO level on which to create an irq request. 0 15:12 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 19:16 tx_depth_irq Set the FIFO level on which to create an irq request. 0 31:20 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 477 of 835 NXP Semiconductors UM10360 Chapter 20: LPC17xx I2S interface Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be greater than or equal to X.

5.9.1 Notes on fractional rate generators

The nature of a fractional rate generator is that there will be some output jitter with some divide settings. This is because the fractional rate generator is a fully digital function, so output clock transitions are synchronous with the source clock, whereas a theoretical perfect fractional rate may have edges that are not related to the source clock. So, output jitter will not be greater than plus or minus one source clock between consecutive clock edges. For example, if X = 0x07 and Y = 0x11, the fractional rate generator will output 7 clocks for every 17 (11 hex) input clocks, distributed as evenly as it can. In this example, there is no way to distribute the output clocks in a perfectly even fashion, so some clocks will be longer than others. The output is divided by 2 in order to square it up, which also helps with the jitter. The frequency averages out to exactly (7/17) / 2, but some clocks will be a slightly different length than their neighbors. It is possible to avoid jitter entirely by choosing fractions such that X divides evenly into Y , such as 2/4, 2/6, 3/9, 1/N, etc.

5.10 Receive Clock Rate regi ster (I2SRXRATE - 0x400A 8024)

The MCLK rate for the I2S receiver is determined by the values in the I2SRXRATE register. The required I2SRXRATE setting depends on the peripheral clock rate (PCLK_I2S) and the desired MCLK rate (such as 256 fs). The receiver MCLK rate is generated using a fractional rate generator, dividing down the frequency of PCLK_I2S. Values of the numerator (X) and the denominator (Y) must be chosen to produce a frequency twice that desired for the receiver MCLK, which must be an integer multiple of the receiver bit clock rate. Fractional rate generators have some aspects that the user should be aware of when choosing settings. These are discussed in Section 20–5.9.1. The equation for the fractional rate generator is: I2SRXMCLK = PCLK_I2S * (X/Y) /2 Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be greater than or equal to X. Table 414: Transmit Clock Rate register (I2TXRATE - address 0x400A 8020) bit description Bit Symbol Description Reset Value 7:0 Y_divider I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. 15:8 X_divider I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. 31:16 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

5.11 Transmit Clock Bit Rate re gister (I2STXBITRATE - 0x400A 8028)

The bit rate for the I2S transmitter is determined by the value of the I2STXBITRATE register. The value depends on the audio sample rate desired, and the data size and format (stereo/mono) used. For example, a 48 kHz sample rate for 16-bit stereo data requires a bit rate of 48,000×16×2 = 1.536 MHz.

5.12 Receive Clock Bit Rate regi ster (I2SRXBITRATE - 0x400A 802C)

The bit rate for the I2S receiver is determined by the value of the I2SRXBITRATE register. The value depends on the audio sample rate, as well as the data size and format used. The calculation is the same as for I2SRXBITRATE.

5.13 Transmit Mode Control register (I2STXMODE - 0x400A 8030)

The Transmit Mode Control register contains additional controls for transmit clock source, enabling the 4-pin mode, and how MCLK is used. See Section 20–7 for a summary of useful mode combinations. Table 415: Receive Clock Rate register (I2SRX RATE - address 0x400A 8024) bit description Bit Symbol Description Reset Value 7:0 Y_divider I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. 15:8 X_divider I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. 31:16 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 416: Transmit Clock Rate register (I2TXBITRATE - address 0x400A 8028) bit description Bit Symbol Description Reset Value 5:0 tx_bitrate I 2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock. 31:6 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 417: Receive Clock Rate register (I2SRX BITRATE - address 0x400A 802C) bit description Bit Symbol Description Reset Value 5:0 rx_bitrate I 2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock. 31:6 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

5.14 Receive Mode Control re gister (I2SRXMODE - 0x400A 8034)

The Receive Mode Control register contains additional controls for receive clock source, enabling the 4-pin mode, and how MCLK is used. See Section 20–7 for a summary of useful mode combinations. Table 418: Transmit Mode Control register (I2STXMODE - 0x400A 8030) bit description Bit Symbol Value Description Reset Value 1:0 TXCLKSEL Clock source selection for the transmit bit clock divider. 0

00 Select the TX fractional rate divider clock output as the source

01 Reserved

10 Select the RX_MCLK signal as the TX_MCLK clock source

11 Reserved

2 TX4PIN Transmit 4-pin mode selection. When 1, enables 4-pin mode. 0 3 TXMCENA Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled. 31:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 419: Receive Mode Control register (I2SRXMODE - 0x400A 8034) bit description Bit Symbol Value Description Reset Value 1:0 RXCLKSEL Clock source selection fo r the receive bit clock divider. 0

00 Select the RX fractional rate divider clock output as the source

10 Select the TX_MCLK signal as the RX_MCLK clock source

2 RX4PIN Receive 4-pin mode selection. When 1, enables 4-pin mode. 0 3 RXMCENA Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled. 31:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 480 of 835 NXP Semiconductors UM10360 Chapter 20: LPC17xx I2S interface 6. I 2S transmit and receive interfaces The I2S interface can transmit and receive 8-bit, 16-bit or 32-bit stereo or mono audio information. Some details of I2S implementation are:

When the FIFO is empty, the transmit channel will repeat transmitting the same data until new data is written to the FIFO.
When mute is true, the data value 0 is transmitted.
When mono is false, two successive data words are respectively left and right data.
Data word length is determined by the wordwidth value in the configuration register. There is a separate wordwidth value for the receive channel and the transmit channel. – 0: word is considered to contain four 8-bit data words. – 1: word is considered to contain two 16-bit data words. – 3: word is considered to contain one 32-bit data word.
When the transmit FIFO contains insufficient data the transmit channel will repeat transmitting the last data until new data is available. This can occur when the microprocessor or the DMA at some time is unable to provide new data fast enough. Because of this delay in new data there is a need to fill the gap, which is accomplished by continuing to transmit the last sample. The data is not muted as this would produce an noticeable and undesirable effect in the sound.
The transmit channel and the receive channel only handle 32-bit aligned words, data chunks must be clipped or extended to a multiple of 32 bits. When switching between data width or modes the I2S must be reset via the reset bit in the control register in order to ensure correct synchronization. It is advisable to set the stop bit also until sufficient data has been written in the transmit FIFO. Note that when stopped data output is muted. All data accesses to FIFOs are 32 bits. Figure 20–112 shows the possible data sequences. A data sample in the FIFO consists of:
1×32 bits in 8-bit or 16-bit stereo modes.
1×32 bits in mono modes.
2×32 bits, first left data, second right data, in 32-bit stereo modes. Data is read from the transmit FIFO after the falling edge of WS, it will be transferred to the transmit clock domain after the rising edge of WS. On the next falling edge of WS the left data will be loaded in the shift register and transmitted and on the following rising edge of WS the right data is loaded and transmitted. The receive channel will start receiving data after a change of WS. When word select becomes low it expects this data to be left data, when WS is high received data is expected to be right data. Reception will stop when the bit counter has reached the limit set by wordwidth. On the next change of WS the received data will be stored in the appropriate hold register. When complete data is available it will be written into the receive FIFO.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 481 of 835 NXP Semiconductors UM10360 Chapter 20: LPC17xx I2S interface 7. I 2S operating modes The clocking and WS usage of the I2S interface is configurable. In addition to master and slave modes, which are independently configurable for the transmitter and the receiver, several different clock sources are possible, including variations that share the clock and/or WS between the transmitter and receiver. This last option allows using I 2S with fewer pins, typically four. Many configurations are possible that are not considered useful, the following tables and figures give details of the configurations that are most likely to be useful. Table 420: I 2S transmit modes I2SDAO [5] I2STXMODE [3:0] 0 0 0 0 0 Typical transmitter master mode. See Figure 20–100 . The I2S transmit function operates as a master. The transmit clock source is the fractional rate divider. The WS used is the internally generated TX_WS. The TX_MCLK pin is not enabled for output. 0 0 0 1 0 Transmitter master mode sharing the receiver reference clock. See Figure 20–101 The I2S transmit function operates as a master. The transmit clock source is RX_REF. The WS used is the internally generated TX_WS. The TX_MCLK pin is not enabled for output. 0 0 1 0 0 4-wire transmitter master mode sharing the receiver bit clock and WS. See Figure 20–102 The I2S transmit function operates as a master. The transmit clock source is the RX bit clock. The WS used is the internally generated RX_WS. The TX_MCLK pin is not enabled for output. 0 1 0 0 0 Transmitter master mode with TX_MCLK output. See Figure 20–100 The I2S transmit function operates as a master. The transmit clock source is the fractional rate divider. The WS used is the internally generated TX_WS. The TX_MCLK pin is enabled for output. 1 0 0 0 0 Typical transmitter slave mode. See Figure 20–103 The I2S transmit function operates as a slave. The transmit clock source is the TX_CLK pin. The WS used is the TX_WS pin. 1 0 0 1 0 Transmitter slave mode sharing the receiver reference clock. See Figure 20–104 The I2S transmit function operates as a slave. The transmit clock source is RX_REF. The WS used is the TX_WS pin. 1 0 1 0 0 4-wire transmitter slave mode sharing the receiver bit clock and WS. See Figure 20–105. The I2S transmit function operates as a slave. The transmit clock source is the RX bit clock. The WS used is RX_WS ref.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 482 of 835 NXP Semiconductors UM10360 Chapter 20: LPC17xx I2S interface Fig 100. Typical transmitter master mode, with or without MCLK output I2STXMODE[3] I2S_PCLK ÷N (1 to 64) 8-bit Fractional Rate Divider XY I2STX_MCLK I2S peripheral block (transmit) I2STXBITRATE[5:0] I2STX_WS I2STX_SDA I2STX_CLK TX_REF TX bit clock I2STX_RATE[7:0] I2STX_RATE[15:8] (Pin OE) TX_WS ref Fig 101. Transmitter master mode sharing the receiver reference clock (1 to 64) I2STXBITRATE[5:0] I2STX_WS I2STX_SDA I2STX_CLK RX_REF TX bit clock TX_WS ref I2S peripheral block (transmit) Fig 102. 4-wire transmitter master mode sharing the receiver bit clock and WS I2STX_WS I2STX_SDA I2STX_CLK RX bit clock RX_WS ref I2S peripheral block (transmit) Fig 103. Typical transmitter slave mode (1 to 64) I2S peripheral block (transmit) I2STXBITRATE[5:0] I2STX_WS I2STX_SDA I2STX_CLK TX_REF TX bit clock Fig 104. Transmitter slave mode sharing the receiver reference clock (1 to 64) I2S peripheral block (transmit) I2STXBITRATE[5:0] I2STX_WS I2STX_SDA RX_REF TX bit clock

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 483 of 835 NXP Semiconductors UM10360 Chapter 20: LPC17xx I2S interface Fig 105. 4-wire transmitter slave mode sharing the receiver bit clock and WS I2STX_WS I2STX_SDA RX bit clock RX_WS ref I2S peripheral block (transmit) Table 421: I 2S receive modes I2SDAI [5] I2SRXMODE [3:0] 0 0 0 0 0 Typical receiver master mode. See Figure 20–106. The I2S receive function operates as a master. The receive clock source is the fractional rate divider. The WS used is the internally generated RX_WS. The RX_MCLK pin is not enabled for output. 0 0 0 1 0 Receiver master mode sharing the transmitter reference clock. See Figure 20–107. The I2S receive function operates as a master. The receive clock source is TX_REF. The WS used is the internally generated RX_WS. The RX_MCLK pin is not enabled for output. 0 0 1 0 0 4-wire receiver master mode sharing the transmitter bit clock and WS. See Figure 20–108 The I2S receive function operates as a master. The receive clock source is the TX bit clock. The WS used is the internally generated TX_WS. The RX_MCLK pin is not enabled for output. 0 1 0 0 0 Receiver master mode with RX_MCLK output. See Figure 20–106 The I2S receive function operates as a master. The receive clock source is the fractional rate divider. The WS used is the internally generated RX_WS. The RX_MCLK pin is enabled for output. 1 0 0 0 0 Typical receiver slave mode. See Figure 20–109 The I2S receive function operates as a slave. The receive clock source is the RX_CLK pin. The WS used is the RX_WS pin. 1 0 0 1 0 Receiver slave mode sharing the transmitter reference clock. See Figure 20–110 The I2S receive function operates as a slave. The receive clock source is TX_REF. The WS used is the RX_WS pin. 1 0 1 0 0 This is a 4-wire receiver slave mode sharing the transmitter bit clock and WS. See Figure 20–111 The I2S receive function operates as a slave. The receive clock source is the TX bit clock. The WS used is TX_WS ref.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 484 of 835 NXP Semiconductors UM10360 Chapter 20: LPC17xx I2S interface Fig 106. Typical receiver master mode, with or without MCLK output I2SRXMODE[3] I2S_PCLK ÷N (1 to 64) 8-bit Fractional Rate Divider XY I2SRX_MCLK I2S peripheral block (receive) I2SRXBITRATE[5:0] I2SRX_WS I2SRX_SDA I2SRX_CLK RX_REF RX bit clock I2SRX_RATE[7:0] I2SRX_RATE[15:8] (Pin OE) RX_WS ref Fig 107. Receiver master mode sharing the transmitter reference clock (1 to 64) I2SRXBITRATE[5:0] I2SRX_WS I2SRX_SDA I2SRX_CLK TX_REF RX bit clock RX_WS ref I2S peripheral block (receive) Fig 108. 4-wire receiver master mode sharing the transmitter bit clock and WS I2SRX_WS I2SRX_SDA I2SRX_CLK TX bit clock TX_WS ref I2S peripheral block (receive) Fig 109. Typical receiver slave mode (1 to 64) I2S peripheral block (receive) I2SRXBITRATE[5:0] I2SRX_WS I2SRX_SDA I2SRX_CLK RX_REF RX bit clock Fig 110. Receiver slave mode sharing the transmitter reference clock (1 to 64) I2S peripheral block (receive) I2SRXBITRATE[5:0] I2SRX_WS I2SRX_SDA TX_REF RX bit clock

UM10360_1 © NXP B.V. 2010. All rights reserved. current status of the level comparators can be seen in the APB status register. System signaling occurs when a level detection is true and enabled. Table 422. Conditions for FIFO level comparison Table 423. DMA and interrupt request generation Table 424. Status feedback in the I2SSTATE register

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 486 of 835 NXP Semiconductors UM10360 Chapter 20: LPC17xx I2S interface Fig 112. FIFO contents for various I2S modes LEFT + 17 0 RIGHT + 17 0 LEFT7 0 RIGHT7 0 Stereo 8-bit data mode N + 37 0 N + 27 0 N + 17 0 N7 0 Mono 8-bit data mode N + 115 0 N15 0 Mono 16-bit data mode LEFT15 0 RIGHT15 0 Stereo 16-bit data mode N31 0 Mono 32-bit data mode LEFT31 0 Stereo 32-bit data mode N RIGHT31 0 N + 1

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 487 of 835 1. Basic configuration The Timer 0, 1, 2, and 3 peripherals are configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set bits PCTIM0/1/2/3. Remark: On reset, Timer0/1 are enabled (PCTIM0/1 = 1), and Timer2/3 are disabled (PCTIM2/3 = 0). 2. Peripheral clock: In the PCLKSEL0 register (Table 4–40 ), select PCLK_TIMER0/1; in the PCLKSEL1 register (Table 4–41), select PCLK_TIMER2/3. 3. Pins: Select timer pins through the PINSEL registers. Select the pin modes for the port pins with timer functions through the PINMODE registers (Section 8–5). 4. Interrupts: See register T0/1/2/3MCR (Table 21–430 ) and T0/1/2/3CCR (Table 21–431) for match and capture events. Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 5. DMA: Up to two match conditions can be used to generate timed DMA requests, see Table 31–544. 2. Features Remark: The four Timer/Counters are identical except for the peripheral base address. A minimum of two Capture inputs and two Match outputs are pinned out for all four timers, with a choice of multiple pins for each. Timer 2 brings out all four Match outputs.

A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Counter or Timer operation
Up to two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.
Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following capabilities: – Set low on match. – Set high on match. – Toggle on match. – Do nothing on match. UM10360 Chapter 21: LPC17xx Timer 0/1/2/3 Rev. 01 — 4 January 2010 User manual

Interval Timer for counting internal events.
Pulse Width Demodulator via Capture inputs.
Free running timer. 4. Description The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally-supplied clock, and can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 5. Pin description Table 21–425 gives a brief summary of each of the Timer/Counter related pins.

5.1 Multiple CAP and MAT pins

be used internally without the use of a device pin. Table 425. Timer/Counter pin description Timer/Counter block can select a capture signal as a clock source instead of the PCLK derived clock. functionality of this output. Match Output functionality can be selected on a number of pins in parallel.

UM10360_1 © NXP B.V. 2010. All rights reserved. Table 426. TIMER/COUNTER0-3 register map PCLK. The TC is controlled through the TCR. this value, the next clock increments the TC and clears the PC. controllable through the bus interface. generated and if the TC is reset when a Match occurs. every time MR0 matches the TC. or not an interrupt is generated when a capture takes place.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 490 of 835 NXP Semiconductors UM10360 Chapter 21: LPC17xx Timer 0/1/2/3 [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

6.1 Interrupt Register (T[0 /1/2/3]IR - 0x4000 4000, 0x4000 8000,

0x4009 0000, 0x4009 4000) The Interrupt Register consists of 4 bits for the match interrupts and 4 bits for the capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be high. Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset the interrupt. Writing a zero has no effect. The act of clearing an interrupt for a timer match also clears any corresponding DMA request.

6.2 Timer Control Register (T[0 /1/2/3]CR - 0x4000 4004, 0x4000 8004,

0x4009 0004, 0x4009 4004) The Timer Control Register (TCR) is used to control the operation of the Timer/Counter. CR0 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0(CAP0.0 or CAP1.0 respectively) input. RO 0 T0CR0 - 0x4000 402C T1CR0 - 0x4000 802C T2CR0 - 0x4009 002C T3CR0 - 0x4009 402C CR1 Capture Register 1. See CR0 description. RO 0 T0CR1 - 0x4000 4030 T1CR1 - 0x4000 8030 T2CR1 - 0x4009 0030 T3CR1 - 0x4009 4030 EMR External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). R/W 0 T0EMR - 0x4000 403C T1EMR - 0x4000 803C T2EMR - 0x4009 003C T3EMR - 0x4009 403C CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. R/W 0 T0CTCR - 0x4000 4070 T1CTCR - 0x4000 8070 T2CTCR - 0x4009 0070 T3CTCR - 0x4009 4070 Table 427. Interrupt Register (T[0/1/2/3]IR - addresses 0x4000 4000, 0x4000 8000, 0x4009 0000, 0x4009 4000) bit Bit Symbol Description Reset Value 0 MR0 Interrupt Interrupt flag for match channel 0. 0 1 MR1 Interrupt Interrupt flag for match channel 1. 0 2 MR2 Interrupt Interrupt flag for match channel 2. 0 3 MR3 Interrupt Interrupt flag for match channel 3. 0 4 CR0 Interrupt Interrupt flag for capture channel 0 event. 0 5 CR1 Interrupt Interrupt flag for capture channel 1 event. 0 31:6 - Reserved -

6.3 Count Control Register (T[0/1 /2/3]CTCR - 0x4000 4070, 0x4000 8070,

and in Counter mode to select the pin and edge(s) for counting. bits 1:0 in the CTCR register, will the Timer Counter register be incremented. Effective processing of the externally supplied clock to the counter has some limitations. this case can not be shorter than 1/(2 PCLK). Table 428. Timer Control Register (TCR, TIMERn: TnTCR - addresses 0x4000 4004, 0x4000 8004, 0x4009 0004,

1 Counter Reset When one, the Timer Counter and the Prescale Counter are synchronously reset on the

next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. reserved bit is not defined. Table 429. Count Control Register (T[0/1/2/3]CTCR - addresses 0x4000 4070, 0x4000 8070, 0x4009 0070, (PC), or clear the PC and increment the Timer Counter (TC).

00 Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale

Register. The Prescale Counter is incremented on every rising PCLK edge. 01 Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 10 Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 11 Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.

6.4 Timer Counter registers (T0T C - T3TC, 0x4000 4008, 0x4000 8008,

count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000.

6.5 Prescale register (T0PR - T3PR, 0x4000 400C, 0x4000 800C,

The 32-bit Prescale register specifies the maximum value for the Prescale Counter.

6.6 Prescale Counter register (T 0PC - T3PC, 0x4000 4010, 0x4000 8010,

the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK.

10 Reserved

for that input in the Capture Control Register (TnCCR) must be programmed as 000. reserved bit is not defined.

6.7 Match Registers (MR0 - MR3)

controlled by the settings in the MCR register.

6.8 Match Control Register (T[0 /1/2/3]MCR - 0x4000 4014, 0x4000 8014,

Table 430. Match Control Register (T[0/1/2/3]MCR - addresses 0x4000 4014, 0x4000 8014, 0x4009 0014, 0x4009 4014)

0 This interrupt is disabled

2 MR0S 1 Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches

5 MR1S 1 Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches

8 MR2S 1 Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches

11 MR3S 1 Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches

reserved bit is not defined.

6.9 Capture Registers (CR0 - CR1)

6.10 Capture Control Register (T [0/1/2/3]CCR - 0x4000 4028, 0x4000 8028,

description below, "n" represents the Timer number, 0 or 1. be selected for the other 3 CAP inputs.

6.11 External Match Register (T[0/1/2/3]EMR - 0x4000 403C, 0x4000 803C,

The External Match Register provides both control and status of the external match pins. Table 431. Capture Control Register (T[0/1/2/3]CCR - addresses 0x4000 4028, 0x4000 8020, 0x4009 0028, loaded with the contents of TC. loaded with the contents of TC. loaded with the contents of TC. loaded with the contents of TC. reserved bit is not defined.

6.12 DMA operation

having software write a one to the interrupt flag location, as if clearing a timer interrupt. Table 432. External Match Register (T[0/1/2/3]EMR - addresses 0x4000 403C, 0x4000 803C, 0x4009 003C, MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). Table 433. External Match Control 01 Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). 10 Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). 11 Toggle the corresponding External Match bit/output.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 497 of 835 NXP Semiconductors UM10360 Chapter 21: LPC17xx Timer 0/1/2/3 8. Architecture The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in Figure 21–115. Fig 115. Timer block diagram reset MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER PRESCALE COUNTER PCLK enable RESERVED RESERVED CAPTURE REGISTER 1 CAPTURE REGISTER 0 MATCH REGISTER 3 MATCH REGISTER 2 MATCH REGISTER 1 MATCH REGISTER 0 CAPTURE CONTROL REGISTER CONTROL TIMER COUNTER CSN TCI CE INTERRUPT REGISTER EXTERNAL MATCH REGISTER MATCH CONTROL REGISTER MAT[3:0] INTERRUPT CAP[3:0] STOP ON MATCH DMA CLEAR[1:0] DMA REQUEST[1:0] RESET ON MATCH LOAD[3:0]

32-bit counter running from PCLK. Counter can be free-running, or be reset by a generated interrupt.
32-bit compare value.
32-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 2. Description The Repetitive Interrupt Timer provides a versatile means of generating interrupts at specified time intervals, without using a standard timer. It is intended for repeating interrupts that aren’t related to Operating System interrupts. However, it could be used as an alternative to the Cortex-M3 System Tick Timer (Section 23–1) if there are different system requirements. 3. Register description [1] Reset Value reflects the data stored in used bits only. It does not include content of reserved bits.

3.1 RI Compare Value regist er (RICOMPVAL - 0x400B 0000)

3.2 RI Mask register (RIMASK - 0x400B 0004)

Table 434. Repetitive Interrupt Timer register map the counter and compare register. Table 435. RI Compare Value register (RICOMPVAL - address 0x400B 0000) bit description Table 436. RI Compare Value register (RICOMPVAL - address 0x400B 0004) bit description compare on the corresponding bit of the counter and compare register.

3.3 RI Control register (RICTRL - 0x400B 0008)

3.4 RI Counter register (RICOUNTER - 0x400B 000C)

be reset to zero. Counting will resume from there on the next clock edge. Table 437. RI Control register (RICTRL - address 0x400B 0008) bit description

0 RITINT Interrupt flag 0

1 This bit is set to 1 by hardware whenever the counter value equals the masked

compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect. 0 The counter value does not equal the masked compare value.

1 RITENCLR Timer enable clear

1 The timer will be cleared to 0 whenever the counter value equals the masked compare

on the same clock that sets the interrupt flag. 0 The timer will not be cleared to 0.

2 RITENBR Timer enable for debug 1

1 The timer is halted when the processor is halted for debugging. 0 Debug has no effect on the timer operation. Remark: This can be overruled by a debug halt if enabled in bit 2. reserved bit is not defined. Table 438. RI Counter register (RICOUNT ER - address 0x400B 000C) bit description

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 500 of 835 NXP Semiconductors UM10360 Chapter 22: LPC17xx Repetitive Interrupt Timer (RIT) Counting can be halted in software by writing a ‘0’ to the Enable_Timer bit - RICTRL(2). Counting will also be halted when the processor is halted for debugging provided the Enable_Break bit – RICTRL(1) is set. Both the Enable_Timer and Enable_Break bits are set on reset. The interrupt flag can be cleared in software by writing a ‘1’ to the Interrupt bit – RICTRL(0). Software can load the counter to any value at any time by writing to RICOUNTER. The counter (RICOUNTER), RICOMPVAL register, RIMASK register and RICTRL register can all be read by software at any time. Fig 116. RI timer block diagram 32-bit COUNTER CLR ENA COMPARATOR COMPARE REGISTER SET MASK REGISTER SET S C CLR EQ ENABLE_TIMER ENABLE_BREAK BREAK INTR PBUS PBUS PBUS RESET RESET RESET SET_INT32 PBUS write '1' to clear PBUS PBUSPBUS CLR RESET PBUS PBUS PBUS CNT_ENA CTRL register CLR RESET ENABLE_CLK OperatingSystemTimer

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 501 of 835 1. Basic configuration The System Tick Timer is configured using the following registers: 1. Clock Source: Select either the internal CCLK or external STCLK (P3.26) clock as the source in the STCTRL register. 2. Pins: If STCLK (P3.26) was selected as clock source enable the STCLK pin function in the PINMODE register (Section 8–5). 3. Interrupt: The System Tick Timer Inte rrupt is enabled in the NVIC using the appropriate Interrupt Set Enable register. 2. Features

Times intervals of 10 milliseconds
Dedicated exception vector
Can be clocked internally by the CPU clock or by a clock input from a pin (STCLK) 3. Description The System Tick Timer is an integral part of the Cortex-M3. The System Tick Timer is intended to generate a fixed 10 millisecond interrupt for use by an operating system or other system management software. Since the System Tick Timer is a part of the Cortex-M3, it facilitates porting of software by providing a standard timer that is available on Cortex-M3 based devices. Refer to the Cortex-M3 User Guide appended to this manual (Section 34–4.4) for details of System Tick Timer operation. 4. Operation The System Tick Timer is a 24-bit timer that counts down to zero and generates an interrupt. The intent is to provide a fixed 10 millisecond time interval between interrupts. The System Tick Timer may be clocked either from the CPU clock or from the external pin STCLK. The STCLK function shares pin P3.26 with other functions, and must be selected for use as the System Tick Timer clock. In order to generate recurring interrupts at a specific interval, the STRELOAD register must be initialized with the correct value for the desired interval. A default value is provided in the STCALIB register and may be changed by software. The default value gives a 10 millisecond interrupt rate if the CPU clock is set to 100 MHz. The block diagram of the System Tick Timer is shown below in the Figure 23–117 UM10360 Chapter 23: LPC17xx System Tick Timer Rev. 01 — 4 January 2010 User manual

5.1 System Timer Control and status register (STCTRL - 0xE000 E010)

Table 439. System Tick Timer register map Table 440. System Timer Control and status register (STCTRL - 0xE000 E010) bit description 2 CLKSOURCE System Tick clock source selectio n. When 1, the CPU clock is selected. When 0, the external clock pin (STCLK) is selected.

5.2 System Timer Reload value register (STRELOAD - 0xE000 E014)

5.3 System Timer Current value register (STCURR - 0xE000 E018)

5.4 System Timer Calibration value register (STCALIB - 0xE000 E01C)

by selecting the correct reload value. value read from a reserved bit is not defined. counts down to 0, and is cleared by reading this register. value read from a reserved bit is not defined. Table 441. System Timer Reload value register (STRELOAD - 0xE000 E014) bit description value read from a reserved bit is not defined. Table 442. System Timer Current value register (STCURR - 0xE000 E018) bit description value read from a reserved bit is not defined.

UM10360_1 © NXP B.V. 2010. All rights reserved. Table 443. System Timer Calibration value regist er (STCALIB - 0xE000 E01C) bit description applicable only when using a CPU clock or external STCLK source of 100 MHz. from a reserved bit is not defined.

30 SKEW Indicates whether the TENMS value will generate a precise 10 millisecond time,

selected for the LPC17xx. See the description of TENMS above. TENMS is not considered to be precise.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 505 of 835 NXP Semiconductors UM10360 Chapter 23: LPC17xx System Tick Timer 6. Example timer calculations The following examples illustrate selecting System Tick Timer values for different system configurations. All of the examples calculate an interrupt interval of 10 milliseconds, as the System Tick Timer is intended to be used. Example 1) This example is for the System Tick Timer running from the CPU clock (cclk), which is 100 MHz. STCTRL = 7. This enables the timer and its interrupt, and selects cclk as the clock source. RELOAD = (cclk / 100) - 1 = 1,000,000 - 1 = 999,999 = 0xF423F In this case, there is no rounding error, so the result is as accurate as cclk. Example 2) This example is for the System Tick Timer running from the CPU clock (cclk), which is 80 MHz. STCTRL = 7. This enables the timer and its interrupt, and selects cclk as the clock source. RELOAD = (cclk / 100) - 1 = 800,000 - 1 = 799,999 = 0xC34FF In this case, there is no rounding error, so the result is as accurate as cclk. Example 3) This example is for the CPU clock (cclk) is taken from the Internal RC Oscillator (IRC), factory trimmed to 4 MHz. STCTRL = 7. This enables the timer and its interrupt, and selects cclk as the clock source. RELOAD = (FIRC / 100) - 1 = 40,000 - 1 = 39,999 = 0x9C3F In this case, there is no rounding error, so the result is as accurate as the IRC. Example 4) This example is for the System Tick Timer running from an external clock source (the STCLK pin), which in this case happens to be 32.768 kHz. STCTRL = 3. This enables the timer and its interrupt, and selects the STCLK pin as the clock source. STCLK must be selected as the function of the relevant pin. See Section 8–5.6 RELOAD = (cclk / 100) - 1 = 327.6 - 1 = 327 (rounded up) = 0x0147 In this case, there is rounding error, so the interrupt rate will drift slightly relative to the input frequency.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 506 of 835 1. Basic configuration The PWM is configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set bit PCPWM1. Remark: On reset, the PWM is enabled (PCPWM1 = 1). 2. Peripheral clock: In the PCLKSEL0 register ( Table 4–40), select PCLK_PWM1. 3. Pins: Select PWM pins through the PINSEL registers. Select pin modes for port pins with PWM1 functions through the PINMODE registers (Section 8–5). 4. Interrupts: See registers PWM1MCR ( Table 24–450) and PWM1CCR (Table 24–451) for match and capture events. Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 2. Features

Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source).
Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.
Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate.
Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses.
Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must "release" new match values before they can become effective.
May be used as a standard timer if the PWM mode is not enabled.
A 32-bit Timer/Counter with a programmable 32-bit prescaler.
Two 32-bit capture channels take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. UM10360 Chapter 24: LPC17xx Pulse Width Modulator (PWM) Rev. 01 — 4 January 2010 User manual

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 507 of 835 NXP Semiconductors UM10360 Chapter 24: LPC17xx Pulse Width Modulator (PWM) 3. Description The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC17xx. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). Figure 24–118 shows the block diagram of the PWM. The portions that have been added to the standard timer block are on the right hand side and at the top of the diagram.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 508 of 835 NXP Semiconductors UM10360 Chapter 24: LPC17xx Pulse Width Modulator (PWM) Fig 118. PWM block diagram MATCH REGISTER 3 MATCH REGISTER 2 MATCH REGISTER 0 MATCH REGISTER 4 MATCH REGISTER 5 MATCH REGISTER 6 SHADOW REGISTER 6 LOAD ENABLE MATCH REGISTER 1 SHADOW REGISTER 3 LOAD ENABLE SHADOW REGISTER 2 LOAD ENABLE SHADOW REGISTER 0 LOAD ENABLE SHADOW REGISTER 5 LOAD ENABLE SHADOW REGISTER 4 LOAD ENABLE LOAD ENABLE REGISTER CLEAR Match0 SHADOW REGISTER 1 LOAD ENABLE MATCH CONTROL REGISTER INTERRUPT REGISTER CONTROL M[6:0] INTERRUPT STOP ON MATCH RESET ON MATCH CAPTURE[1:0] CAPTURE CONTROL REGISTER CAPTURE REGISTER 0 CAPTURE REGISTER 1 RESERVED RESERVED LOAD[1:0] = PWMSEL2..6 R S Q EN R S Q EN PWM6 PWMENA6 R S Q EN R S Q EN R S Q EN R S Q EN MUX MUX MUX MUX MUX PWMSEL2 PWMSEL3 PWMSEL4 PWMSEL5 PWMSEL6 Match 0 Match 1 Match 3 Match 4 Match 5 Match 6 PWM5 PWMENA5 PWM4 PWMENA4 PWM3 PWMENA3 PWM2 PWMENA2 PWM1 PWMENA1 Match 2 TIMER CONTROL REGISTER PRESCALE REGISTER PWM CONTROL REGISTER PRESCALE COUNTER TIMER COUNTER PWMENA1..6 MAXVAL TCI CE CSN enablereset

Sample waveform with rules for single and double edge control

A sample of how PWM values relate to waveform outputs is shown in Figure 24–119. types can be mixed if desired. PWM1 cannot be a double edged output. PWM6 for double edge PWM outputs provides the most pairings. The timer is configured for PWM mode (counter resets to 1). Match 0 is configured to reset the timer/counter when a match event occurs. All PWM related Match registers are configured for toggle on match. Control bits PWMSEL2 and PWMSEL4 are set. Table 444. Set and reset inputs for PWM Flip-Flops

1 Match 0 Match 1 Match 0[1] Match 1[1]

2 Match 0 Match 2 Match 1 Match 2

3 Match 0 Match 3 Match 2[2] Match 3[2]

4 Match 0 Match 4 Match 3 Match 4

5 Match 0 Match 5 Match 4[2] Match 5[2]

6 Match 0 Match 6 Match 5 Match 6

4.1 Rules for Single Edge Controlled PWM Outputs

All single edge controlled PWM outputs go high at the beginning of a PWM cycle

unless their match value is equal to 0.

Each PWM output will go low when its match value is reached. If no match occurs (i.e.

4.2 Rules for Double Edge Controlled PWM Outputs

The match values for the next PWM cycle are used at the end of a PWM cycle (a time
A match value equal to 0 or the current PWM rate (the same as the Match channel 0

falling edge at the end of a PWM cycle.

When match values are changing, if one of the "old" match values is equal to the

or the PWM rate, and there was no old match value equal to 0.

If both a set and a clear of a PWM output are requested at the same time, clear takes

or when the set or clear value equals 0 and the other value equals the PWM rate.

If a match value is out of range (i.e. greater than the PWM rate value), no match event

Table 24–445 gives a brief summary of each of PWM related pins. Table 445. Pin summary PWM1[1] Output Output from PWM channel 1. PWM1[2] Output Output from PWM channel 2. PWM1[3] Output Output from PWM channel 3. PWM1[4] Output Output from PWM channel 4. PWM1[5] Output Output from PWM channel 5. PWM1[6] Output Output from PWM channel 6.

UM10360_1 © NXP B.V. 2010. All rights reserved. The PWM1 function includes registers as shown in Table 24–446 below. Table 446. PWM1 register map read to identify which of eight possible interrupt sources are pending. functions. The Timer Counter can be disabled or reset through the TCR. TC Timer Counter. The 32-bi t TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. generated and if the TC is reset when a Match occurs. both the TC and PC, and/or generate an interrupt when it matches the TC. that is in single-edge mode, and sets PWM1 if it’s in double-edge mode. both the TC and PC, and/or generate an interrupt when it matches the TC. edge mode, and sets PWM2 if it’s in double-edge mode. both the TC and PC, and/or generate an interrupt when it matches the TC. edge mode, and sets PWM3 if it’s in double-edge mode. both the TC and PC, and/or generate an interrupt when it matches the TC. edge mode, and sets PWM4 if it’s in double-edge mode. interrupt is generated when a capture takes place. an event on the CAPn.0 input.

6.1 PWM Interrupt Regist er (PWM1IR - 0x4001 8000)

corresponding IR bit will reset the interrupt. Writing a 0 has no effect. both the TC and PC, and/or generate an interrupt when it matches the TC. edge mode, and sets PWM5 if it’s in double-edge mode. both the TC and PC, and/or generate an interrupt when it matches the TC. edge mode, and sets PWM6 if it’s in double-edge mode. both the TC and PC, and/or generate an interrupt when it matches the TC. types as either single edge or double edge controlled. mode, and in Counter mode selects the signal and edge(s) for counting.

4 PWMCAP0

5 PWMCAP1

reserved bit is not defined. reserved bit is not defined.

6.2 PWM Timer Control Re gister (PWM1TCR 0x4001 8004)

The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM Timer Counter. The function of each of the bits is shown in Table 24–448.

6.3 PWM Count Control Regi ster (PWM1CTCR - 0x4001 8070)

The Count Control Register (CTCR) is used to select between Timer and Counter mode, and in Counter mode to select the pin and edge(s) for counting. The function of each of the bits is shown in Table 24–449. Table 448: PWM Timer Control Register (PWM1TCR address 0x4001 8004) bit description Bit Symbol Value Description Reset Value 0 Counter Enable 1 The PWM Timer Counter and PWM Prescale Counter are enabled for counting. 0 0 The counters are disabled.

1 Counter Reset 1 The PWM Timer Counter and the PWM Prescale Counter are synchronously reset

on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero. 0 Clear reset. 2 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 3 PWM Enable 1 PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective. 0 Timer mode is enabled (counter resets to 0). 31:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 449: PWM Count control Register (PWM1CTCR - address 0x4001 8004) bit description Bit Symbol Value Description Reset Value 1:0 Counter/ Timer Mode Register.

01 Counter Mode: the TC is incremented on rising edges of the PCAP input selected by

bits 3:2.

10 Counter Mode: the TC is incremented on falling edges of the PCAP input selected by

bits 3:2.

11 Counter Mode: the TC is incremented on both edges of the PCAP input selected by

bits 3:2. 3:2 Count Input Select When bits 1:0 of this register are not 00, these bits select which PCAP pin which carries the signal used to increment the TC. 00 PCAP1.0 01 PCAP1.1 (Other combinations are reserved) 31:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

6.4 PWM Match Control Regi ster (PWM1MCR - 0x4001 8014)

The PWM Match Control Registers are used to control what operations are performed when one of the PWM Match Registers matches the PWM Timer Counter. The function of each of the bits is shown in Table 24–450. Table 450: Match Control Register (PWM1MCR - address 0x4000 4014) bit description Bit Symbol Value Description Reset Value

0 PWMMR0I 1 Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in

the PWMTC. 0 This interrupt is disabled. 1 PWMMR0R 1 Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it. 0 0 This feature is disabled.

2 PWMMR0S 1 Stop on PWMMR0: t he PWMTC and PWMPC will be stopped and PWMTCR[0] will be

set to 0 if PWMMR0 matches the PWMTC.

0 This feature is disabled

3 PWMMR1I 1 Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in

the PWMTC. 0 This interrupt is disabled. 4 PWMMR1R 1 Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it. 0 0 This feature is disabled.

5 PWMMR1S 1 Stop on PWMMR1: t he PWMTC and PWMPC will be stopped and PWMTCR[0] will be

set to 0 if PWMMR1 matches the PWMTC. 0 This feature is disabled.

6 PWMMR2I 1 Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in

the PWMTC. 0 This interrupt is disabled. 7 PWMMR2R 1 Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it. 0 0 This feature is disabled.

8 PWMMR2S 1 Stop on PWMMR2: t he PWMTC and PWMPC will be stopped and PWMTCR[0] will be

set to 0 if PWMMR2 matches the PWMTC.

9 PWMMR3I 1 Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in

the PWMTC. 0 This interrupt is disabled. 10 PWMMR3R 1 Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it. 0

11 PWMMR3S 1 Stop on PWMMR3: The PWMTC and PWMPC will be stopped and PWMTCR[0] will

be set to 0 if PWMMR3 matches the PWMTC.

12 PWMMR4I 1 Interrupt on PWMMR4: An interrupt is generated when PWMMR4 matches the value

in the PWMTC. 0 This interrupt is disabled. 13 PWMMR4R 1 Reset on PW MMR4: the PWMTC will be reset if PWMMR4 matches it. 0 0 This feature is disabled.

6.5 PWM Capture Control Regi ster (PWM1CCR - 0x4001 8028)

The Capture Control Register is used to control whether one of the four Capture Registers is loaded with the value in the Timer Counter when a capture event occurs, and whether an interrupt is generated by the capture event. Setting both the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges. In the descriptions below, “n” represents the Timer number, 0 or 1. Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for that input in this register should be programmed as 000, but capture and/or interrupt can be selected for the other 3 CAP inputs.

14 PWMMR4S 1 Stop on PWMMR4 : the PWMTC and PWMPC will be stopped and PWMTCR[0] will be

set to 0 if PWMMR4 matches the PWMTC.

15 PWMMR5I 1 Interrupt on PWMMR5: An interrupt is generated when PWMMR5 matches the value

in the PWMTC. 0 This interrupt is disabled. 16 PWMMR5R 1 Reset on PW MMR5: the PWMTC will be reset if PWMMR5 matches it. 0 0 This feature is disabled.

17 PWMMR5S 1 Stop on PWMMR5 : the PWMTC and PWMPC will be stopped and PWMTCR[0] will be

set to 0 if PWMMR5 matches the PWMTC.

18 PWMMR6I 1 Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in

the PWMTC. 0 This interrupt is disabled. 19 PWMMR6R 1 Reset on PW MMR6: the PWMTC will be reset if PWMMR6 matches it. 0 0 This feature is disabled.

20 PWMMR6S 1 Stop on PWMMR6 : the PWMTC and PWMPC will be stopped and PWMTCR[0] will be

set to 0 if PWMMR6 matches the PWMTC. 31:21 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 450: Match Control Register (PWM1MCR - address 0x4000 4014) bit description Bit Symbol Value Description Reset Value Table 451: PWM Capture Control Register (P WM1CCR - address 0x4001 8028) bit description Bit Symbol Value Description Reset Value

0 Capture on

CAPn.0 rising edge 0 This feature is disabled. 0 1 A synchronously sampled rising edge on the CAPn.0 input will cause CR0 to be loaded with the contents of the TC.

1 Capture on

CAPn.0 falling edge 0 This feature is disabled. 0 1 A synchronously sampled falling edge on CAPn.0 will cause CR0 to be loaded with the contents of TC.

2 Interrupt on

CAPn.0 event 0 This feature is disabled. 0 1 A CR0 load due to a CAPn.0 event will generate an interrupt.

6.6 PWM Control Register (PWM1PCR - 0x4001 804C)

The PWM Control Register is used to enable and select the type of each PWM channel. The function of each of the bits are shown in Table 24–452.

3 Capture on

CAPn.1rising edge 0 This feature is disabled. 0 1 A synchronously sampled rising edge on the CAPn.1 input will cause CR1 to be loaded with the contents of the TC.

4 Capture on

CAPn.1falling edge 0 This feature is disabled. 0 1 A synchronously sampled falling edge on CAPn.1 will cause CR1 to be loaded with the contents of TC.

5 Interrupt on

CAPn.1 event 0 This feature is disabled. 0 1 A CR1 load due to a CAPn.1 event will generate an interrupt. 31:6 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 451: PWM Capture Control Register (P WM1CCR - address 0x4001 8028) bit description Bit Symbol Value Description Reset Value Table 452: PWM Control Register (PWM1PCR - address 0x4001 804C) bit description Bit Symbol Value Description Reset Value 1:0 Unused Unused, always zero. NA 2 PWMSEL2 1 Selects double edge controlled mode for the PWM2 output. 0 0 Selects single edge controlled mode for PWM2. 3 PWMSEL3 1 Selects double edge controlled mode for the PWM3 output. 0 0 Selects single edge controlled mode for PWM3. 4 PWMSEL4 1 Selects double edge controlled mode for the PWM4 output. 0 0 Selects single edge controlled mode for PWM4. 5 PWMSEL5 1 Selects double edge controlled mode for the PWM5 output. 0 0 Selects single edge controlled mode for PWM5. 6 PWMSEL6 1 Selects double edge controlled mode for the PWM6 output. 0 0 Selects single edge controlled mode for PWM6. 8:7 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 9 PWMENA1 1 The PWM1 output enabled. 0 0 The PWM1 output disabled. 10 PWMENA2 1 The PWM2 output enabled. 0 0 The PWM2 output disabled. 11 PWMENA3 1 The PWM3 output enabled. 0 0 The PWM3 output disabled. 12 PWMENA4 1 The PWM4 output enabled. 0 0 The PWM4 output disabled. 13 PWMENA5 1 The PWM5 output enabled. 0 0 The PWM5 output disabled.

6.7 PWM Latch Enable Regist er (PWM1LER - 0x4001 8050)

The PWM Latch Enable Registers are used to control the update of the PWM Match registers when they are used for PWM generation. When software writes to the location of a PWM Match register while the Timer is in PWM mode, the value is captured, but not used immediately. When a PWM Match 0 event occurs (normally also resetting the timer in PWM mode), the contents of shadow registers will be transferred to the shadow registers if the corresponding bit in the Latch Enable Register has been set. At that point, the new values will take effect and determine the course of the next PWM cycle. Once the transfer of new values has taken place, all bits of the LER are automatically cleared. Until the corresponding bit in the PWMLER is set and a PWM Match 0 event occurs, any value written to the PWM Match registers has no effect on PWM operation. For example, if PWM2 is configured for double edge operation and is currently running, a typical sequence of events for changing the timing would be:

Write a new value to the PWM Match1 register.
Write a new value to the PWM Match2 register.
Write to the PWMLER, setting bits 1 and 2 at the same time.
The altered values will become effective at the next reset of the timer (when a PWM Match 0 event occurs). The order of writing the two PWM Match registers is not important, since neither value will be used until after the write to LER. This insures that both values go into effect at the same time, if that is required. A single value may be altered in the same way if needed. The function of each of the bits in the LER is shown in Table 24–453. 14 PWMENA6 1 The PWM6 output enabled. 0 0 The PWM6 output disabled. 31:15 Unused Unused, always zero. NA Table 452: PWM Control Register (PWM1PCR - address 0x4001 804C) bit description Bit Symbol Value Description Reset Value Table 453: PWM Latch Enable Register (PWM1LER - address 0x4001 8050) bit description Bit Symbol Description Reset Value

0 Enable PWM

Writing a one to this bit allows the last value written to the PWM Match 0 register to be become effective when the timer is next reset by a PWM Match event. See Section 24–6.4 “PWM Match Control Register (PWM1MCR - 0x4001 8014)”.

1 Enable PWM

Writing a one to this bit allows the last value written to the PWM Match 1 register to be become effective when the timer is next reset by a PWM Match event. See Section 24–6.4 “PWM Match Control Register (PWM1MCR - 0x4001 8014)”.

2 Enable PWM

Writing a one to this bit allows the last value written to the PWM Match 2 register to be become effective when the timer is next reset by a PWM Match event. See Section 24–6.4 “PWM Match Control Register (PWM1MCR - 0x4001 8014)”.

3 Enable PWM

Writing a one to this bit allows the last value written to the PWM Match 3 register to be become effective when the timer is next reset by a PWM Match event. See Section 24–6.4 “PWM Match Control Register (PWM1MCR - 0x4001 8014)”.

4 Enable PWM

Writing a one to this bit allows the last value written to the PWM Match 4 register to be become effective when the timer is next reset by a PWM Match event. See Section 24–6.4 “PWM Match Control Register (PWM1MCR - 0x4001 8014)”.

5 Enable PWM

Writing a one to this bit allows the last value written to the PWM Match 5 register to be become effective when the timer is next reset by a PWM Match event. See Section 24–6.4 “PWM Match Control Register (PWM1MCR - 0x4001 8014)”.

6 Enable PWM

Writing a one to this bit allows the last value written to the PWM Match 6 register to be become effective when the timer is next reset by a PWM Match event. See Section 24–6.4 “PWM Match Control Register (PWM1MCR - 0x4001 8014)”. 31:7 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 453: PWM Latch Enable Register (PWM1LER - address 0x4001 8050) bit description Bit Symbol Description Reset Value

a 32-bit Timer/Counter (TC)
a 32-bit Limit register (LIM)
a 32-bit Match register (MAT)
a 10-bit dead-time register (DT) and an associated 10-bit dead-time counter
a 32-bit capture register (CAP)
two modulated outputs (MCOA and MCOB) with opposite polarities
a period interrupt, a pulse-width interrupt, and a capture interrupt Input pins MCI0-2 can trigger TC capture or increment a channel’s TC. A global Abort input can force all of the channels into “A passive” state and cause an interrupt. 3. Pin description Table 25–454 lists the MCPWM pins. UM10360 Chapter 25: LPC17xx Motor Control PWM Rev. 01 — 4 January 2010 User manual

Table 454. Pin summary

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 520 of 835 NXP Semiconductors UM10360 Chapter 25: LPC17xx Motor Control PWM 4. Block Diagram Fig 120. MCPWM Block Diagram Clock selection PCLK MCI0-2 Clock selection Clock selectionTC0 Event selection TC1 Event selection TC2 Event selection MCCNTCON MCCAPCON =MAT0 (oper) MAT0 (write) LIM0 (oper) LIM0 (write) CAP0 channel output control dead-time counter DT0 A0 B0 MCCON RT0 cntl =MAT1 (oper) MAT1 (write) LIM1 (oper) LIM1 (write) CAP1 channel output control dead-time counter DT1 A1 B1 MCCON RT1 MAT2 (oper) MAT2 (write) LIM2 (oper) LIM2 (write) global output control MCCON MCCP MCABORT MCOA0 MCOB0 MCOA1 MCOB1 MCOA2 MCOB2 mux ACMODE cntl cntl CAP2 channel output control dead-time counter DT2 A2 B2 MCCON RT2 mux ACMODE interrupt logic MCABORT MCINTEN MCINTF mux muxACMODE ACMODE

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 521 of 835 NXP Semiconductors UM10360 Chapter 25: LPC17xx Motor Control PWM 5. Configuring other modules for MCPWM use Configure the following registers in other modules before using the Motor Control PWM: 1. Power: in the PCONP register ( Table 4–46), set bit PCMCPWM. Remark: On reset the MCPWM is disabled (PCMCPWM = 0). 2. Peripheral clock: in the PCLKSEL1 register ( Table 4–40) select PCLK_MCPWM. 3. Pins: select MCPWM functions through the PINSEL registers. Select modes for these pins through the PINMODE registers (Section 8–5). 4. Interrupts: See Section 25–7.3 for motor control PWM related interrupts. Interrupts can be enabled in the NVIC using the appropriate Interrupt Set Enable register. 6. General Operation Section 25–8 includes detailed descriptions of the various modes of MCPWM operation, but a quick preview here will provide background for the register descriptions below. The MCPWM includes 3 channels, each of which controls a pair of outputs that in turn can control something off-chip, like one set of coils in a motor. Each channel includes a Timer/Counter (TC) register that is incremented by a processor clock (timer mode) or by an input pin (counter mode). Each channel has a Limit register that is compared to the TC value, and when a match occurs the TC is “recycled” in one of two ways. In “edge-aligned mode” the TC is reset to 0, while in “centered mode” a match switches the TC into a state in which it decrements on each processor clock or input pin transition until it reaches 0, at which time it starts counting up again. Each channel also includes a Match register that holds a smaller value than the Limit register. In edge-aligned mode the channel’s outputs are switched whenever the TC matches either the Match or Limit register, while in center-aligned mode they are switched only when it matches the Match register. So the Limit register controls the period of the outputs, while the Match register controls how much of each period the outputs spend in each state. Having a small value in the Limit register minimizes “ripple” if the output is integrated into a voltage, and allows the MCPWM to control devices that operate at high speed. The “downside” of small values in the Limit register is that they reduce the resolution of the duty cycle controlled by the Match register. If you have 8 in the Limit register, the Match register can only select the duty cycle among 0%, 12.5%, 25%, …, 87.5%, or 100%. In general, the resolution of each step in the Match value is 1 divided by the Limit value. This trade-off between resolution and period/frequency is inherent in the design of pulse width modulators.

UM10360_1 © NXP B.V. 2010. All rights reserved. “Control” registers and “interrupt” registers have separate read, set, and clear addresses. Reading such a register’s read address(e.g. MCCON) yields the state of the register bits. to the clear address (e.g. MCCON_CLR) clears register bit(s). MCPER, MCPW, MCDEADTIME, and MCCP) are normal read-write registers. Table 455. Motor Control Pulse Widt h Modulator (MCPWM) register map

7.1 MCPWM Control register

7.1.1 MCPWM Control read address (MCCON - 0x400B 8000)

Table 456. MCPWM Control read address (MCCON - 0x400B 8000) bit description 0 Passive state is LOW, active state is HIGH. 1 Passive state is HIGH, active state is LOW.

0 Functional registers are updated from the write registers at the end of each PWM

1 Functional registers remain the same as long as the timer is running. 0 Passive state is LOW, active state is HIGH. 1 Passive state is HIGH, active state is LOW. 1 Functional registers remain the same as long as the timer is running.

7.1.2 MCPWM Control set address (MCCON_SET - 0x400B 8004)

Writing ones to this write-only address sets the corresponding bits in MCCON.

7.1.3 MCPWM Control clear address (MCCON_CLR - 0x400B 8008)

Writing ones to this write-only address clears the corresponding bits in MCCON. 0 Passive state is LOW, active state is HIGH. 1 Passive state is HIGH, active state is LOW. 1 Functional registers remain the same as long as the timer is running. to 1 only in 3-phase DC mode.

0 The MCOB outputs have opposite polarity from the MCOA outputs (aside from

1 3-phase DC mode on: The internal MCOA0 output is routed through the MCCP (i.e. a mask) register to all six PWM outputs. Table 457. MCPWM Control set address (M CCON_SET - 0x400B 8004) bit description 31:0 Writing ones to this address sets the corresponding bits in the MCCON register. See Table 25–456.

7.2 MCPWM Capture Control register

7.2.1 MCPWM Capture Control read address (MCCAPCON - 0x400B 800C)

be modified by writing to addresses MCCAPCON_SET and MCCAPCON_CLR.

7.2.2 MCPWM Capture Control se t address (MCCAPCON_SET - 0x400B 8010)

Writing ones to this write-only address sets the corresponding bits in MCCAPCON. Table 458. MCPWM Control clear address (MCCON_CLR - 0x400B 8008) bit description 31:0 Writing ones to this address clears the co rresponding bits in the MCCON register. See Table 25–456. Table 459. MCPWM Capture Control read address (MCCAPCON - 0x400B 800C) bit description

21 HNFCAP0 Hardware noise filter: if this bit is 1, channel 0 capture events are delayed as described in

22 HNFCAP1 Hardware noise filter: if this bit is 1, channel 1 capture events are delayed as described in

23 HNFCAP2 Hardware noise filter: if this bit is 1, channel 2 capture events are delayed as described in

7.2.3 MCPWM Capture control clear address (MCCAPCON_CLR - 0x400B 8014)

Writing ones to this write-only address clears the corresponding bits in MCCAPCON.

7.3 MCPWM Interrupt registers

All MCPWM interrupt registers contain one bit for each source as shown in Table 25–463.

7.3.1 MCPWM Interrupt Enable r ead address (MCINTEN - 0x400B 8050)

MCINTEN_SET and MCINTEN_CLR. Table 460. MCPWM Capture Control set address (MCCAPCON_SET - 0x400B 8010) bit description 31:0 Writing ones to this address sets the corresponding bits in the MCCAPCON register. See Table 25–459. Table 461. MCPWM Capture control clear register (MCCAPCON_CLR - address 0x400B 8014) bit description 31:0 Writing ones to this address clears the corresponding bits in the MCCAPCON register. See Table 25–459. Table 462. Motor Control PWM interrupts ILIM0/1/2 Limit interrupts for channels 0, 1, 2. IMAT0/1/2 Match interrupts for channels 0, 1, 2. ICAP0/1/2 Capture interrupts for channels 0, 1, 2. Table 463. Interrupt sources bit allocation table Table 464. MCPWM Interrupt Enable read address (MCINTEN - 0x400B 8050) bit description

7.3.2 MCPWM Interrupt Enable set address (MCINTEN_SET - 0x400B 8054)

7.3.3 MCPWM Interrupt Enable clear address (MCINTEN_CLR - 0x400B 8058)

7.3.4 MCPWM Interrupt Flags read address (MCINTF - 0x400B 8068)

7.3.5 MCPWM Interrupt Flags set address (MCINTF_SET - 0x400B 806C)

possibly simulating hardware interrupt(s).

7.3.6 MCPWM Interrupt Flags clear address (MCINTF_CLR - 0x400B 8070)

Table 465. PWM interrupt enable set register (MCINTEN_SET - address 0x400B 8054) bit description 31:0 Writing ones to this address sets the corresponding bits in MCINTEN, thus enabling interrupts. See Table 25–463. Table 466. PWM interrupt enable clear register (MC INTEN_CLR - address 0x400B 8058) bit description Table 467. MCPWM Interrupt Flags read address (MCINTF - 0x400B 8068) bit description

1 If the corresponding bit in MCINTEN is 1, the MCPWM module is asserting its interrupt request to

0 This interrupt source is not contributing to the MCPWM interrupt request. Table 468. MCPWM Interrupt Flags set address (PWMINTF_SET - 0x400B 806C) bit description simulating hardware interrupt(s). See Table 25–463.

7.4 MCPWM Count Control register

7.4.1 MCPWM Count Control read address (MCCNTCON - 0x400B 805C)

MCCNTCON_SET or MCCNTCON_CLR address. Table 469. MCPWM Interrupt Flags clear address (PWMINTF_CLR - 0x400B 8070) bit description corresponding interrupt request(s). See Table 25–463. Table 470. MCPWM Count Control read address (MCCNTCON - 0x400B 805C) bit description 0 A rising edge on MCI0 does not affect counter 0. 0 A falling edge on MCI0 does not affect counter 0. 0 A rising edge on MCI1 does not affect counter 0. 0 A falling edge on MCI1 does not affect counter 0. 0 A rising edge on MCI0 does not affect counter 0. 0 A falling edge on MCI0 does not affect counter 0. 0 A rising edge on MCI0 does not affect counter 1. 0 A falling edge on MCI0 does not affect counter 1. 0 A rising edge on MCI1 does not affect counter 1. 0 A falling edge on MCI0 does not affect counter 1. 0 A rising edge on MCI2 does not affect counter 1. 0 A falling edge on MCI2 does not affect counter 1. 0 A rising edge on MCI0 does not affect counter 2.

7.4.2 MCPWM Count Control set address (MCCNTCON_SET - 0x400B 8060)

Writing one(s) to this write-only address sets the corresponding bit(s) in MCCNTCON.

7.4.3 MCPWM Count Control clear address (MCCNTCON_CLR - 0x400B 8064)

Writing one(s) to this write-only address clears the corresponding bit(s) in MCCNTCON.

7.5 MCPWM Timer/Counter 0-2 registers (MCTC0-2 - 0x400B 8018,

corresponding MCPER register (or is stopped by writing to MCCON_CLR). be stopped. If not, the write will not take place, no exception is generated. 0 A falling edge on MCI0 does not affect counter 2. 0 A rising edge on MCI1 does not affect counter 2. 0 A falling edge on MCI1 does not affect counter 2. 0 A rising edge on MCI2 does not affect counter 2. 0 A falling edge on MCI2 does not affect counter 2. 0 Channel 0 is in timer mode. 0 Channel 1 is in timer mode. 0 Channel 2 is in timer mode. Table 471. MCPWM Count Control set address (MCCNTCON_SET - 0x400B 8060) bit description Table 472. MCPWM Count Control clear address (MCCAPCON_CLR - 0x400B 8064) bit description

7.6 MCPWM Limit 0-2 registers (MCLIM0-2 - 0x400B 8024, 0x400B 8028,

time it begins counting up again. switches the channel’s B output from “passive” to “active” state. output switches from “passive” to “active” state. effect on its A and B outputs. from the write registers until software stops the channel. Reading an MCLIM address always returns the operating value. and the Match register to be the “Pulse Width register”.

7.7 MCPWM Match 0-2 registers (MC MAT0-2 - 0x400B 8030, 0x400B 8034,

7.6 above for details of reading and writing both Limit and Match registers. corresponding Limit register. Table 473. MCPWM Timer/Counter 0-2 registers (MCTC0-2 - 0x400B 8018, 0x400B 801C, 0x400B 8020) bit description Table 474. MCPWM Limit 0-2 registers (MCLIM0-2 - 0x400B 8024, 0x400B 8028, 0x400B 802C) bit description

7.7.1 Match register in Edge-Aligned mode

If the channel’s CENTER bit in MCCON is 0 selecting edge-aligned mode, a match between TC and MAT switches the channel’s B output from “active” to “passive” state. If the channel’s CENTER and DTE bits in MCCON are both 0, the match simultaneously switches the channel’s A output from “passive” to “active” state. If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s deadtime counter to begin counting -- when the deadtime counter expires, the channel’s A output switches from “passive” to “active” state.

7.7.2 Match register in Center-Aligned mode

If the channel’s CENTER bit in MCCON is 1 selecting center-aligned mode, a match between TC and MAT while the TC is incrementing switches the channel’s B output from “active” to “passive” state, and a match while the TC is decrementing switches the A output from “active” to “passive”. If the channel’s CENTER bit in MCCON is 1 but the DTE bit is 0, a match simultaneously switches the channel’s other output in the opposite direction. If the channel’s CENTER and DTE bits are both 1, a match between TC and MAT triggers the channel’s deadtime counter to begin counting -- when the deadtime counter expires, the channel’s B output switches from “passive” to “active” if the TC was counting up at the time of the match, and the channel’s A output switches from “passive” to “active” if the TC was counting down at the time of the match. 7.7.3 0 and 100% duty cycle To lock a channel’s MCO outputs at the state “B active, A passive”, write its Match register with a higher value than you write to its Limit register. The match never occurs. To lock a channel’s MCO outputs at the opposite state, “A active, B passive”, simply write 0 to its Match register.

7.8 MCPWM Dead-time regi ster (MCDT - 0x400B 803C)

This register holds the dead-time values for the three channels. If a channel’s DTE bit in MCCON is 1 to enable its dead-time counter, the counter counts down from this value whenever one its channel’s outputs changes from “active” to “passive” state. When the dead-time counter reaches 0, the channel changes its other output from “passive” to “active” state. The motivation for the dead-time feature is that power transistors, like those driven by the A and B outputs in a motor-control application, take longer to fully turn off than they take to start to turn on. If the A and B transistors are ever turned on at the same time, a wasteful and damaging current will flow between the power rails through the transistors. In such applications, the dead-time register should be programmed with the number of PCLK periods that is greater than or equal to the transistors’ maximum turn-off time minus their minimum turn-on time. Table 475. MCPWM Match 0-2 registers (MCMAT0-2 - addresses 0x400B 8030, 0x400B 8034, 0x400B 8038) bit Bit Symbol Description Reset value 31:0 MCMAT0/1/2 Match values for TC0, 1, 2. 0xFFFF FFFF

7.9 MCPWM Commutation Pattern register (MCCP - 0x400B 8040)

7.10 MCPWM Capture Registers

7.10.1 MCPWM Capture read addresse s (MCCAP0-2 - 0x400B 8044, 0x400B 8048,

occurs, the current TC value for that channel is stored in its read-only Capture register.

7.10.2 MCPWM Capture clear address (MCCAP_CLR - 0x400B 8074)

Writing ones to this write-only address clears the selected CAP register(s). Table 476. MCPWM Dead-time register (MCDT - address 0x400B 803C) bit description Table 477. MCPWM Commutation Pattern register (MCCP - address 0x400B 8040) bit description Table 478. MCPWM Capture read addresses (MCCAP0/1/2 - 0x400B 8044, 0x400B 8048, 0x400B 804C) bit description

UM10360_1 © NXP B.V. 2010. All rights reserved. Table 479. MCPWM Capture clear address (CAP_CLR - 0x400B 8074) bit description 0 CAP_CLR0 Writing a 1 to this bit clears the MCCAP0 register. 1 CAP_CLR1 Writing a 1 to this bit clears the MCCAP1 register. 2 CAP_CLR2 Writing a 1 to this bit clears the MCCAP2 register.

8.1 Pulse-width modulation

Each channel of the MCPWM has two outputs, A and B, that can drive a pair of transistors to switch a controlled point between two power rails. Most of the time the two outputs have opposite polarity, but a dead-time feature can be enabled (on a per-channel basis) to delay both signals’ transitions from “passive” to “active” state so that the transistors are never both turned on simultaneously. In a more general view, the states of each output pair can be thought of “high”, “low”, and “floating” or “up”, “down”, and “center-off”. Each channel’s mapping from “active” and “passive” to “high” and “low” is programmable. After Reset, the three A outputs are passive/low, and the B outputs are active/high. The MCPWM can perform edge-aligned and center-aligned pulse-width modulation. Note: In timer mode, the period of a channel’s modulated MCO outputs is determined by its Limit register, and the pulse width at the start of the period is determined by its Match register. If it suits your way of thinking, consider the Limit register to be the “Period register” and the Match register to be the “Pulse Width register”. Edge-aligned PWM without dead-time In this mode the timer TC counts up from 0 to the value in the LIM register. As shown in Figure 25–121 , the MCO state is “A passive” until the TC matches the Match register, at which point it changes to “A active”. When the TC matches the Limit register, the MCO state changes back to “A passive”, and the TC is reset and starts counting up again. Center-aligned PWM without dead-time In this mode the timer TC counts up from 0 to the value in the LIM register, then counts back down to 0 and repeats. As shown in Figure 25–122 , while the timer counts up, the MCO state is “A passive” until the TC matches the Match register, at which point it changes to “A active”. When the TC matches the Limit register it starts counting down. When the TC matches the Match register on the way down, the MCO state changes back to “A passive”. Fig 121. Edge-aligned PWM waveform without dead time, POLA = 0 MAT MATLIM LIM0 POLA = 0 timer reset timer reset MCOA MCOB active activepassive passive passive passiveactive active

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 535 of 835 NXP Semiconductors UM10360 Chapter 25: LPC17xx Motor Control PWM Dead-time counter When the a channel’s DTE bit is set in MCCON, the dead-time counter delays the passive-to-active transitions of both MCO outputs. The dead-time counter starts counting down, from the channel’s DT value (in the MCDT register) to 0, whenever the channel’s A or B output changes from active to passive. The transition of the other output from passive to active is delayed until the dead-time counter reaches 0. During the dead time, the MCOA and MCOB output levels are both passive. Figure 25–123 shows operation in edge aligned mode with dead time, and Figure 25–124 shows center-aligned operation with dead time. Fig 122. Center-aligned PWM waveform without dead time, POLA = 0 Fig 123. Edge-aligned PWM waveform with dead time, POLA = 0 MAT MAT LIMLIM 00 POLA = 0MCOA MCOB active activepassive passive passive passiveactive active MAT MATLIM LIM0 POLA = 0 timer reset timer reset MCOA MCOB active active passive passive passive passive active active DT DT DT DT

8.2 Shadow registers and simultaneous updates

The Limit, Match, and Commutation Pattern registers (MCLIM, MCMAT, and MCCP) are implemented as register pairs, each consisting of a write register and an operational register. Software writes into the write registers. The operational registers control the actual operation of each channel and are loaded with the current value in the write registers when the TC starts counting up from 0. Updating of the functional registers can be disabled by setting a channel’s DISUP bit in the MCCON register. If the DISUP bits are set, the functional registers are not updated until software stops the channel. If a channel is not running when software writes to its LIM or MAT register, the functional register is updated immediately. Software can write to a TC register only when its channel is stopped.

8.3 Fast Abort (ABORT)

The MCPWM has an external input MCABORT. When this input goes low, all six MCO outputs assume their “A passive” states, and the Abort interrupt is generated if enabled. The outputs remain locked in “A passive” state until the ABORT interrupt flag is cleared or the Abort interrupt is disabled. The ABORT flag may not be cleared before the MCABORT input goes high. In order to clear an ABORT flag, a 1 must be written to bit 15 of the MCINTF_CLR register. This will remove the interrupt request. The interrupt can also be disabled by writing a 1 to bit 15 of the MCINTEN_CLR register.

8.4 Capture events

Each PWM channel can take a snapshot of its TC when an input signal transitions. Any channel may use any combination of rising and/or falling edges on any or all of the MCI0-2 inputs as a capture event, under control of the MCCAPCON register. Rising or falling edges on the inputs are detected synchronously with respect to PCLK. Fig 124. Center-aligned waveform with dead time, POLA = 0 MAT MAT LIMLIM 00 POLA = 0MCOA MCOB active activepassive passive passive passive active active DT DT DT

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 537 of 835 NXP Semiconductors UM10360 Chapter 25: LPC17xx Motor Control PWM If a channel’s HNF bit in the MCCAPCON register is set to enable “noise filtering”, a selected edge on an MCI pin starts the dead-time counter for that channel, and the capture event actions described below are delayed until the dead-time counter reaches 0. This function is targeted specifically for performing three-phase brushless DC motor control with Hall sensors. A capture event on a channel (possibly delayed by HNF) causes the following:

The current value of the TC is stored in the Capture register (CAP).
If the channel’s capture event interrupt is enabled (see Table 25–464), the capture event interrupt flag is set.
If the channel’s RT bit is set in the MCCAPCON register, enabling reset on a capture event, the input event has the same effect as matching the channel’s TC to its LIM register. This includes resetting the TC and switching the MCO pin(s) in edge-aligned mode as described in 7.6 and 8.1.

8.5 External event count ing (Counter mode)

If a channel’s MODE bit is 1 in MCCNTCON, its TC is incremented by rising and/or falling edge(s) (synchronously detected) on the MCI0-2 input(s), rather than by PCLK. The PWM functions and capture functions are unaffected.

8.6 Three-phase DC mode

The three-phase DC mode is selected by setting the DCMODE bit in the MCCON register. In this mode, the internal MCOA0 signal can be routed to any or all of the MCO outputs. Each MCO output is masked by a bit in the current Commutation Pattern register MCCP. If a bit in the MCCP register is 0, its output pin has the logic level for the passive state of output MCOA0. The polarity of the off state is determined by the POLA0 bit. All MCO outputs that have 1 bits in the MCCP register are controlled by the internal MCOA0 signal. The three MCOB output pins are inverted when the INVBDC bit is 1 in the MCCON register. This feature accommodates bridge-drivers that have active-low inputs for the low-side switches. The MCCP register is implemented as a shadow register pair, so that changes to the active commutation pattern occur at the beginning of a new PWM cycle. See 7.6 and 8.2 for more about writing and reading such registers. Figure 25–125 shows sample waveforms of the MCO outputs in three-phase DC mode. Bits 1 and 3 in the MCCP register (corresponding to outputs MCOB1 and MCOB0) are set to 0 so that these outputs are masked and in the off state. Their logic level is determined by the POLA0 bit (here, POLA0 = 0 so the passive state is logic LOW). The INVBDC bit is set to 0 (logic level not inverted) so that the B output have the same polarity as the A outputs. Note that this mode differs from other modes in that the MCOB outputs are not the opposite of the MCOA outputs. In the situation shown in Figure 25–125, bits 0, 2, 4, and 5 in the MCCP register are set to 1. That means that MCOA1 and both MCO outputs for channel 2 follow the MCOA0 signal.

8.7 Three phase AC mode

The three-phase AC-mode is selected by setting the ACMODE bit in the MCCON register. In this mode, the value of channel 0’s TC is routed to all channels for comparison with their MAT registers. (The LIM1-2 registers are not used.) Each channel controls its MCO output by comparing its MAT value to TC0. Figure 25–126 shows sample waveforms for the six MCO outputs in three-phase AC mode. The POLA bits are set to 0 for all three channels, so that for all MCO outputs the active levels are high and the passive levels are low. Each channel has a different MAT value which is compared to the MCTC0 value. In this mode the period value is identical for all three channels and is determined by MCLIM0. The dead-time mode is disabled. Fig 125. Three-phase DC mode sample waveforms POLA0 = 0, INVBDC = 0 MCOA2 MCOB1 MCOA1 MCOB0 MCOA0 MCOB2 CCPB1 = 0, off-state CCPB0 = 0, off-state CCPA0 = 1, on-state CCPA2 = 1, on-state CCPA1 = 1, on-state CCPB2 = 1, on-state

8.8 Interrupts

The MCPWM includes 10 possible interrupt sources:

When any channel’s TC matches its Match register.
When any channel’s TC matches its Limit register.
When any channel captures the value of its TC into its Capture register, because a selected edge occurs on any of MCI0-2.
When all three channels’ outputs are forced to “A passive” state because the MCABORT pin goes low. Section 25–7.3 “MCPWM Interrupt registers” explains how to enable these interrupts, and Section 25–7.2 “MCPWM Capture Control register” describes how to map edges on the MCI0-2 inputs to “capture events” on the three channels. Fig 126. Three-phase AC mode sample waveforms, edge aligned PWM mode POLA0 = 0 POLA2 = 0 POLA1 = 0 MCOA2 MCOB1 MCOA1 MCOB0 MCOA0 MCOB2 MAT0 MAT1 MAT1 MAT2 MAT2 LIM0 LIM0 timer reset timer reset

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 540 of 835 1. Basic configuration The QEI is configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set bit PCQEI. Remark: On reset, the QEI is disabled (PCQEI = 0). 2. Peripheral clock: In the PCLKSEL0 register (Table 4–40 ), select PCLK_QEI. 3. Pins: Select QEI pins through the PINSEL registers. Select pin modes for port pins with QEI functions through the PINMODE registers (Section 8–5). 4. Interrupts: See Section 26–6.4 . The QEI interrupt is enabled in the NVIC using the appropriate Interrupt Set Enable register. 2. Features This Quadrature Encoder Interface (QEI) has the following features:

tracks encoder position.
increments/ decrements depending on direction.
programmable for 2X or 4X position counting.
velocity capture using built-in timer.
velocity compare function with less than interrupt.
uses 32-bit registers for position and velocity.
three position compare registers with interrupts.
index counter for revolution counting.
index compare register with interrupts.
can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement.
digital filter with programmable delays for encoder input signals.
can accept decoded signal inputs (clock and direction). 3. Introduction A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. This quadrature encoder interface module decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture the velocity of the encoder wheel. UM10360 Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Rev. 01 — 4 January 2010 User manual

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 541 of 835 NXP Semiconductors UM10360 Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) Fig 127.Encoder interface block diagram 002aad520 index Ph A Ph B PCLK DIGITAL FILTER QUAD DECODER VELOCITY TIMER velocity interrupt (TIM_Int) low velocity interrupt (LVEL_Int) encoder clock interrupt (ENCLK_Int) position 0 interrupt (POS0_Int) position 1 interrupt (POS1_Int) direction interrupt (DIR_Int) revolution interrupt (REV_Int) index interrupt (INX_Int) phase error interrupt (ERR_Int) VELOCITY RELOAD VELOCITY COMPARE VELOCITY CAPTURE VELOCITY COUNTER POSITION COMPARE 0 POSITION COUNTER POSITION COMPARE 1 INDEX COUNTER INDEX COMPARE INX ERR DIR CLK RST RST CLK

4.1 Input signals

and a direction signal to indicate the direction of rotation.). effects of the direction invert (DIRINV) bit.

4.1.1 Quadrature input signals

direction of rotation has changed. [1] All other state transitions are illegal and should set the ERR bit. DIR bit. When set = 1, the direction inversion bit (DIRINV) complements the DIR bit. Table 480. Encoder states Table 481. Encoder state transitions [1]

4.1.2 Digital input filtering

4.2 Position capture

of less range in the positional counter.

4.3 Velocity capture

Table 482. Encoder direction

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 544 of 835 NXP Semiconductors UM10360 Chapter 26: LPC17xx Quadrature Encoder Interface (QEI) number of edges counted in a given time period is directly proportional to the velocity of the encoder. Setting the reset velocity bit (RESV) has the same effect as an overflow of the velocity timer, except that the setting the RESV bit will not generate a velocity interrupt. The following equation converts the velocity counter value into an RPM value: RPM = (PCLK * QEICAP * 60) ÷ (QEILOAD * PPR * Edges) where:

PCLK is the peripheral clock rate for the QEI block. See Section 4–7.3 for more on the possibilities for PCLK).
QEICAP is the captured velocity counter value for the last velocity timer period.
QEILOAD is the velocity timer reload value.
PPR is the number of pulses per revolution of the physical encoder used in the application
Edges is 2 or 4, based on the capture mode set in the QEICON register (2 for CapMode set to 0 and 4 for CapMode set to 1) For example, consider a motor running at 600 RPM. A 2048 pulse per revolution quadrature encoder is attached to the motor, producing 8192 phase edges per revolution (PPR * Edges). This results in 81,920 pulses per second (the motor turns 10 times per second at 600 RPM and there are 8092 edges per revolution). If the timer were clocked at 10,000 Hz, and the QEILOAD was 2,500 (corresponding to ¼ of a second), it would count 20,480 pulses per update. Using the above equation: RPM = (10000 * 1 * 20480 * 60) ÷ (2500 * 2048 * 4) = 600 RPM Now, consider that the motor is sped up to 3000 RPM. This results in 409,600 pulses per second, or 102,400 every ¼ of a second. Again, the above equation gives: RPM = (10000 * 1 * 102400 * 60) ÷ (2500 * 2048 * 4) = 3000 RPM These are simple examples, real-world values will have a higher rate for PCLK, and probably a larger value for QEILOAD as well.

4.4 Velocity compare

In addition to velocity capture, the velocity measurement system includes a programmable velocity compare register. After every velocity capture event the contents of the velocity capture register (QEICAP) is compared with the contents of the velocity compare register (VELCOMP). If the captured velocity is less than the compare value an interrupt is asserted provided that the velocity compare interrupt enable bit is set. This can be used to determine if a motor shaft is either stalled or moving too slow.

UM10360_1 © NXP B.V. 2010. All rights reserved. control, the QEI is an alternative to feedback directly to the MCPWM. Table 483. QEI pin description MCI0 [1] I Used as the Phase A (PhA) input to the Quadrature Encoder Interface. MCI1 [1] I Used as the Phase B (PhB) input to the Quadrature Encoder Interface. MCI2 [1] I Used as the Index (IDX) input to the Quadrature Encoder Interface.

6.1 Register summary

Table 484. QEI Register summary

6.2 Control registers

6.2.1 QEI Control register (QEICON - 0x400B C000)

This register contains bits which control the operation of the position and velocity counters of the QEI module.

6.2.2 QEI Configuration register (QEICONF - 0x400B C008)

This register contains the configuration of the QEI module.

6.2.3 QEI Status register (QEISTAT - 0x400B C004)

This register provides the status of the encoder interface. Table 485: QEI Control regi ster (QEICON - address 0x400B C000) bit description Bit Symbol Description Reset value 0 RESP Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared. 1 RESPI Reset position coun ter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared. 2 RESV Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared. 3 RESI Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared. 31:4 - reserved 0 Table 486: QEI Configuration register (QEI CONF - address 0x400B C008) bit description Bit Symbol Description Reset value 0 DIRINV Direction invert. When = 1, complements the DIR bit. 0 1 SIGMODE Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal. 2 CAPMODE Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range. 3 INVINX Invert Index. When set, inverts the sense of the index input. 0 31:4 - reserved 0 Table 487: QEI Interrupt Status register (QEISTAT - address 0x400B C004) bit description Bit Symbol Description Reset value 0 DIR Direction bit. In combinati on with DIRINV bit indicates forward or reverse direction. See Table 26–482. 31:1 - reserved 0

6.3 Position, index and timer registers

6.3.1 QEI Position register (QEIPOS - 0x400B C00C)

This register contains the current value of the encoder position. Increments or decrements when encoder counts occur, depending on the direction of rotation.

6.3.2 QEI Maximum Position register (QEIMAXPOS - 0x400B C010)

This register contains the maximum value of the encoder position. In forward rotation the position register resets to zero when the position register exceeds this value. In reverse rotation the position register resets to this value when the position register decrements from zero.

6.3.3 QEI Position Compare register 0 (CMPOS0 - 0x400B C014)

6.3.4 QEI Position Compare register 1 (CMPOS1 - 0x400B C018)

This register contains a position compare value. This value is compared against the current value of the position register. Interrupts can be enabled to interrupt when the compare value is equal to the current value of the position register. Table 488: QEI Position re gister (QEIPOS - address 0x400B C00C) bit description Bit Symbol Description Reset value 31:0 - Current position value. 0 Table 489: QEI Maximum Position register (Q EIMAXPOS - address 0x400B C010) bit description Bit Symbol Description Reset value 31:0 - Current maximum position value. 0 Table 490: QEI Position Compare register 0 (CMPOS0 - address 0x400B C014) bit description Bit Symbol Description Reset value 31:0 - Current position value. 0 Table 491: QEI Position Compare register 1 (CMPOS1 - address 0x400B C018) bit description Bit Symbol Description Reset value 31:0 - Current position value. 0

6.3.5 QEI Position Compare register 2 (CMPOS2 - 0x400B C01C)

6.3.6 QEI Index Count register (INXCNT - 0x400B C020)

This register contains the current value of the encoder position. Increments or decrements when encoder counts occur, depending on the direction of rotation.

6.3.7 QEI Index Compare register (INXCMP - 0x400B C024)

This register contains an index compare value. This value is compared against the current value of the index count register. Interrupts can be enabled to interrupt when the compare value is equal to the current value of the index count register.

6.3.8 QEI Timer Reload register (QEILOAD - 0x400B C028)

This register contains the reload value of the velocity timer. When the timer (QEITIME) overflows or the RESV bit is asserted, this value is loaded into the timer (QEITIME).

6.3.9 QEI Timer register (QEITIME - 0x400B C02C)

This register contains the current value of the velocity timer. When this timer overflows the value of velocity counter (QEIVEL) is stored in the velocity capture register (QEICAP), the velocity counter is reset to zero, the timer is reloaded with the value stored in the velocity reload register (QEILOAD), and the velocity interrupt (TIM_Int) is asserted. Table 492: QEI Position Compare register 2 (CMPOS2 - address 0x400B C01C) bit description Bit Symbol Description Reset value 31:0 - Current position value. 0 Table 493: QEI Index Count register (CMPOS - address 0x400B C020) bit description Bit Symbol Description Reset value 31:0 - Current position value. 0 Table 494: QEI Index Compare register (CMPOS - address 0x400B C024) bit description Bit Symbol Description Reset value 31:0 - Current position value. 0 Table 495: QEI Timer Load register (QEILOAD - address 0x400B C028) bit description Bit Symbol Description Reset value 31:0 - Current velocity timer load value. 0 Table 496: QEI Timer register (QEITIME - address 0x400B C02C) bit description Bit Symbol Description Reset value 31:0 - Current velocity timer value. 0

6.3.10 QEI Velocity register (QEIVEL - 0x400B C030)

This register contains the running count of velocity pulses for the current time period. When the velocity timer (QEITIME) overflows the contents of this register is captured in the velocity capture register (QEICAP). After capture, this register is set to zero. This register is also reset when the velocity reset bit (RESV) is asserted.

6.3.11 QEI Velocity Capture register (QEICAP - 0x400B C034)

This register contains the most recently measured velocity of the encoder. This corresponds to the number of velocity pulses counted in the previous velocity timer period.The current velocity count is latched into this register when the velocity timer overflows.

6.3.12 QEI Velocity Compare register (VELCOMP - 0x400B C038)

This register contains a velocity compare value. This value is compared against the captured velocity in the velocity capture register. If the capture velocity is less than the value in this compare register, a velocity compare interrupt (VELC_Int) will be asserted, if enabled.

6.3.13 QEI Digital Filter register (FILTER - 0x400B C03C)

This register contains the sampling count for the digital filter. A sampling count of zero bypasses the filter. Table 497: QEI Velocity register (QEIVEL - address 0x400B C030) bit description Bit Symbol Description Reset value 31:0 - Current velocity pulse count. 0 Table 498: QEI Velocity Capture register (QEICAP - address 0x400B C034) bit description Bit Symbol Description Reset value 31:0 - Current velocity pulse count. 0 Table 499: QEI Velocity Compare register (VELCOMP - address 0x400B C038) bit description Bit Symbol Description Reset value 31:0 - Current velocity pulse count. 0 Table 500: QEI Digital Filter register (FILTER - address 0x400B C03C) bit description Bit Symbol Description Reset value 31:0 - Digital filter sampling delay 0x0

6.4 Interrupt registers

6.4.1 QEI Interrupt Status register (QEIINTSTAT)

This register provides the status of the encoder interface and the current set of interrupt sources that are asserted to the controller. Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question has not occurred. Writing a 0 to a bit position clears the corresponding interrupt.

6.4.2 QEI Interrupt Set register (QEISET - 0x400B CFEC)

Writing a one to a bit in this register sets the corresponding bit in the QEI Interrupt Status register (QEISTAT). Table 501: QEI Interrupt Status register (QEIINTSTAT - address 0x400B CFE0) bit description Bit Symbol Description Reset value 0 INX_Int Indicates that an index pulse was detected. 0

1 TIM_Int Indicates that a velo city timer overflow occurred 0

2 VELC_Int Indicates that captured velocity is less than compare velocity. 0 3 DIR_Int Indicates that a change of direction was detected. 0 4 ERR_Int Indicates that an encoder phase error was detected. 0 5 ENCLK_Int Indicates that and enc oder clock pulse was detected. 6 POS0_Int Indicates that the position 0 compare value is equal to the current position. 0 7 POS1_Int Indicates that the po sition 1compare value is equal to the current position. 0 8 POS2_Int Indicates that the position 2 compare value is equal to the current position. 0 9 REV_Int Indicates that the index compare va lue is equal to the current index count. 0 10 POS0REV_Int Combined position 0 and revolution coun t interrupt. Set when both the POS0_Int bit is set and the REV_Int is set. 11 POS1REV_Int Combined position 1 and revolution coun t interrupt. Set when both the POS1_Int bit is set and the REV_Int is set. 12 POS2REV_Int Combined position 2 and revolution coun t interrupt. Set when both the POS2_Int bit is set and the REV_Int is set. 31:13 - reserved 0 Table 502: QEI Interrupt Set register (QEISET - address 0x400B CFEC) bit description Bit Symbol Description Reset value 0 INX_Int Indicates that an index pulse was detected. 0

1 TIM_Int Indicates that a velocity timer overflow occurred 0

6.4.3 QEI Interrupt Clear register (QEICLR - 0x400B CFE8)

Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Status register (QEISTAT).

6.4.4 QEI Interrupt Enable register (QEIIE - 0x400B CFE4)

This register enables interrupt sources. Bits set to 1 enable the corresponding interrupt; a 0 bit disables the corresponding interrupt. 10 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set. 11 POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set. 12 POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set. 31:13 - reserved 0 Table 502: QEI Interrupt Set register (QEISET - address 0x400B CFEC) bit description Bit Symbol Description Reset value Table 503: QEI Interrupt Clear register (QEICLR - 0x400B CFE8) bit description Bit Symbol Description Reset value 0 INX_Int Indicates that an index pulse was detected. 0 2 VELC_Int Indicates that captured velocity is less than compare velocity. 0 3 DIR_Int Indicates that a change of direction was detected. 0 4 ERR_Int Indicates that an encoder phase error was detected. 0 5 ENCLK_Int Indicates that and enc oder clock pulse was detected. 6 POS0_Int Indicates that the position 0 compar e value is equal to the current position. 0 7 POS1_Int Indicates that the po sition 1compare value is equal to the current position. 0 8 POS2_Int Indicates that the position 2 compar e value is equal to the current position. 0 9 REV_Int Indicates that the index compare va lue is equal to the current index count. 0 10 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set. 11 POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set. 12 POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set. 31:13 - reserved 0 Table 504: QEI Interrupt Enable register (Q EIIE - address 0x400B CFE4) bit description Bit Symbol Description Reset value 0 INX_Int Indicates that an index pulse was detected. 0 2 VELC_Int Indicates that captured velocity is less than compare velocity. 0 3 DIR_Int Indicates that a change of direction was detected. 0

6.4.5 QEI Interrupt Enable Set register (QEIIES - 0x400B CFDC)

Writing a 1 to a bit in this register sets the corresponding bit in the QEI Interrupt Enable register (QEIIE). 4 ERR_Int Indicates that an encoder phase error was detected. 0 5 ENCLK_Int Indicates that and enc oder clock pulse was detected. 0 6 POS0_Int Indicates that the position 0 compare value is equal to the current position. 0 7 POS1_Int Indicates that the po sition 1compare value is equal to the current position. 0 8 POS2_Int Indicates that the position 2 compare value is equal to the current position. 0 9 REV_Int Indicates that the index compare va lue is equal to the current index count. 0 10 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set. 11 POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set. 12 POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set. 31:13 - reserved 0 Table 504: QEI Interrupt Enable register (Q EIIE - address 0x400B CFE4) bit description Bit Symbol Description Reset value Table 505: QEI Interrupt Enable Set register (QEIIES - address 0x400B CFDC) bit description Bit Symbol Description Reset value 0 INX_EN Indicates that an index pulse was detected. 0

1 TIM_EN Indicates that a velocity timer overflow occurred 0

2 VELC_EN Indicates that captured velo city is less than compare velocity. 0 3 DIR_EN Indicates that a change of direction was detected. 0 4 ERR_EN Indicates that an enc oder phase error was detected. 0 5 ENCLK_EN Indicates that and enc oder clock pulse was detected. 0 6 POS0_Int Indicates that the position 0 compare value is equal to the current position. 0 7 POS1_Int Indicates that the po sition 1compare value is equal to the current position. 0 8 POS2_Int Indicates that the position 2 compare value is equal to the current position. 0 9 REV_Int Indicates that the index compare va lue is equal to the current index count. 0 10 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set. 11 POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set. 12 POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set. 31:13 - reserved 0

6.4.6 QEI Interrupt Enable Clear register (QEIIEC - 0x400B CFD8)

Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Enable register (QEIIE). Table 506: QEI Interrupt Enable Clear register (QEIIEC - address 0x400B CFD8) bit description Bit Symbol Description Reset value 0 INX_EN Indicates that an index pulse was detected. 0 2 VELC_EN Indicates that captured velo city is less than compare velocity. 0 3 DIR_EN Indicates that a change of direction was detected. 0 4 ERR_EN Indicates that an enc oder phase error was detected. 0 5 ENCLK_EN Indicates that and enc oder clock pulse was detected. 0 6 POS0_Int Indicates that the position 0 compar e value is equal to the current position. 0 7 POS1_Int Indicates that the po sition 1compare value is equal to the current position. 0 8 POS2_Int Indicates that the position 2 compar e value is equal to the current position. 0 9 REV_Int Indicates that the index compare va lue is equal to the current index count. 0 10 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set. 11 POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set. 12 POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set. 31:13 - reserved 0

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 555 of 835 1. Basic configuration The RTC is configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set bits PCRTC. Remark: On reset, the RTC is enabled. See Section 27–7 for power saving options. 2. Clock: The RTC uses the 1 Hz clock output from the RTC oscillator as the only clock source. The peripheral clock rate for accessing registers is CCLK/8. 3. Interrupts: See Section 27–6.1 for RTC interrupt handling. Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 2. Features

Measures the passage of time to maintain a calendar and clock. Provides seconds, minutes, hours, day of month, month, year, day of week, and day of year.
Ultra-low power design to support battery powered systems. Less than 1 microamp required for battery operation. Uses power from the CPU power supply when it is present.
20 bytes of Battery-backed storage and RTC operation when power is removed from the CPU.
Dedicated 32 kHz ultra low power oscillator.
Dedicated battery power supply pin.
RTC power supply is isolated from the rest of the chip.
Calibration counter allows adjustment to better than ±1 sec/day with 1 sec resolution.
Periodic interrupts can be generated from increments of any field of the time registers and selected fractional second values.
Alarm interrupt can be generated for a specific date/time. 3. Description The Real Time Clock (RTC) is a set of counters for measuring time when system power is on, and optionally when it is off. It uses very little power when its registers are not being accessed by the CPU, especially reduced power modes. On the LPC17xx, the RTC is clocked by a separate 32 kHz oscillator that produces a 1 Hz internal time reference. The RTC is powered by its own power supply pin, VBAT, which can be connected to a battery, externally tied to a 3V supply, or left floating. The RTC power domain is shown in conceptual form in Figure 27–129 . A detailed view of the time keeping portion of the RTC is shown in Figure 27–130. UM10360 Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers Rev. 01 — 4 January 2010 User manual

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 556 of 835 NXP Semiconductors UM10360 Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers 4. Architecture Fig 129. RTC domain conceptual diagram VBAT pin Ultra-low power regulator Power selector VDD(REG)(3v3) pin Ultra-low power oscillator to main regulator

1 Hz clock

& Interrupt Fig 130. RTC functional block diagram day of year second minute hour day month year alarm compare second minute hour day month year day of week calibration counter calibration compare register calibration control logic calibration compare sign bit match counter reset LSB set LSB out Time Registers Alarm Registers Calibration Alarm out and Alarm Interrupts Counter Increment Interrupts 1 Hz Clock

UM10360_1 © NXP B.V. 2010. All rights reserved. registers are split into five sections by functionality. Table 507. RTC pin description RTCX1 I Input to the RTC oscillator circuit. RTCX2 O Output from the RTC oscillator circuit. Remark: If the RTC is not used, the RTCX1/2 pins can be left floating. powered, the RTC is still powered internally if VDD(REG)(3V3) is present.

UM10360_1 © NXP B.V. 2010. All rights reserved. [1] Reset values apply only to a power-up of the RTC block, other types of reset have no effect on this block. reflects the data stored in used bits only. It does not include reserved bits content. Table 508. Real-Time Clock register map

6.1 RTC interrupts

counter, then an interrupt is generated. Section 4–9 “Wake-up timer” on page 66.

6.2 Miscellaneous register group

6.2.1 Interrupt Location Register (ILR - 0x4002 4000)

6.2.2 Clock Control R egister (CCR - 0x4002 4008)

The clock register is a 4-bit register that controls the operation of the clock divide circuit. should be initialized when the RTC is first turned on. Table 509. Interrupt Location Register (ILR - address 0x4002 4000) bit description location clears the counter increment interrupt. Table 510. Clock Control Register (CCR - address 0x4002 4008) bit description 1 The time counters are enabled. 0 The time counters are disabled so that they may be initialized.

6.2.3 Counter Increment Interrupt Register (CIIR - 0x4002 400C)

1 to bit 0 of the Interrupt Location Register (ILR[0]).

6.2.4 Alarm Mask Register (AMR - 0x4002 4010)

The Alarm Mask Register (AMR) allows the user to mask any of the alarm registers. set, then the alarm is disabled.

1 When one, the elements in the internal oscillator divider are reset, and remain reset until

32.768 kHz crystal. The state of the divider is not visible to software. 1 The calibration counter is disabled and reset to zero. reserved bit is not defined. Table 511. Counter Increment Interrupt Register (CIIR - address 0x4002 400C) bit description

6.2.5 RTC Auxiliary control register (RTC_AUX - 0x4002 405C)

6.2.6 RTC Auxiliary Enable register (RTC_AUXEN - 0x4002 4058)

represented in the RTC Auxiliary control register are enabled. Table 512. Alarm Mask Register (AMR - address 0x4002 4010) bit description reserved bit is not defined. Table 513. RTC Auxiliary control register (RTC_AUX - address 0x4002 405C) bit description reserved bit is not defined. 4 RTC_OSCF RTC Oscillator Fail detect flag. RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag. reserved bit is not defined. reserved bit is not defined. 4 RTC_OSCFEN Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 27–6.2.5. reserved bit is not defined.

6.3 Consolidated time registers

Counters, the Time Counter addresses should be used.

6.3.1 Consolidated Time Register 0 (CTIME0 - 0x4002 4014)

6.3.2 Consolidated Time Register 1 (CTIME1 - 0x4002 4018)

The Consolidate Time Register 1 contains the Day of Month, Month, and Year values.

6.3.3 Consolidated Time Register 2 (CTIME2 - 0x4002 401C)

The Consolidate Time Register 2 contains just the Day of Year value. Table 515. Consolidated Time register 0 (CTIME0 - address 0x4002 4014) bit description reserved bit is not defined. reserved bit is not defined. reserved bit is not defined. reserved bit is not defined. Table 516. Consolidated Time register 1 (CTIME1 - address 0x4002 4018) bit description reserved bit is not defined. reserved bit is not defined. reserved bit is not defined.

6.4 Time Counter Group

The time value consists of the eight counters shown in Table 27–518 and Table 27–519. These counters can be read or written at the locations shown in Table 27–519. [1] These values are simply incremented at the appropriate intervals and reset at the defined overflow point. They are not calculated and must be correctly initialized in order to be meaningful.

6.4.1 Leap year calculation

of month, and year counters.

6.4.2 Calibration register (CALIBRATION - address 0x4002 4040)

The following register is used to calibrate the time counter. Table 517. Consolidated Time register 2 (CTIME2 - address 0x4002 401C) bit description reserved bit is not defined. Table 518. Time Counter relationships and values Table 519. Time Counter registers

6.5 Calibration procedure

externally trim the RTC oscillator. by one second. That value is used to determine CALVAL. RTC oscillator frequency may be helpful in that process.

The SEC timer and the calibration counter count up for every 1 Hz clock cycle.
When the calibration counter reaches CALVAL, a calibration match occurs and all RTC timers will be stopped for one clock cycle so that the timers will not increment in the next cycle.
If an alarm match event occurs in the same cycle as the calibration match, the alarm interrupt will be delayed by one cycle to avoid a double alarm interrupt. Forward calibration Enable the RTC timer and calibration in the CCR register (set bits CLKEN = 1 and CCALEN = 0). In the CALIBRATION register, set the calibration value CALVAL ≥ 1 and select CALDIR = 0.
The SEC timer and the calibration counter count up for every 1 Hz clock cycle.
When the calibration counter reaches CALVAL, a calibration match occurs and the RTC timers are incremented by 2.
When the calibration event occurs, the LSB of the ALSEC register is forced to be one so that the alarm interrupt will not be missed when skipping a second.

Table 520. Calibration register (CALIBRATION - address 0x4002 4040) bit description 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0.

17 CALDIR Calibration direction NC

timers will stop incrementing for 1 second. reserved bit is not defined.

6.6 General purpose registers

6.6.1 General purpose registers 0 to 4 (GPREG0 to GPREG4 - addresses

off. The value in these registers is not affected by chip reset.

6.7 Alarm register group

bit 1 of the Interrupt Location Register (ILR[1]). Table 521. General purpose registers 0 to 4 (GPREG0 to GPREG4 - addresses 0x4002 4044 Table 522. Alarm registers

Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate Watchdog reset.
Programmable 32-bit timer with internal pre-scaler.
Selectable time period from (TWDCLK × 256 × 4) to (TWDCLK × 232 × 4) in multiples of TWDCLK × 4.
The Watchdog clock (WDCLK) source can be selected from the Internal RC oscillator (IRC), the APB peripheral clock (PCLK, see Table 4–40), or the RTC oscillator. This gives a wide range of potential timing choices for Watchdog operation under different power reduction conditions. For increased reliability, it also provides the ability to run the Watchdog timer from an entirely internal source that is not dependent on an external crystal and its associated components and wiring.
The Watchdog timer can be configured to run in Deep Sleep mode when using the IRC as the clock source. 2. Applications The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the Watchdog will generate a system reset if the user program fails to "feed" (or reload) the Watchdog within a predetermined amount of time. For interaction of the on-chip watchdog and other peripherals, especially the reset and boot-up procedures, please read Section 3–4 “ Reset” on page 18 of this document. UM10360 Chapter 28: LPC17xx Watchdog Timer (WDT) Rev. 01 — 4 January 2010 User manual

Set the Watchdog timer constant reload value in WDTC register.
Setup the Watchdog timer operating mode in WDMOD register.
Enable the Watchdog by writing 0xAA followed by 0x55 to the WDFEED register.
The Watchdog should be fed again before the Watchdog counter underflows to prevent reset/interrupt. When the Watchdog is in the reset mode and the counter underflows, the CPU will be reset, loading the stack pointer and program counter from the vector table as in the case of external reset. The Watchdog time-out flag (WDTOF) can be examined to determine if the Watchdog has caused the reset condition. The WDTOF flag must be cleared by software. The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB accesses to the watchdog registers. The WDCLK is used for the watchdog timer counting. There is some synchronization logic between these two clock domains. When the WDMOD and WDTC registers are updated by APB operations, the new value will take effect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog timer is counting on WDCLK, the synchronization logic will first lock the value of the counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV register by the CPU. 4. Register description The Watchdog contains 4 registers as shown in Table 28–523 below. [1] Reset Value reflects the data stored in used bi ts only. It does not include reserved bits content.

Table 523. Watchdog register map status of the Watchdog Timer. register reloads the Watchdog timer with the value contained in WDTC.

4.1 Watchdog Mode regi ster (WDMOD - 0x4000 0000)

changes to the WDMOD register take effect. flags are cleared by an external reset or a Watchdog timer underflow. the device when the watchdog overflows. reserved bit is not defined. Table 525. Watchdog operating modes selection 0 X (0 or 1) Debug/Operate without the Watchdog running. 1 0 Watchdog interrupt mode: debug with the Watchdog interrupt but no WDRESET enabled. Watchdog interrupt request will be generated. 1 1 Watchdog reset mode: operate with the Watchdog interrupt and WDRESET enabled. watchdog reset will clear the WDINT flag.

4.2 Watchdog Timer Constant register (WDTC - 0x4000 0004)

The WDTC register determines the time-out value. Every time a feed sequence occurs the WDTC content is reloaded in to the Watchdog timer. It’s a 32-bit register with 8 LSB set to 1 on reset. Writing values below 0xFF will cause 0x0000 00FF to be loaded to the WDTC. Thus the minimum time-out interval is TWDCLK × 256 × 4.

4.3 Watchdog Feed regi ster (WDFEED - 0x4000 0008)

Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the Watchdog. A valid feed sequence must be completed after setting WDEN before the Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing 0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled. The reset will be generated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence. Interrupts should be disabled during the feed sequence. An abort condition will occur if an interrupt happens during the feed sequence.

4.4 Watchdog Timer Value re gister (WDTV - 0x4000 000C)

The WDTV register is used to read the current value of Watchdog timer. When reading the value of the 32-bit timer, the lock and synchronization procedure takes up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual value of the timer when it's being read by the CPU.

4.5 Watchdog Timer Cloc k Source Selection register (WDCLKSEL -

0x4000 0010) This register allows selecting the clock source for the Watchdog timer. The possibilities are the Internal RC oscillator (IRC) or the APB peripheral clock (pclk). The function of bits in WDCLKSEL are shown in Table 28–529. The clock source selection can be locked by software, so that it cannot be modified. On reset, the clock source selection bits are always unlocked. Table 526: Watchdog Constant register (WDTC - address 0x4000 0004) bit description Bit Symbol Description Reset Value 31:0 Count Watchdog time-out interval. 0x0000 00FF Table 527: Watchdog Feed register (WDFEED - address 0x4000 0008) bit description Bit Symbol Description Reset Value 7:0 Feed Feed value should be 0xAA followed by 0x55. NA 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 528: Watchdog Timer Value register (WDTV - address 0x4000 000C) bit description Bit Symbol Description Reset Value 31:0 Count Counter timer value. 0x0000 00FF

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 570 of 835 NXP Semiconductors UM10360 Chapter 28: LPC17xx Watchdog Timer (WDT) When the IRC is chosen as the watchdog clock source, the watchdog timer can remain running in deep sleep mode, and can reset or wake up the device from that mode. 5. Block diagram The block diagram of the Watchdog is shown below in the Figure 28–131. The synchronization logic (PCLK - WDCLK) is not shown in the block diagram. Table 529: Watchdog Timer Clock Source Selection register (WDCLKSEL - address 0x4000 0010) bit description Bit Symbol Value Description Reset Value 1:0 WDSEL These bits select the clock source for the Watchdog timer as described below. Warning: Improper setting of this value may result in incorrect operation of the Watchdog timer, which could adversely affect system operation. If the WDLOCK bit in this register is set, the WDSEL bit cannot be modified. 00 Selects the Internal RC oscillator (irc_clk) as the Watchdog clock source (default). 01 Selects the APB peripheral clock (watchdog pclk) as the Watchdog clock source. 10 Selects the RTC oscillator (rtc_clk) as the Watchdog clock source. 11 Reserved, this setting should not be used. 30:2 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 31 WDLOCK 0 This bit is set to 0 on any reset. It cannot be cleared by software. 0 1 Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register cannot be modified. Fig 131. Watchdog block diagram WDTC 32-BIT DOWN COUNTER WDINT WDTOF WDRESET WDEN SHADOW BIT reset interrupt ÷ 4 WDFEED WDCLKSEL pclk RTC oscillator internal RC oscillator feed ok feed error wdclk underflow enable count WMOD register feed sequence WDTV

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 571 of 835 1. Basic configuration The ADC is configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set the PCADC bit. Remark: On reset, the ADC is disabled. To enable the ADC, first set the PCADC bit, and then enable the ADC in the AD0CR register (bit PDN Table 29–532). To disable the ADC, first clear the PDN bit, and then clear the PCADC bit. 2. Clock: In the PCLKSEL0 register ( Table 4–40), select PCLK_ADC. To scale the clock for the ADC, see bits CLKDIV in Table 29–532. 3. Pins: Enable ADC0 pins through PINSEL r egisters. Select the pin modes for the port pins with ADC0 functions through the PINMODE registers (Section 8–5). 4. Interrupts: To enable in terrupts in the ADC, see Table 29–536. Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. Disable the ADC interrupt in the NVIC using the appropriate Interrupt Set Enable register. 5. DMA: See Section 29–6.4. For GPDMA system connections, see Table 31–544. 2. Features

12-bit successive approximation analog to digital converter.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage level).
12-bit conversion rate of 200 kHz.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal. 3. Description Basic clocking for the A/D converters is provided by the APB clock. A programmable divider is included in each converter to scale this clock to the clock (maximum 13 MHz) needed by the successive approximation process. A fully accurate conversion requires 65 of these clocks. UM10360 Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) Rev. 01 — 4 January 2010 User manual

UM10360_1 © NXP B.V. 2010. All rights reserved. Table 29–530 gives a brief summary of each of ADC related pins. Table 530. ADC pin description AD0.7 to AD0.0 Input Analog Inputs. The ADC cell can measure the voltage on any of these input signals. selected on that pin in the Pin Select register. used as 5 V tolerant digital IO pins. the ADC and DAC are not used. VDD(3V3) and VSSA should be tied to VSS if the ADC and DAC are not used.

UM10360_1 © NXP B.V. 2010. All rights reserved. The A/D Converter registers are shown in Table 29–531. [1] Reset value reflects the data stored in used bits only. It does not include reserved bits content. Table 531. ADC registers operating mode before A/D conversion can occur. the result of the most recent A/D conversion. contributing to the generation of an A/D interrupt. recent conversion completed on channel 0. recent conversion completed on channel 1. recent conversion completed on channel 2. recent conversion completed on channel 3. recent conversion completed on channel 4. recent conversion completed on channel 5. recent conversion completed on channel 6. recent conversion completed on channel 7. for all of the A/D channels, as well as the A/D interrupt/DMA flag.

5.1 A/D Control Regist er (AD0CR - 0x4003 4000)

Table 532: A/D Control Register (AD0CR - address 0x4003 4000) bit description Bit Symbol Value Description Reset value 7:0 SEL Selects which of the AD0.7:0 pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01. 0x01 15:8 CLKDIV The APB clock (PCLK_ADC0) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 13 MHz. Typically, software should program the smallest value in this field that yields a clock of 13 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.

16 BURST 1 The AD converter does repeated conversions at up to 200 kHz, scanning (if necessary)

through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that’s in progress when this bit is cleared will be completed. Remark: START bits must be 000 when BURST = 1 or conversions will not start. 0 Conversions are software controlled and require 65 clocks. 20:17 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 21 PDN 1 The A/D converter is operational. 0 0 The A/D converter is in power-down mode. 23:22 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 26:24 START When the BURST bit is 0, these bits control whether and when an A/D conversion is started: 000 No start (this value should be used when clearing PDN to 0). 001 Start conversion now. 010 Start conversion when the edge selected by bit 27 occurs on the P2.10 / EINT0 / NMI pin. 011 Start conversion when the edge selected by bit 27 occurs on the P1.27 / CLKOUT / USB_OVRCRn / CAP0.1 pin. 100 Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin. 101 Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin. 110 Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin. 111 Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin. 27 EDGE This bit is significant only when the START field contains 010-111. In these cases: 0 1 Start conversion on a falling edge on the selected CAP/MAT signal. 0 Start conversion on a rising edge on the selected CAP/MAT signal. 31:28 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

5.2 A/D Global Data Regi ster (AD0GDR - 0x4003 4004)

The A/D Global Data Register holds the result of the most recent A/D conversion that has completed, and also includes copies of the status flags that go with that conversion. Results of ADC conversion can be read in one of two ways. One is to use the A/D Global Data Register to read all data from the ADC. Another is to use the A/D Channel Data Registers. It is important to use one method consistently because the DONE and OVERRUN flags can otherwise get out of synch between the AD0GDR and the A/D Channel Data Registers, potentially causing erroneous interrupts or DMA activity.

5.3 A/D Interrupt Enable re gister (AD0INTEN - 0x4003 400C)

This register allows control over which A/D channels generate an interrupt when a conversion is complete. For example, it may be desirable to use some A/D channels to monitor sensors by continuously performing conversions on them. The most recent results are read by the application program whenever they are needed. In this case, an interrupt is not desirable at the end of each conversion for some A/D channels. Table 533: A/D Global Data Register (AD0GDR - address 0x4003 4004) bit description Bit Symbol Description Reset value 3:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 15:4 RESULT When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0x3FF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. NA 23:16 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 26:24 CHN These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...). NA 29:27 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

30 OVERRUN This bit is 1 in burst mode if the resu lts of one or more conversions was (were) lost

and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register. 31 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. Table 534: A/D Status register (AD0INTEN - address 0x4003 400C) bit description Bit Symbol Value Description Reset value 0 ADINTEN0 0 Completion of a conversion on ADC channel 0 will not generate an interrupt. 0 1 Completion of a conversion on ADC channel 0 will generate an interrupt. 1 ADINTEN1 0 Completion of a conversion on ADC channel 1 will not generate an interrupt. 0 1 Completion of a conversion on ADC channel 1 will generate an interrupt. 2 ADINTEN2 0 Completion of a conversion on ADC channel 2 will not generate an interrupt. 0 1 Completion of a conversion on ADC channel 2 will generate an interrupt.

5.4 A/D Data Registers (AD0DR0 to AD0DR7 - 0x4003 4010 to

0x4003 402C) The A/D Data Registers hold the result of the last conversion for each A/D channel, when an A/D conversion is complete. They also include the flags that indicate when a conversion has been completed and when a conversion overrun has occurred. Results of ADC conversion can be read in one of two ways. One is to use the A/D Global Data Register to read all data from the ADC. Another is to use the A/D Channel Data Registers. It is important to use one method consistently because the DONE and OVERRUN flags can otherwise get out of synch between the AD0GDR and the A/D Channel Data Registers, potentially causing erroneous interrupts or DMA activity. 3 ADINTEN3 0 Completion of a conversion on ADC channel 3 will not generate an interrupt. 0 1 Completion of a conversion on ADC channel 3 will generate an interrupt. 4 ADINTEN4 0 Completion of a conversion on ADC channel 4 will not generate an interrupt. 0 1 Completion of a conversion on ADC channel 4 will generate an interrupt. 5 ADINTEN5 0 Completion of a conversion on ADC channel 5 will not generate an interrupt. 0 1 Completion of a conversion on ADC channel 5 will generate an interrupt. 6 ADINTEN6 0 Completion of a conversion on ADC channel 6 will not generate an interrupt. 0 1 Completion of a conversion on ADC channel 6 will generate an interrupt. 7 ADINTEN7 0 Completion of a conversion on ADC channel 7 will not generate an interrupt. 0 1 Completion of a conversion on ADC channel 7 will generate an interrupt.

8 ADGINTEN 0 Only the individual ADC channels enabled by ADINTEN7:0 will generate

interrupts. 1 Only the global DONE flag in ADDR is enabled to generate an interrupt. 31:17 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 534: A/D Status register (AD0INTEN - address 0x4003 400C) bit description Bit Symbol Value Description Reset value Table 535: A/D Data Registers (AD0DR0 to AD0DR7 - 0x4003 4010 to 0x4003 402C) bit description Bit Symbol Description Reset value 3:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 15:4 RESULT When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of V REFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0x3FF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. NA 29:16 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

30 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and

overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register. 31 DONE This bit is set to 1 when an A/D conversion co mpletes. It is cleared when this register is read. NA

5.5 A/D Status regist er (ADSTAT - 0x4003 4030)

The A/D Status register allows checking the status of all A/D channels simultaneously. The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found in ADSTAT.

5.6 A/D Trim regist er (ADTRIM - 0x4003 4034)

This register will be set by the bootcode on start-up. It contains the trim values for the DAC and the ADC. The offset trim values for the ADC can be overwritten by the user. All 12 bits are visible when this register is read. Table 536: A/D Status register (AD0STAT - address 0x4003 4030) bit description Bit Symbol Description Reset value 0 DONE0 This bit mirrors the DONE status flag from the result register for A/D channel 0. 0 1 DONE1 This bit mirrors the DONE status flag from the result register for A/D channel 1. 0 2 DONE2 This bit mirrors the DONE status flag from the result register for A/D channel 2. 0 3 DONE3 This bit mirrors the DONE status flag from the result register for A/D channel 3. 0 4 DONE4 This bit mirrors the DONE status flag from the result register for A/D channel 4. 0 5 DONE5 This bit mirrors the DONE status flag from the result register for A/D channel 5. 0 6 DONE6 This bit mirrors the DONE status flag from the result register for A/D channel 6. 0 7 DONE7 This bit mirrors the DONE status flag from the result register for A/D channel 7. 0 8 OVERRUN0 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0. 0 9 OVERRUN1 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1. 0 10 OVERRUN2 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2. 0 11 OVERRUN3 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3. 0 12 OVERRUN4 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4. 0 13 OVERRUN5 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5. 0 14 OVERRUN6 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6. 0 15 OVERRUN7 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7. 0 16 ADINT This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. 31:17 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Table 537: A/D Trim register (ADTRM - address 0x4003 4034) bit description Bit Symbol Description Reset value 3:0 - reserved. NA 7:4 ADCOFFS Offset trim bits for ADC operation. Initializ ed by the boot code. Can be overwritten by the user. 0 11:8 TRIM written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write. 31:12 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 578 of 835 NXP Semiconductors UM10360 Chapter 29: LPC17xx Analog-to-Digital Converter (ADC) 6. Operation Once an ADC conversion is started, it cannot be interrupted. A new software write to launch a new conversion or a new edge-trigger event will be ignored while the previous conversion is in progress.

6.1 Hardware-triggered conversion

If the BURST bit in the ADCR is 0 and the START field contains 010-111, the ADC will start a conversion when a transition occurs on a selected pin or Timer Match signal. The choices include conversion on a specified edge of any of 4 Match signals, or conversion on a specified edge of either of 2 Capture/Match pins. The pin state from the selected pad or the selected Match signal, XORed with ADCR bit 27, is used in the edge detection logic.

6.2 Interrupts

An interrupt request is asserted to the NVIC when the DONE bit is 1. Software can use the Interrupt Enable bit for the A/D Converter in the NVIC to control whether this assertion results in an interrupt. DONE is negated when the ADDR is read. 6.3 Accuracy vs. digital receiver The ADC function must be selected via the PINSEL registers in order to get accurate voltage readings on the monitored pin. The PINMODE should also be set to the mode for which neither pull-up nor pull-down resistor is enabled. For a pin hosting an ADC input, it is not possible to have a have a digital function selected and yet get valid ADC readings. An inside circuit disconnects ADC hardware from the associated pin whenever a digital function is selected on that pin.

6.4 DMA control

A DMA transfer request is generated from the ADC interrupt request line. To generate a DMA transfer the same conditions must be met as the conditions for generating an interrupt (see Section 29–6.2 and Section 29–5.3). Remark: If the DMA is used, the ADC interrupt must be disabled in the NVIC. For DMA transfers, only burst requests are supported. The burst size can be set to one in the DMA channel control register (see Section 31–5.20 ). If the number of ADC channels is not equal to one of the other DMA-supported burst sizes (applicable DMA burst sizes are 1, 4, 8 - see Section 31–5.20), set the burst size to one. The DMA transfer size determines when a DMA interrupt is generated. The transfer size can be set to the number of ADC channels being converted (see Section 31–5.20 Non-contiguous channels can be transferred by the DMA using the scatter/gather linked lists (see Section 31–5.19).

Power: The DAC is always connected to V DDA. Register access is determined by

PINSEL and PINMODE settings (see below).

Clock: In the PCLKSEL0 register ( Table 4–40), select PCLK_DAC.
Pins: Enable the DAC pin through the PINSEL registers. Select pin mode for port pin

accessing any DAC registers.

DMA: The DAC can be connected to the GPDMA controller (see Section 30–4.2). For

GPDMA connections, see Table 31–544.

10-bit digital to analog converter
Resistor string architecture
Buffered output
Power-down mode
Selectable speed vs. power
Maximum update rate of 1 MHz. 3. Pin description Table 30–538 gives a brief summary of each of DAC related pins. UM10360 Chapter 30: LPC17xx Digital-to-Analog Converter (DAC) Rev. 01 — 4 January 2010 User manual

Table 538. D/A Pin Description the voltage on this pin (with respect to VSSA) is VALUE × ((VREFP - VREFN)/1024) + VREFN. VREFP, VREFN Reference Voltage References. These pins provide a voltage reference level for the ADC and DAC. and VSSA should be tied to VSS if the ADC and DAC are not used.

4.1 D/A Converter Regist er (DACR - 0x4008 C000)

4.2 D/A Converter Control re gister (DACCTRL - 0x4008 C004)

This read/write register enables the DMA operation and controls the DMA timer. Table 539. DAC registers converted to analog and a power control bit. the DAC DMA/Interrupt timer. reserved bit is not defined. the AOUT pin (with respect to VSSA) is VALUE × ((VREFP - VREFN)/1024) + VREFN. a maximum update rate of 1 MHz. maximum update rate of 400 kHz. reserved bit is not defined.

4.3 D/A Converter Counter Value register (DACCNTVAL - 0x4008 C008)

This read/write register contains the reload value for the Interrupt/DMA counter.

5.1 DMA counter

DMA request bit INT_DMA_REQ will be set in hardware. accessible, but the timer itself is not accessible for either read or write.

5.2 Double buffering

same time the counter is reloaded with the COUNTVAL register value. contents of the pre-buffer register. Table 541. D/A Control regi ster (DACCTRL - address 0x4008 C004) bit description 1 This bit is set by hardware when the timer times out.

1 When this bit and the CNT_ENA bit are both set, the double-buffering feature in the

pre-buffer and then transferred to the DACR on the next time-out of the counter. 1 Time-out counter operation is enabled.

1 DMA Burst Request Input 7 is enabled for the DAC (see Table 31–544

from a reserved bit is not defined.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 582 of 835 NXP Semiconductors UM10360 Chapter 30: LPC17xx Digital-to-Analog Converter (DAC) If either the CNT_ENA or the DBLBUF_ENA bits are 0, any writes to the DACR address will go directly to the DACR register. Fig 132. DAC control with DMA interrupt and timer CNTVAL COUNTER PRE-BUFFER MUX DACR LD LD LDEN pbus pbus set_intrpt dblbuf_ena cnt_ena ena_cnt_and_dblbuf pbus_wr_to_DACR 1 0 pbus pbus pbus_wr_toDACR zero DAC value C set_intrpt pbus pbus_wr_to_DACR DMA_ena intrptDMA_req

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 583 of 835 1. Basic configuration The GPDMA is configured using the following registers: 1. Power: In the PCONP register ( Table 4–46), set bit PCGPDMA. Remark: On reset, the GPDMA is disabled (PCGPDMA = 0). 2. Clock: see Table 4–38. 3. Interrupts: Inte rrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register. 4. Programming: see Section 31–6. 2. Introduction The DMA controller allows peripheral-to memory, memory-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bi-directional port requires one stream for transmit and one for receives. The source and destination areas can each be either a memory region or a peripheral. 3. Features

Eight DMA channels. Each channel can support an unidirectional transfer.
16 DMA request lines.
Memory-to-memory, memory-to-peripheral, and peripheral-to-memory transfers are supported.
GPDMA supports the SSP, I2S, UART, A/D Converter, and D/A Converter peripherals. DMA can also be triggered by a timer match condition. Memory-to-memory transfers and transfers to or from GPIO are also supported.
Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory.
Hardware DMA channel priority.
AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface.
One AHB bus master for transferring data. The interface transfers data when a DMA request goes active.
32-bit AHB master bus width.
Incrementing or non-incrementing addressing for source and destination.
Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data.
Internal four-word FIFO per channel. UM10360 Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller Rev. 01 — 4 January 2010 User manual

Supports 8-bit, 16-bit, and 32-bit wide transactions.
Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset.
An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred.
Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking.
DMA can operate in Sleep mode. (Note that in Sleep mode the GPDMA cannot access the flash memory). 4. Functional description This section describes the major functional blocks of the DMA Controller.

4.1 DMA controller functional description

The DMA Controller enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. Figure 31–133 shows a block diagram of the DMA Controller. The functions of the DMA Controller are described in the following sections.

4.1.1 AHB slave interface

All transactions to DMA Controller registers on the AHB slave interface are 32 bits wide. 8-bit and 16-bit accesses are not supported and will result in an exception. Fig 133. DMA controller block diagram GPDMA AHB SLAVE INTERFACE CONTROL LOGIC AND REGISTERS DMA REQUEST AND RESPONSE INTERFACE CHANNEL LOGIC AND REGISTERS INTERRUPT REQUEST DMA requests DMA responses DMA Interrupts AHB BUS AHB MASTER INTERFACE AHB BUS

4.1.2 Control logic and register bank

The register block stores data written or to be read across the AHB interface.

4.1.3 DMA request and response interface

See Section 31–4.2 for information on the DMA request and response interface.

4.1.4 Channel logic and channel register bank

The channel logic and channel register bank contains registers and logic required for each DMA channel.

4.1.5 Interrupt request

The interrupt request generates the interrupt to the ARM processor.

4.1.6 AHB master interface

The DMA Controller contains one AHB master interface. The AHB master is capable of dealing with all types of AHB transactions, including:

Split, retry, and error responses from slaves. If a peripheral performs a split or retry, the DMA Controller stalls and waits until the transaction can complete.
Locked transfers for source and destination of each stream.
Setting of protection bits for transfers on each stream.

4.1.6.1 Bus and transfer widths

The physical width of the AHB bus is 32 bits. Source and destination transfers can be of differing widths and can be the same width or narrower than the physical bus width. The DMA Controller packs or unpacks data as appropriate.

4.1.6.2 Endian behavior

The DMA Controller can cope with both little-endian and big-endian addressing. Internally the DMA Controller treats all data as a stream of bytes instead of 16-bit or 32-bit quantities. This means that when performing mixed-endian activity, where the endianness of the source and destination are different, byte swapping of the data within the 32-bit data bus is observed. Note: If byte swapping is not required, then use of different endianness between the source and destination addresses must be avoided. Table 31–543 shows endian behavior for different source and destination combinations.

4.1.6.3 Error conditions

error interrupt to the CPU. This error interrupt can be masked.

4.1.7 Channel hardware

Each stream is supported by a dedicated hardware channel, including source and destination controllers, as well as a FIFO. This enables better latency than a DMA controller with only a single hardware channel shared between several DMA streams and simplifies the control logic.

4.1.8 DMA request priority

DMA channel priority is fixed. DMA channel 0 has the highest priority and DMA channel 7 has the lowest priority. If the DMA Controller is transferring data for the lower priority channel and then the higher priority channel goes active, it completes the number of transfers delegated to the master interface by the lower priority channel before switching over to transfer data for the higher priority channel. Transfers delegated to the master interface are staged in the DMA channel FIFO, so the amount of data that needs to transfer could be as large as a 4 words. It is recommended that memory-to-memory transactions use the lowest priority channel.

4.1.9 Interrupt generation

A combined interrupt output is generated as an OR function of the individual interrupt requests of the DMA Controller and is connected to the interrupt controller.

4.2 DMA system connections

4.2.1 DMA request signals

The DMA request signals are used by peripherals to request a data transfer. The DMA request signals indicate whether a single or burst transfer of data is required. The DMA available request signals are: DMACBREQ[15:0] — Burst request signals. These cause a programmed burst number of data to be transferred. DMACSREQ[15:0] — Single transfer request signals. These cause a single data to be transferred. The DMA controller transfers a single transfer to or from the peripheral. DMACLBREQ[15:0] — Last burst request signals. DMACLSREQ[15:0] — Last single transfer request signals. Note that peripherals on this device do not support “last” request types, and many do not support both single and burst request types. See Section 31–4.2.3

4.2.2 DMA response signals

The DMA response signals indicate whether the transfer initiated by the DMA request signal has completed. The response signals can also be used to indicate whether a complete packet has been transferred. The DMA response signals from the DMA controller are: DMACCLR[15:0] — DMA clear or acknowledge signals. The DMACCLR signal is used by the DMA controller to acknowledge a DMA request from the peripheral.

4.2.3 DMA request connections

8 through 15 are chosen via the DMAREQSEL register, see Section 31–5.15. [1] Generates an interrupt and/or DMA request depending on software setup. Table 544. DMA Connections

UM10360_1 © NXP B.V. 2010. All rights reserved. relate to the DMA Controller. There are also global DMA control and status registers. The DMA Controller registers are shown in Table 31–545. Table 545. GPDMA register map

5.1 DMA Interrupt Status register (DMACIntStat - 0x5000 4000)

request can be generated from either the error or terminal count interrupt requests. Table 31–546 shows the bit assignments of the DMACIntStat Register.

5.2 DMA Interrupt Terminal Coun t Request Status register

after masking. Table 31–547 shows the bit assignments of the DMACIntTCStat Register.

5.3 DMA Interrupt Terminal Co unt Request Clear register

5.4 DMA Interrupt Error Status regi ster (DMACIntErrStat - 0x5000 400C)

after masking. Table 31–549 shows the bit assignments of the DMACIntErrStat Register. Table 546. DMA Interrupt Status register (DMACIntStat - 0x5000 4000) 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. reserved bit is not defined. Table 547. DMA Interrupt Terminal Count Request Status register (DMACIntTCStat - 0x5000 4004) 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. reserved bit is not defined. Table 548. DMA Interrupt Terminal Count Request Clear register (DMACIntTCClear - 0x5000 4008) 7:0 IntTCClear Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. reserved bit is not defined.

5.5 DMA Interrupt Error Clear regi ster (DMACIntErrClr - 0x5000 4010)

5.6 DMA Raw Interrupt Termin al Count Status register

the bit assignments of the DMACRawIntTCStat Register.

5.7 DMA Raw Error Interrupt Status register (DMACRawIntErrStat -

the DMACRawIntErrStat Register. Table 549. DMA Interrupt Error Status register (DMACIntErrStat - 0x5000 400C) 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. reserved bit is not defined. Table 550. DMA Interrupt Error Clear register (DMACIntErrClr - 0x5000 4010) 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. reserved bit is not defined. Table 551. DMA Raw Interrupt Terminal Count Status register (DMACRawIntTCStat - 0x5000 4014) 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. reserved bit is not defined.

5.8 DMA Enabled Channel regist er (DMACEnbldChns - 0x5000 401C)

that a DMA channel is enabled. A bit is cleared on completion of the DMA transfer. Table 31–553 shows the bit assignments of the DMACEnbldChns Register.

5.9 DMA Software Burst Request re gister (DMACSoftBReq - 0x5000 4020)

shows the bit assignments of the DMACSoftBReq Register. Table 552. DMA Raw Error Interrupt Status register (DMACRawIntErrStat - 0x5000 4018) 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. reserved bit is not defined. Table 553. DMA Enabled Channel register (DMACEnbldChns - 0x5000 401C) 0 - DMA channel is disabled. reserved bit is not defined. Table 554. DMA Software Burst Request register (DMACSoftBReq - 0x5000 4020) 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. reserved bit is not defined.

5.10 DMA Software Single Request register (DMACSoftSReq - 0x5000

5.11 DMA Software Last Burst Request register (DMACSoftLBReq - 0x5000

shows the bit assignments of the DMACSoftLBReq Register.

5.12 DMA Software Last Single Requ est register (DMACSoftLSReq -

shows the bit assignments of the DMACSoftLSReq Register. Table 555. DMA Software Single Request register (DMACSoftSReq - 0x5000 4024) 0 - writing 0 has no effect. reserved bit is not defined. Table 556. DMA Software Last Burst Request register (DMACSoftLBReq - 0x5000 4028) 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. reserved bit is not defined.

5.13 DMA Configuration register (DMACConfig - 0x5000 4030)

bit of this register. The AHB master interface is set to little-endian mode on reset. Table 31–558 shows the bit assignments of the DMACConfig Register.

5.14 DMA Synchronization regi ster (DMACSync - 0x5000 4034)

Table 557. DMA Software Last Single Request register (DMACSoftLSReq - 0x5000 402C) 0 - writing 0 has no effect. reserved bit is not defined. Table 558. DMA Configuration register (DMACConfig - 0x5000 4030)

0 E DMA Controller enable:

0 = disabled (default). Disabling the DMA Controller reduces power consumption.

1 M AHB Master endianness configuration:

0 = little-endian mode (default). reserved bit is not defined. Table 559. DMA Synchronization register (DMACSync - 0x5000 4034) 0 - synchronization logic for the corresponding DMA request signals are disabled. 1 - synchronization logic for the corresponding request line signals are enabled. reserved bit is not defined.

5.15 DMA Request Select regist er (DMAReqSel - 0x400F C1C4)

5.16 DMA Channel registers

Eight DMACCxSrcAddr Registers.
Eight DMACCxDestAddr Registers.
Eight DMACCxLLI Registers.
Eight DMACCxControl Registers.
Eight DMACCxConfig Registers. When performing scatter/gather DMA, the first four of these are automatically updated.

Table 560. DMA Request Select register (DMAReqSel - 0x400F C1C4)

0 DMASEL08 Selects the DMA request for GPDMA input 8:

1 - Timer 0 match 0 is selected.

1 DMASEL09 Selects the DMA request for GPDMA input 9:

1 - Timer 0 match 1 is selected.

2 DMASEL10 Selects the DMA request for GPDMA input 10:

1 - Timer 1match 0 is selected.

3 DMASEL11 Selects the DMA request for GPDMA input 11:

1 - Timer 1match 1 is selected.

4 DMASEL12 Selects the DMA request for GPDMA input 12:

1 - Timer 2 match 0 is selected.

5 DMASEL13 Selects the DMA request for GPDMA input 13:

1 - Timer 2 match 1 is selected.

6 DMASEL14 Selects the DMA request for GPDMA input 14:

1 - Timer 3 match 0 is selected.

7 DMASEL15 Selects the DMA request for GPDMA input 15:

1 - Timer 3 match 1 is selected. reserved bit is not defined.

5.17 DMA Channel Source Address registers (DMACCxSrcAddr -

As the source address is incremented.
By following the linked list when a complete packet of data has been transferred. Reading the register when the channel is active does not provide useful information. This is because by the time software has processed the value read, the address may have progressed. It is intended to be read-only when the channel has stopped, in which case it shows the source address of the last item read. Note: The source and destination addresses must be aligned to the source and destination widths. Table 31–561 shows the bit assignments of the DMACCxSrcAddr Registers.

5.18 DMA Channel Destination Addr ess registers (DMACCxDestAddr -

has stopped, in which case it shows the destination address of the last item read. shows the bit assignments of the DMACCxDestAddr Register.

5.19 DMA Channel Linked List Item registers (DMACCxLLI - 0x5000 41x8)

Table 561. DMA Channel Source Address registers (DMACCxSrcAddr - 0x5000 41x0) 31:0 SrcAddr DMA source address. Reading this register will return the current source address. Table 562. DMA Channel Destination Addre ss registers (DMACCxDestAddr - 0x5000 41x4)

5.20 DMA channel control register s (DMACCxControl - 0x5000 41xC)

5.20.1 Protection and access information

are used as shown in Table 31–564. Table 563. DMA Channel Linked List It em registers (DMACCxLLI - 0x5000 41x8) 1:0 - Reserved, and must be written as 0. 31:2 LLI Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.

UM10360_1 © NXP B.V. 2010. All rights reserved. Table 564. DMA channel control registers (DMACCxControl - 0x5000 41xC) channel is enabled. Transfer size is updated as data transfers are completed. only when a channel is enabled and then disabled. active in the source peripheral. the DMACBREQ signal goes active in the destination peripheral. and unpacks the data as required. 25:24 - Reserved, and must be written as 0.

5.21 DMA Channel Configuration regi sters (DMACCxConfig - 0x5000 41x0)

with the exception of bit[17] which is read-only. Used these to configure the DMA channel. assignments of the DMACCxConfig Register.

26 SI Source increment:

0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer.

27 DI Destination increment:

0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. mode or privileged mode. This information is not used in the LPC17xx. 1 - access is in privileged mode. access is bufferable or not bufferable. This information is not used in the LPC17xx. 0 - access is not bufferable. access is cacheable or not cacheable. This information is not used in the LPC17xx. 0 - access is not cacheable. 31 I Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled.

UM10360_1 © NXP B.V. 2010. All rights reserved. Table 565. DMA Channel Configuration registers (DMACCxConfig - 0x5000 41x0) A channel is enabled by setting this bit. Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. reached, the DMA transfer is completed, or if a channel error is encountered. 10:6 DestPeripheral Destination peripheral. This value selects the DMA destination request peripheral. for peripheral identification. Refer to Table 31–566 for the encoding of this field. interrupt of the relevant channel.

17 A Active:

0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. DMA channel. This is a read-only bit.

18 H Halt:

1 = ignore further source DMA requests. The contents of the channel FIFO are drained. reserved bit is not defined.

5.21.1 Lock control

Controller permit it to perform a source fetch followed by a destination drain back-to-back.

5.21.2 Transfer type

Table 31–566 lists the bit values of the transfer type bits identified in Table 31–565. Table 566. Transfer type bits

000 Memory to memory DMA

001 Memory to peripheral DMA

010 Peripheral to memory DMA

011 Source peripheral to destination peripheral DMA

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 604 of 835 NXP Semiconductors UM10360 Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller 6. Using the DMA controller

6.1 Programming the DMA controller

All accesses to the DMA Controller internal register must be word (32-bit) reads and writes.

6.1.1 Enabling the DMA controller

To enable the DMA controller set the Enable bit in the DMACConfig register.

6.1.2 Disabling the DMA controller

To disable the DMA controller:

Read the DMACEnbldChns register and ensure that all the DMA channels have been disabled. If any channels are active, see Disabling a DMA channel.
Disable the DMA controller by writing 0 to the DMA Enable bit in the DMACConfig register.

6.1.3 Enabling a DMA channel

To enable the DMA channel set the channel enable bit in the relevant DMA channel configuration register. Note that the channel must be fully initialized before it is enabled.

6.1.4 Disabling a DMA channel

A DMA channel can be disabled in three ways:

By writing directly to the channel enable bit. Any outstanding data in the FIFO’s is lost if this method is used.
By using the active and halt bits in conjunction with the channel enable bit.
By waiting until the transfer completes. This automatically clears the channel. Disabling a DMA channel and losing data in the FIFO Clear the relevant channel enable bit in the relevant channel configuration register. The current AHB transfer (if one is in progress) completes and the channel is disabled. Any data in the FIFO is lost. Disabling the DMA channel without losing data in the FIFO
Set the halt bit in the relevant channel configuration register. This causes any future DMA request to be ignored.
Poll the active bit in the relevant channel configuration register until it reaches 0. This bit indicates whether there is any data in the channel that has to be transferred.
Clear the channel enable bit in the relevant channel configuration register

6.1.5 Setting up a new DMA transfer

To set up a new DMA transfer: If the channel is not set aside for the DMA transaction:

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 605 of 835 NXP Semiconductors UM10360 Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller 1. Read the DMACEnbldChns controller register and find out which channels are inactive. 2. Choose an inactive channel that has the required priority. 3. Program the DMA controller

6.1.6 Halting a DMA channel

Set the halt bit in the relevant DMA channel configuration register. The current source request is serviced. Any further source DMA request is ignored until the halt bit is cleared.

6.1.7 Programming a DMA channel

Choose a free DMA channel with the priority needed. DMA channel 0 has the highest priority and DMA channel 7 the lowest priority. 2. Clear any pending interrupts on the channel to be used by writing to the DMACIntTCClear and DMACIntErrClear register. The previous channel operation might have left interrupt active. 3. Write the source address into the DMACCxSrcAddr register. 4. Write the destination address into the DMACCxDestAddr register. 5. Write the address of the next LLI into the DMACCxLLI register. If the transfer comprises of a single packet of data then 0 must be written into this register. 6. Write the control information in to the DMACCxControl register. 7. Write the channel configurat ion information into the DMACCxConfig register. If the enable bit is set then the DMA channel is automatically enabled.

6.2 Flow control

The device that controls the length of the packet is known as the flow controller. On the LPC17xx, the flow controller is always the DMA Controller, and the packet length is programmed by software before the DMA channel is enabled. When the DMA transfer is completed: 1. The DMA Controller issues an acknowledge to the peripheral in order to indicate that the transfer has finished. 2. A TC interrupt is generated, if enabled. 3. The DMA Controller moves on to the next LLI. The following sections describe the DMA Controller data flow sequences for the four allowed transfer types:

Memory-to-peripheral.
Peripheral-to-memory.
Memory-to-memory.
Peripheral-to-peripheral. Table 31–567 indicates the request signals used for each type of transfer.

6.2.1 Peripheral-to-memory or memory-to-peripheral DMA flow

Program and enable the DMA channel.
The DMA Controller starts transferring data when:

– The DMA request goes active. – The DMA stream has the highest pending priority. – The DMA Controller is the bus master of the AHB bus.

If an error occurs while transferring the data, an error interrupt is generated and

disables the DMA stream, and the flow sequence ends.

Decrement the transfer count.
If the transfer has completed (indicated by the transfer count reaching 0):

– The DMA Controller responds with a DMA acknowledge. – The terminal count interrupt is generated (this interrupt can be masked).

6.2.2 Peripheral-to-peripheral DMA flow

Program and enable the DMA channel.
Wait for a source DMA request.
The DMA Controller starts transferring data when:

– The DMA request goes active. – The DMA stream has the highest pending priority. – The DMA Controller is the bus master of the AHB bus.

If an error occurs while transferring the da ta an error interrupt is generated, the DMA

stream is disabled, and the flow sequence ends.

Decrement the transfer count.
If the transfer has completed (indicated by the transfer count reaching 0):

– The DMA Controller responds with a DMA acknowledge to the source peripheral. – Further source DMA requests are ignored. Table 567. DMA request signal usage

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 607 of 835 NXP Semiconductors UM10360 Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller 7. When the destination DMA request goes active and there is data in the DMA Controller FIFO, transfer data into the destination peripheral. 8. If an error occurs while transferring the da ta, an error interrupt is generated, the DMA stream is disabled, and the flow sequence ends. 9. If the transfer has completed it is indica ted by the transfer count reaching 0. The following happens: – The DMA Controller responds with a DMA acknowledge to the destination peripheral. – The terminal count interrupt is generated (this interrupt can be masked). – If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr, DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go to back to step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow sequence ends.

6.2.3 Memory-to-memory DMA flow

For a memory-to-memory DMA flow the following sequence occurs: 1. Program and enable the DMA channel. 2. Transfer data whenever the DMA channel has the highest pending priority and the DMA Controller gains mastership of the AHB bus. 3. If an error occurs while transferring the data, generate an error interrupt and disable the DMA stream. 4. Decrement the transfer count. 5. If the count has reached zero: – Generate a terminal count interrupt (the interrupt can be masked). – If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr, DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go to back to step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow sequence ends. Note: Memory-to-memory transfers should be programmed with a low channel priority, otherwise other DMA channels cannot access the bus until the memory-to-memory transfer has finished, or other AHB masters cannot perform any transaction.

6.3 Interrupt requests

Interrupt requests can be generated when an AHB error is encountered or at the end of a transfer (terminal count), after all the data corresponding to the current LLI has been transferred to the destination. The interrupts can be masked by programming bits in the relevant DMACCxControl and DMACCxConfig Channel Registers. The interrupt requests from all DMA channels can be found in the DMACRawIntTCStat and DMACRawIntErrStat registers. The masked versions of the DMA interrupt data is contained in the DMACIntTCStat and DMACIntErrStat registers. The DMACIntStat register then combines the DMACIntTCStat and DMACIntErrStat requests into a single register to enable the source of an interrupt to be found quickly. Writing to the DMACIntTCClear or the DMACIntErrClr Registers with a bit set to 1 enables selective clearing of interrupts.

6.3.1 Hardware interrupt sequence flow

When a DMA interrupt request occurs, the Interrupt Service Routine needs to: 1. Read the DMACIntTCStat Register to determine whether the interrupt was generated due to the end of the transfer (terminal count). A 1 bit indicates that the transfer completed. If more than one request is active, it is recommended that the highest priority channels be checked first. 2. Read the DMACIntErrStat Register to determine whether the interrupt was generated due to an error occurring. A 1 bit indicates that an error occurred. 3. Service the interrupt request. 4. For a terminal count interr upt, write a 1 to the relevant bit of the DMACIntTCClr Register. For an error interrupt write a 1 to the relevant bit of the DMACIntErrClr Register to clear the interrupt request.

6.4 Address generation

Address generation can be either incrementing or non-incrementing (address wrapping is not supported). Some devices, especially memories, disallow burst accesses across certain address boundaries. The DMA controller assumes that this is the case with any source or destination area, which is configured for incrementing addressing. This boundary is assumed to be aligned with the specified burst size. For example, if the channel is set for 16-transfer burst to a 32-bit wide device then the boundary is 64-bytes aligned (that is address bits [5:0] equal 0). If a DMA burst is to cross one of these boundaries, then, instead of a burst, that transfer is split into separate AHB transactions.

6.4.1 Word-aligned transfers across a boundary

The channel is configured for 16-transfer bursts, each transfer 32-bits wide, to a destination for which address incrementing is enabled. The start address for the current burst is 0x0C000024, the next boundary (calculated from the burst size and transfer width) is 0x0C000040. The transfer will be split into two AHB transactions:

a 7-transfer burst starting at address 0x0C000024
a 9-transfer burst starting at address 0x0C000040.

6.5 Scatter/gather

Scatter/gather is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas in memory. Where scatter/gather is not required, the DMACCxLLI Register must be set to 0. The source and destination data areas are defined by a series of linked lists. Each Linked List Item (LLI) controls the transfer of one block of data, and then optionally loads another LLI to continue the DMA operation, or stops the DMA stream. The first LLI is programmed into the DMA Controller. The data to be transferred described by an LLI (referred to as the packet of data) usually requires one or more DMA bursts (to each of the source and destination).

6.5.1 Linked list items

A Linked List Item (LLI) consists of four words. These words are organized in the following order: 1. DMACCxSrcAddr. 2. DMACCxDestAddr. 3. DMACCxLLI. 4. DMACCxControl. Note: The DMACCxConfig DMA channel Configuration Register is not part of the linked list item.

6.5.1.1 Programming the DMA controller for scatter/gather DMA

To program the DMA Controller for scatter/gather DMA: 1. Write the LLIs for the complete DMA transfer to memory. Each linked list item contains four words: – Source address. – Destination address. – Pointer to next LLI. – Control word. The last LLI has its linked list word pointer set to 0. 2. Choose a free DMA channel with the priority required. DMA channel 0 has the highest priority and DMA channel 7 the lowest priority. 3. Write the first linked list item, previously wr itten to memory, to the relevant channel in the DMA Controller. 4. Write the channel configuration information to the channel Configuration Register and set the Channel Enable bit. The DMA Controller then transfers the first and then subsequent packets of data as each linked list item is loaded. 5. An interrupt can be generated at the end of each LLI depending on the Terminal Count bit in the DMACCxControl Register. If this bit is set an interrupt is generated at the end of the relevant LLI. The interrupt request must then be serviced and the relevant bit in the DMACIntTCClear Register must be set to clear the interrupt.

6.5.1.2 Example of scatter/gather DMA

See Figure 31–134 for an example of an LLI. A section of memory is to be transferred to a peripheral. The addresses of each LLI entry are given, in hexadecimal, at the left-hand side of the figure. In this example, the LLIs describing the transfer are to be stored contiguously from address 0x2002 0000, but they could be located anywhere. The right side of the figure shows the memory containing the data to be transferred.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 610 of 835 NXP Semiconductors UM10360 Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller The first LLI, stored at 0x2002 0000, defines the first block of data to be transferred, which is the data stored from address 0x2002 A200 to 0x2002 ADFF:

Source start address 0x2002 A200.
Destination address set to the destination peripheral address.
Transfer width, word (32-bit).
Transfer size, 3072 bytes (0XC00).
Source and destination burst sizes, 16 transfers.
Next LLI address, 0x2002 0010. The second LLI, stored at 0x2002 0010, describes the next block of data to be transferred:
Source start address 0x2002 B200.
Destination address set to the destination peripheral address.
Transfer width, word (32-bit).
Transfer size, 3072 bytes (0xC00).
Source and destination burst sizes, 16 transfers.
Next LLI address, 0x2002 0020. A chain of descriptors is built up, each one pointing to the next in the series. To initialize the DMA stream, the first LLI, 0x2002 0000, is programmed into the DMA Controller. When the first packet of data has been transferred the next LLI is automatically loaded. The final LLI is stored at 0x2002 0070 and contains: Fig 134. LLI example LLI1 0x2002 0000 Source address = 0x 2002 A200 Destination address = peripheral Next LLI address = 0x2002 0010 Control information = length 3072 Source address = 0x 2002 B200 Destination address = peripheral Next LLI address = 0x2002 0020 Control information = length 3072 Source address = 0x 2002 C200 Destination address = peripheral Next LLI address = 0x2002 0030 Control information = length 3072 Source address = 0x 2003 1200 Destination address = peripheral Next LLI address = 0 (end of list) Control information = length 3072 LLI2 0x2002 0010 LLI3 0x2002 0020 LLI8 0x2002 0070 Linked List Array 3072 bytes of data 0x2002 A200 0x2002 ADFF 3072 bytes of data 0x2002 B200 0x2002 BDFF 3072 bytes of data 0x2002 C200 0x2002 CDFF 3072 bytes of data 0x2003 1200 0x2003 1DFF

Source start address 0x2003 1200.
Destination address set to the destination peripheral address.
Transfer width, word (32-bit).
Transfer size, 3072 bytes (0xC00).
Source and destination burst sizes, 16 transfers.
Next LLI address, 0x0. Because the next LLI address is set to zero, this is the last descriptor, and the DMA channel is disabled after transferring the last item of data. The channel is probably set to generate an interrupt at this point to indicate to the ARM processor that the channel can be reprogrammed.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 612 of 835 1. Introduction The boot loader controls initial operation after reset and also provides the tools for programming the flash memory. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system. 2. Features

In-System Programming: In-System programming (ISP) is programming or reprogramming the on-chip flash memory, using the boot loader software and UART0 serial port. This can be done when the part resides in the end-user board.
In Application Programming: In-Application (IAP) programming is performing erase and write operation on the on-chip flash memory, as directed by the end-user application code.
Flash signature generation: built-in hardware can generate a signature for a range of flash addresses, or for the entire flash memory. 3. Description The flash boot loader code is executed every time the part is powered on or reset. The loader can execute the ISP command handler or the user application code. A LOW level after reset at pin P2.10 is considered an external hardware request to start the ISP command handler. Assuming that power supply pins are on their nominal levels when the rising edge on RESET pin is generated, it may take up to 3 ms before P2.10 is sampled and the decision on whether to continue with user code or ISP handler is made. If P2.10 is sampled low and the watchdog overflow flag is set, the external hardware request to start the ISP command handler is ignored. If there is no request for the ISP command handler execution (P2.10 is sampled HIGH after reset), a search is made for a valid user program. If a valid user program is found then the execution control is transferred to it. If a valid user program is not found, the auto-baud routine is invoked. Pin P2.10 is used as a hardware request signal for ISP and therefore requires special attention. Since P2.10 is in high impedance mode after reset, it is important that the user provides external hardware (a pull-up resistor or other device) to put the pin in a defined state. Otherwise unintended entry into ISP mode may occur. When ISP mode is entered after a power on reset, the IRC and PLL are used to generate the CCLK of 14.748 MHz. The baud rates that can easily be obtained in this case are: 9600 baud, 19200 baud, 38400 baud, 57600 baud, 115200 baud, and 230400 baud. This may not be the case when ISP is invoked by the user application (see Section 32–8.9 “Re-invoke ISP” on page 633). UM10360 Chapter 32: LPC17xx Flash memory interface and programming Rev. 01 — 4 January 2010 User manual

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 613 of 835 NXP Semiconductors UM10360 Chapter 32: LPC17xx Flash memory interface and programming A hardware flash signature generation capability is built into the flash memory. this feature can be used to create a signature that can then be used to verify flash contents. Details of flash signature generation are in Section 32–10.

3.1 Memory map after any reset

When a user program begins execution after reset, the interrupt vectors are set to point to the beginning of flash memory.

3.1.1 Criterion for Valid User Code

The reserved Cortex-M3 exception vector location 7 (offset 0x 001C in the vector table) should contain the 2’s complement of the check-sum of table entries 0 through 6. This causes the checksum of the first 8 table entries to be 0. The boot loader code checksums the first 8 locations in sector 0 of the flash. If the result is 0, then execution control is transferred to the user code. If the signature is not valid, the auto-baud routine synchronizes with the host via serial port 0. The host should send a “?” (0x3F) as a synchronization character and wait for a response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity. The auto-baud routine measures the bit time of the received synchronization character in terms of its own frequency and programs the baud rate generator of the serial port. It also Fig 135. Map of lower memory

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 614 of 835 NXP Semiconductors UM10360 Chapter 32: LPC17xx Flash memory interface and programming sends an ASCII string ("Synchronized<CR><LF>") to the host. In response to this the host should send the same string ("Synchronized<CR><LF>"). The auto-baud routine looks at the received characters to verify synchronization. If synchronization is verified then "OK<CR><LF>" string is sent to the host. The host should respond by sending the crystal frequency (in kHz) at which the part is running. For example, if the part is running at 10 MHz, the response from the host should be "10000<CR><LF>". "OK<CR><LF>" string is sent to the host after receiving the crystal frequency. If synchronization is not verified then the auto-baud routine waits again for a synchronization character. For auto-baud to work correctly in case of user invoked ISP, the CCLK frequency should be greater than or equal to 10 MHz. For more details on Reset, PLL and startup/boot code interaction see Section 4–5.1.1 “PLL0 and startup/boot code interaction”. Once the crystal frequency is received the part is initialized and the ISP command handler is invoked. For safety reasons an "Unlock" command is required before executing the commands resulting in flash erase/write operations and the "Go" command. The rest of the commands can be executed without the unlock command. The Unlock command is required to be executed once per ISP session. The Unlock command is explained in Section 32–7 “ ISP commands” on page 620.

3.2 Communication protocol

All ISP commands should be sent as single ASCII strings. Strings should be terminated with Carriage Return (CR) and/or Line Feed (LF) control characters. Extra <CR> and <LF> characters are ignored. All ISP responses are sent as <CR><LF> terminated ASCII strings. Data is sent and received in UU-encoded format.

3.2.1 ISP command format

"Command Parameter_0 Parameter_1 … Parameter_n<CR><LF>" "Data" (Data only for Write commands).

3.2.2 ISP response format

Response_n<CR><LF>" "Data" (Data only for Read commands).

3.2.3 ISP data format

The data stream is in UU-encoded format. The UU-encode algorithm converts 3 bytes of binary data in to 4 bytes of printable ASCII character set. It is more efficient than Hex format which converts 1 byte of binary data in to 2 bytes of ASCII hex. The sender should send the check-sum after transmitting 20 UU-encoded lines. The length of any UU-encoded line should not exceed 61 characters (bytes) i.e. it can hold 45 data bytes. The receiver should compare it with the check-sum of the received bytes. If the check-sum matches then the receiver should respond with "OK<CR><LF>" to continue further transmission. If the check-sum does not match the receiver should respond with "RESEND<CR><LF>". In response the sender should retransmit the bytes.

3.2.4 ISP flow control

A software XON/XOFF flow control scheme is used to prevent data loss due to buffer overrun. When the data arrives rapidly, the ASCII control character DC3 (0x13) is sent to stop the flow of data. Data flow is resumed by sending the ASCII control character DC1 (0x11). The host should also support the same flow control scheme.

3.2.5 ISP command abort

Commands can be aborted by sending the ASCII control character "ESC" (0x1B). This feature is not documented as a command under "ISP Commands" section. Once the escape code is received the ISP command handler waits for a new command.

3.2.6 Interrupts during IAP

The on-chip flash memory is not accessible during erase/write operations. When the user application code starts executing the interrupt vectors from the user flash area are active. The user should either disable interrupts, or ensure that user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM, before making a flash erase/write IAP call. The IAP code does not use or disable interrupts.

3.2.7 RAM used by ISP command handler

ISP commands use on-chip RAM from 0x1000 0118 to 0x1000 01FF. The user could use this area, but the contents may be lost upon reset. Flash programming commands use the top 32 bytes of on-chip RAM. The stack is located at RAM top - 32. The maximum stack usage is 256 bytes and it grows downwards.

3.2.8 RAM used by IAP command handler

Flash programming commands use the top 32bytes of on-chip RAM. The maximum stack usage in the user allocated stack space is 128 bytes and it grows downwards.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 616 of 835 NXP Semiconductors UM10360 Chapter 32: LPC17xx Flash memory interface and programming 4. Boot process flowchart (1) For details on handling the crystal frequency, see Section 32–8.9 “ Re-invoke ISP” on page 633 (2) For details on available ISP commands based on the CRP settings see Section 32–6 “Code Read Protection (CRP)” Fig 136. Boot process flowchart WATCHDOG FLAG SET? CRP1/2/3 ENABLED? yes no INITIALIZE RESET ENABLE DEBUG yes RUN ISP COMMAND HANDLER 2 RECEIVE CRYSTAL FREQUENCY 1 no AUTO-BAUD SUCCESSFUL? yes RUN AUTO-BAUD USER CODE VALID? yes no CRP3 ENABLED? Enter ISP MODE? (P2.10=LOW) USER CODE VALID? yes yes no yes no no A A EXECUTE INTERNAL USER CODE

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 618 of 835 NXP Semiconductors UM10360 Chapter 32: LPC17xx Flash memory interface and programming 6. Code Read Protection (CRP) Code Read Protection is a mechanism that allows user to enable different levels of security in the system so that access to the on-chip flash and use of the ISP can be restricted. When needed, CRP is invoked by programming a specific pattern in flash location at 0x000002FC. IAP commands are not affected by the code read protection. Important: Any CRP change becomes effective only after the device has gone through a power cycle. Table 569. Code Read Protection options CRP1 0x12345678 Access to chip via the JTAG pins is disabled. This mode allows partial flash update using the following ISP commands and restrictions:

Write to RAM command can not access RAM below 0x10000200. This is due to use of the RAM by the ISP code, see Section 32–3.2.7
Read Memory command: disabled.
Copy RAM to Flash command: cannot write to Sector 0.
Go command: disabled.
Erase sector(s) command: can erase any individual sector except sector 0 only, or can erase all sectors at once.
Compare command: disabled This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. The compare command is disabled, so in the case of partial flash updates the secondary loader should implement a checksum mechanism to verify the integrity of the flash. CRP2 0x87654321 This is similar to CRP1 with the following additions:
Write to RAM command: disabled.
Copy RAM to Flash: disabled.
Erase command: only allows erase of all sectors. CRP3 0x43218765 This is similar to CRP2, but ISP entry by pulling P2.10 LOW is disabled if a valid user code is present in flash sector 0. This mode effectively disables ISP override using the P2.10 pin. It is up to the user’s application to provide for flash updates by using IAP calls or by invoking ISP with UART0. Caution: If CRP3 is selected, no future factory testing can be performed on the device.

7.1 Unlock <Unlock code>

Table 571. ISP command summary Table 572. ISP Unlock command Description This command is used to unlock Flash Write, Erase, and Go commands. Example "U 23130<CR><LF>" unlocks the Flash Write/Erase & Go commands.

7.2 Set Baud Rate <Baud Rate> <stop bit>

7.3 Echo <setting>

7.4 Write to RAM <start address> <number of bytes>

20 UU-encoded lines then the check-sum should be of the actual number of bytes sent. Table 573. ISP Set Baud Rate command after the command handler sends the CMD_SUCCESS return code. Example "B 57600 1<CR><LF>" sets the serial port to baud rate 57600 bps and 1 stop bit. Table 574. Correlation between possible ISP baudrates and CCLK frequency (in MHz) Table 575. ISP Echo command sends the received serial data back to the host. Example "A 0<CR><LF>" turns echo off.

UM10360_1 © NXP B.V. 2010. All rights reserved. handler sends the data again. Table 576. ISP Write to RAM command Example "W 268435968 4<CR><LF>" writes 4 bytes of data to address 0x1000 0200. Table 577. ISP Read Memory command Number of Bytes: Number of bytes to be read. Count should be a multiple of 4. blocked when any level of code read protection is enabled. Example "R 268435968 4<CR><LF>" reads 4 bytes of data from address 0x1000 0200.

7.6 Prepare sector(s) for write ope ration <start sector number> <end

This command makes flash write/erase operation a two step process.

7.7 Copy RAM to Flash <f lash address> <RAM address> <no of bytes>

Table 578. ISP Prepare sector(s) for write operation command End Sector Number: Should be greater than or equal to start sector number. prepare a single sector use the same "Start" and "End" sector numbers. Example "P 0 0<CR><LF>" prepares the flash sector 0. Table 579. ISP Copy command written. The destination address should be a 256 byte boundary. RAM Address(SRC): Source RAM address from where data bytes are to be read. automatically protected again once the copy command is successfully executed. other than sector 0 can be written. 0x1000 8000 to the flash address 0.

7.8 Go <address> <mode>

configured to generate a CPU clock with a frequency of approximately 14.7456 MHz.

7.9 Erase sector(s) <sta rt sector number> <end sector number>

Table 580. ISP Go command Input Address: Flash or RAM address from which the code execution is to be started. This address should be on a word boundary. Example "G 0 T<CR><LF>" branches to address 0x0000 0000. Table 581. ISP Erase sector command End Sector Number: Should be greater than or equal to start sector number. erased. All sectors can be erased at once in CRP1 and CRP2. Example "E 2 3<CR><LF>" erases the flash sectors 2 and 3.

7.10 Blank check sector(s) <sector number> <end sector number>

7.11 Read Part Identification number

Table 582. ISP Blank check sector command End Sector Number: Should be greater than or equal to start sector number. Description This command is used to blank check one or more sectors of on-chip flash memory. Example "I 2 3<CR><LF>" blank c hecks the flash sectors 2 and 3. Table 583. ISP Read Part Identification command “LPC17xx part identification numbers”). normally change as a result of technical revisions. Table 584. LPC17xx part identification numbers

7.12 Read Boot Co de version number

7.13 Read device serial number

7.14 Compare <address1> <address2> <no of bytes>

Table 585. ISP Read Boot Code version number command Return Code CMD_SUCCESS fo llowed by 2 bytes of boot code version number in ASCII format. It is to be interpreted as <byte1(Major)>.<byte0(Minor)>. Description This command is used to read the boot code version number. Table 586. ISP Read device serial number command each representing a 32-bit value. used to uniquely identify a single unit among all LPC17xx devices. Table 587. ISP Compare command Input Address1 (DST): Starting flash or RAM address of data bytes to be compared. This address should be a word boundary. Address2 (SRC): Starting flash or RAM address of data bytes to be compared. This address should be a word boundary. Number of Bytes: Number of bytes to be compared; should be a multiple of 4. command is blocked when any level of code read protection is enabled. 0x1000 0200 to the 4 bytes from the flash address 0x2000.

7.15 ISP Return Codes

Table 588. ISP Return Codes Summary been completely and successfully executed. 1 INVALID_COMMAND Invalid command. 2 SRC_ADDR_ERROR Source address is not on word boundary. 3 DST_ADDR_ERROR Destination address is not on a correct boundary. 4 SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map.

5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory

6 COUNT_ERROR Byte count is not multiple of 4 or is not a permitted

7 INVALID_SECTOR Sector number is invalid or end sector number is

greater than start sector number. 8 SECTOR_NOT_BLANK Sector is not blank.

9 SECTOR_NOT_PREPARED_FOR_

10 COMPARE_ERROR Source and destination data not equal. 11 BUSY Flash programming hardware interface is busy.

12 PARAM_ERROR Insufficient number of parameters or invalid

13 ADDR_ERROR Address is not on word boundary. value is taken in to consideration where applicable. 15 CMD_LOCKED Command is locked. 16 INVALID_CODE Unlock code is invalid. 17 INVALID_BAUD_RATE Invalid baud rate setting. 18 INVALID_STOP_BIT Invalid stop bit setting.

19 CODE_READ_PROTECTION_

Code read protection enabled.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 628 of 835 NXP Semiconductors UM10360 Chapter 32: LPC17xx Flash memory interface and programming 8. IAP commands For in application programming the IAP routine should be called with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters. Result of the IAP command is returned in the result table pointed to by register r1. The user can reuse the command table for result by passing the same pointer in registers r0 and r1. The parameter table should be big enough to hold all the results in case if number of results are more than number of parameters. Parameter passing is illustrated in the Figure 32–137 . The number of parameters and results vary according to the IAP command. The maximum number of parameters is 5, passed to the "Copy RAM to Flash" command. The maximum number of results is 4, returned by the "Read device serial number" command. The command handler sends the status code INVALID_COMMAND when an undefined command is received. The IAP routine resides at location 0x1FFF 1FF0. The IAP function could be called in the following way using C. Define the IAP location entry point. Bit 0 of the IAP location is set since the Cortex-M3 uses only Thumb mode. #define IAP_LOCATION 0x1FFF1FF1 Define data structure or pointers to pass IAP command table and result table to the IAP function: unsigned long command[5]; unsigned long result[5]; or unsigned long * command; unsigned long * result; command=(unsigned long *) 0x…… result= (unsigned long *) 0x…… Define pointer to function type, which takes two parameters and returns void. Note the IAP returns the result with the base address of the table residing in R1. typedef void (*IAP)(unsigned int [],unsigned int[]); IAP iap_entry; Setting function pointer: iap_entry=(IAP) IAP_LOCATION; Whenever you wish to call IAP you could use the following statement. iap_entry (command, result); The IAP call could be simplified further by using the symbol definition file feature supported by ARM Linker in ADS (ARM Developer Suite). You could also call the IAP routine using assembly code.

0002 A-05) up to 4 parameters can be passed in the r0, r1, r2 and r3 registers

suggested parameter passing scheme reduces such risk. programming is permitted in the application. Table 589. IAP Command Summary

8.1 Prepare sector(s) for write operation

This command makes flash write/erase operation a two step process.

8.2 Copy RA M to Flash

Table 590. IAP Prepare sector(s) for write operation command prepare a single sector use the same "Start" and "End" sector numbers. Table 591. IAP Copy RAM to Flash command address should be a 256 byte boundary. address should be a word boundary. Param2: Number of bytes to be written. Should be 256 | 512 | 1024 | 4096. Param3: CPU Clock Frequency (CCLK) in kHz.

8.3 Erase Sector(s)

8.4 Blank check sector(s)

8.5 Read part identification number

Table 592. IAP Erase Sector(s) command Param2: CPU Clock Frequency (CCLK) in kHz. memory. To erase a single sector use the same "Start" and "End" sector numbers. Table 593. IAP Blank check sector(s) command Result1: Contents of non blank word location. Table 594. IAP Read part identification number command Result Result0: Part Identification Number.

8.6 Read Boot Code version number

8.7 Read device serial number

8.8 Compare <address1> <address2> <no of bytes>

Table 595. IAP Read Boot Code version number command Description This command is used to read the boot code version number. Table 596. IAP Read device serial number command may be used to uniquely identify a single unit among all LPC17xx devices. Table 597. IAP Compare command address should be a word boundary. address should be a word boundary. Param2: Number of bytes to be compared; should be a multiple of 4. Result0: Offset of the first mismatch if the Status Code is COMPARE_ERROR. Description This command is used to compare the memory contents at two locations.

8.9 Re-invoke ISP

8.10 IAP Status Codes

JTAG flash programming interface

"Copy RAM to Flash" repeatedly with proper offset. Table 598. Re-invoke ISP PLL are used to generate CCLK = 14.748 MHz. Table 599. IAP Status Codes Summary 0 CMD_SUCCESS Command is executed successfully. 1 INVALID_COMMAND Invalid command. 2 SRC_ADDR_ERROR Source address is not on a word boundary. 3 DST_ADDR_ERROR Destination address is not on a correct boundary. 4 SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map.

5 DST_ADDR_NOT_MAPPED Destination addr ess is not mapped in the memory

7 INVALID_SECTOR Sector number is invalid. 8 SECTOR_NOT_BLANK Sector is not blank.

9 SECTOR_NOT_PREPARED_

10 COMPARE_ERROR Source and destination data is not same. 11 BUSY Flash programming hardware interface is busy.

Flash signature generation

contents against a calculated signature (e.g. during programming). i.e. 128-bit boundaries. Once started, signature generation completes independently. signature generation should also be placed outside of the flash memory.

10.1 Register description for signature generation

Table 600. Register overview: FMC (base address 0x2020 0000)

10.1.1 Signature generation address and control registers

Signature generation is started by setting the SIG_START bit in the FMSSTOP register. FMSSTOP registers respectively.

10.1.2 Signature generation result registers

FMSW0, FMSW1, FMSW2 and FMSW3. Table 601. Flash Module Signature Start register (FMSSTART - 0x4008 4020) bit description reserved bit is not defined. Table 602. Flash Module Signature Stop register (FMSSTOP - 0x4008 4024) bit description read from a reserved bit is not defined.

0 Signature generation is stopped

1 Initiate signature generation

Table 603. FMSW0 register bit description (FMSW0, address: 0x2020 002C) Table 604. FMSW1 register bit description (FMSW1, address: 0x2020 0030)

10.1.3 Flash Module Status register (FMSTAT - 0x0x4008 4FE0)

indicate completion of a previous operation.

10.1.4 Flash Module Status Clear register (FMSTATCLR - 0x0x4008 4FE8)

The FMSTATCLR register is used to clear the signature generation completion flag. Table 605. FMSW2 register bit description (FMSW2, address: 0x2020 0034) Table 606. FMSW3 register bit description (FMSW3, address: 0x2020 0038) Table 607. Flash module Status register (FMSTAT - 0x4008 4FE0) bit description from a reserved bit is not defined. FMSTATCLR register description for clearing this flag. from a reserved bit is not defined. Table 608. Flash Module Status Clear register (FMSTATCLR - 0x0x4008 4FE8) bit description from a reserved bit is not defined.

2 SIG_DONE_CLR Writing a 1 to this bits clears the signature generation completion flag

(SIG_DONE) in the FMSTAT register. from a reserved bit is not defined.

10.2 Algorithm and procedure for signature generation

A signature can be generated for any part of the flash contents. The address range to be used for signature generation is defined by writing the start address to the FMSSTART register, and the stop address to the FMSSTOP register. The signature generation is started by writing a ‘1’ to FMSSTOP .MISR_START. Starting the signature generation is typically combined with defining the stop address, which is done in another field FMSSTOP .FMSSTOP of the same register. The time that the signature generation takes is proportional to the address range for which the signature is generated. Reading of the flash memory for signature generation uses a self-timed read mechanism and does not depend on any configurable timing settings for the flash. A safe estimation for the duration of the signature generation is: Duration = int( (60 / tcy) + 3 ) x (FMSSTOP - FMSSTART + 1) When signature generation is triggered via software, the duration is in AHB clock cycles, and tcy is the time in ns for one AHB clock. The SIG_DONE bit in FMSTAT can be polled by software to determine when signature generation is complete. If signature generation is triggered via JTAG, the duration is in JTAG tck cycles, and tcy is the time in ns for one JTAG clock. Polling the SIG_DONE bit in FMSTAT is not possible in this case. After signature generation, a 128-bit signature can be read from the FMSW0 to FMSW3 registers. The 128-bit signature reflects the corrected data read from the flash. The 128-bit signature reflects flash parity bits and check bit values. Content verification The signature as it is read from the FMSW0 to FMSW3 registers must be equal to the reference signature. The algorithms to derive the reference signature is given in Figure 32–138 Fig 138. Algorithm for generating a 128 bit signature sign = 0 FOR address = FMSTART.FMSTART TO FMSTOP.FMSTOP FOR i = 0 TO 126 nextSign[i] = f_Q[address][i] XOR sign[i+1] nextSign[127] = f_Q[address][127] XOR sign[0] XOR sign[2] XOR sign[27] XOR sign[29] sign = nextSign signature128 = sign

Supports both standard JTAG and ARM Serial Wire Debug modes.
Direct debug access to all memories, registers, and peripherals.
No target resources are required for the debugging session.
Trace port provides CPU instruction trace capability. Output can be via a 4-bit trace data port, or Serial Wire Viewer.
Eight Breakpoints. Six instruction breakpoints that can also be used to remap instruction addresses for code patches. Two data comparators that can be used to remap addresses for patches to literal values.
Four data Watchpoints that can also be used as trace triggers.
Instrumentation Trace Macrocell allows additional software controlled trace. 2. Introduction Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watchpoints. 3. Description Debugging with the LPC17xx defaults to JTAG. Once in the JTAG debug mode, the debug tool can switch to Serial Wire Debug mode. Trace can be done using either a 4-bit parallel interface or the Serial Wire Output. When the Serial Wire Output is used, less data can be traced, but it uses no application related pins. Parallel trace has a greater bandwidth, but uses 5 functional pins that may be needed in the application. Note that the trace function available for the Cortex-M3 is functionally very different than the trace that was available for previous ARM7 based devices, using only 5 pins instead of 10. 4. Pin Description The tables below indicate the various pin functions related to debug and trace. Some of these functions share pins with other functions which therefore may not be used at the same time. Use of the JTAG port excludes use of Serial Wire Debug and Serial Wire Output. Use of the parallel trace requires 5 pins that may be part of the user application, limiting debug possibilities for those features. Trace using the Serial Wire Output does not have this limitation, but has a limited bandwidth. UM10360 Chapter 33: LPC17xx JTAG, Serial Wire Debug, and Trace Rev. 01 — 4 January 2010 User manual

UM10360_1 © NXP B.V. 2010. All rights reserved. recommended not to use these modes during debug. Table 609. JTAG pin description TDI Input JTAG Test Data In. This is the serial data input for the shift register. LPC23xx series devices that share the same pinout as this device. RTCK is not normally used with the Cortex-M3. considerations Application Note 72 (ARM DAI 0072A)". Table 610. Serial Wire Debug pin description ITM and/or the ETM for an external debug tool to evaluate. Table 611. Parallel Trace pin description

UM10360_1 © NXP B.V. 2010. All rights reserved. normal operation in an application. operations, such as single stepping. Debugging is disabled if code read protection is enabled. correct the mapping automatically in this case, so that a user does not need to deal with it.

6.1 Memory Mapping Control re gister (MEMMAP - 0x400F C040)

Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description 0 Boot mode. A portion of the Boot ROM is mapped to address 0. 1 User mode. The on-chip Flash memory is mapped to address 0.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 641 of 835 1. ARM Cortex-M3 User Guide: Introduction The material in this appendix is provided by ARM Limited for inclusion in the User Manuals of devices containing the Cortex-M3 CPU. Minimal changes have been made to reflect implementation options and other distinctions that apply specifically to LPC17xx devices.

1.1 About the processor and core peripherals

The Cortex-M3 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including:

outstanding processing performance combined with fast interrupt handling
enhanced system debug with extensive breakpoint and trace capabilities
efficient processor core, system and memories
ultra-low power consumption with integrated sleep modes
platform security, with optional integrated memory protection unit (MPU). The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including single-cycle 32x32 multiplication and dedicated hardware division. UM10360 Chapter 34: Appendix: Cortex-M3 User Guide Rev. 01 — 4 January 2010 User manual Fig 139. Typical Cortex-M3 implementation 3URFHVVRU FRUH (PEHGGHG 7UDFH0DFURFHOO19,& 'HEXJ $FFHVV 3RUW 0HPRU\\ SURWHFWLRQXQLW :,& 6HULDO :LUH YLHZHU %XVPDWUL[ &RGH LQWHUIDFH 65$0DQG SHULSKHUDOLQWHUIDFH 'DWD ZDWFKSRLQWV )ODVK SDWFK &RUWH[0 SURFHVVRU

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 642 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M3 processor implements a version of the Thumb instruction set, ensuring high code density and reduced program memory requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M3 processor closely integrates a configurable nested interrupt controller (NVIC), to deliver industry-leading interrupt performance. The NVIC includes a non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require any assembler stubs, removing any code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to be rapidly powered down. LPC17xx devices support additional reduced power modes, see Section 4–8 “Power control” for details.

1.1.1 System level interface

The Cortex-M3 processor provides multiple interfaces using AMBA technology to provide high speed, low latency memory accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe Boolean data handling. The Cortex-M3 processor has an optional memory protection unit (MPU) that provides fine grain memory control, enabling applications to implement security privilege levels, separating code, data and stack on a task-by-task basis. Such requirements are becoming critical in many embedded applications such as automotive. The MPU is included in LPC17xx devices.

1.1.2 Integrated configurable debug

The Cortex-M3 processor implements a complete hardware debug solution. This provides high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. The MCU vendor determines the debug feature configuration and therefore this can differ across different devices and families. For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. The optional Embedded Trace Macrocell (ETM) delivers unrivalled instruction trace capture in an area far smaller than traditional trace units, enabling many low cost MCUs to implement full instruction trace for the first time.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 643 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide LPC17xx devices support JTAG and Serial Wire Debug, Serial Wire Viewer, and include the Embedded Trace Macrocell. See Section 33–1 for additional information.

1.1.3 Cortex-M3 processor features and benefits summary

tight integration of system peripherals reduces area and development costs
Thumb instruction set combines high code density with 32-bit performance
code-patch ability for ROM system updates
power control optimization of system components
integrated sleep modes for low power consumption
fast code execution permits slower processor clock or increases sleep mode time
hardware division and fast multiplier
deterministic, high-performance interrupt handling for time-critical applications
optional memory protection unit (MPU) for safety-critical applications
extensive debug and trace capabilities: – Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing.

1.1.4 Cortex-M3 core peripherals

These are:

Nested Vectored Interrupt Controller The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low latency interrupt processing.
System control block The System control block (SCB) is the programmers model interface to the processor. It provides system implementation information and system control, including configuration, control, and reporting of system exceptions.
System timer The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System (RTOS) tick timer or as a simple counter.
Memory protection unit The Memory protection unit (MPU) improves system reliability by defining the memory attributes for different memory regions. It provides up to eight different regions, and an optional predefined background region.

ARM Cortex-M3 User Guide: Instruction Set

2.1 Instruction set summary

angle brackets, <>, enclose alternative forms of the operand
braces, {}, enclose optional operands
the Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
most instructions can use an optional condition code suffix. For more information on the instructions and operands, see the instruction descriptions.

Table 613. Cortex-M3 instructions

2.2 Intrinsic functions

function, you might have to use inline assembler to access some instructions.

2.3 About the instruction descriptions

Table 614. CMSIS intrinsic functions to generate some Cortex-M3 instructions Table 615. CMSIS intrinsic functions to access the special registers

Section 34–2.3.1 “Operands”
Section 34–2.3.2 “Restrictions when using PC or SP”
Section 34–2.3.3 “Flexible second operand”
Section 34–2.3.4 “Shift Operations”
Section 34–2.3.5 “Address alignment”
Section 34–2.3.6 “PC-relative expressions”
Section 34–2.3.7 “Conditional execution”
Section 34–2.3.8 “Instruction width selection”.

2.3.1 Operands

An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. When there is a destination register in the instruction, it is usually specified before the operands. Operands in some instructions are flexible in that they can either be a register or a constant. See Section 34–2.3.3.

2.3.2 Restrictions when using PC or SP

Many instructions have restrictions on whether you can use the Program Counter (PC) or Stack Pointer (SP) for the operands or destination register. See instruction descriptions for more information. Remark: Bit[0] of any address you write to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1 for correct execution, because this bit indicates the required instruction set, and the Cortex-M3 processor only supports Thumb instructions.

2.3.3 Flexible second operand

Many general data processing instructions have a flexible second operand. This is shown as Operand2 in the descriptions of the syntax of each instruction. Operand2 can be a:

Section 34–2.3.3.1 “Constant”
Section 34–2.3.3.2 “Register with optional shift”

2.3.3.1 Constant

You specify an Operand2 constant in the form: constant where constant can be:

any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word
any constant of the form 0x00XY00XY
any constant of the form 0xXY00XY00
any constant of the form 0xXYXYXYXY .

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 649 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide Remark: In the constants shown above, X and Y are hexadecimal digits. In addition, in a small number of instructions, constant can take a wider range of values. These are described in the individual instruction descriptions. When an Operand2 constant is used with the instructions MOVS , MVNS , ANDS , ORRS , ORNS , EORS , BICS , TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2 is any other constant. Instruction substitution: Your assembler might be able to produce an equivalent instruction in cases where you specify a constant that is not permitted. For example, an assembler might assemble the instruction CMP Rd, #0xFFFFFFFE as the equivalent instruction CMN Rd, #0x2 .

2.3.3.2 Register with optional shift

You specify an Operand2 register in the form: Rm {, shift} where: Rm is the register holding the data for the second operand. shift is an optional shift to be applied to Rm. It can be one of: ASR#n: arithmetic shift right n bits, 1 ≤ n ≤ 32. LSL#n: logical shift left n bits, 1 ≤ n ≤ 31. LSR#n: logical shift right n bits, 1 ≤ n ≤ 32. ROR#n: rotate right n bits, 1 ≤ n ≤ 31. RRX: rotate right one bit, with extend. —: if omitted, no shift occurs, equivalent to LSL#0 . If you omit the shift, or specify LSL #0, the instruction uses the value in Rm. If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the instruction. However, the contents in the register Rm remains unchanged. Specifying a register with shift also updates the carry flag when used with certain instructions. For information on the shift operations and how they affect the carry flag, see Section 34–2.3.4 “ Shift Operations”

2.3.4 Shift Operations

Register shift operations move the bits in a register left or right by a specified number of bits, the shift length. Register shift can be performed:

directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a destination register
during the calculation of Operand2 by the instructions that specify the second operand as a register with shift, see Section 34–2.3.3. The result is used by the instruction.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 650 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide The permitted shift lengths depend on the shift type and the instruction, see the individual instruction description or Section 34–2.3.3. If the shift length is 0, no shift occurs. Register shift operations update the carry flag except when the specified shift length is 0. The following sub-sections describe the various shift operations and how they affect the carry flag. In these descriptions, Rm is the register containing the value to be shifted, and n is the shift length.

2.3.4.1 ASR

Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of the register into the left-hand n bits of the result. See Figure 34–140. You can use the ASR #n operation to divide the value in the register Rm by 2n, with the result being rounded towards negative-infinity. When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS , MVNS , ANDS , ORRS , ORNS , EORS , BICS , TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm. Note

If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.

2.3.4.2 LSR

Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it sets the left-hand n bits of the result to 0. See Figure 34–141. You can use the LSR #n operation to divide the value in the register Rm by 2n, if the value is regarded as an unsigned integer. When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS , MVNS , ANDS , ORRS , ORNS , EORS , BICS , TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm. Note

If n is 32 or more, then all the bits in the result are cleared to 0. Fig 140. ASR #3 &DUU\\ )ODJ

If n is 33 or more and the carry flag is updated, it is updated to 0.

2.3.4.3 LSL

Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32-n bits of the result. And it sets the right-hand n bits of the result to 0. See Figure 34–142. You can use he LSL #n operation to multiply the value in the register Rm by 2n, if the value is regarded as an unsigned integer or a two’s complement signed integer. Overflow can occur without warning. When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with the instructions MOVS , MVNS , ANDS , ORRS , ORNS , EORS , BICS , TEQ or TST, the carry flag is updated to the last bit shifted out, bit[32-n], of the register Rm. These instructions do not affect the carry flag when used with LSL #0. Note

If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.

2.3.4.4 ROR

Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it moves the right-hand n bits of the register into the left-hand n bits of the result. See Figure 34–143. When the instruction is RORS or when ROR #n is used in Operand2 with the instructions MOVS , MVNS , ANDS , ORRS , ORNS , EORS , BICS , TEQ or TST, the carry flag is updated to the last bit rotation, bit[n-1], of the register Rm. Note Fig 141. LSR#3 &DUU\\ )ODJ Fig 142. LSL#3 &DUU\\ )ODJ

If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated to bit[31] of Rm.
ROR with shift length, n, more than 32 is the same as ROR with shift length n-32.

2.3.4.5 RRX

Rotate right with extend moves the bits of the register Rm to the right by one bit. And it copies the carry flag into bit[31] of the result. See Figure 34–144. When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS , MVNS , ANDS , ORRS , ORNS , EORS , BICS , TEQ or TST, the carry flag is updated to bit[0] of the register Rm.

2.3.5 Address alignment

An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned. The Cortex-M3 processor supports unaligned access only for the following instructions:

LDR, LDRT
LDRH , LDRHT
LDRSH , LDRSHT
STR, STRT
STRH , STRHT All other load and store instructions generate a usage fault exception if they perform an unaligned access, and therefore their accesses must be address aligned. For more information about usage faults see Section 34–3.4 “Fault handling”. Fig 143. ROR#3 &DUU\\ )ODJ Fig 144. RRX &DUU\\ )ODJ

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 653 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses are aligned. To avoid accidental generation of unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control Register to trap all unaligned accesses, see Section 34–4.3.8 “Configuration and Control Register”.

2.3.6 PC-relative expressions

A PC-relative expression or label is a symbol that represents the address of an instruction or literal data. It is represented in the instruction as the PC value plus or minus a numeric offset. The assembler calculates the required offset from the label and the address of the current instruction. If the offset is too big, the assembler produces an error. Note

For B, BL, CBNZ , and CBZ instructions, the value of the PC is the address of the current instruction plus 4 bytes.
For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it word-aligned.
Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a number, or an expression of the form [PC, #number] .

2.3.7 Conditional execution

Most data processing instructions can optionally update the condition flags in the Application Program Status Register (APSR) according to the result of the operation, see Section 34–3.1.3.5 “ Program Status Register”. Some instructions update all flags, and some only update a subset. If a flag is not updated, the original value is preserved. See the instruction descriptions for the flags they affect. You can execute an instruction conditionally, based on the condition flags set in another instruction, either:

immediately after the instruction that updated the flags
after any number of intervening instructions that have not updated the flags. Conditional execution is available by using conditional branches or by adding condition code suffixes to instructions. See Table 34–616 for a list of the suffixes to add to instructions to make them conditional instructions. The condition code suffix enables the processor to test a condition based on the flags. If the condition test of a conditional instruction fails, the instruction:
does not execute
does not write any value to its destination register
does not affect any of the flags
does not generate any exception. Conditional instructions, except for conditional branches, must be inside an If-Then instruction block. See Section 34–2.9.3 for more information and restrictions when using the IT instruction. Depending on the vendor, the assembler might automatically insert an IT instruction if you have conditional instructions outside the IT block.

Section 34–2.3.7.1 “The condition flags”
Section 34–2.3.7.2 “Condition code suffixes”.

2.3.7.1 The condition flags

N — Set to 1 when the result of the operat ion was negative, cleared to 0 otherwise. Z — Set to 1 when the result of the operation was zero, cleared to 0 otherwise. C — Set to 1 when the operation resulted in a carry, cleared to 0 otherwise. V — Set to 1 when the operation caused overflow, cleared to 0 otherwise.

if the result of an addition is greater than or equal to 232
if the result of a subtraction is positive or zero
as the result of an inline barrel shifter operation in a move or logical instruction. Overflow occurs if the result of an add, subtract, or compare is greater than or equal to 231, or less than –231. Remark: Most instructions update the status flags only if the S suffix is specified. See the instruction descriptions for more information.

2.3.7.2 Condition code suffixes

meet the specified condition. Table 34–616 shows the condition codes to use. Table 616. Condition code suffixes

2.3.8 Instruction width selection

encoding of the requested width, it generates an error. operand is the label of an instruction or literal data, as in the case of branch instructions. This is because the assembler might not automatically generate the right size encoding. Always. This is the default when no suffix is specified.

2.3.8.1 Example: Instruction width selection

BCS.W label ; creates a 32-bit instruction even for a short branch ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same ; operation can be done by a 16-bit instruction

2.4 Memory access instructions

Table 617. Memory access instructions

2.4.1 ADR

Load PC-relative address.

2.4.1.1 Syntax

ADR{cond} Rd, label where: cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rd is the destination register. label is a PC-relative expression. See Section 34–2.3.6 “PC-relative expressions”.

2.4.1.2 Operation

ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register. ADR produces position-independent code, because the address is PC-relative. If you use ADR to generate a target address for a BX or BLX instruction, you must ensure that bit[0] of the address you generate is set to1 for correct execution. Values of label must be within the range of −4095 to +4095 from the address in the PC. Remark: You might have to use the .W suffix to get the maximum offset range or to generate addresses that are not word-aligned. See Section 34–2.3.8 “Instruction width selection”.

2.4.1.3 Restrictions

Rd must not be SP and must not be PC.

2.4.1.4 Condition flags

This instruction does not change the flags.

2.4.1.5 Examples

ADR R1, TextMessage ; Write address value of a location labelled as ; TextMessage to R1

2.4.2 LDR and STR, immediate offset

Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.

2.4.2.1 Syntax

op{type}{cond} Rt, [Rn {, #offset}] ; immediate offset op{type}{cond} Rt, [Rn, #offset]! ; pre-indexed op{type}{cond} Rt, [Rn], #offset ; post-indexed opD{cond} Rt, Rt2, [Rn {, #offset}] ; immediate offset, two words opD{cond} Rt, Rt2, [Rn, #offset]! ; pre-indexed, two words opD{cond} Rt, Rt2, [Rn], #offset ; post-indexed, two words where: op is one of: LDR: Load register. STR: Store register. type is one of: B: unsigned byte, zero extend to 32 bits on loads. SB: signed byte, sign extend to 32 bits (LDR only). H: unsigned halfword, zero extend to 32 bits on loads. SH: signed halfword, sign extend to 32 bits (LDR only). —: omit, for word. cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an offset from Rn. If offset is omitted, the address is the contents of Rn. Rt2 is the additional register to load or store for two-word operations.

2.4.2.2 Operation

LDR instructions load one or two registers with a value from memory. STR instructions store one or two register values to memory. Load and store instructions with immediate offset can use the following addressing modes:

Offset addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access. The register Rn is unaltered. The assembly language syntax for this mode is:

Pre-indexed addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn. The assembly language syntax for this mode is: [Rn, #offset]!
Post-indexed addressing The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for this mode is: [Rn], #offset The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or unsigned. See Section 34–2.3.5 “ Address alignment”. Table 34–618 shows the ranges of offset for immediate, pre-indexed and post-indexed forms.

2.4.2.3 Restrictions

Rt can be SP or PC for word loads only
Rt must be different from Rt2 for two-word loads
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms. When Rt is PC in a word load instruction:
bit[0] of the loaded value must be 1 for correct execution
a branch occurs to the address created by changing bit[0] of the loaded value to 0
if the instruction is conditional, it must be the last instruction in the IT block. For store instructions:
Rt can be SP for word stores only
Rt must not be PC
Rn must not be PC
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.

2.4.2.4 Condition flags

These instructions do not change the flags. Table 618. Offset ranges

2.4.2.5 Examples

LDR R8, [R10] ; Loads R8 from the address in R10. LDRNE R2, [R5, #960]! ; Loads (conditionally) R2 from a word ; 960 bytes above the address in R5, and ; increments R5 by 960. STR R2, [R9,#const-struc] ; const-struc is an expression evaluating ; to a constant in the range 0-4095. STRH R3, [R4], #4 ; Store R3 as halfword data into address in ; R4, then increment R4 by 4 LDRD R8, R9, [R3, #0x20] ; Load R8 from a word 32 bytes above the ; address in R3, and load R9 from a word 36 ; bytes above the address in R3 STRD R0, R1, [R8], #-16 ; Store R0 to address in R8, and store R1 to ; a word 4 bytes above the address in R8, ; and then decrement R8 by 16.

2.4.3 LDR and STR, register offset

Load and Store with register offset.

2.4.3.1 Syntax

op{type}{cond} Rt, [Rn, Rm {, LSL #n}] where: op is one of: LDR: Load Register. STR: Store Register. type is one of: B: unsigned byte, zero extend to 32 bits on loads. SB: signed byte, sign extend to 32 bits (LDR only). H: unsigned halfword, zero extend to 32 bits on loads. SH: signed halfword, sign extend to 32 bits (LDR only). —: omit, for word. cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rt is the register to load or store. Rn is the register on which the memory address is based. Rm is a register containing a value to be used as the offset. LSL #n is an optional shift, with n in the range 0 to 3.

2.4.3.2 Operation

LDR instructions load a register with a value from memory. STR instructions store a register value into memory. The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the register Rm and can be shifted left by up to 3 bits using LSL. The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned. See Section 34–2.3.5 “Address alignment”.

2.4.3.3 Restrictions

In these instructions:

Rn must not be PC
Rm must not be SP and must not be PC
Rt can be SP only for word loads and word stores
Rt can be PC only for word loads. When Rt is PC in a word load instruction:

bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address
if the instruction is conditional, it must be the last instruction in the IT block.

2.4.3.4 Condition flags

These instructions do not change the flags.

2.4.3.5 Examples

STR R0, [R5, R1] ; Store value of R0 into an address equal to ; sum of R5 and R1 LDRSB R0, [R5, R1, LSL #1] ; Read byte value from an address equal to ; sum of R5 and two times R1, sign extended it ; to a word value and put it in R0 STR R0, [R1, R2, LSL #2] ; Stores R0 to an address equal to sum of R1 ; and four times R2

2.4.4 LDR and STR, unprivileged

Load and Store with unprivileged access.

2.4.4.1 Syntax

op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset where: op is one of: LDR: Load Register. STR: Store Register. type is one of: B: unsigned byte, zero extend to 32 bits on loads. SB: signed byte, sign extend to 32 bits (LDR only). H: unsigned halfword, zero extend to 32 bits on loads. SH: signed halfword, sign extend to 32 bits (LDR only). —: omit, for word. cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the value in Rn.

2.4.4.2 Operation

These load and store instructions perform the same function as the memory access instructions with immediate offset, see Section 34–2.4.2. The difference is that these instructions have only unprivileged access even when used in privileged software. When used in unprivileged software, these instructions behave in exactly the same way as normal memory access instructions with immediate offset.

2.4.4.3 Restrictions

In these instructions:

Rn must not be PC
Rt must not be SP and must not be PC.

2.4.4.4 Condition flags

These instructions do not change the flags.

2.4.4.5 Examples

STRBTEQ R4, [R7] ; Conditionally store least significant byte in ; R4 to an address in R7, with unprivileged access LDRHT R2, [R2, #8] ; Load halfword value from an address equal to ; sum of R2 and 8 into R2, with unprivileged access

2.4.5 LDR, PC-relative

2.4.5.1 Syntax

B: unsigned byte, zero extend to 32 bits on loads. SB: signed byte, sign extend to 32 bits (LDR only). H: unsigned halfword, zero extend to 32 bits on loads. SH: signed halfword, sign extend to 32 bits (LDR only). cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rt is the register to load or store. Rt2 is the second register to load or store. label is a PC-relative expression. See Section 34–2.3.6 “PC-relative expressions”.

2.4.5.2 Operation

address is specified by a label or by an offset from the PC. possible offsets between label and the PC. Section 34–2.3.8 “Instruction width selection”.

2.4.5.3 Restrictions

Rt can be SP or PC only for word loads
Rt2 must not be SP and must not be PC
Rt must be different from Rt2. When Rt is PC in a word load instruction:

Table 619. Offset ranges

bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address
if the instruction is conditional, it must be the last instruction in the IT block.

2.4.5.4 Condition flags

These instructions do not change the flags.

2.4.5.5 Examples

LDR R0, LookUpTable ; Load R0 with a word of data from an address ; labelled as LookUpTable LDRSB R7, localdata ; Load a byte value from an address labelled ; as localdata, sign extend it to a word ; value, and put it in R7

2.4.6 LDM and STM

Load and Store Multiple registers.

2.4.6.1 Syntax

where: op is one of: LDM: Load Multiple registers. STM: Store Multiple registers. addr_mode is any one of the following: IA: Increment address After each access. This is the default. DB: Decrement address Before each access. cond is an optional condition code, see Section 34–2.3.7 “Conditional execution”. Rn is the register on which the memory addresses are based. ! is an optional writeback suffix. If ! is present the final address, that is loaded from or stored to, is written back into Rn. reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range, see Section 34–2.4.6.5. LDM and LDMFD are synonyms for LDMIA . LDMFD refers to its use for popping data from Full Descending stacks. LDMEA is a synonym for LDMDB , and refers to its use for popping data from Empty Ascending stacks. STM and STMEA are synonyms for STMIA . STMEA refers to its use for pushing data onto Empty Ascending stacks. STMFD is s synonym for STMDB , and refers to its use for pushing data onto Full Descending stacks

2.4.6.2 Operation

LDM instructions load the registers in reglist with word values from memory addresses based on Rn. STM instructions store the word values in the registers in reglist to memory addresses based on Rn. For LDM, LDMIA , LDMFD , STM, STMIA , and STMEA the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of registers in reglist. The accesses happens in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4 * (n-1) is written back to Rn.

UM10360_1 © NXP B.V. 2010. All rights reserved. User manual Rev. 01 — 4 January 2010 669 of 835 NXP Semiconductors UM10360 Chapter 34: Appendix: Cortex-M3 User Guide For LDMDB , LDMEA , STMDB , and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist. The accesses happen in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn. The PUSH and POP instructions can be expressed in this form. See Section 34–2.4.7 for details.

2.4.6.3 Restrictions

In these instructions:

Rn must not be PC
reglist must not contain SP
in any STM instruction, reglist must not contain PC
in any LDM instruction, reglist must not contain PC if it contains LR
reglist must not contain Rn if you specify the writeback suffix. When PC is in reglist in an LDM instruction:
bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfword-aligned address
if the instruction is conditional, it must be the last instruction in the IT block.

2.4.6.4 Condition flags

These instructions do not change the flags.

2.4.6.5 Examples

LDM R8,{R0,R2,R9} ; LDMIA is a synonym for LDM STMDB R1!,{R3-R6,R11,R12}

2.4.6.6 Incorrect examples

STM R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable LDM R2, {} ; There must be at least one register in the list

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Product Information

UM10360 specifications and overview.

Summary

LPC17xx User manual Rev. 01-4 January 2010

Description

LPC17xx User manual Rev. 01-4 January 2010

Source title UM10360 Datasheet(PDF) - NXP Semiconductors

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