UD61256

UD61256 ZMD | Alldatasheet

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Technical content

Features

/G70 Dynam ic random access m em ory 262144 x 1 bit m anufactured using a CM OS technology /G70 R A S access tim es 70 ns, 80 ns /G70 TTL-com patible /G70 Three-state output /G70 256 refresh cycles 4 m s refresh cycle time /G70 FAST PAGE M O DE /G70 O perating m odes: R ead, W rite, Read - W rite, R A S only Refresh, H idden R efresh w ith address transfer /G70 P ow er Supply Voltage 5 V /G70 P ackages PDIP 16 ( 300 m il) SOJ2 0/26 (300 m il) /G70 O perating tem perature range 0 to 70 °C /G70 Q uality assessm ent according to C E C C 90000, CECC 90100 and C E CC 90112

Description

The UD 61256 is a dynam ic W rite- Read-m em ory w ith random access. FPM facilitates faster data operation w ith predefined row address. Via 9 address inputs the 18 address bits are transm itted into the internal address m em ories in a tim e-m ulti- plex operation. The falling R AS- edge takes over the row a ddress. Du ring R A S L ow, t he column address together w ith the CA S signal are taken over. The selection of one or m ore m em ory circuits can be m ade by activation of the RA S input. Re ad-Write-Control The choice betw een Read or Wr ite cycle is m ade at the W input. HIGH at the W input causes a Read cycle, m eanw hile LO W leads to a W rite cycle. Both C AS-controlled and W -control- led W rite cycles are possible w ith activated RA S signal. Data O utput Control The usual state of the data output is the High-Z state. W henever CA S is inactive (HIGH), Q w ill float (High-Z). Thus, CAS functions as data output control. After access time , in case of a Read cycle, the output is activated, and it contains the logic „0“ or „1“. Q is then valid until C AS returns into to inactive state (H IGH). The m em ory cycle being a Read, Read-W rite or a Wr ite cycle (W -con- trolled), Q ch anges from H igh-Z state to the active state („0“ or „1“). After the access time the contents of the selected cell is available, except for the W rite cycle. The output rem ains active until CA S becom es inactive, irrespective of RAS becom ing inactive or not. The m em ory cycle being a W rite cycle (CAS -controlled), the data o utput keeps its High-Z state throughout the w hole cycle. This configuration m akes Q fully controllable by the user merely through the tim ing of W . The output storaging the data, they rem ain valid from the end of access time until the start of another cycle. Pin Configuration 1A8 VS S16 2D C AS15 4R A S A613 5A0 A312

3 Q14

W 1A8 V26 2D C A S25 4R AS A623 10A0 A317

3 Q24

W 5n.c. n.c.22 9n.c. n.c.18 Pin Description Signal N am e Signal D escription A0 - A 8 Address Inputs D Da ta Input W Read, W rite Control R A S Row A ddress Strobe U CC Power Supply Voltage U SS Ground C A S Column A ddress Strobe Q Da ta Output n.c. no connected Top View Top View 256K x 1 DR A M SOJ PD IP

December 12, 1997 UD61256 Operation Function RAS CAS W Address Data RCDQ Stand-by H X X X X X High-Z Read LL H R o w C o l u m n X Output Data Write L L L Row Column Input Data High-Z Read-W rite L L H → L Row Column Input Data Output Data FPM Read 1st cycle LH → LH R o w C o l u m nX Output Data 2nd cycle L H → LH C o l u m nX Output Data FPM Write 1st cycle LH → L L Row Column Input Data High-Z 2nd cycle LH → L L Column Input Data High-Z FPM Read-W rite 1st cycle LH → LH → L Row Column Input Data Output Data 2nd cycle LH → LH → L Column Input Data Output Data RAS only Refresh L H X Row X High-Z HIDDEN Refresh Read L → H → LL H R o wC o l u m n X Output Data Write L → H → L L L Row Column Input Data High-Z *) Transfer of Refresh Address required Block Diagram Output Control QCAS D W RAS VCC VSS Row Decoder Row Decoder A0X to A7X A0Y to A7Y Data Input Amplifier Write-Read Control Clock Generator Decoder 1 out of 4 Data Output Amplifier M U X

4 Write-Read

128 Kbit Array with

December 12, 1997 UD61256 Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and operating temperature range indicated below. Absolute Maximum Ratings Symbol Min. Max. Unit Power Supply Voltage V CC -0.5 7.0 V Input Voltage 1) VI -1.0 7.0 V Output Voltage 1) VO -1.0 7.0 V Output Current I O -50 50 mA Power Dissipation P D 1W Operating T emperature T a 07 0 °C Storage T emperature T stg -55 125 °C Remarks: see page 7 Recommended Operating Conditions Symbol Min. Max. Unit Power Supply Voltage V CC 4.5 5.5 V Input Low Voltage 1) VIL -1.0 0.8 V Input High Voltage V IH 2.4 5.5 V Remark: see page 7 Capacitances Conditions Symbol Min. Max. Unit Input Capacitance A0 to A8, D VCC = 5.0 V VI = V SS f = 1 MHz T a = 25 °C C I1 6p F Input Capacitance RAS , CAS, W C I2 7p F Output Capacitance C O 7p F All pins not under test must be connected with ground by capacitors.

December 12, 1997 UD61256 Static Characteristics Conditions Symbol Min. Max. Unit 07 08 07 08 Power Supply Current (average value of RAS-CAS cycles) 2) tcW = tcWmin tcR = tcRmin ICC1 70 60 mA Refresh Current (average value of RAS cycles) 2) tcW = tcWmin tcR = tcRmin CAS = VIH ICC2 70 60 mA FPM Current (average value of FPM cycles) 2) tcPG = tcPGmin RAS = VIL ICC3 50 40 mA Stand-by Current (TTL Level) RAS = CAS = VIH ICC4 22 m A Stand-by Current (CMOS Level) RAS = CAS = VCC - 0.2 V ICC5 11 m A Output High Voltage I OH = -5 mA V OH 2.4 2.4 V Output Low Voltage I OL = 4.2 mA V OL 0.4 0.4 V Input Leakage Current at any input, all other pins = 0 V V I = 0 V to 5.5 V II -10 -10 10 10 µA Output Leakage Current Q = High-Z VO = 0 V to 5.5 V RAS = CAS = VIH IO -10 -10 10 10 µA Remarks: see page 7

December 12, 1997 UD61256 Dynamic Characteristics 3) Symbol Min. Max. Unit A l t . I E C 0 70 80 70 8 /G70 ALL CYCLES Transition Time (Rise and Fall) 4) tT tt 3 3 50 50 ns RAS Precharge Time CAS Precharge Time tRP tCP tw(RASH) tw(CASH) ns ns Row Address Set-up Time Column Address Set-up Time tASR tASC tsu(RA-RAS) tsu(CA-CAS) ns ns Row Address Hold Time Column Address Hold Time Column Address Hold Time ref. to RAS tRAH tCAH tAR th(RAS-RA) th(CAS-CA) th(RAS-CA) ns ns ns Output Buffer Turn-off Delay 5) tOFF tv(CAS) 0 0 20 20 ns CAS to RAS Precharge Time RAS to Column Address Delay Time Column Address to RAS Lead Time CAS to Output in Low-Z Refresh Period tCRP tRAD tRAL tCLZ tREF tCASH-RASL tRAS-CA tCA-RASH tCASL-QX trf ns ns ns ns ms /G70 READ Random Read Cycle Time 12) tRC tcR 130 150 ns Access Time from RAS Access Time from Column Address Access Time from CAS tRAC tAA tCAC ta(RAS) ta(CA) ta(CAS) ns ns ns RAS Pulse Width CAS Pulse Width tRAS tCAS tw(RASL) tw(CASL) 10000 10000 10000 10000 ns ns Read Command Set-up Time Read Command Hold Time ref. to RAS Read Command Hold Time tRCS tRRH tRCH tsu(R-CAS) th(RAS-R) th(CAS-R) ns ns ns RAS to CAS Delay Time CAS Hold Time RAS Hold Time 6) tRCD tCSH tRSH tRASL-CASL tRASL-CASH tCASL-RASH 50 60 ns ns ns /G70 WRITE Random Write Cycle Time 12) tRC tcW 130 150 ns RAS Pulse Width CAS Pulse Width Write Command Pulse Width tRAS tCAS tWP tw(RASL) tw(CASL) tw(W) 10000 10000 10000 10000 ns ns ns Remarks: see page 7 7), 7), 7),

December 12, 1997 UD61256 /G70 WRITE (continuation) Write Command Set-up Time Data Set-up Time ref. to CAS Data Set-up Time ref. to W 10) 11) 11) tWCS tDS tDS tsu(W-CAS) tsu(D-CAS) tsu(D-W) ns ns ns Write Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data Hold Time ref. to RAS Data Hold Time ref. to CAS Data Hold Time ref. to W tWCH tRWL tCWL tDHR tDH tDH th(CAS-W) th(W-RAS) th(W-CAS) th(RAS-D) th(CAS-D) th(W-D) ns ns ns ns ns ns RAS to CAS Delay Time CAS Hold Time RAS Hold Time 6) tRCD tCSH tRSH tRASL-CASL tRASL-CASH tCASL-RASH 50 60 ns ns ns /G70 READ-WRITE Read-Write Cycle Time 12) tRWC tcRW 155 175 ns RAS Pulse Width CAS Pulse Width tRAS tCAS tw(RASL)RW tw(CASL)RW 105 10000 10000 10000 10000 ns ns CAS Hold Time RAS to WRITE Delay Time CAS to WRITE Delay Time Column to WRITE Delay Time 10) 10) 10) tCSH tRWD tCWD tAWD t(RASL- CASH)RW tRAS-W tCAS-W t(CA-W)RW 105 ns ns ns ns /G70 FPM Fast Page Mode Cycle Time RAS Pulse Width 12) tPC tRASP tcPG tw(RASL) 80 100000 100000 ns ns Access Time from CAS Precharge t CPA ta(CASH) 35 40 ns /G70 HIDDEN-REFRESH CAS Hold Time (CAS before RAS Cycle) t CHR tRASL-CASH 15 15 ns Remarks: see page 7 Dynamic Characteristics 3) Symbol Min. Max. Unit A l t . I E C 0 70 80 70 8

December 12, 1997 UD61256 Remarks: 1) The Input Low Voltage must not drop below -0.3 V for more than 40 ns. 2) The current is inversely propor- tional to the cycle time; the max. current is measured in the shor- test cycle time. 3) For test conditions see test con- figuration for functional test and timing diagrams. 4) VIHmin and VILmax are reference levels for time measurement of the input signals; transition times are measured between V IH and VIL. 5) tv(CAS) and tv(RAS) define the time at which the data output goes to High-Z; this time is not related to any level. 6) tRASL-CASLmax and t RAS-CA are given as reference points only; they do not represent restrictive conditions. 7) The access time is determined by the three times t a(RAS), ta(CAS) and ta(CA): - if tRASL-CASL < tRASL-CASLmax and tRAS-CA < t RAS-CAmax ta(RAS) is valid, - if tRASL-CASL > tRASL-CASLmax and tsu(CA-CAS) < (ta(CA)max - ta(CAS)max ) ta(CA) is valid, - if tRASL-CASL > tRASL-CASLmax and tsu(CA-CAS) > (ta(CA)max - ta(CAS)max ) ta(CAS) is valid. 8) Measured with a load equivalent to 2 TTL loads. 9) In a READ cycle either th(RAS-R) or th(CAS-R) must be kept. 10)tsu(W-CAS), tRAS-W , tCAS-W and tsu(A) do not represent restrictive para- meters: - if t su(W-CAS) ≥ tsu(W-CA S)min, the cycle is a WRITE cycle (CAS- controlled) and the data output remains in High-Z throughout the whole CAS cycle, - if tCAS-W > tCAS-Wmin , tRAS-W > tRAS-Wmin and tsu(CA-W)RW > tsu(CA-W)RWmin , the cycle is a READ-WRITE cycle and the content of the cell is available at the data output, - if none of these conditions is satisfied, the condition of the data output (at access time) is indeterminate, since a WRITE cycle (W -controlled) is carried out. 11)These parameters refer to CAS in the WRITE cycle (CAS-con- trolled) and to W during WRITE (W -controlled) or to W in the READ-WRITE cycle, resp. 12)The values of tcmin are used for indication of the particular cycle time in which full function is gua- ranteed in the temperature range from 0 to 70 °C. Values below the one shown above may cause permanent damage to the com- ponent.

December 12, 1997 UD61256 IC Code Numbers Test Configuration for Functional Check The date of manufacture is given by the 4 last digits of the mark, the 2 first digits indicating the year, and the last 2 digits the calendar week. DUD61256 07C Access Time Package 07 = 70 ns 08 = 80 ns Operating Temperature Range C = 0 to 70 °C Type D = PDIP J= S O J Output voltage check according to timing diagrams Input voltage according to timing diagrams (at least 8 operating cycles before measurement). All addresses are to be checked. VCC 5 V 1,2 K VSS 100 pF 680 VIH VIL RAS CAS W D Q

December 12, 1997 UD61256 VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL RAS CAS W A0-A8 D VOH VOL Q VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAAA AAAA AAAA A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A High-Z AAA AAA AAA AAAA AAAA AAAA AA AA AA AAA AAA AAA Read Write (CAS-controlled) tcR tw(RASL) tw(RASH) tCASH-RASL th(RAS-R) th(CAS-R) tCASL-RASH tRASL-CASH tw(CASL)tRASL-CASLtCASH-RASL tsu(R-CAS) tsu(CA-CAS) tCA-RASH th(RAS-CA )tsu(RA-RAS) th(RAS-RA ) th(CAS-CA) tRAS-CA ta(CA ) ta(RA S) ta(CA S) tCASL-QX tv(CA S) RAS CAS W A0-A8 Q tcW tw(RA SL) tw(RASH) tCASH-RASL tRASL-CASH tCASL-RASH tw(CASL)tRASL-CASLtCASH-RASL tsu(W-CAS) th(W-CAS) th(W-RAS) tw(W) th(RAS-CA) th(CAS-W) tCA-RASH tsu(RA -RA S) th(RAS-RA ) th(RAS-D) th(CAS-D)tsu(D-CAS) tsu(CA -CA S) th(CAS-CA)

December 12, 1997 UD61256 VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AAAA AAAA AAAA A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AAAA AAAA AAAA AAA AAA AAA AAAA AAAA AAAA AAA AAA AAA AAAA AAAA AAAA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AAAA AAAA AAAA A A A AAAA AAAA AAAA AAAA AAAA AAAA A A A AAAA AAAA AAAA AAAA AAAA AAAA tcRW tw(RASL)RW tw(RA SH) tRASL-CASH tRASL-CASLtCASH-RASL tCASL-RASH tCASH-RASL tw(CA SL)RW tCAS-Wtsu(R-CAS) th(W-CAS) tRAS-W th(W-RAS) tw(W) th(RAS-CA) th(CAS-CA)th(RAS-RA)tsu(RA-RAS) tsu(CA-CAS) t(CA-W)RW tsu(D-W) th(W-D) ta(CA S) ta(CA) ta(RAS) tv(CA S) tCASL-QX RAS CAS W A0-A8 D Q tw(RA SL) tw(RASH) tcPG tcPG tCASL-RASH tRASL-CASH tw(CASH) tw(CA SL) tw(CASH) tw(CASL tRA SL-CA SL tw(CASL)tCASH-RASL tsu(R-CAS) tsu(R-CAS) th(CAS-R) th(CAS-R) tsu(R-CAS) th(CAS-R) th(RAS-R) tsu(CA-CAS) tsu(CA-CAS) th(CAS-CA)th(CAS-CA)tsu(RA-RAS) tCA-RASH tsu(CA-CAS) th(CAS-CA) ta(CAS)ta(CAS)ta(CAS)th(RAS-RA) th(RAS-CA) ta(CA) ta(CA ) tCASL-QXtCASL-QXta(CA)tRAS-CA tCASL-QX tv(CAS) tv(CAS) tv(CA S) ta(CASH)ta(CASH)ta(RA S) RAS CAS W Q A0-A8 Read-Write FPM Read AAAA AAAA AAAA

December 12, 1997 UD61256 VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AAA AAAA AAAA AAAA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A AAAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAAA AAAA AAAA AA AA AA High-Z AAAA AAAA AAAA A A A AAAA AAAA AAAA A A A tCASH-RASL AAAA AAAA AAAA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA FPM Write (CAS-controlled) RAS only Refresh tw(RASL) tw(RASH)tRASL-CASH tcPG tcPG tCASL-RASH tRA SL-CA SLtCASH-RASL tw(CASL) tw(CASH) tw(CA SL) tw(CA SH) tw(CASL) tw(W) tw(W) tw(W) th(CAS-W) th(CAS-W) th(CAS-W)tsu(W-CAS) th(W-RAS) tsu(RA-RAS) tsu(CA-CAS) th(CAS-CA) tsu(CA-CAS) tsu(W-CAS) tsu(W-CAS) th(CAS-CA) tsu(CA-CAS) tCA -RA SH th(RAS-RA) th(RAS-CA) th(CAS-CA) th(CASL-D)th(CASL-D)th(CA SL-D) th(RAS-D) tsu(D-CAS) tsu(D-CAS) tsu(D-CAS) RAS CAS W A0-A8 D Q tcR tw(RA SL) tw(RASH) tsu(RA-RAS) th(RAS-RA) RAS CAS W A0-A8 D Q High-Z

Decem ber 12, 1997 UD61256 VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL RAS CAS W A0-A8 Q AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A AAAA AAAA AAAA A A A AAAA AAAA AAAA AAAA AAAA AAAA A A A AAAA AAAA AAAA AA AA AA tcR tcR tw (RA SL) tw (RA SL)tw(R AS H) tw(R AS H) tC AS H-R AS L tR AS L-C ASL tC AS L-R ASH tsu(R -C AS) th(RA S-R ) th(RA S-C A) tsu(R A-R AS ) th(RA S-R A) tCA -RA SH tsu(RA -RA S) th(R AS -RA ) tR AS -C A ta(C A) ta(CA S) tC AS L-Q X ta(R AS) tv(C AS) tRA SL-CA SH tCAS H-R AS L H ID D E N-Refresh w ith address transfer

ZM D products are not designed, intended, or authorized for use as components in systems intend for surgical im plant into the body, or other applications intended to support or sustain life, or for any other application in w hich the failure of the ZM D product could create a situation where personal injury or death m ay occur. Co m ponents used in life-support devices or systems must be expressly authorized by ZM D for such purpose. The inform ation describes the type of com ponent and shall not be considered as assured characteristics. Term s of delivery and rights to change design reserved. Memory Products 1998 256K x 1 DRAM UD61256 Zentrum M ikroelektronik D resden G m bH Grenzstraße 28 • D-01109 D resden • P. O. B. 80 01 34 • D -01101 D resden • Germ any Phone: +49 351 88 22-3 06 • Fax: +49 351 88 22-3 37 • Em ail: sales@ zmd .de Internet W eb Site: http://w w w .zmd.de