UPD431000A-X RENESAS | Alldatasheet
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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. MOS INTEGRATED CIRCUIT μ PD431000A-X 1M-BIT CMOS STATIC RAM 128K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION DATA SHEET Document No. M10430EJBV0DS00 (11th edition) Date Published November 2008 Printed in Japan 1995
Description
The μPD431000A-X is a high speed, low power, and 1,048,576 bits (131,072 words by 8 bits) CMOS static RAM. The μPD431000A-X has two chip enable pins (/CE1, CE2) to ex tend the capacity. And batte ry backup is available. In addition to this, A and B versions are low voltage operations. The μPD431000A-X is packed in 32-pin PLASTIC SOP, 32-pin PLASTIC TSOP (I) (8 × 13.4 mm) and (8 × 20 mm).
Features
- 131,072 words by 8 bits organization
- Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
- Low voltage operation (A version: V CC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)
- Operating ambient temperature: TA = –25 to +85 °C
- Low VCC data retention: 2.0 V (MIN.)
- Output Enable input for easy application
- Two Chip Enable inputs: /CE1, CE2 Part number Access time Operating s upply Operating ambient Supply current ns (MAX.) voltage temperature At operating At standby At data retention V °C mA (MAX.) μA (MAX.) μA (MAX.) Note1 μPD431000A-xxX 70, 85 4.5 to 5.5 –25 to +85 70 50 2.5 μPD431000A-AxxX 70 Note2 , 100 3.0 to 5.5 35 Note3 Note5 μPD431000A-BxxX 70 Note2 , 100, 120, 150 2.7 to 5.5 30 Note4 Note6 Notes 1. TA ≤ 40 °C 2. VCC = 4.5 to 5.5 V 3. 70 mA (VCC > 3.6 V) 4. 70 mA (VCC > 3.3 V) 5. 50 μA (VCC > 3.6 V) 6. 50 μA (VCC > 3.3 V)
Data Sheet M10430EJBV0DS 2 μPD431000A-X
Ordering Information
Part number Package Access time Operat ing supply Operating ambient Remark ns (MAX.) voltage temperature V °C μPD431000AGW-70X 32-pin PLASTIC SOP 70 4.5 to 5.5 –25 to +85 – (13.34 mm (525)) μPD431000AGZ-70X-KJH 32-pin PLASTIC TSOP (I) μPD431000AGZ-85X-KJH (8 × 20) (Normal bent) 85 μPD431000AGZ-A10X-KJH 100 3.0 to 5.5 A version μPD431000AGZ-B10X-KJH 100 2.7 to 5.5 B version μPD431000AGZ-B12X-KJH 120 μPD431000AGZ-B15X-KJH 150 μPD431000AGU-B10X-9JH 32-pin PLASTIC TSOP (I) 100 2.7 to 5.5 B version μPD431000AGU-B12X-9JH (8 × 13.4) (Normal bent) 120 μPD431000AGU-B15X-9JH 150 μPD431000AGW-70X-A 32-pin PLASTIC SOP 70 4.5 to 5.5 – (13.34 mm (525)) μPD431000AGZ-70X-KJH-A 32-pin PLASTIC TSOP (I) μPD431000AGZ-85X-KJH-A (8 × 20) (Normal bent) 85 μPD431000AGZ-A10X-KJH-A 100 3.0 to 5.5 A version μPD431000AGZ-B10X-KJH-A 100 2.7 to 5.5 B version μPD431000AGZ-B12X-KJH-A 120 μPD431000AGZ-B15X-KJH-A 150 μPD431000AGU-B10X-9JH-A 32-pin PLASTIC TSOP (I) 100 2.7 to 5.5 B version μPD431000AGU-B12X-9JH-A (8 × 13.4) (Normal bent) 120 μPD431000AGU-B15X-9JH-A 150 Remark Products with -A at the end of the part number are lead-free products.
Data Sheet M10430EJBV0DS 3 μPD431000A-X Pin Configurations (Marking Side) /xxx indicates active low signal. 32-pin PLASTIC SOP (13.34 mm (525)) [μPD431000AGW-xxX] [μPD431000AGW-xxX-A] NC A16 A14 A12 I/O1 I/O2 I/O3 GND V CC A15 CE2 /WE A13 A11 /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 A0 - A16 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable V CC : Power supply GND : Ground NC : No connection Remark Refer to Package Drawings for the 1-pin index mark
Data Sheet M10430EJBV0DS 4 μPD431000A-X 32-pin PLASTIC TSOP (I) (8×20) (Normal bent) [μPD431000AGZ-xxX-KJH] [μPD431000AGZ-AxxX-KJH] [μPD431000AGZ-BxxX-KJH] [μPD431000AGZ-xxX-KJH-A] [μPD431000AGZ-AxxX-KJH-A] [μPD431000AGZ-BxxX-KJH-A] A11 A13 /WE CE2 A15 VCC NC A16 A14 A12 /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 - A16 : Address inputs /OE : Output Enable I/O1 - I/O8 : Data inputs / outputs VCC : Power supply /CE1, CE2 : Chip Enable 1, 2 GND : Ground /WE : Write Enable NC : No connection Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M10430EJBV0DS 5 μPD431000A-X 32-pin PLASTIC TSOP (I) (8×13.4) (Normal bent) [μPD431000AGU-BxxX-9JH] [μPD431000AGU-BxxX-9JH-A] A11 A13 /WE CE2 A15 VCC NC A16 A14 A12 /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 - A16 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable V CC : Power supply GND : Ground NC : No connection Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M10430EJBV0DS 6 μPD431000A-X Block Diagram Address buffer Address buffer Row decoder Memory cell array 1,048,576 bits Input data controller A16 Sense amplifier / Switching circuit Column decoder /CE1 /WE /OE CE2 Output data controller VCC GND I/O1 I/O8 Truth Table /CE1 CE2 /OE /WE Mode I/O Supply current H × × × Not selected High impedance ISB × L × × L H H H Output disable I CCA L H L H Read D OUT L H × L Write D IN Remark × : VIH or VIL
Data Sheet M10430EJBV0DS 7 μPD431000A-X Electrical Specifications Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Supply voltage VCC –0.5 Note to +7.0 V Input / Output voltage VT –0.5 Note to VCC + 0.5 V Operating ambient temperature TA –25 to +85 °C Storage temperature Tstg –55 to +125 °C Note –3.0 V (MIN.) (Pulse width: 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this speci fication. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition μPD431000A-xxX μPD431000A-AxxX μPD431000A-BxxX Unit Low level input voltage VIL –0.3 Note +0.6 –0.3 Note +0.5 –0.3 Note +0.5 V Operating ambient temperature T A –25 +85 –25 +85 –25 +85 °C Note –3.0 V (MIN.) (Pulse width: 30 ns) Capacitance (T A = 25 °C, f = 1 MHz) Parameter Symbol Test conditions MIN. TYP. MAX. Unit Input capacitance CIN V IN = 0 V 6 pF Input / Output capacitance C I/O V I/O = 0 V 10 pF Remarks 1. VIN : Input voltage V I/O : Input / Output voltage 2. These parameters ar e not 100% tested.
Data Sheet M10430EJBV0DS 8 μPD431000A-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Test condition μPD431000A-xxX μPD431000A-AxxX μPD431000A-BxxX Unit c u r r e n t current /CE1 = V IH or CE2 = VIL or /WE = V IL or /OE = VIH Operating I CCA1 /CE1 = V IL, CE2 = VIH, 40 70 40 70 40 70 mA supply current I I/O = 0 mA VCC ≤ 3.6 V – – 15 35 – – Minimum cycle time V CC ≤ 3.3 V – – 15 30 I CCA2 /CE1 = V IL, CE2 = VIH, 15 15 15 II/O = 0 mA, V CC ≤ 3.6 V – 10 – Cycle time = ∞ V CC ≤ 3.3 V – – 8 I CCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, 10 10 10 Cycle time = 1 μs, II/O = 0 m A , VIL ≤ 0.2 V, V CC ≤ 3.6 V – 8 – VIH ≥ VCC – 0.2 V V CC ≤ 3.3 V – – 7 Standby I SB /CE1 = V IH or CE2 = VIL 3 3 3 mA supply current VCC ≤ 3.6 V – 2 – V CC ≤ 3.3 V – – 2 I SB1 /CE1 ≥ VCC − 0.2 V, 1 50 – 50 – 50 μA CE2 ≥ VCC − 0.2 V V CC ≤ 3.6 V – – 0.5 26 – – I SB2 CE2 ≤ 0.2 V 1 50 – 50 – 50 output voltage I OH = –0.5 mA – 2.4 2.4 output voltage I OL = 1.0 mA – 0.4 0.4 Remarks 1. VIN : Input voltage V I/O : Input / Output voltage 2. These DC characteristics are in common regardless product classification.
Data Sheet M10430EJBV0DS 9 μPD431000A-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions μPD431000A-70X, μPD431000A-85X] Input Waveform (Rise and Fall Time ≤ 5 ns) Test points1.5 V 1.5 V 2.4 V 0.6 V Output Waveform Test points1.5 V 1.5 V Output Load AC characteristics should be measured with the following output load conditions. Figure 1 Figure 2 (tAA, tCO1, tCO2, tOE, tOH) (tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW) +5 V I/O (Output) 1.8 kΩ 5 pF CL 990 Ω +5 V I/O (Output) 1.8 kΩ 100 pF C L 990 Ω Remark C L includes capacitance of the probe and jig, and stray capacitance. [μPD431000A-A10X, μPD431000A-B10X, μPD431000A-B12X, μPD431000A-B15X] Input Waveform (Rise and Fall Time ≤ 5 ns) Test points1.5 V 1.5 V 2.4 V 0.5 V Output Waveform Test points1.5 V 1.5 V Output Load AC characteristics should be measured with the following output load conditions. Part number Output load condition t AA, tCO1, tCO2, tOE, tOH tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW μPD431000A-A10X, μPD431000A-B10X, μPD431000A-B12X 1TTL + 50 pF 1TTL + 5 pF μPD431000A-B15X 1TTL + 100 pF 1TTL + 5 pF
Data Sheet M10430EJBV0DS 10 μPD431000A-X Read Cycle (1/2) Parameter Symbol V CC ≥ 4.5 V VCC ≥ 3.0 V Unit Condition μPD431000A-70X μPD431000A-85X μPD431000A-A10X μPD431000A-AxxX μPD431000A-BxxX Read cycle time tRC 70 85 100 ns Address access time tAA 70 85 100 ns Note /CE1 access time tCO1 70 85 100 ns CE2 access time tCO2 70 85 100 ns /OE to output valid tOE 35 45 50 ns Output hold from address change t OH 10 10 10 ns /CE1 to output in low impedance t LZ1 10 10 10 ns CE2 to output in low impedance t LZ2 10 10 10 ns /OE to output in low impedance t OLZ 5 5 5 ns /CE1 to output in high impedance t HZ1 25 30 35 ns CE2 to output in high impedance t HZ2 25 30 35 ns /OE to output in high impedance t OHZ 25 30 35 ns Note See the output load. Remark These AC characteristics are in common regardless of package types. Read Cycle (2/2) Parameter Symbol VCC ≥ 2.7 V Unit Condition μPD431000A-B10X μPD431000A-B12X μPD431000A-B15X Read cycle time tRC 100 120 150 ns Address access time tAA 100 120 150 ns Note /CE1 access time tCO1 100 120 150 ns CE2 access time tCO2 100 120 150 ns /OE to output valid tOE 50 60 70 ns Output hold from address change t OH 10 10 10 ns /CE1 to output in low impedance t LZ1 10 10 10 ns CE2 to output in low impedance t LZ2 10 10 10 ns /OE to output in low impedance t OLZ 5 5 5 ns /CE1 to output in high impedance t HZ1 35 40 50 ns CE2 to output in high impedance t HZ2 35 40 50 ns /OE to output in high impedance t OHZ 35 40 50 ns Note See the output load. Remark These AC characteristics are in common regardless of package types.
Data Sheet M10430EJBV0DS 11 μPD431000A-X Read Cycle Timing Chart tHZ2 tRC tOH tHZ1 tLZ2 tCO2 tLZ1 tCO1 tAA High impedance Data out CE2 (Input) /CE1 (Input) Address (Input) I/O (Output) tOLZ tOE tOHZ /OE (Input) Remark In read cycle, /WE should be fixed to high level.
Data Sheet M10430EJBV0DS 12 μPD431000A-X Write Cycle (1/2) Parameter Symbol V CC ≥ 4.5 V VCC ≥ 3.0 V Unit Condition μPD431000A-70X μPD431000A-85X μPD431000A-A10X μPD431000A-AxxX μPD431000A-BxxX Write cycle time tWC 70 85 100 ns /CE1 to end of write tCW1 55 70 80 ns CE2 to end of write tCW2 55 70 80 ns Address valid to end of write tAW 55 70 80 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 50 60 60 ns Write recovery time tWR 5 5 0 ns Data valid to end of write tDW 35 35 60 ns Data hold time tDH 0 0 0 ns /WE to output in high impedance t WHZ 25 30 35 ns Note Output active from end of write t OW 5 5 5 ns Note See the output load. Remark These AC characteristics are in common regardless of package types. Write Cycle (2/2) Parameter Symbol VCC ≥ 2.7 Unit Condition μPD431000A-B10X μPD431000A-B12X μPD431000A-B15X Write cycle time tWC 100 120 150 ns /CE1 to end of write tCW1 80 100 120 ns CE2 to end of write tCW2 80 100 120 ns Address valid to end of write tAW 80 100 120 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 60 85 100 ns Write recovery time tWR 0 0 0 ns Data valid to end of write tDW 60 60 80 ns Data hold time tDH 0 0 0 ns /WE to output in high impedance t WHZ 35 40 50 ns Note Output active from end of write t OW 5 5 5 ns Note See the output load. Remark These AC characteristics are in common regardless of package types.
Data Sheet M10430EJBV0DS 13 μPD431000A-X Write Cycle Timing Chart 1 (/WE Controlled) tWC tCW1 tWHZ tDW tDH tOW Indefinite data out High impe- dance High impe- dance Data in Indefinite data out Address (Input) /CE1 (Input) I/O (Input / Output) CE2 (Input) tCW2 tAW tWPtAS tWR /WE (Input) Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, t he I/O pins are always high impedance. When /WE is at high level, read operation is executed. Ther efore /OE should be at high level to make the I/O pins high impedance.
Data Sheet M10430EJBV0DS 14 μPD431000A-X Write Cycle Timing Chart 2 (/CE1 Controlled) tWC tAS tCW1 tDW tDH Data in High impedance Address (Input) /CE1 (Input) I/O (Input) High impedance CE2 (Input) tCW2 tAW tWP tWR /WE (Input) Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. Write Cycle Timing Chart 3 (CE2 Controlled) tWC tAS tCW2 tDW tDH Data in High impedance Address (Input) CE2 (Input) I/O (Input) High impedance /CE1 (Input) tCW1 tAW tWP tWR /WE (Input) Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
Data Sheet M10430EJBV0DS 15 μPD431000A-X Low VCC Data Retention Characteristics (TA = –25 to +85 °C) Parameter Symbol Test Condition μPD431000A-xxX Unit μPD431000A-AxxX μPD431000A-BxxX MIN. TYP. MAX. Data retention supply voltage V CCDR1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V 2.0 5.5 V V CCDR2 CE2 ≤ 0.2 V 2.0 5.5 Data retention supply current I CCDR1 V CC = 3.0 V, /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V 0.5 20 Note μA I CCDR2 V CC = 3.0 V, CE2 ≤ 0.2 V 0.5 20 Note Chip deselection tCDR 0 ns to data retention mode Operation recovery time t R 5 ms Note 2.5 μA (TA ≤ 40 °C)
Data Sheet M10430EJBV0DS 16 μPD431000A-X Data Retention Timing Chart (1) /CE1 Controlled VIH (MIN.) VCCDR (MIN.) VIL (MAX.) /CE1 /CE1 ≥ VCC – 0.2 V GND 4.5 V Note tCDR Data retention mode tR VCC Note A version : 3.0 V, B version : 2.7 V Remark On the data retention mode by controlling /CE1, the input level of CE2 must be CE2 ≥ V CC − 0.2 V or CE2 ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. (2) CE2 Controlled VIH (MIN.) VCCDR (MIN.) VIL (MAX.) VCC CE2 CE2 ≤ 0.2 V GND 4.5 V Note tCDR Data retention mode tR Note A version : 3.0 V, B version : 2.7 V Remark On the data retention mode by controlling CE2, the other pi ns (/CE1, Address, I/O, /WE, /OE) can be in high impedance state.
Data Sheet M10430EJBV0DS 17 μPD431000A-X Package Drawings 32 17 11 6 S 32-PIN PLASTIC SOP (13.34 mm (525)) NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS C 0.78 MAX.B 20.61 MAX.A 1.27 (T.P.) E 0.15± 0.05 F 2.95 MAX. G 2.7 H 14.1± 0.3 I 11.3 J 1.4± 0.2 D 0.40 +0.10 −0.05 M 0.12 N 0.10 L 0.8± 0.2 K 0.20 +0.10 −0.05 P3 °+7° −3° P32GW-50-525A-1 K L G P DM B J detail of lead end S N A H I M F E C
Data Sheet M10430EJBV0DS 18 μPD431000A-X NOTES 32-PIN PLASTIC TSOP(I) (8x20) ITEM MILLIMETERS A B C E I 8.0± 0.1 0.5 (T.P.) 0.1± 0.05 0.45 MAX. K 1.2 MAX. 18.4± 0.1 0.145± 0.05 F 0.10M D 0.22± 0.05 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) R L 0.97± 0.08G L 0.5 0.10N P 20.0± 0.2 Q3 °+5° −3° 0.25R S32GZ-50-KJH1-2 S 0.60± 0.15 J 0.8± 0.2 G F E S Q detail of lead end S N S C D MM B A P K I J
Data Sheet M10430EJBV0DS 19 μPD431000A-X 32-PIN PLASTIC TSOP(I) (8x13.4) NOTES 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS P32GU-50-9JH-2 B 0.45 MAX. C 0.5 (T.P.) detail of lead end A 8.0± 0.1 H 12.4± 0.2 B T D 0.22± 0.05 G 1.0± 0.05 I 11.8± 0.1 J 0.8± 0.2 K L 0.5 M 0.08 N 0.08 Q 0.1± 0.05 P 13.4± 0.2 S 1.2 MAX. R3 ° T 0.25 U 0.6± 0.15 +5° −3° 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) M U L R Q S DM C G J 0.145 +0.025 −0.015 S S NK H P I A
Data Sheet M10430EJBV0DS 20 μPD431000A-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the μPD431000A-X. Types of Surface Mount Device μPD431000AGW-xxX : 32-pin PLASTIC SOP (13.34 mm (525)) μPD431000AGZ-xxX-KJH : 32-pin PLASTIC TSOP (I) (8 ×20) (Normal bent) μPD431000AGZ-AxxX-KJH : 32-pin PLASTIC TSOP (I) (8 ×20) (Normal bent) μPD431000AGZ-BxxX-KJH : 32-pin PLASTIC TSOP (I) (8 ×20) (Normal bent) μPD431000AGU-BxxX-9JH : 32-pin PLASTIC TSOP (I) (8 ×13.4) (Normal bent) μPD431000AGW-xxX-A : 32-pin PLASTIC SOP (13.34 mm (525)) μPD431000AGZ-xxX-KJH-A : 32-pin PLASTIC TSOP (I) (8 ×20) (Normal bent) μPD431000AGZ-AxxX-KJH-A : 32-pin PLASTIC TSOP (I) (8×20) (Normal bent) μPD431000AGZ-BxxX-KJH-A : 32-pin PLASTIC TSOP (I) (8×20) (Normal bent) μPD431000AGU-BxxX-9JH-A : 32-pin PLASTIC TSOP (I) (8×13.4) (Normal bent)
Data Sheet M10430EJBV0DS 21 μPD431000A-X
Revision History
Edition/ Page Type of Description Date This Previous revision edition edition 11th edition/ through through Modification Ordering Information revised. Nov. 2008
Data Sheet M10430EJBV0DS 22 μPD431000A-X [MEMO]
Data Sheet M10430EJBV0DS 23 μPD431000A-X VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V IL (MAX) and V IH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V IL (MAX) and VIH (MIN). HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. NOTES FOR CMOS DEVICES
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