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• PDF pages: 1817

Technical content

Datasheet sections

• 1.1 General
• 1.2 Features
• 1.3 Application Fields
• 1.4 Ordering Information
• 1.5 Pin Configuration (Top View)
• 1.6 Function Block Configuration
• 1.6.1 Internal block diagram
• 1.6.2 Internal units
• 2.1 List of Pin Functions
• 2.2 Pin States
• 2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins
• 2.4 Cautions
• 3.1 Features
• 3.2 CPU Register Set
• 3.2.1 Program register set
• 3.2.2 System register set
• 3.3 Operation Modes
• 3.3.1 Specifying operation mode
• 3.4 Address Space
• 3.4.1 CPU address space
• 3.4.3 Memory map
• 3.4.4 Areas
• 3.4.5 Recommended use of address space
• 3.4.6 Peripheral I/O registers
• 3.4.7 Programmable peripheral I/O registers
• 3.4.8 Special registers
• 3.4.9 Cautions
• 4.1 Features
• 4.2 Basic Port Configuration
• 4.3 Port Configuration
• 4.3.1 Port
• 4.3.2 Port
• 4.3.3 Port
• 4.3.4 Port

User’s Manual All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various m eans, including the Renesas Electronics Corp. website (http://www.renesas.com). V850ES/JH3-E, V850ES/JJ3-E User’s Manual: Hardware Rev.3.00 Sep, 2011 RENESAS MCU V850ES/Jx3-E Microcontrollers www.renesas.com V850ES/JH3-E V850ES/JH3-H μPD70F3778 μPD70F3784 μPD70F3779 μPD70F3785 μPD70F3780 μPD70F3786 μPD70F3781 μPD70F3782 μPD70F3783

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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V IL (MAX) and V IH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V IL (MAX) and VIH (MIN). HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. NOTES FOR CMOS DEVICES

Readers This manual is intended for users who wish to understand the functions of the V850ES/JH3-E and V850ES/JJ3-E and des ign application systems using the V850ES/JH3-E and V850ES/JJ3-E. Purpose This manual is intended to give users an understanding of the hardwar e functions of the V850ES/JH3-E and V850ES/JJ3-E shown in the Organization below. Organization The manual of these products is divided into two volumes: Hardware (this volume) and Architecture (V850ES Architecture User’s Manual). Hardware Architecture

• Pin functions • Data types
• CPU function • Register set
• On-chip peripheral functions • Instruction format and instruction set
• Flash memory programming • Interrupts and exceptions
• Electrical specifications • Pipeline operation How to Read This Manual It is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. To understand the overall functions of the V850ES/JH3-E and V850ES/JJ3-E → Read this manual according to the CONTENTS. Register format → The name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. To understand the details of an instruction function → Refer to the V850ES Architecture User’s Manual available separately. To know the electrical specifications of the V850ES/JH3-E and V850ES/JJ3-E → Refer to the CHAPTER 35 ELECTRICAL SPECIFICATIONS. The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note with caution that if “xxx.yyy” is described as is in a program, however, the compiler/assembler cannot recognize it correctly. The mark <R> shows major revised points. The revised points can be easily searched by copying an “<R>” in the PDF file and specifying it in the “Find what: ” field.

Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (ove rscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numeric representation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Prefix indicating power of 2 (address space, memory capacity): K (kilo): 2 = 1,024 M (mega): 2 = 1,024 G (giga): 2 = 1,024

Related Documents The related documents indicated in this pub lication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JH3-E and V850ES/JJ3-E Document Name Document No. V850ES Architecture User’s Manual U15943E V850ES/JH3-E, V850ES/JJ3-E Hardware User’s Manual This manual Documents related to development tools Document Name Document No. QB-V850ESJX3E In-Circuit Emulator U19170E QB-V850MINI On-Chip Debug Emulator U17638E QB-MINI2 On-Chip Debug Emulator with Programming Function U18371E Operation U18512E C Language U18513E Assembly Language U18514E CA850 Ver. 3.20 C Compiler Package Link Directives U18515E PM+ Ver. 6.30 Project Manager U18416E ID850QB Ver. 3.40 Integrated Debugger Operation U18604E SM850 Ver. 2.50 System Simulator Operation U16218E SM850 Ver. 2.00 or Later System Simulator External Part User Open Interface Specification U14873E Operation U18601E SM+ System Simulator User Open Interface U18212E Basics U13430E Installation U17419E Technical U13431E RX850 Ver. 3.20 Real-Time OS Task Debugger U17420E Basics U18165E Installation U17421E RX850 Pro Ver. 3.21 Real-Time OS Task Debugger U17422E AZ850 Ver. 3.30 System Performance Analyzer U17423E PG-FP5 Flash Memory Programmer U18865E

Caution: This product uses SuperFlash ® technology licensed from Silicon Storage Technology, Inc. EEPROM is a trademark of Renesas Electronics Corporation. IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in the United States of America. Windows and Windows NT are either regist ered trademarks or trademarks of Mi crosoft Corporation in the United States and/or other countries. SuperFlash is a registered trademark of Silicon Stor age Technology, Inc. in sever al countries, including the United States and Japan. PC/AT is a trademark of International Business Machines Corporation. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. TRON is an abbreviation of The Real-Time Operating system Nucleus. ITRON is an abbreviation of Industrial TRON.

17.3.2 Mode switching between UARTC1, CSIF1 and I

17.3.3 Mode switching between UARTC2, I

17.3.4 Mode switching between UARTC3, CSIF0, and I

17.3.6 Mode switching between UARTC5, CSIE1 and I

19.3.1 Switching between CSIF0, UARTC3, and I

19.3.2 Mode switching between CSIF1, UARTC1, and I

20.3 Mode Switching of I

20.3.1 Mode switching between I

20.3.2 Mode switching between I

20.3.3 Mode switching between I

20.3.4 Mode switching between I

20.5 I 20.6 I 20.7 I

R01UH0290EJ0300 Rev.3.00 Page 24 of 1817 Sep 19, 2011 R01UH0290EJ0300 Rev.3.00 Sep 19, 2011 V850ES/JH3-E, V850ES/JJ3-E RENESAS MCU CHAPTER 1 INTRODUCTION The V850ES/JH3-E and V850ES/JJ3-E are products in the low- power series of Renesas Electronics’ V850 single-chip microcontrollers designed for real-time control applications.

1.1 General

The V850ES/JH3-E and V850ES/JJ3-E are 32-bit single-chi p microcontrollers that use the V850ES CPU core and incorporate peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, a D/A converter, a DMA controller, CAN, a USB function controller, and an Ethernet controller. In addition to high real-time response characteristics and 1-clock-pitch bas ic instructions, the V850ES/JH3-E and V850ES/JJ3-E feature multiply instructions realized by a hardware multiplier, saturated operation instructions, and bit manipulation instructions. Table 1-1 lists the products of the V850ES/JH3-E, and Table 1-2 lists the products of the V850ES/JJ3-E.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 1 INTRODUCTION R01UH0290EJ0300 Rev.3.00 Page 25 of 1817 Sep 19, 2011 Table 1-1. V850ES/JH3-E Product List Generic Name V850ES/JH3-E Part Number μPD70F3778 μPD70F3779 μPD70F3780 μPD70F3781 μPD70F3782 μPD70F3783 Flash memory 256 KB 384 KB 512 KB 384 KB 512 KB 512 KB Internal RAM 60 KB 60 KB 60 KB 60 KB 60 KB 60 KB Internal memory Data-only RAM 16 KB 16 KB 16 KB 64 KB 64 KB 64 KB Logical space 64 MB Memory space External memory area 5 MB External bus interface Address bus: 22, Address/data bus: 16 Separate bus/Multiplexed bus General-purpose register 32 bits × 32 registers Main clock PLL mode: f X = 3 to 6.25 MHz, fXX = 24 to 50 MHz (multiplied by 8) Clock through mode: fX = 3 to 6.25 MHz (Internal: fXX = 3 to 6.25 MHz) Subclock f XT = 32.768 kHz Internal oscillator f R = 220 kHz (TYP .) Clock Minimum instruction execution time 20 ns (main clock (f XX) = 50 MHz) I/O port I/O: 84 (5 V tolerant: 38) 16-bit TAA 6 channels 16-bit TAB 2 channels 16-bit TMM 4 channels 16-bit TMT 1 channel Motor control 1 channel (functions with combination of TAA and TAB; includes Hi-Z output control function) Watch timer 1 channel (RTC) Timer WDT 1 channel Real-time output function 6 bits × 1 channel 10-bit A/D converter 10 channels CSIF/UARTC 1 channel CSIF/UARTC/I C 2 channels CSIE/UARTC 1 channel CSIE Note 1 /UARTC/I C 1 channel CSIF/UARTB 2 channels (including one ch annel that is assigned to two pins) CSIE Note 1 1 channel UARTC/I C 1 channel − UARTC/I C/CAN − 1 channel USB controller USB function (full speed):1 channel Serial interface Ethernet controller 1 channel DMA controller 4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory) External Notes 2, 3 22 (22) 22 (22) 22 (22) 22 (22) 22 (22) 22 (22) Interrupt source Internal 78 78 78 78 78 82 Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode Reset source RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI) On-chip debugging MINICUBE ®, MINICUBE2 supported Operating power supply voltage 2.85 to 3.6 V Operating ambient temperature −40 to +85°C Package 128-pin plastic LQFP (fine pitch) (14 × 20 mm) Notes 1. CSIE of the same channel is assigned to two pins. 2. The figures in parentheses indicate the number of external interrupts that can release STOP mode. 3. Including NMI.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 1 INTRODUCTION R01UH0290EJ0300 Rev.3.00 Page 26 of 1817 Sep 19, 2011 Table 1-2. V850ES/JJ3-E Product List Generic Name V850ES/JJ3-E Part Number μPD70F3784 μPD70F3785 μPD70F3786 Flash memory 512 KB 512 KB 512 KB Internal RAM 60 KB 60 KB 60 KB Internal memory Data-only RAM 16 KB 64 KB 64 KB Logical space 64 MB Memory space External memory area 13 MB External bus interface Address bus: 24, Address/data bus: 16 Separate bus/Multiplexed bus General-purpose register 32 bits × 32 registers Main clock PLL mode: f X = 3 to 6.25 MHz, fXX = 24 to 50 MHz (multiplied by 8) Clock through mode: fX = 3 to 6.25 MHz (Internal: fXX = 3 to 6.25 MHz) Subclock f XT = 32.768 kHz Internal oscillator f R = 220 kHz (TYP .) Clock Minimum instruction execution time 20 ns (main clock (fXX) = 50 MHz) I/O port I/O: 100 (5 V tolerant: 47) 16-bit TAA 6 channels 16-bit TAB 2 channels 16-bit TMM 4 channels 16-bit TMT 1 channel Motor control 1 channel (functions with combination of TAA and TAB; includes Hi-Z output control function) Watch timer 1 channel(RTC) Timer WDT 1 channel Real-time output function 8 bits × 1 channel 10-bit A/D converter 12 channels CSIF/UARTC 3 channels CSIF/UARTC/I C 2 channels CSIE/UARTC 1 channel CSIE Note 1 /UARTC/I C 1 channel CSIF/UARTB 2 channels (including one ch annel that is assigned to two pins) CSIE Note 1 1 channel I C 1 channel UARTC/I C 1 channel − UARTC/I C/CAN − 1 channel USB controller USB function (full speed):1 channel Serial interface Ethernet controller 1 channel DMA controller 4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory) External Notes 2, 3 27 (27) 27 (27) 27 (27) Interrupt source Internal 84 84 88 Power save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode Reset source RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI) On-chip debugging MINICUBE, MINICUBE2 supported Operating power supply voltage 2.85 to 3.6 V Operating ambient temperature −40 to +85°C Package 144-pin plastic LQFP (fine pitch) (20 × 20 mm) Notes 1. CSIE of the same channel is assigned to two pins. 2. The figures in parentheses indicate the number of external interrupts that can release STOP mode. 3. Including NMI.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 1 INTRODUCTION R01UH0290EJ0300 Rev.3.00 Page 27 of 1817 Sep 19, 2011

1.2 Features

{ Minimum instruction execution time: 20.0 ns (main clock (fXX) = 50 MHz: VDD = 2.85 to 3.6 V) 30.5 μs (subclock (fXT) = 32.768 kHz) { General-purpose registers: 32 bits × 32 registers { CPU features: Signed multiplication (16 × 16 → 32): 1 or 2 clocks Signed multiplication (32 × 32 → 64): 1 to 5 clocks Saturated operations (overflow and underflow detection functions included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format { Memory space: 64 MB of linear address space (for programs and data) External expansion: Up to 14 MB (including 1 MB used as internal ROM/RAM space)

• Internal memory: RAM: 76/124 KB (see Table 1-1 and Table 1-2) Flash memory: 256/384/512 KB (see Table 1-1 and Table 1-2)
• External bus interface: Separate bus/multiplexed bus selectable 8/16-bit data bus sizing function Wait function
• Programmable wait function
• External wait function Idle state function Bus hold function { Interrupts and exceptions: Internal External Non-maskable Maskable Total Non-maskable Maskable Total μPD70F3778 1 78 79 1 21 22 μPD70F3779 1 78 79 1 21 22 μPD70F3780 1 78 79 1 21 22 μPD70F3781 1 78 79 1 21 22 μPD70F3782 1 78 79 1 21 22 V850ES/JH3-E μPD70F3783 1 82 83 1 21 22 μPD70F3784 1 83 84 1 26 27 μPD70F3785 1 83 84 1 26 27 V850ES/JJ3-E μPD70F3786 1 87 88 1 26 27 Software exceptions: 32 sources Exception trap: 2 sources { I/O lines: I/O ports: 84 (V850ES/JH3-E) 100 (V850ES/JJ3-E) { Timer function: 16-bit interv al timer M (TMM): 4 channels 16-bit timer/event counter AA (TAA): 6 channels 16-bit timer/event counter AB (TAB): 2 channels 16-bit timer/event counter T (TMT): 1 channel Motor control function (timers used: TAB1, TAA4) 6-phase PWM function with dead-time function of 16-bit accuracy High-impedance output control function A/D trigger generation by timer-tuned operation function Arbitrary cycle setting function Arbitrary dead-time setting function Real-time counter (RTC): 1 channel

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 1 INTRODUCTION R01UH0290EJ0300 Rev.3.00 Page 28 of 1817 Sep 19, 2011 Watchdog timer: 1 channel { Real-time output port: 6 bits × 1 channel { Serial interface: Asynchronous serial interface B with FIFO (UARTB) Asynchronous serial interface C (UARTC) 3-wire variable-length serial interface E with FIFO (CSIE) 3-wire variable-length serial interface F (CSIF) I C bus interface (I CAN interface USB function controller Ethernet controller Remark For the number of channels incorporated, see Tables 1-1 and 1-2. { A/D converter (10-bit resolution): 10ch (V850ES/JH3-E) 12ch (V850ES/JJ3-E) { DMA controller: 4 channels { DCU (debug control unit): JTAG interface { Clock generator: Main clock or subclock operation: 7-level CPU clock (f XX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT) Clock-through mode/PLL mode selectable { Internal oscillation clock: 220 kHz (TYP .) { Power-save functions: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode { Package: 128-pin plastic LQFP (fine pitch) (14 × 20) (V850ES/JH3-E) 144-pin plastic LQFP (fine pitch) (20 × 20) (V850ES/JJ3-E)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 1 INTRODUCTION R01UH0290EJ0300 Rev.3.00 Page 29 of 1817 Sep 19, 2011

1.3 Application Fields

Equipment requiring an Ethernet cont roller, industrial equipment, FA equipment, network control including building management system.

1.4 Ordering Information

• V850ES/JH3-E Part Number Package Internal Flash Memory μPD70F3778GF-GAT-AX μPD70F3779GF-GAT-AX μPD70F3780GF-GAT-AX μPD70F3781GF-GAT-AX μPD70F3782GF-GAT-AX μPD70F3783GF-GAT-AX 128-pin plastic LQFP (fine pitch) (14 × 20) 128-pin plastic LQFP (fine pitch) (14 × 20) 128-pin plastic LQFP (fine pitch) (14 × 20) 128-pin plastic LQFP (fine pitch) (14 × 20) 128-pin plastic LQFP (fine pitch) (14 × 20) 128-pin plastic LQFP (fine pitch) (14 × 20) 256 KB 384 KB 512 KB 384 KB 512 KB 512 KB
• V850ES/JJ3-E Part Number Package Internal Flash Memory μPD70F3784GJ-GAE-AX μPD70F3785GJ-GAE-AX μPD70F3786GJ-GAE-AX 144-pin plastic LQFP (fine pitch) (20 × 20) 144-pin plastic LQFP (fine pitch) (20 × 20) 144-pin plastic LQFP (fine pitch) (20 × 20) 512 KB 512 KB 512 KB Remark The V850ES/JH3-E and V850ES/JJ3-E are lead-free products.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 1 INTRODUCTION R01UH0290EJ0300 Rev.3.00 Page 30 of 1817 Sep 19, 2011

1.5 Pin Configuration (Top View)

• V850ES/JH3-E 128-pin plastic LQFP (fine pitch) (14 × 20) μPD70F3778GF-GAT -AX μPD70F3779GF-GAT -AX μPD70F3780GF-GAT -AX μPD70F3781GF-GAT -AX μPD70F3782GF-GAT -AX μPD70F3783GF-GAT -AX P21/TIAB00/TOAB00/RTCDIV/RTCCL P22/TIAB01/TOAB01/RTC1HZ/INTP02 P1TXD0 P1TXD1 P1TXD2 P1TXD3 P1TXER P1TXEN P1TXCLK P1RXD0 P1RXD1 P1RXD2 P1RXD3 P1RXDV P1RXER P1RXCLK P1CRS P1COL P1MDC P1MDIO P23/SIF1/TXDC1/SDA00/INTP03 V SS EVDD P24/SOF1/RXDC1/SCL00/INTP04 P25/SCKF1/TIAA30/TOAA30/UDMARQ0 P26/TIAA31/TOAA31/INTP05/UDMAAK0 AVREF0 AVSS P40/SIF0/TXDC3/SDA01/RTP00 P41/SOF0/RXDC3/SCL01/RTP01 P42/SCKF0/TIAA40/TOAA40/RTP02 P43/SIE0/TXDC4/RTP03/HLDAK P44/SOE0/RXDC4/RTP04/HLDRQ P45/SCKE0/TIAA41/TOAA41/RTP05 UDMF UDPF UVDD FLMD0Note 1 VDD REGCNote 2 VSS RESET XT1 XT2 P02/NMI P03/INTP00/ADTRG/EXCLK P50/INTP07/DDI P51/INTP08/DDO P52/INTP09/DCK P53/INTP10/DMS P54/INTP11/DRST P30/TXDC0/SIF2/TIAA00/TOAA00 P31/RXDC0/SOF2/TIAA01/TOAA01 P32/ASCKC0/SCKF2/TIAA10/TOAA10 P33/SIF4/TXDB0/TIAA11/TOAA11 P34/SOF4/RXDB0/TIAA20/TOAA20 P35/SCKF4/TIAA21/TOAA21/TOAA1OFF/INTP06 V SS EVDD P36/TXDC2/SDA02(/CTXD0Note 3) P37/RXDC2/SCL02(/CRXD0Note 3) P20/TIAB02/TOAB02/INTP01 P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 P78/ANI8 P79/ANI9 EV DD VSS PCS2/CS2 PCS0/CS0 PCT6/ASTB PCT4/RD PCT1/WR1 PCT0/WR0 PDH5/A21/SCKF4 PDH4/A20/SOF4/RXDB0 PDH3/A19/SIF4/TXDB0 PDH2/A18/SCKE1 PDH1/A17/SOE1 PDH0/A16/SIE1 PDL15/AD15 PDL14/AD14 102 101 100 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103EVDD VSS PDL13/AD13 PDL12/AD12 PDL11/AD11 PDL10/AD10 PDL9/AD9 PDL8/AD8 PDL7/AD7 PDL6/AD6 PDL5/AD5/FLMD1 PDL4/AD4 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 PCM0/WAIT EV DD VSS REGCNote 2 VDD PCM1/CLKOUT P915/SCKF3/TIAA51/TOAA51/A15 P914/SOF3/RXDB1/INTP20/A14 P913/SIF3/TXDB1/INTP19/A13 P912/TOAB1OFF/INTP18/A12 P911/SCKE1/TIAA50/TOAA50/A11 P910/SOE1/RXDC5/SCL03/A10 P99/SIE1/TXDC5/SDA03/A9 P98/TENC01/INTP17/A8 P97/TENC00/TIT01/KR7/TOT01/A7 P96/TECR0/TIT00/KR6/TOT00/A6 P95/TOAB1B3/EVTB1/KR5/INTP16/A5 P94/TOAB1T3/TOAB13/TIAB13/KR4/INTP15/A4 P93/TOAB1B2/TRGAB1/KR3/INTP14/A3 P92/TOAB1T2/TOAB12/TIAB12/KR2/INTP13/A2 P91/TOAB1B1/TIAB10/KR1/TOAB10/A1 P90/TOAB1T1/TOAB11/TIAB11/KR0/INTP12/A0 Notes 1. Connect this pin to VSS in the normal mode. 2. Connect the REGC pin to VSS via a 4.7 μF (recommend value) capacitor. 3. μPD70F3783 only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 1 INTRODUCTION R01UH0290EJ0300 Rev.3.00 Page 31 of 1817 Sep 19, 2011

• V850ES/JJ3-E 144-pin plastic LQFP (fine pitch) (20 × 20) μPD70F3784GJ-GAE-AX μPD70F3785GJ-GAE-AX μPD70F3786GJ-GAE-AX EVDD VSS PDL13/AD13 PDL12/AD12 PDL11/AD11 PDL10/AD10 PDL9/AD9 PDL8/AD8 PDL7/AD7 PDL6/AD6 PDL5/AD5/FLMD1 PDL4/AD4 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 PCM0/WAIT EV DD VSS REGCNote 2 VDD PCM1/CLKOUT P915/SCKF3/TIAA51/TOAA51/A15 P914/SOF3/RXDB1/INTP20/A14 P913/SIF3/TXDB1/INTP19/A13 P912/TOAB1OFF/INTP18/A12 P911/SCKE1/TIAA50/TOAA50/A11 P910/SOE1/RXDC5/SCL03/A10 P99/SIE1/TXDC5/SDA03/A9 P98/TENC01/INTP17/A8 P97/TENC00/TIT01/KR7/TOT01/A7 P96/TECR0/TIT00/KR6/TOT00/A6 P95/TOAB1B3/EVTB1/KR5/INTP16/A5 P94/TOAB1T3/TOAB13/TIAB13/KR4/INTP15/A4 P93/TOAB1B2/TRGAB1/KR3/INTP14/A3 P92/TOAB1T2/TOAB12/TIAB12/KR2/INTP13/A2 AV REF0 AVSS P40/SIF0/TXDC3/SDA01/RTP00 P41/SOF0/RXDC3/SCL01RTP01 P42/SCKF0/TIAA40/TOAA40/RTP02 P43/SIE0/TXDC4/RTP03 P44/SOE0/RXDC4/RTP04 P45/SCKE0/TIAA41/TOAA41/RTP05 UDMF UDPF UVDD FLMD0Note 1 VDD REGCNote 2 VSS RESET XT1 XT2 P02/NMI P03/INTP00/ADTRG/EXCLK P50/INTP07/DDI P51/INTP08/DDO P52/INTP09/DCK P53/INTP10/DMS P54/INTP11/DRST P30/TXDC0/SIF2/TIAA00/TOAA00 P31/RXDC0/SOF2/TIAA01/TOAA01 P32/ASCKC0/SCKF2/TIAA10/TOAA10 P33/SIF4/TXDB0/TIAA11/TOAA11 P34/SOF4/RXDB0/TIAA20/TOAA20 P35/SCKF4/TIAA21/TOAA21/TOAA1OFF/INTP06 V SS EVDD P36/TXDC2/SDA02(/CTXD0Note 3) P37/RXDC2/SCL02(/CTXD0Note 3) P20/TIAB02/TOAB02/INTP01 P21/TIAB00/TOAB00/RTCDIV/RTCCL P22/TIAB01/TOAB01/RTC1HZ/INTP02 P27/TIAB03/TOAB03/INTP21 P55/SDA04/INTP23/UDMARQ1 P56/SCL04/INTP24/UDMAAK1 P1TXD0 P1TXD1 P1TXD2 P1TXD3 P1TXER P1TXEN P1TXCLK P1RXD0 P1RXD1 P1RXD2 P1RXD3 P1RXDV P1RXER P1RXCLK P1CRS P1COL P1MDC P1MDIO P57/SIF6/TXDC7 P58/SOF6/RXDC7 P59/SCKF6/INTP25 P23/SIF1/TXDC1/SDA00/INTP03 V SS EVDD P24/SOF1/RXDC1/SCL00/INTP04 P25/SCKF1/TIAA30/TOAA30/UDMARQ0 P26/TIAA31/TOAA31/INTP05/UDMAAK0 P90/TOAB1T1/TOAB11/TIAB11/KR0/INTP12/A0 P91/TOAB1B1/TIAB10/KR1/TOAB10/A1 P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 P78/ANI8 P79/ANI9 P710/ANI10 P711/ANI11 EV DD VSS P48/SCKF5/INTP22 P47/SOF5/RXDC6/RTP07 P46/SIF5/TXDC6/RTP06 PCS3/CS3 PCS2/CS2 PCS0/CS0 PCT6/ASTB PCT4/RD PCT1/WR1 PCT0/WR0 PCM3/HLDRQ PCM2/HLDAK PDH7/A23 PDH6/A22 PDH5/A21/SCKF4 PDH4/A20/SOF4/RXDB0 PDH3/A19/SIF4/TXDB0 PDH2/A18/SCKE1 PDH1/A17/SOE1 PDH0/A16/SIE1 PDL15/AD15 PDL14/AD14 108 107 106 105 104 103 102 101 100 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 Notes 1. Connect this pin to VSS in the normal mode. 2. Connect the REGC pin to VSS via a 4.7 μF (recommend value) capacitor. 3. μPD70F3786 only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 1 INTRODUCTION R01UH0290EJ0300 Rev.3.00 Page 32 of 1817 Sep 19, 2011 Pin names A0 to A23: AD0 to AD15: ADTRG: ANI0 to ANI11: ASCKC0: ASTB: AV REF0: AVSS: CLKOUT: CRXD0: CS0, CS2, CS3: CTXD0: DCK: DDI: DDO: DMS: DRST: EV DD: EVTAB1: EXCLK: FLMD0, FLMD1: HLDAK: HLDRQ: INTP00 to INTP25: KR0 to KR7: NMI: P02, P03: P1COL, P1CRS, P1MDC, P1MDIO, P1RXCLK, P1RXD0 to P1RXD3, P1RXDV, P1RXER, P1TXCLK, P1TXD0 to P1TXD3, P1TXEN, P1TXER: P20 to P27: P30 to P37: P40 to P48: P50 to P59: P70 to P711: P90 to P915: PCM0 to PCM3: PCS0, PCS2 PCS03: PCT0, PCT1, PCT4, PCT6: PDH0 to PDH7: PDL0 to PDL15: RD: REGC: RESET: RTC1HZ, RTCCL, RTCDIV: Address bus Address/data bus A/D trigger input Analog input Asynchronous serial clock Address strobe Analog reference voltage Grand for analog pin Clock output CAN receive data Chip select CAN transmit data Debug clock Debug data input Debug data output Debug mode select Debug reset Power supply for external pin Timer event count input External clock input Flash programming mode Hold acknowledge Hold request External interrupt input Key return Non-maskable interrupt request Port 0 Ethernet PHY interface Port 2 Port 3 Port 4 Port 5 Port 7 Port 9 Port CM Port CS Port CT Port DH Port DL Read strobe Regulator control Reset Real-time counter clock output RTP00 to RTP07: RXDB0, RXDB1: RXDC0 to RXDC7: SCKE0, SCKE1: SCKF0 to SCKF6 SCL00 to SCL04: SDA00 to SDA04: SIE0, SIE1: SIF0 to SIF6 SOE0, SOE1: SOF0 to SOF6 TECR0: TENC00, TENC01: TIAA00, TIAA01, TIAA10, TIAA11, TIAA20, TIAA21, TIAA30, TIAA31, TIAA40, TIAA41, TIAA50, TIAA51, TIAB00 to TIAB03, TIAB10 to TIAB13, TIT00, TIT01: TOAA00, TOAA01, TOAA10, TOAA11, TOAA20, TOAA21, TOAA30, TOAA31, TOAA40, TOAA41, TOAA50, TOAA51, TOAB00 to TOAB03, TOAB10 to TOAB13, TOAB1B1 to TOAB1B3, TOAB1T1 to TOAB1T3, TOT00, TOT01: TOAA1OFF, TOAB1OFF: TRGAB1: TXDB0, TXDB1 TXDC0 to TXDC5: UDMAAK0, UDMAAK1: UDMARQ0, UDMARQ1: UDMF: UDPF: UV DD: VDD: VSS: WAIT: WR0: WR1: X1, X2 XT1, XT2: Real-time output port Receive data Serial clock Serial clock Serial data Serial input Serial output Timer encoder clear input Timer encoder input Timer input Timer output Timer output off Timer trigger input Serial output DMA acknowledge for external USB DMA request for external USB USB data I/O (−) function USB data I/O (+) function Power supply for external USB Power supply Ground External wait input Lower byte write strobe Upper byte write strobe Crystal for main clock Crystal for subclock

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 1 INTRODUCTION R01UH0290EJ0300 Rev.3.00 Page 33 of 1817 Sep 19, 2011

1.6 Function Block Configuration

1.6.1 Internal block diagram

• V850ES/JH3-E NMI INTP00 to INTP20 RTP00 to RTP05 KR0 to KR7 RTO WDT DCU RTC ROM RAM PC ALU CPU HLDRQ HLDAK ASTB RD WAIT WR0, WR1 CS0, CS2 A0 to A21 AD0 to AD15 Port Timer/counter function Serial interface function PDL0 to PDL15 PDH0 to PDH5 PCT0, PCT1, PCT4, PCT6 PCS0, PCS2 PCM0, PCM1 P90 to P915 P70 to P79 P50 to P54 P40 to P45 P30 to P37 P20 to P26 P02, P03 AV REF0 AVSS ANI0 to ANI9 VDD REGC EVDD UVDD VSS FLMD0 FLMD1 DRST DMS DDI DCK DDO DMA Ethernet controller USB function INTC EXCLK CG PLL CLKOUT XT1 XT2 RESET Debug function Interrupt function BCU TIAA00 to TIAA50, TIAA01 to TIAA51, TOAA1OFF TOAB00 to TOAB02, TOAB10 to TOAB13 TOAB1T1 to TOAB1T3, TOAB1B1 to TOAB1B3 TIAB00 to TIAB02, TIAB10 to TIAB13, EVTAB1, TRGAB1, TOAB1OFF TOAA00 to TOAA50, TOAA01 to TOAA51 TOT00, TOT01 TECR0, TENC00, TENC01, EVTT0, TIT00, TIT01 RTC1HZ RTCCL RTCDIV RXDC0 to RXDC5 TXDC0 to TXDC5 ASCKC0 RXDB0, RXDB1 TXDB0, TXDB1 UARTB: 2 ch IIC0: 4 ch UARTC: 6 ch CSIE: 2 ch SIE0, SIE1 SOE0, SOE1 SCKE0, SCKE1 CSIF: 5 ch SIF0 to SIF4 SOF0 to SOF4 SCKF0 to SCKF4 SDA00 to SDA03 SCL00 to SCL03 CANNote 3: 1 ch CRXD0 CTXD0 Note 1 Note 2 16-bit timer/ event counter AB: 2 ch 32-bit barrel shifter 16-bit timer/ event counter AA: 6 ch 16-bit interval timer M: 4 ch 16-bit timer/ counter T: 1 ch Flash memory controller System register General-purpose registers 32 bits × 32 Multiplier 16 × 16 → 32 Key return function Regulator A/D converter Notes 1. μPD70F3778: 256 KB μPD70F3779, 70F3781: 384 KB μPD70F3780, 70F3782, 70F3783: 512 KB 2. μPD70F3778, 70F3779, 70F3780: 76 KB μPD70F3781, 70F3782, 70F3783: 124 KB 3. μPD70F3783 only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 1 INTRODUCTION R01UH0290EJ0300 Rev.3.00 Page 34 of 1817 Sep 19, 2011

• V850ES/JJ3-E NMI INTP00 to INTP25 RTP00 to RTP07 KR0 to KR7 RTO WDT DCU RTC ROM RAM PC ALU CPU HLDRQ HLDAK ASTB RD WAIT WR0, WR1 CS0, CS2, CS3 A0 to A23 AD0 to AD15 Timer/counter function Serial interface function PDL0 to PDL15 PDH0 to PDH7 PCT0, PCT1, PCT4, PCT6 PCS0, PCS2, PCS3 PCM0 to PCM3 P90 to P915 P70 to P711 P50 to P59 P40 to P48 P30 to P37 P20 to P27 P02, P03 AV REF0 AVSS ANI0 to ANI11 VDD REGC EVDD UVDD VSS FLMD0 FLMD1 DRST DMS DDI DCK DDO DMA Ethernet controller INTC EXCLK CG PLL CLKOUT XT1 XT2 RESET Debug function Interrupt function BCU TIAA00 to TIAA50, TIAA01 to TIAA51, TOAA1OFF TOAB00 to TOAB03, TOAB10 to TOAB13 TOAB1T1 to TOAB1T3, TOAB1B1 to TOAB1B3 TIAB00 to TIAB03, TIAB10 to TIAB13, EVTAB1, TRGAB1, TOAB1OFF TOAA00 to TOAA50, TOAA01 to TOAA51 TOT00, TOT01 TECR0, TENC00, TENC01, EVTT0, TIT00, TIT01 RTC1HZ RTCCL RTCDIV RXDC0 to RXDC7 TXDC0 to TXDC7 ASCKC0 RXDB0, RXDB1 TXDB0, TXDB1 UARTB: 2 ch IIC0: 5 ch UARTC: 8 ch CSIE: 2 ch SIE0, SIE1 SOE0, SOE1 SCKE0, SCKE1 CSIF: 7 ch SIF0 to SIF6 SOF0 to SOF6 SCKF0 to SCKF6 SDA00 to SDA04 SCL00 to SCL04 CANNote 3: 1 ch CRXD0 CTXD0 USB function16-bit timer/ event counter AB: 2 ch 16-bit timer/ event counter AA: 6 ch 16-bit interval timer M: 4 ch 16-bit timer/ counter T: 1 ch Note 1 Note 2 Flash memory controller 32-bit barrel shifter System register General-purpose registers 32 bits × 32 Multiplier 16 × 16 → 32 Ports Regulator Key return function A/D converter Notes 1. μPD70F3784: 512 KB μPD70F3785: 512 KB μPD70F3786: 512 KB 2. μPD70F3784: 76 KB μPD70F3785, 70F3786: 124 KB 3. μPD70F3786 only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 1 INTRODUCTION R01UH0290EJ0300 Rev.3.00 Page 35 of 1817 Sep 19, 2011

1.6.2 Internal units

(1) CPU The CPU uses five-stage pipeline control to enable single-cl ock execution of address calc ulations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing. (2) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetc hes the instruction code. The prefetch ed instruction code is stored in an instruction queue. (3) Flash memory (ROM) This is a 512/384/256 KB flash memory mapped to addresses 0000000H to 007FFFFH/0000000H to 005FFFFH/0000000H to 003FFFFH. It can be accessed from the CPU in one clock during instruction fetch. (4) RAM This is a 60 KB RAM mapped to addresses 3FF0000H to 3FFEFFFH. It can be accessed from the CPU in one clock during data access. An 16/64 KB data-only RAM is incorporated at addresses 00280000H to 00283FFFH/00280000H to 0028FFFFH. (5) Interrupt controller (INTC) This controller handles hardware interrupt requests (N MI, INTP00 to INTP25) from on-chip peripheral hardware and external hardware. Eight levels of interrupt prio rities can be specified for these interrupt requests, and multiplexed servicing control can be performed. (6) Clock generator (CG) A main clock oscillator and subclock oscillator are pr ovided and generate the main clock oscillation frequency (f X) and subclock frequency (fXT), respectively. There are two modes: In the clock-through mode, fX is used as the main clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 8. The CPU clock frequency (fCPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT. (7) Internal oscillator An internal oscillator is provided on chip. The oscillati on frequency is 220 kHz (TYP). The internal oscillator supplies the clock for watchdog timer 2 and timer M. (8) Timer/counter Six-channel 16-bit timer/event counter AA (TAA), two-channel 16-bit timer/event counter AB (TAB), one-channel 16- bit timer/event counter T (TMT), and fou r-channel 16-bit interval timer M (TMM) are provided on chip. The motor control function can be realized using TAB1 and TAA4 in combination.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 1 INTRODUCTION R01UH0290EJ0300 Rev.3.00 Page 36 of 1817 Sep 19, 2011 (9) Real-time counter (for watch) The real-time counter count s the reference time (one second) for wa tch counting based on the subclock (32.768 kHz) or main clock. This can simultaneously be used as the interval timer based on the main clock. Hardware counters dedicated to year, month, da y of week, day, hour, minute, and second are provided, and can count up to 99 years. (10) Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. The internal oscillation clock, the main clock, or the subclock can be selected as the source clock. Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal (WDT2RES) after an overflow occurs. (11) Serial interface The V850ES/JH3-E and V850ES/JJ3-E include eight kinds of serial interfaces (asynchronous serial interface C (UARTC), asynchronous serial interface B with FIFO (UARTB), 3-wire variable-length serial interface F (CSIF), 3- wire variable-length serial interface E with FIFO (CSIE), an I C bus interface (I C), a CAN controller (CAN) Note , a USB function controller (USBF), and a Ethernet controller). UARTC transfers data via the TXDC0 to TXDC5 and RXDC0 to RXDC5 pins. UARTB transfers data via the TXDB0, TXDB1, RXDB0, and RXDB1 pins. CSIF transfers data via the SOF0 to SOF6, SIF0 to SIF6, and SCKF0 to SCKF6 pins. CSIE transfers data via the SOE0, SOE1, SIE0, SIE1, SCKE0, and SCKE1 pins. I C transfers data via the SDA00 to SDA04 and SCL00 to SCL04 pins. CAN Note transfers data via the CRXD0 Note and CTXD0 Note pins. USBF transfers data via the UDMF and UDPF pins. Ethernet transfers data via the P1COL, P1CRS, P1MDC, P1MDIO, P1RXCLK, P1RXD0, P1RXD1, P1RXD2, P1RXD3, P1RXDV, P1RXER, P1TXCLK, P1TXD0, P1TXD1, P1TXD2, P1TXD3, P1TXEN, and P1TXER pins. Note μPD70F3783, 70F3786 only (12) A/D converter This 10-bit A/D converter includes 10 or 12 analog input pins. Conversion is performed using the successive approximation method. (13) DMA controller A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM, on-chip peripheral I/O devices, and external memory in response to interrupt requests sent by on-chip peripheral I/O devices. (14) Key interrupt function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (8 channels). (15) Real-time output function The real-time output function transfe rs preset 6/8-bit data to output la tches upon the occurrence of a timer compare register match signal.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 1 INTRODUCTION R01UH0290EJ0300 Rev.3.00 Page 37 of 1817 Sep 19, 2011 (16) CRC function A CRC operation circuit that generates a 16-bit CRC (Cycl ic Redundancy Check) code upon setting of 8-bit data is provided on-chip. (17) DCU (debug control unit) An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is provided. Switching between the normal port function and on-chip de bugging function is done with the control pin input level and the OCDM register. (18) Ports The following general-purpose port functions and control pin functions are available.

• V850ES/JH3-E Port I/O Alternate Function P0 2-bit I/O NMI, external interrupt, A/D converter trigger, external clock input P2 7-bit I/O Timer I/O, serial interface, external interrupt, real-time counter P3 8-bit I/O External interrupt, serial interface, timer I/O P4 6-bit I/O External interrupt, serial interface, timer I/O P5 5-bit I/O Timer I/O, serial interface, real-time output, key interrupt input, debug I/O P7 10-bit I/O A/D converter analog input P9 16-bit I/O Serial interface, key interrupt input, timer I/O, external interrupt, address bus PCM 2-bit I/O External bus control signal PCS 2-bit I/O External bus control signal PCT 4-bit I/O External bus control signal PDH 6-bit I/O External address bus, serial interface PDL 16-bit I/O External address/data bus
• V850ES/JJ3-E Port I/O Alternate Function P0 2-bit I/O NMI, external interrupt, A/D converter trigger, external clock input P2 8-bit I/O Timer I/O, serial interface, external interrupt, real-time counter P3 8-bit I/O External interrupt, serial interface, timer I/O P4 9-bit I/O External interrupt, serial interface, timer I/O P5 10-bit I/O Timer I/O, serial interface, real-time output, key interrupt input, debug I/O P7 12-bit I/O A/D converter analog input P9 16-bit I/O Serial interface, key interrupt input, timer I/O, external interrupt, address bus PCM 4-bit I/O External bus control signal PCS 3-bit I/O External bus control signal PCT 4-bit I/O External bus control signal PDH 8-bit I/O External address bus, serial interface PDL 16-bit I/O External address/data bus

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 38 of 1817 Sep 19, 2011 CHAPTER 2 PIN FUNCTIONS

2.1 List of Pin Functions

The names and functions of the pins of the V850ES/JH3-E and V850ES/JJ3-E are described below. There are three types of pin I/O buffer power supplies: AVREF0, EVDD, and UVDD. The relationship between these power supplies and the pins is described below. Table 2-1. Pin I/O Buffer Power Supplies Corresponding Pins Power Supply V850ES/JH3-E V850ES/JJ3-E AVREF0 Port 7 Port 7 EVDD RESET, ports 0, 2 to 5, 9, CM, CS, CT, DH, DL RESET, ports 0, 2 to 5, 9, CM, CS, CT, DH, DL UVDD UDPF , UDMF UDPF , UDMF

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 39 of 1817 Sep 19, 2011 (1) Port pins (1/3) Pin No. Pin Name I/O Function Alternate Function JH3-E JJ3-E P02 NMI 21 21 P03 I/O Port 0 2-bit I/O port Input/output can be specified in 1-bit units. 5 V tolerant. INTP00/ADTRG/EXCLK 22 22 P20 TIAB02/TOAB02/INTP01 38 38 P21 TIAB00/TOAB00/RTGDIV/RTCCL 39 39 P22 TIAB01/TOAB01/RTC1HZ/INTP02 40 40 P23 SIF1/TXDC1/SDA00/INTP03 59 65 P24 SOF1/RXDC1/SDL00/INTP04 62 68 P25 SCKF1/TIAA30/TOAA30/UDMARQ0 63 69 P26 TIAA31/TOAA31/INTP05/UDMAAK0 64 70 P27 I/O Port 2 7-bit I/O port (V850ES/JH3-E) 8-bit I/O port (V850ES/JJ3-E) Input/output can be specified in 1-bit units. 5 V tolerant. TIAB03/TOAB03/INTP21 − 41 P30 TXDC0/SIF2/TIAA00/TOAA00 28 28 P31 RXDC0/SOF2/TIAA01/TOAA01 29 29 P32 ASCKC0/SCKF2/TIAA10/TOAA10 30 30 P33 SIF4/TXDB0/TIAA11/TOAA11 31 31 P34 SOF4/RXDB0/TIAA20/TOAA20 32 32 P35 SCKF4/TIAA21/TOAA21/TOAA21OFF/INTP06 33 33 P36 TXDC2/SDA02/CTXD0 Note 36 36 P37 I/O Port 3 8-bit I/O port Input/output can be specified in 1-bit units. 5 V tolerant. RXDC2/SCL02/CRXD0 Note 37 37 P40 SIF0/TXDC3/SDA01/RTP00 3 3 P41 SOF0/RXDC3/SCL01/RTP01 4 4 P42 SCKF0/TIAA40/TOAA40/RTP02 5 5 SIE0/TXDC4/RTP03 − 6 P43 SIE0/TXDC4/RTP03/HLDAK 6 − SOE0/RXDC4/RTP04 − 7 P44 SOE0/RXDC4/RTP04/HLDRQ 7 − P45 SCKE0/TIAA41/TOAA41/RTP05 8 8 P46 SIF5/TXDC6/RTP06 − 128 P47 SOF5/RXDC6/RTP07 − 129 P48 I/O Port 4 6-bit I/O port (V850ES/JH3-E) 9-bit I/O port (V850ES/JJ3-E) Input/output can be specified in 1-bit units. 5 V tolerant (P46 to P48). SCKF5/INTP22 − 130 Note Internal CAN controller only Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E <R>

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 40 of 1817 Sep 19, 2011 (2/3) Pin No. Pin Name I/O Function Alternate Function JH3-E JJ3-E P50 INTP07/DDI 23 23 P51 INTP08/DDO 24 24 P52 INTP09/DCK 25 25 P53 INTP10/DMS 26 26 P54 INTP11/DRST 27 27 P55 SDA04/INTP23/UDMARQ1 − 42 P56 SCL04/INTP24/UDMAAK1 − 43 P57 SIF6/TXDC7 − 62 P58 SOF6/RXDC7 − 63 P59 I/O Port 5 5-bit I/O port (V850ES/JH3-E) 10-bit I/O port (V850ES/JJ3-E) Input/output can be specified in 1-bit units. 5 V tolerant. SCKF6/INTP25 − 64 P70 ANI0 128 144 P71 ANI1 127 143 P72 ANI2 126 142 P73 ANI3 125 141 P74 ANI4 124 140 P75 ANI5 123 139 P76 ANI6 122 138 P77 ANI7 121 137 P78 ANI8 120 136 P79 ANI9 119 135 P710 ANI10 − 134 P711 I/O Port 7 10-bit I/O port (V850ES/JH3-E) 12-bit I/O port (V850ES/JJ3-E) Input/output can be specified in 1-bit units. ANI11 − 133 P90 TOAB1T1/TOAB11/TIAB11/KR0/INTP12/A0 65 71 P91 TOAB1B1/TIAB10/KR1/TOAB10/A1 66 72 P92 TOAB1T2/TOAB12/TIAB12/KR2/INTP13/A2 67 73 P93 TOAB1B2/TRGAB1/KR3/INTP14/A3 68 74 P94 TOAB1T3/TOAB13/TIAB13/KR4/INTP15/A4 69 75 P95 TOAB1B3/EVTB1/KR5/INTP16/A5 70 76 P96 TECR0/TIT00/KR6/TOT00/A6 71 77 P97 TENC00/TIT01/KR7/TOT01/A7 72 78 P98 TENC01/INTP17/A8 73 79 P99 SIE1/TXDC5/SDA03/A9 74 80 P910 SOE1/RXDC5/SCL03/A10 75 81 P911 SCKE1/TIAA50/TOAA50/A11 76 82 P912 TOAB1OFF/INTP18/A12 77 83 P913 SIF3/TXDB1/INTP19/A13 78 84 P914 SOF3/RXDB1/INTP20/A14 79 85 P915 I/O Port 9 16-bit I/O port Input/output can be specified in 1-bit units. 5 V tolerant. SCKF3/TIAA51/TOAA51/A15 80 86 Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 41 of 1817 Sep 19, 2011 (3/3) Pin No. Pin Name I/O Function Alternate Function JH3-E JJ3-E PCM0 WAIT 86 92 PCM1 CLKOUT 81 87 PCM2 HLDAK − 119 PCM3 I/O Port CM 2-bit I/O port (V850ES/JH3-E) 4-bit I/O port (V850ES/JJ3-E) Input/output can be specified in 1-bit units. HLDRQ − 120 PCS0 CS0 115 125 PCS2 CS2 116 126 PCS3 I/O Port CS 2-bit I/O port (V850ES/JH3-E) 3-bit I/O port (V850ES/JJ3-E) Input/output can be specified in 1-bit units. CS3 − 127 PCT0 WR0 111 121 PCT1 WR1 112 122 PCT4 RD 113 123 PCT6 I/O Port CT 4-bit I/O port Input/output can be specified in 1-bit units. ASTB 114 124 PDH0 A16/SIE1 105 111 PDH1 A17/SOE1 106 112 PDH2 A18/SCKE1 107 113 PDH3 A19/SIF4/TXDB0 108 114 PDH4 A20/SOF4/RXDB0 109 115 PDH5 A21/SCKF4 110 116 PDH6 A22 − 117 PDH7 I/O Port DH 6-bit I/O port (V850ES/JH3-E) 8-bit I/O port (V850ES/JJ3-E) Input/output can be specified in 1-bit units. A23 − 118 PDL0 AD0 87 93 PDL1 AD1 88 94 PDL2 AD2 89 95 PDL3 AD3 90 96 PDL4 AD4 91 97 PDL5 AD5/FLMD1 92 98 PDL6 AD6 93 99 PDL7 AD7 94 100 PDL8 AD8 95 101 PDL9 AD9 96 102 PDL10 AD10 97 103 PDL11 AD11 98 104 PDL12 AD12 99 105 PDL13 AD13 100 106 PDL14 AD14 103 109 PDL15 I/O Port DL 16-bit I/O port Input/output can be specified in 1-bit units. AD15 104 110 Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 42 of 1817 Sep 19, 2011 (2) Non-port Pins (1/9) Pin No. Pin Name I/O Function Alternate Function JH3-E JJ3-E A0 P90/TOAB1T1/TOAB11/TIAB11/ KR0/INTP12 65 71 A1 P91/TOAB1B1/TIAB10/KR1/ TOAB10 66 72 A2 P92/TOAB1T2/TOAB12/TIAB12/ KR2/INTP13 67 73 A3 P93/TOAB1B2/TRGAB1/KR3/ INTP14 68 74 A4 P94/TOAB1T3/TOAB13/TIAB13/ KR4/INTP15 69 75 A5 P95/TOAB1B3/EVTAB1/KR5/ INTP16 70 76 A6 P96/TECR0/TIT00/KR6/TOT00 71 77 A7 P97/TENC00/TIT01/KR7/TOT01 72 78 A8 P98/TENC01/INTP17 73 79 A9 P99/SIE1/TXDC5/SDA03 74 80 A10 P910/SOE1/RXDC5/SCL03 75 81 A11 P911/SCKE1/TIAA50/TOAA50 76 82 A12 P912/TOAB1OFF/INTP18 77 83 A13 P913/SIF3/TXDB1/INTP19 78 84 A14 P914/SOF3/RXDB1/INTP20 79 85 A15 P915/SCKF3/TIAA51/TOAA51 80 86 A16 PDH0/SIE1 105 111 A17 PDH1/SOE1 106 112 A18 PDH2/SCKE1 107 113 A19 PDH3/SIF4/TXDB0 108 114 A20 PDH4/SOF4/RXDB0 109 115 A21 PDH5/SCKF4 110 116 A22 PDH6 − 117 A23 Output Address bus for external memory (when using separate bus) 5 V tolerant (A0 to A15). PDH7 − 118 Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E <R>

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 43 of 1817 Sep 19, 2011 (2/9) Pin No. Pin Name I/O Function Alternate Function JH3-E JJ3-E AD0 PDL0 87 93 AD1 PDL1 88 94 AD2 PDL2 89 95 AD3 PDL3 90 96 AD4 PDL4 91 97 AD5 PDL5/FLMD1 92 98 AD6 PDL6 93 99 AD7 PDL7 94 100 AD8 PDL8 95 101 AD9 PDL9 96 102 AD10 PDL10 97 103 AD11 PDL11 98 104 AD12 PDL12 99 105 AD13 PDL13 100 106 AD14 PDL14 103 109 AD15 I/O Address/data bus for external memory PDL15 104 110 ADTRG Input External trigger input for A/D converter, 5 V tolerant. P03/INTP00/EXCLK 22 22 ANI0 P70 128 144 ANI1 P71 127 143 ANI2 P72 126 142 ANI3 P73 125 141 ANI4 P74 124 140 ANI5 P75 123 139 ANI6 P76 122 138 ANI7 P77 121 137 ANI8 P78 120 136 ANI9 P79 119 135 ANI10 P710 − 134 ANI11 Input Analog voltage input for A/D converter P711 − 133 ASCKC0 Input UARTC0 baud rate clock input, 5 V tolerant. P32/SCKF2/TIAA10/TOAA10 30 30 ASTB Output Address strobe signal output for external memory PCT6 114 124 AVREF0 − Reference voltage input for A/D converter, Port ground potential − 1 1 AVSS − Ground potential for A/D converters − 2 2 CLKOUT Output Internal system clock output PCM1 81 87 CRXD0 Note Input CAN receive data input, 5 V tolerant. P37/RXDC2/SCL02 37 37 CS0 PCS0 115 125 CS2 PCS2 116 126 CS3 Output Chip select output PCS3 − 127 CTXD0 Note Output CAN transmit data output, 5 V tolerant. P36/TXDC2/SDA02 36 36 Note Internal CAN controller only Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 44 of 1817 Sep 19, 2011 (3/9) Pin No. Pin Name I/O Function Alternate Function JH3-E JJ3-E DCK Input Clock input for on-chip debug, 5 V tolerant. P52/INTP09 25 25 DDI Input Data input for on-chip debug, 5 V tolerant. P50/INTP07 23 23 DDO Output Data output for on-chip debugging, In the on-chip debug mode, high-level output is forcibly set, 5 V tolerant. P51/INTP08 24 24 DMS Input Mode select signal input for on-chip debugging, 5 V tolerant. P53/INTP10 26 26 DRST Input Reset signal inpu t for on-chip debugging, 5 V tolerant. P54/INTP11 27 27 EVDD − Positive power supply for external devices (same potential as VDD) − 35, 61, 85, 102, 118 35, 67, 91, 108, 132 EVTAB1 Input TAB1 external event count input TOAB1B3/KR5/INTP16/A5 70 76 EXCLK Input External USB clock signal input P03/INTP00/ADTRG 22 22 FLMD0 Input − 12 12 FLMD1 Input Flash memory programming mode setting pin PDL5/AD5 92 98 PCM2 − 119HLDAK Output Bus hold acknowledge output P43/SIE0/TXDC4/RTP03 6 − PCM3 − 120HLDRQ Input Bus hold request input P44/SOE0/RXDC4/RTP04 7 − INTP00 P03/ADTRG/EXCLK 22 22 INTP01 P20/TIAB02/TOAB02 38 38 INTP02 P22/TIAB01/TOAB01/RTC1HZ 40 40 INTP03 P23/SIF1/TXDC1/SDA00 59 65 INTP04 P24/SOF1/RXDC1/SDL00 62 68 INTP05 P26/TIAA31/TOAA31/UDMAAK0 64 70 INTP06 P35/SCKF4/TIAA21/TOAA21/ TOAA1OFF 33 33 INTP07 P50/DDI 23 23 INTP08 P51/DDO 24 24 INTP09 P52/DCK 25 25 INTP10 P53/DMS 26 26 INTP11 P54/DRST 27 27 INTP12 P90/TOAB1T1/TOAB11/TIAB11/ KR0/A0 65 71 INTP13 P92/TOAB1T2/TOAB12/TIAB12/ KR2/A2 67 73 INTP14 P93/TOAB1B2/TRGAB1/KR3/A3 68 74 INTP15 P94/TOAB1T3/TOAB13/TIAB13/ KR4/A4 69 75 INTP16 P95/TOAB1B3/EVTAB1/KR5/A5 70 76 INTP17 P98/TENC01/A8 73 79 INTP18 P912/TOAB1OFF/A12 77 83 INTP19 Input External interrupt request input (maskable, analog noise elimination) Analog noise elimination or digital noise elimination selectable for INTP02 pin. 5 V tolerant. P913/SIF3/TXDB1/A13 78 84 Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 45 of 1817 Sep 19, 2011 (4/9) Pin No. Pin Name I/O Function Alternate Function JH3-E JJ3-E INTP20 P914/SOF3/RXDB1/A14 79 85 INTP21 P27/TIAB03/TOAB03 − 41 INTP22 P48/SCKF5 − 130 INTP23 P55/SDA04/UDMARQ1 − 42 INTP24 P56/SCL04/UDMAAK1 − 43 INTP25 Input External interrupt request input (maskable, analog noise elimination) 5 V tolerant. P59/SCKF6 − 64 KR0 P90/TOAB1T1/TOAB11/TIAB11/ INTP12/A0 65 71 KR1 P91/TOAB1B1/TIAB10/TOAB10/ 66 72 KR2 P92/TOAB1T2/TOAB12/TIAB12/ INTP13/A2 67 73 KR3 P93/TOAB1B2/TRGAB1/INTP14/ 68 74 KR4 P94/TOAB1T3/TOAB13/TIAB13/ INTP15/A4 69 75 KR5 P95/TOAB1B3/EVTAB1/INTP16/ 70 76 KR6 P96/TECR0/TIT00/TOT00/A6 71 77 KR7 Input Key interrupt input (on-chip analog noise eliminator) 5 V tolerant. P97/TENC00/TIT01/TOT01/A7 72 78 NMI Input External interrupt input (non-maskable, analog noise elimination) 5 V tolerant. P02 21 21 P1COL Input Conflict detection input for Ethernet − 56 59 P1CRS Input Carrier detection input for Ethernet − 55 58 P1MDC Output Serial transfer clock output − 57 60 P1MDIO I/O Serial I/O − 58 61 P1RXCLK Input Receive clock input for Ethernet − 54 57 P1RXD0 Input Receive data input for Ethernet − 48 51 P1RXD1 Input Receive data input for Ethernet − 49 52 P1RXD2 Input Receive data input for Ethernet − 50 53 P1RXD3 Input Receive data input for Ethernet − 51 54 P1RXDV Input Receive data VALID input for Ethernet − 52 55 P1RXER Input Receive data error input for Ethernet − 53 56 P1TXCLK Input Transmit clock input for Ethernet − 47 50 P1TXD0 Output Transmit data output for Ethernet − 41 44 P1TXD1 Output Transmit data output for Ethernet − 42 45 P1TXD2 Output Transmit data output for Ethernet − 43 46 P1TXD3 Output Transmit data output for Ethernet − 44 47 P1TXEN Output Transmit data enable output for Ethernet − 46 49 P1TXER Output Transmit Error output for Ethernet − 45 48 Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 46 of 1817 Sep 19, 2011 (5/9) Pin No. Pin Name I/O Function Alternate Function JH3-E JJ3-E RD Output Read strobe signal output for external memory PCT4 113 123 REGC − Connection of regulator output stabilization capacitance (4.7 μF: recommend value) − 14, 83 14, 89 RESET Input System reset input − 18 18 RTC1HZ Output Real-time counter correction clock (1 Hz) output, 5 V tolerant. P22/TIAB01/TOAB01/INTP02 40 40 RTCCL Output Real-time counter clock (32 kHz primary oscillation) output, 5 V tolerant. P21/TIAB00/TOAB00/RTCDIV 39 39 RTCDIV Output Real-time counter clock (32 kHz division) output, 5 V tolerant. P21/TIAB00/TOAB00/RTCCL 39 39 RTP00 P40/SIF0/TXDC3/SDA01 3 3 RTP01 P41/SOF0/RXDC3/SCL01 4 4 RTP02 P42/SCKF0/TIAA40/TOAA40 5 5 P43/SIE0/TXDC4 − 6 RTP03 P43/SIE0/TXDC4/HLDAK 6 − P44/SOE0/RXDC4 − 7 RTP04 P44/SOE0/RXDC4/HLDRQ 7 − RTP05 P45/SCKE0/TIAA41/TOAA41 8 8 RTP06 P46/SIF5/TXDC6 − 128 RTP07 Output Real-time output port RTP00, RTP01, RTP06, and RTP07 are N-ch open-drain output selectable, 5 V tolerant (RTP06, RTP07). P47/SOF5/RXDC6 − 129 Serial receive data input (UARTB0), 5 V tolerant. P34/SOF4/TIAA20/TOAA20 32 32 RXDB0 Serial receive data input (UARTB0) PDH4/A20/SOF4 109 115 RXDB1 Input Serial receive data input (UARTB1), 5 V tolerant. P914/SOF3/INTP20/A14 79 85 RXDC0 P31/SOF2/TIAA01/TOAA01 29 29 RXDC1 P24/SOF1/RXDC1/SDL00/INTP04 62 68 RXDC2 P37/SCL02/CRXD0 Note 37 37 RXDC3 P41/SOF0/SCL01/RTP01 4 4 P44/SOE0/RTP04 − 7 RXDC4 P44/SOE0/RTP04/HLDRQ 7 − RXDC5 P910/SOE1/SCL03/A10 75 81 RXDC6 P47/SOF5/RTP07 − 129 RXDC7 Input Serial receive data input (UARTC0 to UARTC7)

5 V tolerant

(RXDC0 to RXDC2, RXDC5, RXDC6). P58/SOF6 − 63 SCKE0 Serial clock I/O (CSIE0) P45/TIAA41/TOAA41/RTP05 8 8 Serial clock I/O (CSIE1) , 5 V tolerant. P911/TIAA50/TOAA50/A11 76 82 SCKE1 I/O Serial clock I/O (CSIE1) PDH2/A18 107 113 SCKF0 P42/TIAA40/TOAA40/RTP02 5 5 SCKF1 P25/TIAA30/TOAA30/UMDARQ0 63 69 SCKF2 P32/ASCKC0/TIAA10/TOAA10 30 30 SCKF3 Serial clock I/O (CSIF0 to CSIF3) 5 V tolerant (SCKF1 to SCKF3). P915/TIAA51/TOAA51/A15 80 86 Serial clock I/O (CSIF4) 5 V tolerant. P35/TIAA21/TOAA21/TOAA1OFF/ INTP06 33 33 SCKF4 Serial clock I/O (CSIF4) PDH5/A21 110 116 SCKF5 P48/INTP22 − 130 SCKF6 I/O Serial clock I/O (CSIF5, CSIF6) 5 V tolerant. P59/INTP25 − 64 Note Internal CAN controller only Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 47 of 1817 Sep 19, 2011 (6/9) Pin No. Pin Name I/O Function Alternate Function JH3-E JJ3-E SCL00 P24/SOF1/RXDC1/INTP04 62 68 SCL01 P41/SOF0/RXDC3/RTP01 4 4 SCL02 P37/RXDC2/CRXD0 Note 37 37 SCL03 P910/SOE1/RXDC5/A10 75 81 SCL04 I/O Serial clock I/O (I C00 to I C04) N-ch open-drain output selectable 5 V tolerant (SCL00, SCL02 to SCL04). P56/INTP24/UDMAAK1 − 43 SDA00 P23/SIF1/TXDC1/INTP03 59 65 SDA01 P40/SIF0/TXDC3/RTP00 3 3 SDA02 P36/TXDC2/CTXD0 Note 36 36 SDA03 P99/SIE1/TXDC5/A9 74 80 SDA04 I/O Serial transmit/receive data I/O (I C00 to I C04) N-ch open-drain output selectable 5 V tolerant (SDA00, SDA02 to SDA04) . P55/INTP23/UDMARQ1 − 42 P43/TXDC4/RTP03 − 6 SIE0 Serial receive data input (CSIE0) P43/TXDC4/RTP03/HLDAK 6 − Serial receive data input (CSIE1), 5 V tolerant P99/TXDC5/SDA03/A9 74 80 SIE1 Input Serial receive data input (CSIE1) PDH0/A16 105 111 SIF0 P40/TXDC3/SDA01/RTP00 3 3 SIF1 P23/TXDC1/SDA00/INTP03 59 65 SIF2 P30/TXDC0/TIAA00/TOAA00 28 28 SIF3 Serial receive data input (CSIF0 to CSIF3) 5 V tolerant (SIF1 to SIF3). P913/TXDB1/INTP19/A13 78 84 Serial receive data input (CSIF4), 5 V tolerant. P33/TXDB0/TIAA11/TOAA11 31 31 SIF4 Serial receive data input (CSIF4) PDH3/TXDB0 108 114 SIF5 P46/TXDC6/RTP06 − 128 SIF6 Input Serial receive data input (CSIF5, CSIF6) 5 V tolerant. P57/TXDC7 − 62 P44/RXDC4/RTP04 − 7 SOE0 Serial transmit data output (CSIE0) P44/RXDC4/RTP04/HLDRQ 7 − Serial transmit data output (CSIE1), 5 V tolerant. P910/RXDC5/SCL03/A10 75 81 SOE1 Output Serial transmit data output (CSIE1) PDH1/A17 106 112 SOF0 P41/RXDC3/SCL01/RTP01 4 4 SOF1 P24/RXDC1/SDL00/INTP04 62 68 SOF2 P31/RXDC0/TIAA01/TOAA01 29 29 SOF3 Serial transmit data output (CSIF0 to CSIF3) N-ch open-drain output selectable 5 V tolerant (SOF1 to SOF3). P914/RXDB1/INTP20/A14 79 85 Serial transmit data output (CSIF4) N-ch open-drain output selectable, 5 V tolerant P34/RXDB0/TIAA20/TOAA20 32 32 SOF4 Serial transmit data output (CSIF4) PDH4/A20/RXDB0 109 115 SOF5 P47/RXDC6/RTP07 − 129 SOF6 Output Serial transmit data output (CSIF5, CSIF6) N-ch open-drain output selectable, 5 V tolerant. P58/RXDC7 − 63 TECR0 TMT0 encoder clear input N-ch open-drain output selectable, 5 V tolerant. P96/TIT00/KR6/TOT00/A6 71 77 TENC00 Encoder input/external event count input/ external trigger input N-ch open-drain output selectable, 5 V tolerant. P97/TIT01/KR7/TOT01/A7 72 78 TENC01 Input Encoder input N-ch open-drain output selectable, 5 V tolerant. P98/INTP17/A8 73 79 Note Internal CAN controller only Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 48 of 1817 Sep 19, 2011 (7/9) Pin No. Pin Name I/O Function Alternate Function JH3-E JJ3-E TIAA00 External event count input/capture trigger input/external trigger input (TAA0) , 5 V tolerant. P30/TXDC0/SIF2/TOAA00 28 28 TIAA01 Capture trigger input (TAA0) , 5 V tolerant. P31/RXDC0/SOF2/TOAA01 29 29 TIAA10 External event count input/capture trigger input/external trigger input (TAA1) , 5 V tolerant. P32/ASCKC0/SCKF2/TOAA10 30 30 TIAA11 Capture trigger input (TAA1) , 5 V tolerant. P33/SIF4/TXDB0/TOAA11 31 31 TIAA20 External event count input/capture trigger input/external trigger input (TAA2) , 5 V tolerant. P34/SOF4/RXDB0/TOAA20 32 32 TIAA21 Capture trigger input (TAA2) , 5 V tolerant. P35/SCKF4/TOAA21/TOAA1OFF/ INTP06 33 33 TIAA30 External event count input/capture trigger input/external trigger input (TAA3) , 5 V tolerant. P25/SCKF1/TOAA30/UDMARQ0 63 69 TIAA31 Capture trigger input (TAA3) , 5 V tolerant. P26/TOAA31/INTP05/UDMAAK0 64 70 TIAA40 External event count input/capture trigger input/external trigger input (TAA4) P42/SCKF0/TOAA40/RTP02 5 5 TIAA41 Capture trigger input (TAA4) P45/SCKE0/TOAA41/RTP05 8 8 TIAA50 External event count input/capture trigger input/external trigger input (TAA5) , 5 V tolerant. P911/SCKE1/TOAA50/A11 76 82 TIAA51 Input Capture trigger input (TAA5) , 5 V tolerant. P915/SCKF3/TOAA51/A15 80 86 TIAB00 External event count input/capture trigger input /external trigger input (TAB0) , 5 V tolerant. P21/TOAB00/RTCDIV/RTCCL 39 39 TIAB01 P22/TOAB01/RTC1HZ/INTP02 40 40 TIAB02 P20/TOAB02/INTP01 38 38 TIAB03 Input Capture trigger input (TAB0) , 5 V tolerant. P27/TOAB03/INTP21 − 41 TIAB10 Input Capture trigger input/external event count input/external trigger input (TAB1) N-ch open-drain output selectable, 5 V tolerant. P91/TOAB1B1/KR1/TOAB10/A1 66 72 TIAB11 P90/TOAB1T1/TOAB11/KR0/ INTP12/A0 65 71 TIAB12 P92/TOAB1T2/TOAB12/KR2/ INTP13/A2 67 73 TIAB13 Input Capture trigger input (TAB1) N-ch open-drain output selectable 5 V tolerant. P94/TOAB1T3/TOAB13/KR4/ INTP15/A4 69 75 TIT00 Input P96/TECR0/KR6/TOT00/A6 71 77 TIT01 Input TMT0 capture trigger input N-ch open-drain output selectable, 5 V tolerant. P97/TENC00/KR7/TOT01/A7 72 78 TOAA00 P30/TXDC0/SIF2/TIAA00 28 28 TOAA01 Timer output (TAA0) N-ch open-drain output selectable, 5 V tolerant. P31/RXDC0/SOF2/TIAA01 29 29 TOAA10 P32/ASCKC0/SCKF2/TIAA10 30 30 TOAA11 Output Timer output (TAA1) N-ch open-drain output selectable, 5 V tolerant. P33/SIF4/TXDB0/TIAA11 31 31 TOAA1OFF Input TAA1 high-impedance output control signal input 5 V tolerant. P35/SCKF4/TIAA21/TOAA21 /INTP06 33 33 Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 49 of 1817 Sep 19, 2011 (8/9) Pin No. Pin Name I/O Function Alternate Function JH3-E JJ3-E TOAA20 P34/SOF4/RXDB0/TIAA20 32 32 TOAA21 Timer output (TAA2) N-ch open-drain output selectable, 5 V tolerant. P35/SCKF4/TIAA21/TOAA1OFF/ INTP06 33 33 TOAA30 P25/SCKF1/TIAA30/UDMARQ0 63 69 TOAA31 Timer output (TAA3) N-ch open-drain output selectable, 5 V tolerant. P26/TIAA31/INTP05/UDMAAK0 64 70 TOAA40 P42/SCKF0/TIAA40/RTP02 5 5 TOAA41 Timer output (TAA4) N-ch open-drain output selectable P45/SCKE0/TIAA41/RTP05 8 8 TOAA50 P911/SCKE1/TIAA50/A11 76 82 TOAA51 Output Timer output (TAA5) N-ch open-drain output selectable, 5 V tolerant. P915/SCKF3/TIAA51/A15 80 86 TOAB00 P21/TIAB00/RTCDIV/RTCCL 39 39 TOAB01 P22/TIAB01/RTC1HZ/INTP02 40 40 TOAB02 P20/TIAB02/INTP01 38 38 TOAB03 Output Timer output (TAB0) N-ch open-drain output selectable, 5 V tolerant. P27/TIAB03/INTP21 − 41 TOAB10 P91/TOAB1B1/TIAB10/KR1/A1 66 72 TOAB11 P90/TOAB1T1/TIAB11/KR0/ INTP12/A0 65 71 TOAB12 P92/TOAB1T2/TIAB12/KR2/ INTP13/A2 67 73 TOAB13 Output Timer output (TAB1) N-ch open-drain output selectable, 5 V tolerant. P94/TOAB1T3/TIAB13/KR4/ INTP15/A4 69 75 TOAB1B1 P91/TIAB10/KR1/TOAB10/A1 66 72 TOAB1B2 P93/TRGAB1/KR3/INTP14/A3 68 74 TOAB1B3 Output Pulse signal output for 6-phase PWM low-arm of TAB1 N-ch open-drain output selectable, 5 V tolerant. P95/EVTAB1/KR5/INTP16/A5 70 76 TOAB1OFF Input TAB1 high-impedance output control signal input, 5 V tolerant. P912/INTP18/A12 77 83 TOAB1B1 P90/TOAB11/TIAB11/KR0/ INTP12/A0 65 71 TOAB1B2 P92/TOAB12/TIAB12/KR2/ INTP13/A2 67 73 TOAB1B3 Output Pulse signal output for 6-phase PWM high-arm of TAB1 N-ch open-drain output selectable, 5 V tolerant. P94/TOAB13/TIAB13/KR4/ INTP15/A4 69 75 TOT00 P96/TECR0/TIT00/KR6/A6 71 77 TOT01 Output Timer output (TMT0) N-ch open-drain output selectable, 5 V tolerant. P97/TENC00/TIT01/KR7/A7 72 78 TRGAB1 Input External trigger input of TAB1 N-ch open-drain output selectable, 5 V tolerant. P93/TOAB1B2/KR3/INTP14/A3 68 74 Serial transmit data output (UARTB0), 5 V tolerant. P33/SIF4/TIAA11/TOAA11 31 31 TXDB0 Serial transmit data output (UARTB0) PDH3/A19/SIF4 108 114 TXDB1 Output Serial transmit data output (UARTB1), 5 V tolerant. P913/SIF3/INTP19/A13 78 84 Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 50 of 1817 Sep 19, 2011 (9/9) Pin No. Pin Name I/O Function Alternate Function JH3-E JJ3-E TXDC0 P30/SIF2/TIAA00/TOAA00 28 28 TXDC1 P23/SIF1/SDA00/INTP03 59 65 TXDC2 Serial transmit data output (UARTC0 to UARTC2) N-ch open-drain output selectable 5 V tolerant. P36/SDA02/CTXD0 Note 36 36 TXDC3 P40/SIF0/SDA01/RTP00 3 3 P43/SIE0/RTP03 − 6 TXDC4 Serial transmit data output (UARTC3, UARTC4) P43/SIE0/RTP03/HLDAK 6 − TXDC5 P99/SIE1/SDA03/A9 74 80 TXDC6 P46/SIF5/RTP06 − 128 TXDC7 Output Serial transmit data output (UARTC5 to UARTC7) N-ch open-drain output selectable 5 V tolerant. P57/SIF6 − 62 EXCLK Input External USB clock signal i nput, 5 V tolerant. P03/INTP00/ADTRG 22 22 UDMAAK0 P26/TIAA31/TOAA31/INTP05 64 70 UDMAAK1 Output DMA acknowledge for USB, 5 V tolerant. P56/SCL04/INTP24 − 43 UDMARQ0 P25/SCKF1/TIAA30/TOAA30 63 69 UDMARQ1 Input DMA request for USB, 5 V tolerant. P55/SDL04/INTP23 − 42 UDMF USB data I/O ( −) function − 9 9 UDPF I/O USB data I/O (+) function − 10 10 UVDD − 3.3 V positive power supply for USB − 11 11 VDD − Positive power supply pin for internal unit − 13, 82 13, 88 VSS − Ground potential for internal unit − 15, 34, 60, 84, 101, 117 15, 34, 66, 90, 107, 131 WAIT Input External wait input PCM0 86 92 WR0 Write strobe for external memory (lower 8 bits) PCT0 111 121 WR1 Output Write strobe for external memory (higher 8 bits) PCT1 112 122 X1 Input − 16 16 X2 − Connecting resonator for main clock − 17 17 XT1 Input − 19 19 XT2 − Connecting resonator for subclock − 20 20 Note Internal CAN controller only Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 51 of 1817 Sep 19, 2011

2.2 Pin States

The operation states of pins in the various operation modes are described below. Table 2-2. Pin Operation Status in Each Operation Mode Pin Name When Power Is Turned On Note 1 During Reset (Other than When Power Is Turned On) HALT Mode Note 2 IDLE1, IDLE2, Sub-IDLE Mode Note 2 STOP Mode Note 2 Idle State Note 3 Bus Hold DRST Pull down Pull down Note 4 Held Held Held Held Held DDO Undefined Hi-Z Note 5 Held Held Held Held Held AD0 to AD15 Undefined Note 7 A0 to A15 Note 8 A16 to A23 Undefined Note 7 Hi-Z Hi-Z Held Hi-Z WAIT Note 7 − − − − WR0, WR1 RD ASTB CS0, CS2, CS3 H Note 7 Hi-Z HLDAK H H H L HLDRQ − − − Operating CLKOUT Hi-Z Note 6 Hi-Z Note 6 Operating L L Operating Operating Other port pins Hi-Z Hi-Z Held Held Held Held Held Notes 1. Duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower limit) when the power is turned on. 2. Operates while alternat e functions are operating. 3. The state of the pins in the idle state inserted after the T3 state is shown. 4. Pulled down during external reset. During internal reset by the watchdog timer or clock monitor, etc., the state of this pin differs according to the OCDM.OCDM0 bit setting. 5. In the on-chip debug mode, data is output from the DDO pin. 6. The bus control pins function alternately as port pins, so they are initialized to the input mode (port mode). 7. Operates even in the HALT mode, during DMA operation. 8. The A0 to A15 pins are used in the separate bus mode. Remark Hi-Z High impedance Held: The state during the immediately preceding external bus cycle is held. L: Low-level output H: High-level output −: Input without sampling (not acknowledged)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 52 of 1817 Sep 19, 2011

2.3 Pin I/O Circuit Types, I/O Buffer Powe r Supplies and Connection of Unused Pins

Table 2-3. Pin I/O Circuit Types and Connection of Unused Pins (1/4) Pin Name Alternate Function I/O Ci rcuit Type Recommended Connection JH3-E JJ3-E P02 NMI √ √ P03 INTP00/ADTRG/EXCLK 10-D Input: Independently connect to EV DD or VSS via a resistor. Output: Leave open. √ √ P20 TIAB02/TOAB02/INTP01 √ √ P21 TIAB00/TOAB00/RTCDIV/RTCCL √ √ P22 TIAB01/TOAB01/RTC1HZ/INTP02 √ √ P23 SIF1/TXDC1/SDA00/INTP03 √ √ P24 SOF1/RXDC1/SDL00/INTP04 √ √ P25 SCKF1/TIAA30/TOAA30/UDMARQ0 √ √ P26 TIAA31/TOAA31/INTP05/UDMAAK0 √ √ P27 TIAB03/TOAB03/INTP21 10-D Input: Independently connect to EV DD or VSS via a resistor. Output: Leave open. − √ P30 TXDC0/SIF2/TIAA00/TOAA00 √ √ P31 RXDC0/SOF2/TIAA01/TOAA01 √ √ P32 ASCKC0/SCKF2/TIAA10/TOAA10 √ √ P33 SIF4/TXDB0/TIAA11/TOAA11 √ √ P34 SOF4/RXDB0/TIAA20/TOAA20 √ √ P35 SCKF4/TIAA21/TOAA21/ TOAA1OFF/INTP06 √ √ P36 TXDC2/SDA02/CTXD0 Note √ √ P37 RXDC2/SCL02/CRXD0 Note 10-D Input: Independently connect to EV DD or VSS via a resistor. Output: Leave open. √ √ P40 SIF0/TXDC3/SDA01/RTP00 √ √ P41 SOF0/RXDC3/SCL01/RTP01 √ √ P42 SCKF0/TIAA40/TOAA40/RTP02 √ √ SIE0/TXDC4/RTP03 − √ P43 SIE0/TXDC4/RTP03/HLDAK √ − SOE0/RXDC4/RTP04 − √ P44 SOE0/RXDC4/RTP04/HLDRQ √ − P45 SCKE0/TIAA41/TOAA41/RTP05 √ √ P46 SIF5/TXDC6/RTP06 − √ P47 SOF5/RXDC6/RTP07 − √ P48 SCKF5/INTP22 10-D Input: Independently connect to EV DD or VSS via a resistor. Output: Leave open. − √ Note Internal CAN controller only Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 53 of 1817 Sep 19, 2011 Table 2-3. Pin I/O Circuit Types and Connection of Unused Pins (2/4) Pin Name Alternate Function I/O Ci rcuit Type Recommended Connection JH3-E JJ3-E P50 INTP07/DDI √ √ P51 INTP08/DDO √ √ P52 INTP09/DCK √ √ P53 INTP10/DMS 10-D Input: Independently connect to EVDD or VSS via a resistor. Output: Leave open. √ √ P54 INTP11/DRST 10-N Input: Independently connect to EV SS via a resistor. Fixing to VDD level is prohibited. Output: Leave open. Internally pulled down after reset by RESET pin. √ √ P55 SDA04/INTP23/UDMARQ1 − √ P56 SCL04/INTP24/UDMAAK1 − √ P57 SIF6/TXDC7 − √ P58 SOF6/RXDC7 − √ P59 SCKF6/INTP25 10-D − √ P70 to P79 ANI0 to ANI9 √ √ P710, P711 ANI10, ANI11 11-G Input: Independently connect to AVREF0 or AVSS via a resistor. Output: Leave open. − √ P90 TOAB1T1/TOAB11/TIAB11/KR0/ INTP12/A0 √ √ P91 TOAB1B1/TIAB10/KR1/TOAB10/A1 √ √ P92 TOAB1T2/TOAB12/TIAB12/KR2/ INTP13/A2 √ √ P93 TOAB1B2/TRGAB1/KR3/INTP14/A3 √ √ P94 TOAB1T3/TOAB13/TIAB13/KR4/ INTP15/A4 √ √ P95 TOAB1B3/EVTB1/KR5/INTP16/A5 √ √ P96 TECR0/TIT00/KR6/TOT00/A6 √ √ P97 TENC00/TIT01/KR7/TOT01/A7 √ √ P98 TENC01/INTP17/A8 √ √ P99 SIE1/TXDC5/SDA03/A9 √ √ P910 SOE1/RXDC5/SCL03/A10 √ √ P911 SCKE1/TIAA50/TOAA50/A11 √ √ P912 TOAB1OFF/INTP18/A12 √ √ P913 SIF3/TXDB1/INTP19/A13 √ √ P914 SOF3/RXDB1/INTP20/A14 √ √ P915 SCKF3/TIAA51/TOAA51/A15 10-D Input: Independently connect to EVDD or VSS via a resistor. Output: Leave open. √ √ PCM0 WAIT √ √ PCM1 CLKOUT √ √ PCM2 HLDAK − √ PCM3 HLDRQ

5 Input: Independently connect to

EVDD or VSS via a resistor. Output: Leave open. − √ Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 54 of 1817 Sep 19, 2011 Table 2-3. Pin I/O Circuit Types and Connection of Unused Pins (3/4) Pin Name Alternate Function I/O Ci rcuit Type Recommended Connection JH3-E JJ3-E PCS0 CS0 √ √ PCS2 CS2 √ √ PCS3 CS3 EVDD or VSS via a resistor. Output: Leave open. − √ PCT0 WR0 √ √ PCT1 WR1 √ √ PCT4 RD √ √ PCT6 ASTB EVDD or VSS via a resistor. Output: Leave open. √ √ PDH0 A16/SIE1 10-D √ √ PDH1 A17/SOE1 5 √ √ PDH2 A18/SCKE1 √ √ PDH3 A19/SIF4/TXDB0 √ √ PDH4 A20/SOF4/RXDB0 √ √ PDH5 A21/SCKF4 10-D √ √ PDH6, PDH7 A22, A23 5 Input: Independently connect to EVDD or VSS via a resistor. Output: Leave open. − √ PDL0 to PDL4 AD0 to AD4 √ √ PDL5 AD5/FLMD1 √ √ PDL6 to PDL15 AD6 to AD15 EVDD or VSS via a resistor. Output: Leave open. √ √ AVREF0 − − Directly connect to VDD and always supply power. (The same applies during standby.) √ √ AVSS − − Always directly connect to ground. (The same applies during standby.) √ √ EVDD − − Directly connect to VDD and always supply power. √ √ FLMD0 − − Directly connect to VSS in other than flash mode. √ √ P1COL − 5 √ √ P1CRS − 5 √ √ P1MDIO − 5 √ √ P1RXCLK − 5 √ √ P1RXD0 − 5 √ √ P1RXD1 − 5 √ √ P1RXD2 − 5 √ √ P1RXD3 − 5 √ √ P1RXDV − 5 √ √ P1RXER − 5 √ √ P1TXCLK − 5 Independently connect to EVDD or VSS via a resistor. √ √

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 55 of 1817 Sep 19, 2011 Table 2-3. Pin I/O Circuit Types and Connection of Unused Pins (4/4) Pin Name Alternate Function I/O Ci rcuit Type Recommended Connection JH3-E JJ3-E P1MDC − 5 √ √ P1TXD0 − 5 √ √ P1TXD1 − 5 √ √ P1TXD2 − 5 √ √ P1TXD3 − 5 √ √ P1TXEN − 5 √ √ P1TXER − 5 Leave open. √ √ REGC − − Connect to regulator output stabilization capacitor (4.7 μF (recommend value)). √ √ RESET − 2 − √ √ UDMF − − Leave open. √ √ UDPF − − Always directly connect to ground via a resistor. √ √ UVDD − − Always directly connect to ground. (The same applies during standby.) √ √ VDD − − Always directly connect to ground. (The same applies during standby.) √ √ VSS − − Always directly connect to ground. (The same applies during standby.) √ √ XT1 − 16-C Connect to V SS via a resistor. √ √ XT2 − 16-C Leave open. √ √ Remark JH3-E: V850ES/JH3-E, JJ3-E: V850ES/JJ3-E

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 2 PIN FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 56 of 1817 Sep 19, 2011 Figure 2-1. Pin I/O Circuits Type 2 Schmitt-triggered input with hysteresis characteristics Type 5 IN Data Output disable P-ch IN/OUT EVDD VSS N-ch Input enable Type 11-G Type 10-D Data Output disable EVDD VSSNote P-ch IN/OUT N-ch Open drain Input enable Data Output disable AV REF0 P-ch IN/OUT N-ch P-ch N-ch VREF0 (Threshold voltage) Comparator Input enable AVSS AVSS Data Output disable EV DD VSS P-ch IN/OUT N-ch Open drain Input enable OCDM0 bit Note N-ch Type 16-C P-ch Feedback cut-off XT1 XT2 Type 10-N Note Hysteresis characteristics are not available in port mode.

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2.4 Cautions

When the power is turned on, the following pins may output an undefined level temporarily even during reset.

• P51/INTP08/DDO pin

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 58 of 1817 Sep 19, 2011 CHAPTER 3 CPU FUNCTION The CPU of the V850ES/JH3-E and V850ES/JJ3-E is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline.

3.1 Features

Minimum instruction execution time: 20 ns (operating with main clock (fXX) of 50 MHz: VDD = 2.85 to 3.6 V) 30.5 μs (operating with subclock (fXT) of 32.768 kHz) Memory space Program (physical address) space: 64 MB linear Data (logical address) space: 4 GB linear General-purpose registers: 32 bits × 32 registers Internal 32-bit architecture 5-stage pipeline control Multiplication/division instruction Saturation operation instruction 32-bit shift instruction: 1 clock Load/store instruction with long/short format Four types of bit manipulation instructions

• SET1
• CLR1
• NOT1
• TST1

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3.2 CPU Register Set

The registers of the V850ES/JH3-E and V850ES/JJ3-E can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual. (1) Program register set (2) System register set r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (Zero register) (Assembler-reserved register) (Stack pointer (SP)) (Global pointer (GP)) (Text pointer (TP)) (Element pointer (EP)) (Link pointer (LP)) PC (Program counter) PSW (Program status word) ECR (Interrupt source register) FEPC FEPSW (NMI status saving register) (NMI status saving register) EIPC EIPSW (Interrupt status saving register) (Interrupt status saving register) 31 0 31 0 31 0 CTBP (CALLT base pointer) DBPC DBPSW (Exception/debug trap status saving register) (Exception/debug trap status saving register) CTPC CTPSW (CALLT execution status saving register) (CALLT execution status saving register)

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3.2.1 Program register set

The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are ava ilable. Any of these register s can be used to store a data variable or an address variable. However, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the SLD and SST instructions as a base pointer when these instructions access the memory. r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. When using these registers, save their contents for protection, and then restore the contents after using the registers. r2 is some times used by the real-time OS. If the real-time OS does not use r2, it can be used as a register for variables. Table 3-1. Program Registers Name Usage Operation r0 Zero register Always holds 0. r1 Assembler-reserved register Used as work ing register to create 32-bit immediate data r2 Register for address/data variable (if real-time OS does not use r2) r3 Stack pointer Used to create a stack frame when a function is called r4 Global pointer Used to access a global variable in the data area r5 Text pointer Used as register that indicates the beginning of a text area (area where program codes are located) r6 to r29 Register for address/data variable r30 Element pointer Used as base pointer to access memory r31 Link pointer Used when t he compiler calls a function PC Program counter Holds the instruction address during program execution Remark For further details on the r1, r3 to r5, and r31 that are used in the assembler and C compiler, refer to the CA850 (C Compiler Package) Assembly Language User’s Manual. (2) Program counter (PC) The program counter holds the instruction address during program execution. The lower 32 bits of this register are valid. Bits 31 to 26 are fixed to 0. A carry from bit 25 to 26 is ignored even if it occurs. Bit 0 is fixed to 0. This means that execution cannot branch to an odd address. 31 26 25 1 0 PC Fixed to 0 Instruction address during program execution 0 Default value 00000000H

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3.2.2 System register set

The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store inst ructions (LDSR and STSR), using the system register numbers listed below. Table 3-2. System Register Numbers Operand Specification System Register Number System Register Name LDSR Instruction STSR Instruction

0 Interrupt status saving register (EIPC)

√ √

1 Interrupt status saving register (EIPSW)

√ √

2 NMI status saving register (FEPC)

√ √

3 NMI status saving register (FEPSW)

√ √

4 Interrupt source register (ECR) × √

5 Program status word (PSW) √ √

6 to 15 Reserved for future function expansion (operation is not guaranteed if these registers are accessed) × ×

16 CALLT execution status saving register (CTPC) √ √

17 CALLT execution status saving register (CTPSW) √ √

18 Exception/debug trap status saving register (DBPC) √

19 Exception/debug trap status saving register (DBPSW) √

20 CALLT base pointer (CTBP) √ √

21 to 31 Reserved for future function expansion (operation is not guaranteed if these registers are accessed) × × Notes 1. Because only one set of these registers is availabl e, the contents of these registers must be saved by program if multiple interrupts are enabled. 2. These registers can be accessed only during the inte rval between the execution of the DBTRAP instruction or illegal opcode and DBRET instruction execution. Caution Even if EIPC or FEPC, or bi t 0 of CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when execution is returned to the main routine by the RETI in struction after interr upt servicing (this is because bit 0 of the PC is fixed to 0). Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0). Remark √: Can be accessed ×: Access prohibited

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 62 of 1817 Sep 19, 2011 (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program stat us word (PSW) are saved to EIPSW (these contents are saved to the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs). The address of the instruction next to the instruction under execution, except some instructions (see 25.8 Periods in Which Interrupts Are Not Acknowledged by CPU), is saved to EIPC when a software exception or a maskable interrupt occurs. The current contents of the PSW are saved to EIPSW. Because only one set of interrupt status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are rese rved for future function expansion (these bits are always fixed to 0). The value of EIPC is restored to the PC and the value of EIPSW to the PSW by the RETI instruction. 31 0 EIPC (Contents of saved PC)00 Default value 0xxxxxxxH (x: Undefined) 26 25 0 0 0 0 31 0 EIPSW (Contents of saved PSW)00 Default value 000000xxH (x: Undefined) 0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 63 of 1817 Sep 19, 2011 (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs. If an NMI occurs, the contents of the pr ogram counter (PC) are saved to F EPC, and those of the program status word (PSW) are saved to FEPSW. The address of the instruction next to the one of the instruction under execution, except some instructions, is saved to FEPC when an NMI occurs. The current contents of the PSW are saved to FEPSW. Because only one set of NMI status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are re served for future function expansion (these bits are always fixed to 0). The value of FEPC is restored to the PC and the value of FEPSW to the PSW by the RETI instruction. 31 0 FEPC (Contents of saved PC)00 Default value 0xxxxxxxH (x: Undefined) 26 25 0 0 0 0 31 0 FEPSW (Contents of saved PSW)00 Default value 000000xxH (x: Undefined) 0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0 (3) Interrupt source register (ECR) The interrupt source register (ECR) holds the source of an e xception or interrupt if an exception or interrupt occurs. This register holds the exception code of each interrupt s ource. Because this register is a read-only register, data cannot be written to this register using the LDSR instruction. 31 0 ECR FECC EICC Default value 00000000H 16 15 Bit position Bit name Meaning 31 to 16 FECC Exception code of non-maskable interrupt (NMI) 15 to 0 EICC Exception code of exception or maskable interrupt

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 64 of 1817 Sep 19, 2011 (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this regist er are changed by using the LDSR instru ction, the new contents are validated immediately after completion of LDSR instruction execution. However if the ID flag is set to 1, interrupt requests will not be acknowledged while the LDSR instruction is being executed. Bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0). (1/2) 31 0 PSW RFU Default value 00000020H NP EP ID SAT CY OV SZ Bit position Flag name Meaning 31 to 8 RFU Reserved field. Fixed to 0. 7 NP Indicates that a non-maskable interrupt (NMI) is being serviced. This bit is set to 1 when an NMI request is acknowledged, disabling multiple interrupts. 0: NMI is not being serviced. 1: NMI is being serviced. 6 EP Indicates that an exception is being processed. This bit is set to 1 when an exception occurs. Even if this bit is set, interrupt requests are acknowledged. 0: Exception is not being processed. 1: Exception is being processed. 5 ID Indicates whether a maskable interrupt can be acknowledged. 0: Interrupt enabled 1: Interrupt disabled

4 SAT

Indicates that the result of a saturation operation has overflowed and is saturated. Because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. Use the LDSR instruction to clear this bit. This flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: Not saturated 1: Saturated 3 CY Indicates whether a carry or a borrow occurs as a result of an operation. 0: Carry or borrow does not occur. 1: Carry or borrow occurs. 2 OV Note Indicates whether an overflow occurs during operation. 0: Overflow does not occur. 1: Overflow occurs. 1 S Note Indicates whether the result of an operation is negative. 0: The result is positive or 0. 1: The result is negative. 0 Z Indicates whether the result of an operation is 0. 0: The result is not 0. 1: The result is 0. Remark Also read Note on the next page.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 65 of 1817 Sep 19, 2011 (2/2) Note The result of the operation that has performed satu ration processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is performed. Flag Status Status of Operation Result SAT OV S Result of Operation of Saturation Processing Maximum positive value is exceeded 1 1 0 7FFFFFFFH Maximum negative value is exceeded 1 1 1 80000000H Positive (maximum value is not exceeded) 0 Negative (maximum value is not exceeded) Holds value before operation Operation result itself (5) CALLT execution status saving registers (CTPC and CTPSW) CTPC and CTPSW are CALLT execution status saving registers. When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and those of the program status word (PSW) are saved to CTPSW. The contents saved to CTPC are the address of the instruction next to CALLT. The current contents of the PSW are saved to CTPSW. Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved for future function expansion (fixed to 0). 31 0 CTPC (Saved PC contents)00 Default value 0xxxxxxxH (x: Undefined) 26 25 0 0 0 0 31 0 CTPSW (Saved PSW contents)00 Default value 000000xxH (x: Undefined) 0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 66 of 1817 Sep 19, 2011 (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW. The contents to be saved to DBPC are the address of the instruction next to the one that is being executed when an exception trap or debug trap occurs. The current contents of the PSW are saved to DBPSW. This register can be read or written only during the inte rval between the execution of the DBTRAP instruction or illegal opcode and the DBRET instruction. Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion (fixed to 0). The value of DBPC is restored to the PC and the value of DBPSW to the PSW by the DBRET instruction. 31 0 DBPC (Saved PC contents)00 Default value 0xxxxxxxH (x: Undefined) 26 25 0 0 0 0 31 0 DBPSW (Saved PSW contents)00 Default value 000000xxH (x: Undefined) 0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0 (7) CALLT base pointer (CTBP) The CALLT base pointer (CTBP) is used to specify a table address or generate a target address (bit 0 is fixed to 0). Bits 31 to 26 of this register are reserved for future function expansion (fixed to 0). 31 0 CTBP (Base address)00 Default value 0xxxxxxxH (x: Undefined) 26 25 0 0 0 0 0

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3.3 Operation Modes

The V850ES/JH3-E and V850ES/JJ3-E have the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is se t to the port mode after system reset has been released. Execution branches to the reset entry address of the internal ROM, and then instruction processing is started. (2) Flash memory programming mode In this mode, the internal flash memory can be programmed by using a flash programmer. (3) On-chip debug mode The V850ES/JH3-E and V850ES/JJ3-E are provided with an on-chip debug function that employs the JTAG (Joint Test Action Group) communication specifications. For details, see CHAPTER 34 ON-CHIP DEBUG FUNCTION.

3.3.1 Specifying operation mode

Specify the operation mode by using the FLMD0 and FLMD1 pins. In the normal mode, make sure that a low level is input to the FLMD0 pin when reset is released. In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash programmer if a flash programmer is connected, but it must be input from an external circuit in the self-programming mode. Operation When Reset Is Released FLMD0 FLMD1 Operation Mode After Reset L × Normal operation mode H L Flash memory programming mode H H Setting prohibited Remark L: Low-level input H: High-level input ×: Don’t care

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3.4 Address Space

3.4.1 CPU address space

For instruction addressing, up to a combined total of 16 MB of external memory area and internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear addr ess space (data space) is supported. The 4 GB address space, however, is viewed as 64 images of a 64 MB physical address space. This means that the same 64 MB physical address space is accessed regardless of the value of bits 31 to 26. Figure 3-1. Image on Address Space Program space Internal RAM area Use-prohibited area Use-prohibited area External memory area Internal ROM area (external memory area) Data space Image 63 Image 1 Image 0 Peripheral I/O area Internal RAM area Use-prohibited area External memory area Internal ROM area (external memory area) 16 MB 4 GB 64 MB 64 MB

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3.4.2 Wraparound of CPU address space

(1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. Therefore, the highest address of the program space, 03FFFFFFH, and t he lowest address, 00000000H, are contiguous addresses. That the highest address and the lo west address of the progra m space are contiguous in this way is called wraparound. Caution Because the 4 KB area of ad dresses 03FFF000H to 03FFFFFFH is an on-chip peripheral I/O area, instructions cannot be fetched fr om this area. Therefore, do no t execute an operation in which the result of a branch address calculation affects this area. Program space Program space (+) direction ( −) direction 00000001H 00000000H 03FFFFFFH 03FFFFFEH (2) Data space The result of an operand address calculation operation that exceeds 32 bits is ignored. Therefore, the highest address of the data space, FFFFFFFFH, and t he lowest address, 00000000H, are contiguous, and wraparound occurs at the boundary of these addresses. Data space Data space (+) direction ( −) direction 00000001H 00000000H FFFFFFFFH FFFFFFFEH

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3.4.3 Memory map

The areas shown below are reserved in the V850ES/JH3-E and V850ES/JJ3-E. Figure 3-2. Data Memory Map (Physical Addresses) CS3 CS2 CS0 CS1Note 2 (80 KB) Use prohibited External memory areaNote 1 (8 MB) Internal ROM areaNote 6 (1 MB) External memory area (1 MB) Internal RAM area (60 KB) On-chip peripheral I/O area (4 KB) External memory area (4 MB) USB function/ Ethernet used area (Refer to Figure3-3.) (2 MB) Use prohibitedNote 3 Programmable peripheral I/O areaNote 4 use prohibitedNote 5 00000000H 001FFFFFH 00200000H 003FFFFFH 00400000H 007FFFFFH 00800000H 00FFFFFFH 03FFFFFFH 03FFFFFFH 03FFF000H 03FFEFFFH 03FF0000H 03FEF000H 03FEEFFFH 03FEFFFFH 00000000H 00100000H 001FFFFFH 000FFFFFH 03FEC000H01000000H 03FEBFFFH 03FEC000H Notes 1. Use of this area is allowed only for the V850ES/JJ3-E. This area cannot be used in the V850ES/JH3-E. 2. CS1 is not provided as an external signal of the V850 ES/Jx3-E; it is used internally as a chip select signal for the USB and Ethernet. 3. Use of addresses 03FEF000H to 03FEFFFFH is prohibited becaus e they overlap an on-chip peripheral I/O area. 4. The programmable peripheral I/O area is seen as 256 MB areas in the 4 GB address space. 5. In on-chip CAN controller products, addre sses 03FEC000H to 03FEE FFFH are assigned to addresses 03FEC000H to 03FECBFFH as a program mable peripheral I/O area. In other products, use of this area is prohibited. 6. This area is used as an external memory area when data write access to this area is executed.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 71 of 1817 Sep 19, 2011 Figure 3-3. Memory Map of CS1 MACAD register MFF register EtherMAC register USB function area (512 KB) 02FFFFFFH 002F0004H 002F0003H 002F0000H 002FFFFFH 002E0400H 002E03FFH 002E0300H 002E02FFH 002E0200H 002E01FFH 002E0000H 002EFFFFH 002880000H 00287FFFFH 002900000H 0028FFFFFH 00280000H 0027FFFFH 00000000H 32 bits access space 16 bits access space 002C00000H 002BFFFFH Access-prohibited area Bridge-rerated register Access-prohibited area Access-prohibited area Access-prohibited area Data-only RAM (32 KB) Data-only RAM (32 KB)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 72 of 1817 Sep 19, 2011 Figure 3-4. Program Memory Map Internal RAM area (60 KB) Use prohibited (program fetch prohibited area) Use prohibited (program fetch prohibited area) External memory areaNote (8 MB) External memory area (1 MB) Internal ROM area (1 MB) 03FFFFFFH 03FFF000H 03FFEFFFH 01000000H 00FFFFFFH 03FF0000H 03FEFFFFH 00200000H 001FFFFFH 00100000H 000FFFFFH 00000000H Use prohibited (program fetch prohibited area) External memory area (4 MB) 01000000H 00FFFFFFH 01000000H 00FFFFFFH Note Use of this area is allowed only when using t he V850ES/JJ3-E. When using the V850ES/JH3-E, this area cannot be used.

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3.4.4 Areas

(1) Internal ROM area Up to 1 MB is reserved as an internal ROM area. (a) Internal ROM (256 KB) In the μPD70F3778, 256 KB are allocated to addresses 00000000H to 0003FFFFH in the following products. Accessing addresses 00040000H to 000FFFFFH is prohibited. Figure 3-5. Internal ROM Area (256 KB) Access-prohibited area Internal ROM (256 KB) 00040000H 0003FFFFH 00000000H 000FFFFFH (b) Internal ROM (384 KB) 384 KB are allocated to addresses 00000000H to 0005FFFFH in the following products. Accessing addresses 00060000H to 000FFFFFH is prohibited.

• μPD70F3779, 70F3781 Figure 3-6. Internal ROM Area (384 KB) Access-prohibited area Internal ROM (384 KB) 00060000H 0005FFFFH 00000000H 000FFFFFH

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 74 of 1817 Sep 19, 2011 (c) Internal ROM (512 KB) 512 KB are allocated to addresses 00000000H to 0007FFFFH in the following products. Accessing addresses 00080000H to 000FFFFFH is prohibited.

• μPD70F3780, 70F3782, 70F3783, 70F3784, 70F3785, 70F3786 Figure 3-7. Internal ROM Area (512 KB) Access-prohibited area Internal ROM (512 KB) 00080000H 0007FFFFH 00000000H 000FFFFFH (2) Internal RAM area Up to 60 KB are reserved as the internal RAM area. The V850ES/JH3-E and V850ES/JJ3-E include a data-only RAM in addition to the internal RAM. The RAM capacity of V850ES/JH3-E and V850ES/JJ3-E is as follows. Table 3-3 RAM area Generic Name Product Name Internal RAM Data-only RAM Total RAM μPD70F3778, 70F3779, 70F3780

60 KB 16 KB 76 KB V850ES/JH3-E

μPD70F3781, 70F3782, 70F3783

60 KB 64 KB 124 KB

μPD70F3784 60 KB 16 KB 76 KB V850ES/JJ3-E μPD70F3785, 70F3786 60 KB 64 KB 124 KB

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 76 of 1817 Sep 19, 2011 (c) Data-only RAM (64 KB) A data-only RAM of 64 KB is allocated to addresses 00280000H to 0028FFFFH in the following products.

• μPD70F3781, 70F3782, 70F3783, 70F3785, 70F3786 Figure 3-10. Data-Only RAM Area (64 KB) Logical address space Access-prohibited area Access-prohibited area 00290000H 0028FFFFH 00280000H 0027FFFFH Data-only RAM (64 KB)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 77 of 1817 Sep 19, 2011 (3) On-chip peripheral I/O area 4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Figure 3-11. On-Chip Peripheral I/O Area On-chip peripheral I/O area (4 KB) 03FFFFFFH 03FFF000H FFFFFFFFH FFFFF000H Physical address space Logical address space Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the on-chip peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area. Cautions 1. When a register is accessed in word unit s, a word area is accessed twice in halfword units in the order of lower area and higher area, with the lower 2 bits of the address ignored. 2. If a register that can be accessed in byte uni ts is accessed in halfword units, the higher 8 bits are undefined when the register is read, and data is written to the lower 8 bits. 3. Addresses not defined as registers are reser ved for future expansion. The operation is undefined and not guaranteed when these addresses are accessed. 4. The internal ROM/RAM area and on-chip peripheral I/O area are assigned to successive addresses. When accessing the internal ROM/RAM area by incrementing or decrementing addresses using a pointer operation or such, be careful not to acces s the on-chip peripheral I/O area by mistakenly extending over the internal ROM/RAM area boundary. (4) External memory area An area of 5 MB (00100000H to 001FFFFFH and 004 00000H to 007FFFFFH) in V850ES/JH3-E and 13 MB (00100000H to 001FFFFFH and 00400000H to 00FFFFFFH) in V850ES/JJ3-E is allocated as the external memory area. For details, see CHAPTER 5 BUS CONTROL FUNCTION.

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3.4.5 Recommended use of address space

The architecture of the V850ES/JH3-E an d V850ES/JJ3-E requires that a register that serves as a pointer be secured for address generation when operand data in the data spac e is accessed. The address stored in this pointer ±32 KB can be directly accessed by an instruction for operand data. Be cause the number of general- purpose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose registers as possi ble can be secured for variables, and the program size can be reduced. (1) Program space Of the 32 bits of the PC (program count er), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Regarding the program space, therefore, a 64 MB s pace of contiguous addresse s starting from 00000000H unconditionally corresponds to the memory map. To use the internal RAM area as the program space, access the 03FF0000H to 03FFEFFFH addresses. Caution If a branch instruction is at the upper limit of the internal RAM area, a prefetch operation (invalid fetch) straddling the on-chip peripheral I/O area does not occur. (2) Data space With the V850ES/JH3-E and V850ES/JJ3-E, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (b it 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 79 of 1817 Sep 19, 2011 (a) Application example of wraparound If R = r0 (zero register) is specified for the LD/ST di sp16 [R] instruction, a range of addresses 00000000H ±32 KB can be addressed by sign-extended disp16. All the re sources, including the internal hardware, can be addressed by one pointer. The zero register (r0) is a register fixed to 0 by ha rdware, and practically eliminates the need for registers dedicated to pointers. Example: μPD70F3786 Internal ROM area On-chip peripheral I/O area Internal RAM area 32 KB 4 KB 28 KB 0007FFFFH 00007FFFH 00000000H FFFFF000H FFFFEFFFH FFFF8000H FFFF3000H (R = )

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 80 of 1817 Sep 19, 2011 Figure 3-12. Recommended Memory Map Data spaceProgram space On-chip peripheral I/O On-chip peripheral I/O Internal RAM Internal RAM Internal ROM External memory Use prohibited External memory Use prohibited Internal RAM Program space 64 MB Internal ROM Internal ROM FFFFFFFFH FFFFF000H FFFFEFFFH FFFF0000H FFFEFFFFH 04000000H 03FFFFFFH 03FFF000H 03FFEFFFH 03FF0000H 03FEFFFFH 01000000H 00FFFFFFH 00080000H 0007FFFFH 00100000H 000FFFFFH 00000000H FFFFFFFFH FFFFF000H FFFFEFFFH FFFF3000H FFFF2FFFH FFFF0000H FFFEFFFFH 00100000H 000FFFFFH 00000000H Use prohibited Remarks 1. indicates the recommended area. 2. This figure is the recommended memory map of the μPD70F3786.

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3.4.6 Peripheral I/O registers

(1/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFF004H Port DL register PDL √ 0000H Note 1 FFFFF004H Port DL register L PDLL √ √ 00H Note 1 FFFFF005H Port DL register H PDLH √ √ 00H Note 1 FFFFF006H Port DH register Note 2 PDH Note 2 √ √ 00H Note 1 FFFFF008H Port CS register PCS √ √ 00H Note 1 FFFFF00AH Port CT register PCT √ √ 00H Note 1 FFFFF00CH Port CM register PCM √ √ 00H Note 1 FFFFF024H Port DL mode register PMDL √ FFFFH FFFFF024H Port DL mode register L PMDLL √ √ FFH FFFFF025H Port DL mode register H PMDLH √ √ FFH FFFFF026H Port DH mode register Note 2 PMDH Note 2 √ √ FFH FFFFF028H Port CS mode register PMCS √ √ FFH FFFFF02AH Port CT mode register PMCT √ √ FFH FFFFF02CH Port CM mode register PMCM √ √ FFH FFFFF044H Port DL mode control register PMCDL √ 0000H FFFFF044H Port DL mode control register L PMCDLL √ √ 00H FFFFF045H Port DL mode control register H PMCDLH √ √ 00H FFFFF046H Port DH mode control register Note 2 PMCDH Note 2 √ √ 00H FFFFF048H Port CS mode control register PMCCS √ √ 00H FFFFF04AH Port CT mode control register PMCCT √ √ 00H FFFFF04CH Port CM mode control register PMCCM √ √ 00H FFFFF056H Port DH function control register PFCDH √ √ 00H FFFFF064H Peripheral I/O area select control register Note 3 BPC Note 3 √ 0000H FFFFF066H Bus size configuration register BSC √ 5555H FFFFF06EH System wait control register VSWC √ 77H FFFFF080H DMA source address register 0L DSA0L √ Undefined FFFFF082H DMA source address register 0H DSA0H √ Undefined FFFFF084H DMA destination address register 0L DDA0L √ Undefined FFFFF086H DMA destination address register 0H DDA0H √ Undefined FFFFF088H DMA source address register 1L DSA1L √ Undefined FFFFF08AH DMA source address register 1H DSA1H √ Undefined FFFFF08CH DMA destination address register 1L DDA1L √ Undefined FFFFF08EH DMA destination address register 1H DDA1H √ Undefined FFFFF090H DMA source address register 2L DSA2L √ Undefined FFFFF092H DMA source address register 2H DSA2H √ Undefined FFFFF094H DMA destination address register 2L DDA2L √ Undefined FFFFF096H DMA destination address register 2H DDA2H R/W √ Undefined Notes 1 The output latch is 00H or 0000H. When these regist ers are in the input mode, the pin statuses are read. 2. V850ES/JJ3-E only 3. μPD70F3783, 70F3786 only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 82 of 1817 Sep 19, 2011 (2/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFF098H DMA source address register 3L DSA3L √ Undefined FFFFF09AH DMA source address register 3H DSA3H √ Undefined FFFFF09CH DMA destination address register 3L DDA3L √ Undefined FFFFF09EH DMA destination address register 3H DDA3H √ Undefined FFFFF0C0H DMA transfer count register 0 DBC0 √ Undefined FFFFF0C2H DMA transfer count register 1 DBC1 √ Undefined FFFFF0C4H DMA transfer count register 2 DBC2 √ Undefined FFFFF0C6H DMA transfer count register 3 DBC3 √ Undefined FFFFF0D0H DMA addressing control register 0 DADC0 √ 0000H FFFFF0D2H DMA addressing control register 1 DADC1 √ 0000H FFFFF0D4H DMA addressing control register 2 DADC2 √ 0000H FFFFF0D6H DMA addressing control register 3 DADC3 √ 0000H FFFFF0E0H DMA channel control register 0 DCHC0 √ √ 00H FFFFF0E2H DMA channel control register 1 DCHC1 √ √ 00H FFFFF0E4H DMA channel control register 2 DCHC2 √ √ 00H FFFFF0E6H DMA channel control register 3 DCHC3 √ √ 00H FFFFF100H Interrupt mask register 0 IMR0 √ FFFFH FFFFF100H Interrupt mask register 0L IMR0L √ √ FFH FFFFF101H Interrupt mask register 0H IMR0H √ √ FFH FFFFF102H Interrupt mask register 1 IMR1 √ FFFFH FFFFF102H Interrupt mask register 1L IMR1L √ √ FFH FFFFF103H Interrupt mask register 1H IMR1H √ √ FFH FFFFF104H Interrupt mask register 2 IMR2 √ FFFFH FFFFF104H Interrupt mask register 2L IMR2L √ √ FFH FFFFF105H Interrupt mask register 2H IMR2H √ √ FFH FFFFF106H Interrupt mask register 3 IMR3 √ FFFFH FFFFF106H Interrupt mask register 3L IMR3L √ √ FFH FFFFF107H Interrupt mask register 3H IMR3H √ √ FFH FFFFF108H Interrupt mask register 4 IMR4 √ FFFFH FFFFF108H Interrupt mask register 4L IMR4L √ √ FFH FFFFF109H Interrupt mask register 4H IMR4H √ √ FFH FFFFF10AH Interrupt mask register 5 IMR5 √ FFFFH FFFFF10AH Interrupt mask register 5L IMR5L √ √ FFH FFFFF10BH Interrupt mask register 5H IMR5H √ √ FFH FFFFF10CH Interrupt mask register 6 IMR6 √ FFFFH FFFFF10CH Interrupt mask register 6L IMR6L √ √ FFH FFFFF10DH Interrupt mask register 6H IMR6H √ √ FFH FFFFF10EH Interrupt mask register 7 IMR7 √ 001FH FFFFF10EH Interrupt mask register 7L IMR7L √ √ 1FH FFFFF110H Interrupt control register LVIIC √ √ 47H FFFFF112H Interrupt control register PIC00 R/W √ √ 47H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 83 of 1817 Sep 19, 2011 (3/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFF114H Interrupt control register PIC01 √ √ 47H FFFFF116H Interrupt control register PIC02 √ √ 47H FFFFF118H Interrupt control register PIC03 √ √ 47H FFFFF11AH Interrupt control register PIC04 √ √ 47H FFFFF11CH Interrupt control register PIC05 √ √ 47H FFFFF11EH Interrupt control register PIC06 √ √ 47H FFFFF120H Interrupt control register PIC07 √ √ 47H FFFFF122H Interrupt control register PIC08 √ √ 47H FFFFF124H Interrupt control register PIC09 √ √ 47H FFFFF126H Interrupt control register PIC10 √ √ 47H FFFFF128H Interrupt control register PIC11 √ √ 47H FFFFF12AH Interrupt control register PIC12 √ √ 47H FFFFF12CH Interrupt control register PIC13 √ √ 47H FFFFF12EH Interrupt control register PIC14 √ √ 47H FFFFF130H Interrupt control register PIC15 √ √ 47H FFFFF132H Interrupt control register PIC16 √ √ 47H FFFFF134H Interrupt control register PIC17 √ √ 47H FFFFF136H Interrupt control register PIC18 √ √ 47H FFFFF138H Interrupt control register PIC19 √ √ 47H FFFFF13AH Interrupt control register PIC20 √ √ 47H FFFFF13CH Interrupt control register PIC21 Note √ √ 47H FFFFF13EH Interrupt control register PIC22 Note √ √ 47H FFFFF140H Interrupt control register PIC23 Note √ √ 47H FFFFF142H Interrupt control register PIC24 Note √ √ 47H FFFFF144H Interrupt control register PIC25 Note √ √ 47H FFFFF146H Interrupt control register TAB0OVIC √ √ 47H FFFFF148H Interrupt control register TAB0CCIC0 √ √ 47H FFFFF14AH Interrupt control register TAB0CCIC1 √ √ 47H FFFFF14CH Interrupt control register TAB0CCIC2 √ √ 47H FFFFF14EH Interrupt control register TAB0CCIC3 √ √ 47H FFFFF150H Interrupt control register TAB1OVIC √ √ 47H FFFFF152H Interrupt control register TAB1CCIC0 √ √ 47H FFFFF154H Interrupt control register TAB1CCIC1 √ √ 47H FFFFF156H Interrupt control register TAB1CCIC2 √ √ 47H FFFFF158H Interrupt control register TAB1CCIC3 √ √ 47H FFFFF15AH Interrupt control register TT0OVIC √ √ 47H FFFFF15CH Interrupt control register TT0CCIC0 √ √ 47H FFFFF15EH Interrupt control register TT0CCIC1 √ √ 47H FFFFF160H Interrupt control register TT0IECIC √ √ 47H FFFFF162H Interrupt control register TAA0OVIC R/W √ √ 47H Note V850ES/JJ3-E only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 84 of 1817 Sep 19, 2011 (4/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFF164H Interrupt control register TAA0CCIC0 √ √ 47H FFFFF166H Interrupt control register TAA0CCIC1 √ √ 47H FFFFF168H Interrupt control register TAA1OVIC √ √ 47H FFFFF16AH Interrupt control register TAA1CCIC0 √ √ 47H FFFFF16CH Interrupt control register TAA1CCIC1 √ √ 47H FFFFF16EH Interrupt control register TAA2OVIC √ √ 47H FFFFF170H Interrupt control register TAA2CCIC0 √ √ 47H FFFFF172H Interrupt control register TAA2CCIC1 √ √ 47H FFFFF174H Interrupt control register TAA3OVIC √ √ 47H FFFFF176H Interrupt control register TAA3CCIC0 √ √ 47H FFFFF178H Interrupt control register TAA3CCIC1 √ √ 47H FFFFF17AH Interrupt control register TAA4OVIC √ √ 47H FFFFF17CH Interrupt control register TAA4CCIC0 √ √ 47H FFFFF17EH Interrupt control register TAA4CCIC1 √ √ 47H FFFFF180H Interrupt control register TAA5OVIC √ √ 47H FFFFF182H Interrupt control register TAA5CCIC0 √ √ 47H FFFFF184H Interrupt control register TAA5CCIC1 √ √ 47H FFFFF186H Interrupt control register TM0EQIC0 √ √ 47H FFFFF188H Interrupt control register TM1EQIC0 √ √ 47H FFFFF18AH Interrupt control register TM2EQIC0 √ √ 47H FFFFF18CH Interrupt control register TM3EQIC0 √ √ 47H FFFFF18EH Interrupt control register CE0TIC/UC4RIC √ √ 47H FFFFF190H Interrupt control register CE0TIOFIC/ UC4TIC √ √ 47H FFFFF192H Interrupt control register CE1TIC/IICIC3/ UC5RIC √ √ 47H FFFFF194H Interrupt control register CE1TIOFIC/ UC5TIC √ √ 47H FFFFF196H Interrupt control register CF0RIC/IICIC1 /UC3RIC √ √ 47H FFFFF198H Interrupt control register CF0TIC/UC3TIC √ √ 47H FFFFF19AH Interrupt control register CF1RIC/IICIC0 /UC1RIC √ √ 47H FFFFF19CH Interrupt control register CF1TIC/UC1RIC √ √ 47H FFFFF19EH Interrupt control register CF2RIC/UC0RIC √ √ 47H FFFFF1A0H Interrupt control register CF2TIC/UC0RIC √ √ 47H FFFFF1A2H Interrupt control register CF3RIC/ UB1TIRIC √ √ 47H FFFFF1A4H Interrupt control register CF3TIC/ UB1TITIC √ √ 47H FFFFF1A6H Interrupt control register UB1TIFIC R/W √ √ 47H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 85 of 1817 Sep 19, 2011 (5/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFF1A8H Interrupt control register UB1TIREIC √ √ 47H FFFFF1AAH Interrupt control register UB1TITOIC √ √ 47H FFFFF1ACH Interrupt control register CF4RIC/ UB0TIRIC √ √ 47H FFFFF1AEH Interrupt control register CF4TIC/ UB0TITIC √ √ 47H FFFFF1B0H Interrupt control register UB0TIFIC √ √ 47H FFFFF1B2H Interrupt control register UB0TIREIC √ √ 47H FFFFF1B4H Interrupt control register UB0TITOIC √ √ 47H FFFFF1B6H Interrupt control register CF5RIC/UC6RIC Note 1 √ √ 47H FFFFF1B8H Interrupt control register CF5TIC/UC6TIC Note 1 √ √ 47H FFFFF1BAH Interrupt control register CF6RIC/UC7RIC Note 1 √ √ 47H FFFFF1BCH Interrupt control register CF6TIC/UC7TIC Note 1 √ √ 47H FFFFF1BEH Interrupt control register IICIC2/UC2RIC √ √ 47H FFFFF1C0H Interrupt control register UC2TIC √ √ 47H FFFFF1C2H Interrupt control register IICIC4 Note 1 √ √ 47H FFFFF1C4H Interrupt control register ADIC √ √ 47H FFFFF1C6H Interrupt control register DMAIC0 √ √ 47H FFFFF1C8H Interrupt control register DMAIC1 √ √ 47H FFFFF1CAH Interrupt control register DMAIC2 √ √ 47H FFFFF1CCH Interrupt control register DMAIC3 √ √ 47H FFFFF1CEH Interrupt control register KRIC √ √ 47H FFFFF1D0H Interrupt control register RTC0IC √ √ 47H FFFFF1D2H Interrupt control register RTC1IC √ √ 47H FFFFF1D4H Interrupt control register RTC2IC √ √ 47H FFFFF1D6H Interrupt control register UFIC0 √ √ 47H FFFFF1D8H Interrupt control register UFIC1 √ √ 47H FFFFF1ECH Interrupt control register ERRIC0 Note 2 √ √ 47H FFFFF1EEH Interrupt control register WUPIC0 Note 2 √ √ 47H FFFFF1F0H Interrupt control register RECIC0 Note 2 √ √ 47H FFFFF1F2H Interrupt control register TRXIC0 Note 2 R/W √ √ 47H FFFFF1FAH In-service priority register ISPR R √ √ 00H FFFFF1FCH Command register PRCMD W √ Undefined FFFFF1FEH Power save control register PSC √ √ 00H FFFFF200H A/D converter mode register 0 ADA0M0 √ √ 00H FFFFF201H A/D converter mode register 1 ADA0M1 √ √ 00H FFFFF202H A/D converter channel specification register ADA0S √ √ 00H FFFFF203H A/D converter mode register 2 ADA0M2 √ √ 00H FFFFF204H Power-fail compare mode register ADA0PFM √ √ 00H FFFFF205H Power-fail compare threshold value register ADA0PFT R/W √ √ 00H Notes 1 V850ES/JJ3-E only 2. μPD70F3783, 70F3786 only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 86 of 1817 Sep 19, 2011 (6/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFF210H A/D conversion result register 0 ADA0CR0 √ Undefined FFFFF211H A/D conversion result register 0H ADA0CR0H √ Undefined FFFFF212H A/D conversion result register 1 ADA0CR1 √ Undefined FFFFF213H A/D conversion result register 1H ADA0CR1H √ Undefined FFFFF214H A/D conversion result register 2 ADA0CR2 √ Undefined FFFFF215H A/D conversion result register 2H ADA0CR2H √ Undefined FFFFF216H A/D conversion result register 3 ADA0CR3 √ Undefined FFFFF217H A/D conversion result register 3H ADA0CR3H √ Undefined FFFFF218H A/D conversion result register 4 ADA0CR4 √ Undefined FFFFF219H A/D conversion result register 4H ADA0CR4H √ Undefined FFFFF21AH A/D conversion result register 5 ADA0CR5 √ Undefined FFFFF21BH A/D conversion result register 5H ADA0CR5H √ Undefined FFFFF21CH A/D conversion result register 6 ADA0CR6 √ Undefined FFFFF21DH A/D conversion result register 6H ADA0CR6H √ Undefined FFFFF21EH A/D conversion result register 7 ADA0CR7 √ Undefined FFFFF21FH A/D conversion result register 7H ADA0CR7H √ Undefined FFFFF220H A/D conversion result register 8 ADA0CR8 √ Undefined FFFFF221H A/D conversion result register 8H ADA0CR8H √ Undefined FFFFF222H A/D conversion result register 9 ADA0CR9 √ Undefined FFFFF223H A/D conversion result register 9H ADA0CR9H √ Undefined FFFFF224H A/D conversion result register 10 ADA0CR10 Note 1 √ Undefined FFFFF225H A/D conversion result register 10H ADA0CR10H Note 1 √ Undefined FFFFF226H A/D conversion result register 11 ADA0CR11 Note 1 √ Undefined FFFFF227H A/D conversion result register 11H ADA0CR11H Note 1 √ Undefined FFFFF300H Key return mode register KRM √ √ 00H FFFFF308H Selector operation control register 0 SELCNT0 √ √ 00H FFFFF310H CRC input register CRCIN √ 00H FFFFF312H CRC data register CRCD √ 0000H FFFFF320H Prescaler mode register 1 PRSM1 √ √ 00H FFFFF321H Prescaler compare register 1 PRSCM1 √ 00H FFFFF324H Prescaler mode register 2 PRSM2 √ √ 00H FFFFF325H Prescaler compare register 2 PRSCM2 √ 00H FFFFF328H Prescaler mode register 3 PRSM3 √ √ 00H FFFFF329H Prescaler compare register 3 PRSCM3 √ 00H FFFFF32CH Prescaler mode register 4 PRSM4 √ √ 00H FFFFF32DH Prescaler compare register 4 PRSCM4 √ 00H FFFFF340H IIC division clock select register 0 OCKS0 √ 00H FFFFF344H IIC division clock select register 1 OCKS1 √ 00H FFFFF348H IIC division clock select register 2 OCKS2 R √ 00H FFFFF400H Port 0 register P0 √ √ 00H Note 2 FFFFF404H Port 2 register P2 √ √ 00H Note 2 FFFFF406H Port 3 register P3 R/W √ √ 00H Note 2 Notes 1 V850ES/JJ3-E only 2. The output latch is 00H or 0000H. When these registers are in the input mode, the pin statuses are read.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 87 of 1817 Sep 19, 2011 (7/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFF408H Port 4 register P4 √ 0000H Note FFFFF408H Port 4 register L P4L √ √ 00H Note FFFFF409H Port 4 register H P4H √ √ 00H Note FFFFF40AH Port 5 register P5 √ 0000H Note FFFFF40AH Port 5 register L P5L √ √ 00H Note FFFFF40BH Port 5 register H P5H √ √ 00H Note FFFFF40EH Port 7 register P7 √ 0000H Note FFFFF40EH Port 7 register L P7L √ √ 00H Note FFFFF40FH Port 7 register H P7H √ √ 00H Note FFFFF412H Port 9 register P9 √ 0000H Note FFFFF412H Port 9 register L P9L √ √ 00H Note FFFFF413H Port 9 register H P9H √ √ 00H Note FFFFF420H Port 0 mode register PM0 √ √ FFH FFFFF424H Port 2 mode register PM2 √ √ FFH FFFFF426H Port 3 mode register PM3 √ √ FFH FFFFF428H Port 4 mode register PM4 √ FFFFH FFFFF428H Port 4 mode register L PM4L √ √ FFH FFFFF429H Port 4 mode register H PM4H √ √ FFH FFFFF42AH Port 5 mode register PM5 √ FFFFH FFFFF42AH Port 5 mode register L PM5L √ √ FFH FFFFF42BH Port 5 mode register H PM5H √ √ FFH FFFFF42EH Port 7 mode register L PM7L √ √ FFH FFFFF42FH Port 7 mode register H PM7H √ √ FFH FFFFF432H Port 9 mode register PM9 √ FFFFH FFFFF432H Port 9 mode register L PM9L √ √ FFH FFFFF433H Port 9 mode register H PM9H √ √ FFH FFFFF440H Port 0 mode control register PMC0 √ √ 00H FFFFF444H Port 2 mode control register PMC2 √ √ 00H FFFFF446H Port 3 mode control register PMC3 √ √ 00H FFFFF448H Port 4 mode control register PMC4 √ 0000H FFFFF448H Port 4 mode control register L PMC4L √ √ 00H FFFFF449H Port 4 mode control register H PMC4H √ √ 00H FFFFF44AH Port 5 mode control register PMC5 √ 0000H FFFFF44AH Port 5 mode control register L PMC5L √ √ 00H FFFFF44BH Port 5 mode control register H PMC5H √ √ 00H FFFFF452H Port 9 mode control register PMC9 √ 0000H FFFFF452H Port 9 mode control register L PMC9L √ √ 00H FFFFF453H Port 9 mode control register H PMC9H √ √ 00H FFFFF460H Port 0 function control register PFC0 √ √ 00H FFFFF464H Port 2 function control register PFC2 √ √ 00H FFFFF466H Port 3 function control register PFC3 R/W √ √ 00H Note The output latch is 00H or 0000H. When these registers are input, the pin statuses are read.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 88 of 1817 Sep 19, 2011 (8/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFF468H Port 4 function control register PFC4 √ 0000H FFFFF468H Port 4 function control register L PFC4L √ √ 00H FFFFF469H Port 4 function control register H PFC4H √ √ 00H FFFFF46AH Port 5 function control register PFC5 √ 0000H FFFFF46AH Port 5 function control register L PFC5L √ √ 00H FFFFF46BH Port 5 function control register H PFC5H √ √ 00H FFFFF472H Port 9 function control register PFC9 √ 0000H FFFFF472H Port 9 function control register L PFC9L √ √ 00H FFFFF473H Port 9 function control register H PFC9H √ √ 00H FFFFF484H Data wait control register 0 DWC0 √ 7777H FFFFF488H Address wait control register AWC √ FFFFH FFFFF48AH Bus cycle control register BCC √ AAAAH FFFFF540H TAB0 control register 0 TAB0CTL0 √ √ 00H FFFFF541H TAB0 control register 1 TAB0CTL1 √ √ 00H FFFFF542H TAB0 I/O control register 0 TAB0IOC0 √ √ 00H FFFFF543H TAB0 I/O control register 1 TAB0IOC1 √ √ 00H FFFFF544H TAB0 I/O control register 2 TAB0IOC2 √ √ 00H FFFFF545H TAB0 option register 0 TAB0OPT0 √ √ 00H FFFFF546H TAB0 capture/compare register 0 TAB0CCR0 √ 0000H FFFFF548H TAB0 capture/compare register 1 TAB0CCR1 √ 0000H FFFFF54AH TAB0 capture/compare register 2 TAB0CCR2 √ 0000H FFFFF54CH TAB0 capture/compare register 3 TAB0CCR3 R/W √ 0000H FFFFF54EH TAB0 counter read buffer register TAB0CNT R √ 0000H FFFFF550H TAB0 I/O control register 4 TAB0IOC4 √ √ 00H FFFFF560H TAB1 control register 0 TAB1CTL0 √ √ 00H FFFFF561H TAB1 control register 1 TAB1CTL1 √ √ 00H FFFFF562H TAB1 I/O control register 0 TAB1IOC0 √ √ 00H FFFFF563H TAB1 I/O control register 1 TAB1IOC1 √ √ 00H FFFFF564H TAB1 I/O control register 2 TAB1IOC2 √ √ 00H FFFFF565H TAB1 option register 0 TAB1OPT0 √ √ 00H FFFFF566H TAB1 capture/compare register 0 TAB1CCR0 √ 0000H FFFFF568H TAB1 capture/compare register 1 TAB1CCR1 √ 0000H FFFFF56AH TAB1 capture/compare register 2 TAB1CCR2 √ 0000H FFFFF56CH TAB1 capture/compare register 3 TAB1CCR3 R/W √ 0000H FFFFF56EH TAB1 counter read buffer register TAB1CNT R √ 0000H FFFFF570H TAB1 I/O control register 4 TAB1IOC4 √ √ 00H FFFFF580H TAB1 option register 1 TAB1OPT1 √ √ 00H FFFFF581H TAB1 option register 2 TAB1OPT2 √ √ 00H FFFFF582H TAB1 I/O control register 3 TAB1IOC3 √ √ A8H FFFFF584H TAB1 dead time compare register 1 TAB1DTC √ 0000H FFFFF590H High impedance output control register 0 HZA0CTL0 R/W √ √ 00H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 89 of 1817 Sep 19, 2011 (9/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFF591H High impedance output control register 1 HZACTL1 √ √ 00H FFFFF5A0H TAA0 noise elimination control register TANFC0 √ √ 00H FFFFF5A2H TAA1 noise elimination control register TANFC1 √ √ 00H FFFFF5A4H TAA2 noise elimination control register TANFC2 √ √ 00H FFFFF5A6H TAA3 noise elimination control register TANFC3 √ √ 00H FFFFF5A8H TAA4 noise elimination control register TANFC4 √ √ 00H FFFFF5AAH TAA5 noise elimination control register TANFC5 √ √ 00H FFFFF5ACH TMT noise elimination control register TTNFC √ √ 00H FFFFF5B0H Noise elimination control register INTNFC √ √ 00H FFFFF600H TMT0 control register 0 TT0CTL0 √ √ 00H FFFFF601H TMT0 control register 1 TT0CTL1 √ √ 00H FFFFF602H TMT0 control register 2 TT0CTL2 √ √ 00H FFFFF603H TMT0 I/O control register 0 TT0IOC0 √ √ 00H FFFFF604H TMT0 I/O control register 1 TT0IOC1 √ √ 00H FFFFF605H TMT0 I/O control register 2 TT0IOC2 √ √ 00H FFFFF606H TMT0 I/O control register 3 TT0IOC3 √ √ 00H FFFFF607H TMT0 option register 0 TT0OPT0 √ √ 00H FFFFF608H TMT0 option register 1 TT0OPT1 √ √ 00H FFFFF60AH TMT0 capture/compare register 0 TT0CCR0 √ 0000H FFFFF60CH TMT0 capture/compare register 1 TT0CCR1 R/W √ 0000H FFFFF60EH TMT0 counter read buffer register TT0CNT R √ 0000H FFFFF610H TMT0 counter write register TT0TCW √ 0000H FFFFF630H TAA0 control register 0 TAA0CTL0 √ √ 00H FFFFF631H TAA0 control register 1 TAA0CTL1 √ √ 00H FFFFF632H TAA0 I/O control register 0 TAA0IOC0 √ √ 00H FFFFF633H TAA0 I/O control register 1 TAA0IOC1 √ √ 00H FFFFF634H TAA0 I/O control register 2 TAA0IOC2 √ √ 00H FFFFF635H TAA0 option register 0 TAA0OPT0 √ √ 00H FFFFF636H TAA0 capture/compare register 0 TAA0CCR0 √ 0000H FFFFF638H TAA0 capture/compare register 1 TAA0CCR1 R/W √ 0000H FFFFF63AH TAA0 counter read buffer register TAA0CNT R √ 0000H FFFFF63CH TAA0 I/O control register 4 TAA0IOC4 √ √ 00H FFFFF63DH TAA0 option register 1 TAA0OPT1 √ √ 00H FFFFF640H TAA1 control register 0 TAA1CTL0 √ √ 00H FFFFF641H TAA1 control register 1 TAA1CTL1 √ √ 00H FFFFF642H TAA1 I/O control register 0 TAA1IOC0 √ √ 00H FFFFF643H TAA1 I/O control register 1 TAA1IOC1 √ √ 00H FFFFF644H TAA1 I/O control register 2 TAA1IOC2 √ √ 00H FFFFF645H TAA1 option register 0 TAA1OPT0 √ √ 00H FFFFF646H TAA1 capture/compare register 0 TAA1CCR0 √ 0000H FFFFF648H TAA1 capture/compare register 1 TAA1CCR1 R/W √ 0000H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 90 of 1817 Sep 19, 2011 (10/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFF64AH TAA1 counter read buffer register TAA1CNT R √ 0000H FFFFF64CH TAA1 I/O control register 4 TAA1IOC4 √ √ 00H FFFFF650H TAA2 control register 0 TAA2CTL0 √ √ 00H FFFFF651H TAA2 control register 1 TAA2CTL1 √ √ 00H FFFFF652H TAA2 I/O control register 0 TAA2IOC0 √ √ 00H FFFFF653H TAA2 I/O control register 1 TAA2IOC1 √ √ 00H FFFFF654H TAA2 I/O control register 2 TAA2IOC2 √ √ 00H FFFFF655H TAA2 option register 0 TAA2OPT0 √ √ 00H FFFFF656H TAA2 capture/compare register 0 TAA2CCR0 √ 0000H FFFFF658H TAA2 capture/compare register 1 TAA2CCR1 R/W √ 0000H FFFFF65AH TAA2 counter read buffer register TAA2CNT R √ 0000H FFFFF65CH TAA2 I/O control register 4 TAA2IOC4 √ √ 00H FFFFF65DH TAA2 option register 1 TAA2OPT1 √ √ 00H FFFFF660H TAA3 control register 0 TAA3CTL0 √ √ 00H FFFFF661H TAA3 control register 1 TAA3CTL1 √ √ 00H FFFFF662H TAA3 I/O control register 0 TAA3IOC0 √ √ 00H FFFFF663H TAA3 I/O control register 1 TAA3IOC1 √ √ 00H FFFFF664H TAA3 I/O control register 2 TAA3IOC2 √ √ 00H FFFFF665H TAA3 option register 0 TAA3OPT0 √ √ 00H FFFFF666H TAA3 capture/compare register 0 TAA3CCR0 √ 0000H FFFFF668H TAA3 capture/compare register 1 TAA3CCR1 R/W √ 0000H FFFFF66AH TAA3 counter read buffer register TAA3CNT R √ 0000H FFFFF66CH TAA3 I/O control register4 TAA3IOC4 √ √ 00H FFFFF670H TAA4 control register 0 TAA4CTL0 √ √ 00H FFFFF671H TAA4 control register 1 TAA4CTL1 √ √ 00H FFFFF672H TAA4 I/O control register 0 TAA4IOC0 √ √ 00H FFFFF673H TAA4 I/O control register 1 TAA4IOC1 √ √ 00H FFFFF674H TAA4 I/O control register 2 TAA4IOC2 √ √ 00H FFFFF675H TAA4 option register 0 TAA4OPT0 √ √ 00H FFFFF676H TAA4 capture compare register 0 TAA4CCR0 √ 0000H FFFFF678H TAA4 capture compare register 1 TAA4CCR1 R/W √ 0000H FFFFF67AH TAA4 counter read buffer register TAA4CNT R √ 0000H FFFFF67CH TAA4 I/O control register 4 TAA4IOC4 √ √ 00H FFFFF680H TAA5 control register 0 TAA5CTL0 √ √ 00H FFFFF681H TAA5 control register 1 TAA5CTL1 √ √ 00H FFFFF682H TAA5 I/O control register 0 TAA5IOC0 √ √ 00H FFFFF683H TAA5 I/O control register 1 TAA5IOC1 √ √ 00H FFFFF684H TAA5 I/O control register 2 TAA5IOC2 √ √ 00H FFFFF685H TAA5 option register 0 TAA5OPT0 √ √ 00H FFFFF686H TAA5 capture/compare register 0 TAA5CCR0 √ 0000H FFFFF688H TAA5 capture/compare register 1 TAA5CCR1 R/W √ 0000H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 91 of 1817 Sep 19, 2011 (11/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFF68AH TAA5 counter read buffer register TAA5CNT R √ 0000H FFFFF68CH TAA5 I/O control register 4 TAA5IOC4 √ √ 00H FFFFF6C0H Oscillation stabilization time select register OSTS √ 06H FFFFF6C1H PLL lockup time specification register PLLS √ 03H FFFFF6D0H Watchdog timer mode register 2 WDTM2 √ 67H FFFFF6D1H Watchdog timer enable register WDTE √ 9AH FFFFF6E0H Real-time output buffer register 0L RTBL0 √ √ 00H FFFFF6E2H Real-time output buffer register 0H RTBH0 √ √ 00H FFFFF6E4H Real-time output port mode register 0 RTPM0 √ √ 00H FFFFF6E5H Real-time output port control register 0 RTPC0 √ √ 00H FFFFF700H Port 0 function control expansion register PFCE0 √ √ 00H FFFFF704H Port 2 function control expansion register PFCE2 √ √ 00H FFFFF706H Port 3 function control expansion register PFCE3 √ √ 00H FFFFF708H Port 4 function control expansion register L PFCE4L √ √ 00H FFFFF70AH Port 5 function control expansion register L PFCE5L √ √ 00H FFFFF712H Port 9 function control expansion register PFCE9 √ 0000H FFFFF712H Port 9 function control expansion register L PFCE9L √ √ 00H FFFFF713H Port 9 function control expansion register H PFCE9H √ √ 00H FFFFF726H Port DH function control expansion register PFCEDH √ √ 00H FFFFF802H System status register SYS √ √ 00H FFFFF80CH Internal oscillation mode register RCM √ √ 00H FFFFF810H DMA trigger factor register 0 DTFR0 √ √ 00H FFFFF812H DMA trigger factor register 1 DTFR1 √ √ 00H FFFFF814H DMA trigger factor register 2 DTFR2 √ √ 00H FFFFF816H DMA trigger factor register 3 DTFR3 √ √ 00H FFFFF820H Power save mode register PSMR √ √ 00H FFFFF822H Clock control register CKC R/W √ √ 0AH FFFFF824H Lock register LOCKR R √ √ 00H FFFFF828H Processor clock control register PCC √ √ 03H FFFFF82CH PLL control register PLLCTL R/W √ √ 01H FFFFF82EH CPU operation clock status register CCLS R √ √ 00H FFFFF870H Clock monitor mode register CLM √ √ 00H FFFFF888H Reset source flag register RESF √ √ 00H FFFFF890H Low-voltage detection register LVIM √ √ 00H FFFFF892H Internal RAM data status register RAMS √ √ 01H FFFFF8B0H Prescaler mode register 0 PRSM0 √ √ 00H FFFFF8B1H Prescaler compare register 0 PRSCM0 √ 00H FFFFF9FCH On-chip debug mode register OCDM √ √ 01H FFFFFA00H UARTC0 control register 0 UC0CTL0 √ √ 10H FFFFFA01H UARTC0 control register 1 UC0CTL1 √ 00H FFFFFA02H UARTC0 control register 2 UC0CTL2 R/W √ FFH

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 92 of 1817 Sep 19, 2011 (12/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFFA03H UARTC0 option control register 0 UC0OPT0 √ √ 14H FFFFFA04H UARTC0 status register UC0STR R/W √ √ 00H FFFFFA06H UARTC0 receive data register UC0RX R √ 01FFH FFFFFA06H UARTC0 receive data register L UC0RXL √ FFH FFFFFA08H UARTC0 transmit data register UC0TX √ 01FFH FFFFFA08H UARTC0 transmit data register L UC0TXL √ FFH FFFFFA0AH UARTC0 option control register 1 UC0OPT1 √ √ 00H FFFFFA10H UARTC1 control register 0 UC1CTL0 √ √ 10H FFFFFA11H UARTC1 control register 1 UC1CTL1 √ 00H FFFFFA12H UARTC1 control register 2 UC1CTL2 √ FFH FFFFFA13H UARTC1 option control register 0 UC1OPT0 √ √ 14H FFFFFA14H UARTC1 status register UC1STR R/W √ √ 00H FFFFFA16H UARTC1 receive data register UC1RX R √ 01FFH FFFFFA16H UARTC1 receive data register L UC1RXL √ FFH FFFFFA18H UARTC1 transmit data register UC1TX √ 01FFH FFFFFA18H UARTC1 transmit data register L UC1TXL √ FFH FFFFFA1AH UARTC1 option control register 1 UC1OPT1 √ √ 00H FFFFFA20H UARTC2 control register 0 UC2CTL0 √ √ 10H FFFFFA21H UARTC2 control register 1 UC2CTL1 √ 00H FFFFFA22H UARTC2 control register 2 UC2CTL2 √ FFH FFFFFA23H UARTC2 option control register 0 UC2OPT0 √ √ 14H FFFFFA24H UARTC2 status register UC2STR R/W √ √ 00H FFFFFA26H UARTC2 receive data register UC2RX √ 01FFH FFFFFA26H UARTC2 receive data register L UC2RXL R √ FFH FFFFFA28H UARTC2 transmit data register UC2TX √ 01FFH FFFFFA28H UARTC2 transmit data register L UC2TXL √ FFH FFFFFA2AH UARTC2 option control register 1 UC2OPT1 √ √ 00H FFFFFA30H UARTC3 control register 0 UC3CTL0 √ √ 10H FFFFFA31H UARTC3 control register 1 UC3CTL1 √ 00H FFFFFA32H UARTC3 control register 2 UC3CTL2 √ FFH FFFFFA33H UARTC3 option control register 0 UC3OPT0 √ √ 14H FFFFFA34H UARTC3 status register UC3STR R/W √ √ 00H FFFFFA36H UARTC3 receive data register UC3RX √ 01FFH FFFFFA36H UARTC3 receive data register L UC3RXL R √ FFH FFFFFA38H UARTC3 transmit data register UC3TX √ 01FFH FFFFFA38H UARTC3 transmit data register L UC3TXL √ FFH FFFFFA3AH UARTC3 option control register 1 UC3OPT1 √ √ 00H FFFFFA40H UARTC4 control register 0 UC4CTL0 √ √ 10H FFFFFA41H UARTC4 control register 1 UC4CTL1 √ 00H FFFFFA42H UARTC4 control register 2 UC4CTL2 √ FFH FFFFFA43H UARTC4 option control register 0 UC4OPT0 R/W √ √ 14H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 93 of 1817 Sep 19, 2011 (13/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFFA44H UARTC4 status register UC4STR R/W √ √ 00H FFFFFA46H UARTC4 receive data register UC4RX √ 01FFH FFFFFA46H UARTC4 receive data register L UC4RXL R √ FFH FFFFFA48H UARTC4 transmit data register UC4TX √ 01FFH FFFFFA48H UARTC4 transmit data register L UC4TXL √ FFH FFFFFA4AH UARTC4 option control register 1 UC4OPT1 √ √ 00H FFFFFA50H UARTC5 control register 0 UC5CTL0 √ √ 10H FFFFFA51H UARTC5 control register 1 UC5CTL1 √ 00H FFFFFA52H UARTC5 control register 2 UC5CTL2 √ FFH FFFFFA53H UARTC5 option control register 0 UC5OPT0 √ √ 14H FFFFFA54H UARTC5 status register UC5STR R/W √ √ 00H FFFFFA56H UARTC5 receive data register UC5RX √ 01FFH FFFFFA56H UARTC5 receive data register L UC5RXL R √ FFH FFFFFA58H UARTC5 transmit data register UC5TX √ 01FFH FFFFFA58H UARTC5 transmit data register L UC5TXL √ FFH FFFFFA5AH UARTC6 option control register 1 UC6OPT1 Note √ √ 00H FFFFFA60H UARTC6 control register 0 UC6CTL0 Note √ √ 10H FFFFFA61H UARTC6 control register 1 UC6CTL1 Note √ 00H FFFFFA62H UARTC6 control register 2 UC6CTL2 Note √ FFH FFFFFA63H UARTC6 option control register 0 UC6OPT0 Note √ √ 14H FFFFFA64H UARTC6 status register UC6STR Note R/W √ √ 00H FFFFFA66H UARTC6 receive data register UC6RX Note √ 01FFH FFFFFA66H UARTC6 receive data register L UC6RXL Note R √ FFH FFFFFA68H UARTC6 transmit data register UC6TX Note √ 01FFH FFFFFA68H UARTC6 transmit data register L UC6TXL Note √ FFH FFFFFA6AH UARTC6 option control register 1 UC6OPT1 Note √ √ 00H FFFFFA70H UARTC7 control register 0 UC7CTL0 Note √ √ 10H FFFFFA71H UARTC7 control register 1 UC7CTL1 Note √ 00H FFFFFA72H UARTC7 control register 2 UC7CTL2 Note √ FFH FFFFFA73H UARTC7 option register UC7OPT0 Note √ √ 14H FFFFFA74H UARTC7 status register UC7STR Note R/W √ √ 00H FFFFFA76H UARTC7 receive data register UC7RX Note √ 01FFH FFFFFA76H UARTC7 receive data register L UC7RXL Note R √ FFH FFFFFA78H UARTC7 transmit data register UC7TX Note √ 01FFH FFFFFA78H UARTC7 transmit data register L UC7TXL Note √ FFH FFFFFA7AH UARTC7 option control register 1 UC7OPT1 √ √ 00H FFFFFA80H TMM0 control register 0 TM0CTL0 √ √ 00H FFFFFA84H TMM0 compare register 0 TM0CMP0 √ 0000H FFFFFA90H TMM1 control register 0 TM1CTL0 √ √ 00H FFFFFA94H TMM1 compare register 0 TM1CMP0 √ 0000H FFFFFAA0H TMM2 control register 0 TM2CTL0 R/W √ √ 00H Note V850ES/JJ3-E only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 94 of 1817 Sep 19, 2011 (14/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFFAA4H TMM2 compare register 0 TM2CMP0 √ 0000H FFFFFAB0H TMM3 control register 0 TM3CTL0 √ √ 00H FFFFFAB4H TMM3 compare register 0 TM3CMP0 R/W √ 0000H FFFFFAD0H Sub-count register RC1SUBC R √ 0000H FFFFFAD2H Second count register RC1SEC √ 00H FFFFFAD3H Minute count register RC1MIN √ 00H FFFFFAD4H Hour count register RC1HOUR √ 12H FFFFFAD5H Week count register RC1WEEK √ 00H FFFFFAD6H Day count register RC1DAY √ 01H FFFFFAD7H Month count register RC1MONTH √ 01H FFFFFAD8H Y ear count register RC1YEAR √ 00H FFFFFAD9H Time error correction register RC1SUBU √ √ 00H FFFFFADAH Alarm minute set register RC1ALM √ 00H FFFFFADBH Alarm time set register RC1ALH √ 12H FFFFFADCH Alarm week set register RC1ALW √ √ 00H FFFFFADDH RTC control register 0 RC1CC0 √ √ 00H FFFFFADEH RTC control register 1 RC1CC1 √ √ 00H FFFFFADFH RTC control register 2 RC1CC2 √ √ 00H FFFFFAE0H RTC control register 3 RC1CC3 √ √ 00H FFFFFB00H CSIE0 control register 0 CE0CTL0 √ √ 00H FFFFFB01H CSIE0 control register 1 CE0CTL1 R/W √ √ 07H FFFFFB02H CSIE0 receive data register 0 CE0RX0 √ 0000H FFFFFB02H CSIE0 receive data register 0L CE0RXL0 √ 00H FFFFFB03H CSIE0 receive data register 0H CE0RXH0 R √ 00H FFFFFB06H CSIE0 transmit data register CE0TX0 √ 0000H FFFFFB06H CSIE0 transmit data register L CE0TXL0 √ 00H FFFFFB07H CSIE0 transmit data register H CE0TXH0 √ 00H FFFFFB08H CSIE0 status register CE0STR √ √ 20H FFFFFB09H CSIE0 control register 2 CE0CTL2 √ √ 00H FFFFFB0CH CSIE0 control register 3 CE0CTL3 √ √ 00H FFFFFB40H CSIE1 control register 0 CE1CTL0 √ √ 00H FFFFFB41H CSIE1 control register 1 CE1CTL1 R/W √ √ 07H FFFFFB42H CSIE1 receive data register CE1RX0 √ 0000H FFFFFB42H CSIE1 receive data register L CE1RXL0 √ 00H FFFFFB43H CSIE1 receive data register H CE1RXH0 R √ 00H FFFFFB46H CSIE1 transmit data register CE1TX0 √ 0000H FFFFFB46H CSIE1 transmit data register L CE1TXL0 √ 00H FFFFFB47H CSIE1 transmit data register H CE1TXH0 √ 00H FFFFFB48H CSIE1 status register CE1STR √ √ 20H FFFFFB49H CSIE1 control register 2 CE1CTL2 √ √ 00H FFFFFB4CH CSIE1 control register 3 CE1CTL3 R/W √ √ 00H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 95 of 1817 Sep 19, 2011 (15/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFFB80H UARTB0 control register 0 UB0CTL0 √ √ 10H FFFFFB82H UARTB0 control register 2 UB0CTL2 √ FFFFH FFFFFB84H UARTB0 status register UB0STR R/W √ √ 00H FFFFFB86H UARTB0 receive data register AP UB0RXAP √ 00FFH FFFFFB86H UARTB0 receive data register UB0RX R √ FFH FFFFFB88H UARTB0 transmit data register UB0TX √ FFH FFFFFB8AH UARTB0 FIFO control register 0 UB0FIC0 √ √ 00H FFFFFB8BH UARTB0 FIFO control register 1 UB0FIC1 √ √ 00H FFFFFB8CH UARTB0 FIFO control register 2 UB0FIC2 √ 0000H FFFFFB8CH UARTB0 FIFO control register 2L UB0FIC2L √ 00H FFFFFB8DH UARTB0 FIFO control register 2H UB0FIC2H R/W √ 00H FFFFFB8EH UARTB0 status register 0 UB0FIS0 √ 00H FFFFFB8FH UARTB0 status register 1 UB0FIS1 R √ 10H FFFFFBA0H UARTB1 control register 0 UB1CTL0 √ √ 10H FFFFFBA2H UARTB1 control register 2 UB1CTL2 √ FFFFH FFFFFBA4H UARTB1 status register UB1STR R/W √ √ 00H FFFFFBA6H UARTB1 receive data register AP UB1RXAP √ 00FFH FFFFFBA6H UARTB1 receive data register UB1RX R √ FFH FFFFFBA8H UARTB1 transmit data register UB1TX √ FFH FFFFFBAAH UARTB1 FIFO control register 0 UB1FIC0 √ √ 00H FFFFFBABH UARTB1 FIFO control register 1 UB1FIC1 √ √ 00H FFFFFBACH UARTB1 FIFO control register 2 UB1FIC2 √ 0000H FFFFFBACH UARTB1 FIFO control register 2L UB1FIC2L √ 00H FFFFFBADH UARTB1 FIFO control register 2H UB1FIC2H R/W √ 00H FFFFFBAEH UARTB1 status register 0 UB1FIS0 √ 00H FFFFFBAFH UARTB1 status register 1 UB1FIS1 R √ 10H FFFFFBC0H IIC shift register 4 IIC4 √ 00H FFFFFBC2H IIC control register 4 IICC4 √ √ 00H FFFFFBC3H Slave address register 4 SVA4 √ 00H FFFFFBC4H IIC clock selection register 4 IICCL4 √ √ 00H FFFFFBC5H IIC function expansion register 4 IICX4 R/W √ √ 00H FFFFFBC6H IIC status register 4 IICS4 R √ √ 00H FFFFFBCAH IIC flag register 4 IICF4 √ √ 00H FFFFFBE0H Ethernet control register MIICTL √ √ 00H FFFFFC00H External interrupt falling edge specification register 0 INTF0 √ √ 00H FFFFFC04H External interrupt falling edge specification register 2 INTF2 √ √ 00H FFFFFC06H External interrupt falling edge specification register 3 INTF3 √ √ 00H FFFFFC09H External interrupt falling edge specification register 4 INTF4H Note √ √ 00H FFFFFC0AH External interrupt falling edge specification register 5 INTF5 √ 0000H FFFFFC0AH External interrupt falling edge specification register 5L INTF5L √ √ 00H FFFFFC0BH External interrupt falling edge specification register 5H INTF5H R/W √ √ 00H Note V850ES/JJ3-E only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 96 of 1817 Sep 19, 2011 (16/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFFC12H External interrupt falling edge specification register 9 INTF9 √ 0000H FFFFFC12H External interrupt falling edge specification register 9H INTF9H √ √ 00H FFFFFC13H External interrupt falling edge specification register 9L INTF9L √ √ 00H FFFFFC20H External interrupt rising edge specification register 0 INTR0 √ √ 00H FFFFFC24H External interrupt rising edge specification register 2 INTR2 √ √ 00H FFFFFC26H External interrupt rising edge specification register 3 INTR3 √ √ 00H FFFFFC29H External interrupt rising edge specification register 4 Note INTR4H Note √ √ 00H FFFFFC2AH External interrupt rising edge specification register 5 INTR5 √ 0000H FFFFFC2AH External interrupt rising edge specification register 5L INTR5L √ √ 00H FFFFFC2BH External interrupt rising edge specification register 5H INTR5H √ √ 00H FFFFFC32H External interrupt rising edge specification register 9 INTR9 √ 0000H FFFFFC32H External interrupt rising edge specification register 9H INTR9H √ √ 00H FFFFFC33H External interrupt rising edge specification register 9L INTR9L √ √ 00H FFFFFC60H Port 0 function register PF0 √ √ 00H FFFFFC64H Port 2 function register PF2 √ √ 00H FFFFFC66H Port 3 function register PF3 √ √ 00H FFFFFC68H Port 4 function register PF4 √ 0000H FFFFFC68H Port 4 function register L PF4L √ √ 00H FFFFFC69H Port 4 function register H PF4H √ √ 00H FFFFFC6AH Port 5 function register PF5 √ 0000H FFFFFC6AH Port 5 function register L PF5L √ √ 00H FFFFFC6BH Port 5 function register H PF5H √ √ 00H FFFFFC72H Port 9 function register PF9 √ 0000H FFFFFC72H Port 9 function register L PF9L √ √ 00H FFFFFC73H Port 9 function register H PF9H √ √ 00H FFFFFD00H CSIF0 control register 0 CF0CTL0 √ √ 01H FFFFFD01H CSIF0 control register 1 CF0CTL1 √ √ 00H FFFFFD02H CSIF0 control register 2 CF0CTL2 √ 00H FFFFFD03H CSIF0 status register CF0STR R/W √ √ 00H FFFFFD04H CSIF0 receive data register CF0RX √ 0000H FFFFFD04H CSIF0 receive data register L CF0RXL R √ 00H FFFFFD06H CSIF0 transmit data register CF0TX √ 0000H FFFFFD06H CSIF0 transmit data register L CF0TXL √ 00H FFFFFD10H CSIF1 control register 0 CF1CTL0 √ √ 01H FFFFFD11H CSIF1 control register 1 CF1CTL1 √ √ 00H FFFFFD12H CSIF1 control register 2 CF1CTL2 √ 00H FFFFFD13H CSIF1 status register CF1STR R/W √ √ 00H FFFFFD14H CSIF1 receive data register CF1RX √ 0000H FFFFFD14H CSIF1 receive data register L CF1RXL R √ 00H FFFFFD16H CSIF1 transmit data register CF1TX √ 0000H FFFFFD16H CSIF1 transmit data register L CF1TXL R/W √ 00H Note V850ES/JJ3-E only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 97 of 1817 Sep 19, 2011 (17/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFFD20H CSIF2 control register 0 CF2CTL0 √ √ 01H FFFFFD21H CSIF2 control register 1 CF2CTL1 √ √ 00H FFFFFD22H CSIF2 control register 2 CF2CTL2 √ 00H FFFFFD23H CSIF2 status register CF2STR R/W √ √ 00H FFFFFD24H CSIF2 receive data register CF2RX √ 0000H FFFFFD24H CSIF2 receive data register L CF2RXL R √ 00H FFFFFD26H CSIF2 transmit data register CF2TX √ 0000H FFFFFD26H CSIF2 transmit data register L CF2TXL √ 00H FFFFFD30H CSIF3 control register 0 CF3CTL0 √ √ 01H FFFFFD31H CSIF3 control register 1 CF3CTL1 √ √ 00H FFFFFD32H CSIF3 control register 2 CF3CTL2 √ 00H FFFFFD33H CSIF3 status register CF3STR R/W √ √ 00H FFFFFD34H CSIF3 receive data register CF3RX √ 0000H FFFFFD34H CSIF3 receive data register L CF3RXL R √ 00H FFFFFD36H CSIF3 transmit data register CF3TX √ 0000H FFFFFD36H CSIF3 transmit data register L CF3TXL √ 00H FFFFFD40H CSIF4 control register 0 CF4CTL0 √ √ 01H FFFFFD41H CSIF4 control register 1 CF4CTL1 √ √ 00H FFFFFD42H CSIF4 control register 2 CF4CTL2 √ 00H FFFFFD43H CSIF4 status register CF4STR R/W √ √ 00H FFFFFD44H CSIF4 receive data register CF4RX √ 0000H FFFFFD44H CSIF4 receive data register L CF4RXL R √ 00H FFFFFD46H CSIF4 transmit data register CF4TX √ 0000H FFFFFD46H CSIF4 transmit data register L CF4TXL √ 00H FFFFFD50H CSIF5 control register 0 CF5CTL0 Note √ √ 01H FFFFFD51H CSIF5 control register 1 CF5CTL1 Note √ √ 00H FFFFFD52H CSIF5 control register 2 CF5CTL2 Note √ 00H FFFFFD53H CSIF5 status register CF5STR Note R/W √ √ 00H FFFFFD54H CSIF5 receive data register CF5RX Note √ 0000H FFFFFD54H CSIF5 receive data register L CF5RXL Note R √ 00H FFFFFD56H CSIF5 transmit data register CF5TX Note √ 0000H FFFFFD56H CSIF5 transmit data register L CF5TXL Note √ 00H FFFFFD60H CSIF6 control register 0 CF6CTL0 Note √ √ 01H FFFFFD61H CSIF6 control register 1 CF6CTL1 Note √ √ 00H FFFFFD62H CSIF6 control register 2 CF6CTL2 Note √ √ 00H FFFFFD63H CSIF6 status register CF6STR Note R/W √ √ 00H FFFFFD64H CSIF6 receive data register CF6RX Note √ 0000H FFFFFD64H CSIF6 receive data register L CF6RXL Note R √ 00H FFFFFD66H CSIF6 transmit data register CF6TX Note √ 0000H FFFFFD66H CSIF6 transmit data register L CF6TXL Note R/W √ 00H Note V850ES/JJ3-E only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 98 of 1817 Sep 19, 2011 (18/18) Manipulatable Bits Address Function Register Name Symbol R/W 1 8 16 Default Value FFFFFD80H IIC shift register 0 IIC0 √ 00H FFFFFD82H IIC control register 0 IICC0 √ √ 00H FFFFFD83H Slave address register 0 SVA0 √ 00H FFFFFD84H IIC clock select register 0 IICCL0 √ √ 00H FFFFFD85H IIC function expansion register 0 IICX0 R/W √ √ 00H FFFFFD86H IIC status register 0 IICS0 R √ √ 00H FFFFFD8AH IIC flag register 0 IICF0 √ √ 00H FFFFFD90H IIC shift register 1 IIC1 √ 00H FFFFFD92H IIC control register 1 IICC1 √ √ 00H FFFFFD93H Slave address register 1 SVA1 √ 00H FFFFFD94H IIC clock select register 1 IICCL1 √ √ 00H FFFFFD95H IIC function expansion register 1 IICX1 R/W √ √ 00H FFFFFD96H IIC status register 1 IICS1 R √ √ 00H FFFFFD9AH IIC flag register 1 IICF1 √ √ 00H FFFFFDA0H IIC shift register 2 IIC2 R/W √ 00H FFFFFDA2H IIC control register 2 IICC2 √ √ 00H FFFFFDA3H Slave address register 2 SVA2 √ 00H FFFFFDA4H IIC clock select register 2 IICCL2 √ √ 00H FFFFFDA5H IIC function expansion register 2 IICX2 R/W √ √ 00H FFFFFDA6H IIC status register 2 IICS2 R √ √ 00H FFFFFDAAH IIC flag register 2 IICF2 √ √ 00H FFFFFDB0H IIC shift register 3 IIC3 √ 00H FFFFFDB2H IIC control register 3 IICC3 √ √ 00H FFFFFDB3H Slave address register 3 SVA3 √ 00H FFFFFDB4H IIC clock selection register 3 IICCL3 √ √ 00H FFFFFDB5H IIC function expansion register 3 IICX3 R/W √ √ 00H FFFFFDB6H IIC status register 3 IICS3 R √ √ 00H FFFFFDBAH IIC flag register 3 IICF3 √ √ 00H FFFFFF40H USB clock selection register UCKSEL √ √ 00H FFFFFF41H USB function control register UFCKMSK √ √ 03H FFFFFF60H External DMA request enable register EXDRQEN R/W √ 00H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 99 of 1817 Sep 19, 2011

3.4.7 Programmable peripheral I/O registers

The BPC register is used to select the programmable peripheral I/O register area. The BPC register is valid only in the μPD70F3783 and 70F3786. (1) Peripheral I/O area select control register (BPC) This register can be read or written in 16-bit units. Reset sets this register to 0000H. BPC 12 1 08 6 4214 013 11 9 7 5315 PA15 0 PA13 PA1 2 PA11 PA10 PA09 PA08 PA07 PA06 PA05 PA04 PA03 PA02 PA01 PA00 PA15 PA13 to PA00 After reset: 0000H R/W Address: FFFFF064H Do not allow use of programmable peripheral I/O area. Allow use of programmable peripheral I/O area. Allows/does not allow use of programmable peripheral I/O area. Set address of programmable peripheral I/O area. (correspond to A27 to A14) Caution If the PA15 bit is set to 1, be su re to set the BPC register to 8FFBH. If the PA15 bit is set to 0, be su re to set the BPC register to 0000H. For the list of programmable peripheral I/O registers, refer to Table 21-16 Register Access Type.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 100 of 1817 Sep 19, 2011

3.4.8 Special registers

Special registers are registers that ar e protected from being written with ille gal data due to a program loop. The V850ES/JH3-E and V850ES/JJ3-E have the following eight special registers.

• Power save control register (PSC)
• Clock control register (CKC)
• Processor clock control register (PCC)
• Clock monitor mode register (CLM)
• Reset source flag register (RESF)
• Low-voltage detection register (LVIM)
• Internal RAM data status register (RAMS)
• On-chip debug mode register (OCDM) In addition, the PRCDM register is provided to protect agai nst a write access to the special registers so that the application system does not inadvertently stop due to a program loop. A write access to the special registers is made in a specific sequence, and an illegal store operation is reported to the SYS register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 101 of 1817 Sep 19, 2011 (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared in <2> to the PRCMD register. <4> Write the setting data to the special regi ster (by using the following instructions).

• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction) (<5> to <9> Insert NOP instructions (5 instructions).) Note <10> Enable DMA operation if necessary. [Example] With PSC register (setting standby mode) ST.B r11, PSMR[r0] ; Set PSMR register (setting IDLE1, IDLE2, and STOP modes). <1>CLR1 0, DCHCn[r0] ; Disable DMA operation. n = 0 to 3 <2>MOV0x02, r10 <3>ST.B r10, PRCMD[r0] ; Write PRCMD register. <4>ST.B r10, PSC[r0] ; Set PSC register. <5>NOP Note ; Dummy instruction <6>NOP Note ; Dummy instruction <7>NOP Note ; Dummy instruction <8>NOP Note ; Dummy instruction <9>NOP Note ; Dummy instruction <10>SET1 0, DCHCn[r0] ; Enable DMA operation. n = 0 to 3 (next instruction) There is no special sequence to read a special register. Note Five NOP instructions or more must be inserted i mmediately after setting the IDLE1 mode, IDLE2 mode, or STOP mode (by setting the PSC.STP bit to 1). Cautions 1. When a store instruction is executed to store data in the command register, interrupts are not acknowledged. This is because it is assumed that steps <3> and <4> above are performed by successive store instructions. If another instruction is placed between <3> and <4>, and if an interrupt is acknowledged by that instructi on, the above sequence may not be established, causing malfunction. 2. Although dummy data is written to th e PRCMD register, use the same general-purpose register used to set the special register (<4> in Example) to write data to the PRCMD register (<3> in Example). The same applies when a general-purpose register is used for addressing.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 102 of 1817 Sep 19, 2011 (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the regist ers that may seriously af fect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access to a special register is valid after data has been written in adv ance to the PRCMD register. In this way, the value of the special register can be rewritten only in a specific sequence, so as to pr otect the register from an illegal write access. The PRCMD register is write-only, in 8-bit units (undefined data is read when this register is read). REG7PRCMD REG6 REG5 REG4 REG3 REG2 REG1 REG0 After reset: Undefined W Address: FFFFF1FCH

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 103 of 1817 Sep 19, 2011 (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Protection error did not occur Protection error occurred PRERR Detects protection error SYS 0 0 0 0 0 0 PRERR After reset: 00H R/W Address: FFFFF802H < > The PRERR flag operates under the following conditions. (a) Set condition (PRERR flag = 1) (i) When data is written to a special register without writing anything to the PRCMD register (when <4> is executed without executing <3> in 3.4.8 (1) Setting data to special registers) (ii) When data is written to an on-chip peripheral I/O regi ster other than a special register (including execution of a bit manipulation instruction) after writ ing data to the PRCMD register (if <4> in 3.4.8 (1) Setting data to special registers is not the setting of a special register) Remark Even if an on-chip peripheral I/O register is read (except by a bit manipulation instruction) between an operation to write the PRCMD register and an ope ration to write a special register, the PRERR flag is not set, and the set data can be written to the special register. (b) Clear condition (PRERR flag = 0) (i) When 0 is written to the PRERR flag (ii) When the system is reset Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register, immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0 (the write access takes precedence). 2. If data is written to the PRCMD register, which is not a special register, immediately after a write access to the PRCMD register, the PRERR bit is set to 1.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 104 of 1817 Sep 19, 2011

3.4.9 Cautions

(1) Registers to be set first Be sure to set the following registers first when using the V850ES/JH3-E and V850ES/JJ3-E.

• System wait control register (VSWC)
• On-chip debug mode register (OCDM)
• Watchdog timer mode register 2 (WDTM2) After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary. When using the external bus, set each pin to the alternat e-function bus control pin mode by using the port-related registers after setting the above registers. (a) System wait control register (VSWC) The VSWC register controls wait of bus access to the on-chip peripheral I/O registers. Three clocks are required to access an on-chip peripheral I/O register (without a wait cycle). The V850ES/JH3- E and V850ES/JJ3-E require wait cycles according to t he operating frequency. Set the following value to the VSWC register in accordance with the frequency used. The VSWC register can be read or written in 8-bit units. Reset sets this register to 77H. VSWC Operating Frequency (fCPU) fCPU < 16.6 MHz

16.6 MHz ≤ fCPU < 25 MHz

25 MHz ≤ fCPU < 33.3 MHz

33.3 MHz ≤ fCPU ≤ 50 MHz

0 (no waits) After reset: 77H R/W Address: FFFFF06EH (b) On-chip debug mode register (OCDM) For details, see CHAPTER 34 ON-CHIP DEBUG FUNCTION. (c) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2. Watchdog timer 2 automatically starts in the reset mode af ter reset is released. Write the WDTM2 register to activate this operation. For details, see CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 105 of 1817 Sep 19, 2011 (2) Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU bus and the clock of the periphera l bus are asynchronous. If an access to the CPU and an access to the peripheral hardware conflict, therefore, unex pected illegal data may be transferred. If there is a possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is accessed, so that correct data is transferred. As a result, the CPU does not start proce ssing of the next instruction but enters the wait status. If this wait status occurs, the number of cl ocks required to execute an instruction increases by the number of wait clocks shown below. This must be taken into consideration if real-time processing is required. When specific on-chip peripheral I/O registers are accessed, more wait states may be required in addition to the wait states set by the VSWC register. The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks) at this time are shown below. (1/2) Peripheral Function Register Name Access k TAAnCNT Read 1 or 2 Write • 1st access: No wait

• Continuous write: 0 to 3 TAAnCCR0, TAAnCCR1 Read 1 or 2 Write • 1st access: No wait
• Continuous write: 0 to 3 16-bit timer/event counter AA (TAA) (n = 0 to 5) TAAmIOC4 Read 1 or 2 TABnCNT Read 1 or 2 Write • 1st access: No wait
• Continuous write: 0 to 3 TABnCCR0 to TABnCCR3 Read 1 or 2 Write • 1st access: No wait
• Continuous write: 0 to 3 16-bit timer/event counter AB (TAB) (n = 0, 1) TABnIOC4 Read 1 or 2 TAB0OPT1 Write • 1st access: No wait
• Continuous write: 0 to 3 Motor control TAB0DTC Write • 1st access: No wait
• Continuous write: 0 to 3 TT0CNT Read 1 or 2 Write • 1st access: No wait
• Continuous write: 0 to 3 TMT TT0TCR0, TT0TCR1 Read 1 or 2 Watchdog timer 2 (WDT2) WDTM2 Write (when WDT2 operating) Real-time output function (RTO) RTBL0, RTBH0 Write (RTPC0.RTPOE0 bit = 0) ADA0M0 Read 1 or 2 ADA0CR0 to ADA0CR11 Read 1 or 2 A/D converter ADA0CR0H to ADA0CR11H Read 1 or 2

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 106 of 1817 Sep 19, 2011 (2/2) Peripheral Function Register Name Access k CEnCTL0 Write 1 CEnTX0 (CEnTX0H, CEnTX0L) Write 1 CenCS (CEnCSL) Write 1 CSIE (n = 0, 1) CEnSTR Read 1 UBnTX Write 1 UBnRX Read 1 UBnRXAP Read 1 UBnFIS0 Read 1 UARTB (n = 0, 1) UBnFIS1 Read 1 I C00 to I C04 IICS0 to IICS4 Read 1 CRC CRCD Write 1 C0GMABT, C0GMABTD, C0MASKaL, C0MASKaH, C0LEC, C0INFO, C0ERC, C0IE, C0INTS, C0BRP , C0BTR, C0TS Read/Write f XX/fCANMOD + 1) / (2 + j) (MIN.) Note (2 × fXX/fCANMOD + 1) / (2 + j) (MAX.) Note C0GMCTRL, C0GMCS, C0CTRL Read/Write (f XX/fCAN + 1) / (2 + j) (MIN.) Note (2 × fXX/fCAN + 1) / (2 + j) (MAX.) Note Write (fXX/fCANMOD + 1) / (2 + j) (MIN.) Note (2 × fXX/fCANMOD + 1) / (2 + j) (MAX.) Note C0RGPT, C0TGPT Read (3 × fXX/fCANMOD + 1) / (2 + j) (MIN.) Note (4 × fXX/fCANMOD + 1) / (2 + j) (MAX.) Note C0LIPT, C0LOPT Read (3 × fXX/fCANMOD + 1) / (2 + j) (MIN.) Note (4 × fXX/fCANMOD + 1) / (2 + j) (MAX.) Note Write (4 × fXX/fCAN + 1) / (2 + j) (MIN.) Note (5 × fXX/fCAN + 1) / (2 + j) (MAX.) Note C0MCTRLm Read (3 × fXX/fCAN + 1) / (2 + j) (MIN.) Note (4 × fXX/fCAN + 1) / (2 + j) (MAX.) Note Write (8 bits) (4 × fXX/fCANMOD + 1) / (2 + j) (MIN.) Note (5 × fXX/fCANMOD + 1) / (2 + j) (MAX.) Note Write (16 bits) (2 × fXX/fCANMOD + 1) / (2 + j) (MIN.) Note (3 × fXX/fCANMOD + 1) / (2 + j) (MAX.) Note CAN controller (m = 0 to 31, a = 1 to 4) C0MDATA01m, C0MDATA0m, C0MDATA1m, C0MDATA23m, C0MDATA2m, C0MDATA3m, C0MDATA45m, C0MDATA4m, C0MDATA5m, C0MDATA67m, C0MDATA6m, C0MDATA7m, C0MDLCm, C0MCONFm, C0MIDLm, C0MIDHm Read (8/16 bits) (3 × f XX/fCANMOD + 1) / (2 + j) (MIN.) Note (4 × fXX/fCANMOD + 1) / (2 + j) (MAX.) Note

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 107 of 1817 Sep 19, 2011 Number of clocks necessary for access = 3 + i + j + (2 + j) × k Note Digits below the decimal point are rounded up. Caution Accessing the above registers is prohibited in the following statuses. If a wait cycle is generated, it can only be cleared by a reset.  When the CPU operates with the subclock a nd the main clock oscillation is stopped  When the CPU operates with th e internal oscillation clock Remark i: Values (0) of higher 4 bits of VSWC register j: Values (0 or 1) of lower 4 bits of VSWC register

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 3 CPU FUNCTION R01UH0290EJ0300 Rev.3.00 Page 108 of 1817 Sep 19, 2011 (3) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request be fore the instruction in <1> is complete, the execution result of the instruction in <1> may not be stored in a register. Instruction <1>

• Multiplication instruction: mul, mulh, mulhi, mulu Instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 <Example> <i> ld.w [r11], r10 If the decode operation of the mo v instruction <ii> immediately before the sld instruction <iii> and an interrupt request conflic t before execution of the ld instruction <i> is complete, the execution result of instruction <i> may not be stored in a register. <ii> mov r10, r28 <iii> sld.w 0x28, r10 (b) Countermeasure <1> When compiler (CA850) is used Use CA850 Ver. 2.61 or later because generation of the corresponding instruction sequence can be automatically suppressed. <2> For assembler When executing the sld instruction immediately afte r instruction <ii>, avoid the above operation using either of the following methods.
• Insert a nop instruction immediat ely before the sld instruction.
• Do not use the same register as the sld instructi on destination register in t he above instruction <ii> executed immediately before the sld instruction.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 109 of 1817 Sep 19, 2011 CHAPTER 4 PORT FUNCTIONS

4.1 Features

{ I/O ports

• V850ES/JH3-E: 84

5 V tolerant/N-ch open-drain output selectable: 48

• V850ES/JJ3-E: 100

5 V tolerant/N-ch open-drain output selectable: 59

{ Input/output specifiable in 1-bit units

4.2 Basic Port Configuration

The V850ES/JH3-E features a total of 84 I/O ports consisting of ports 0, 2 to 5, 7, 9, CM, CS, CT, DH, and DL. The V850ES/JJ3-E features a total of 100 I/O ports consisting of ports 0, 2 to 5, 7, 9, CM, CS, CT, DH, and DL. The port configuration is shown below. Table 4-1. I/O Buffer Power Supplies for Pins (V850ES/JH3-E) Power Supply Corresponding Pins AVREF0 Port 7 EVDD RESET, ports 0, 2 to 5, 9, CM, CS, CT, DH, DL Table 4-2. I/O Buffer Power Supplies for Pins (V850ES/JJ3-E) Power Supply Corresponding Pins AVREF0 Port 7 EVDD RESET, ports 0, 2 to 5, 9, CM, CS, CT, DH, DL

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 111 of 1817 Sep 19, 2011

4.3 Port Configuration

Table 4-3. Port Configuration (V850ES/JH3-E) Item Configuration Control register Port n mode register (PMn: n = 0, 2 to 5, 7, 9, CM, CS, CT, DH, DL) Port n mode control register (PMCn: n = 0, 2 to 5, 9, CM, CS, CT, DH, DL) Port n function control register (PFCn: n = 0, 2 to 4, 9, DH) Port n function control expansion register (PFCEn: n = 2 to 4, 9, DH) Port n function register (PFn: n = 0, 2 to 5, 9) Ports I/O: 84 Table 4-4. Port Configuration (V850ES/JJ3-E) Item Configuration Control register Port n mode register (PMn: n = 0, 2 to 5, 7, 9, CM, CS, CT, DH, DL) Port n mode control register (PMCn: n = 0, 2 to 5, 9, CM, CS, CT, DH, DL) Port n function control register (PFCn: n = 0, 2 to 5, 9, DH) Port n function control expansion register (PFCEn: n = 2 to 5, 9, DH) Port n function register (PFn: n = 0, 2 to 5, 9) Ports I/O: 100

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 112 of 1817 Sep 19, 2011 (1) Port n register (Pn) Data is input from or output to an external device by writing or reading the Pn register. The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins. Each bit of the Pn register corresponds to one pin of port n, and can be read or written in 1-bit units. Pn7 Outputs 0. Outputs 1. Pnm Control of output data (in output mode) Pn6 Pn5 Pn4 Pn3 Pn2 Pn1 Pn0 01237567 Pn After reset: 00H (output latch) R/W Data is written to or read from the Pn register as follows, regardless of the setting of the PMCn register. Table 4-5. Writing/Reading Pn Register Setting of PMn Register Writing to Pn Register Reading from Pn Register Output mode (PMnm = 0) Data is written to the output latch Note In the port mode (PMCn = 0), the contents of the output latch are output from the pins. The value of the output latch is read. Input mode (PMnm = 1) Data is written to the output latch. The pin status is not affected Note The pin status is read. Note The value written to the output latch is retained until a new value is written to the output latch.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 113 of 1817 Sep 19, 2011 (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of por t n, and the input or output mode can be specified in 1-bit units. PMn7 Output mode Input mode PMnm Control of input/output mode PMn6 PMn5 PMn4 PMn3 PMn2 PMn1 PMn0 PMn After reset: FFH R/W (3) Port n mode control register (PMCn) The PMCn register specifies the port mode or alternate function. Each bit of this register corresponds to one pin of port n, and the mode of the port can be specified in 1-bit units. Port mode Alternate-function mode PMCnm Specification of operation mode PMCn7 PMCn6 PMCn5 PMCn4 PMCn3 PMCn2 PMCn1 PMCn0PMCn After reset: 00H R/W

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 114 of 1817 Sep 19, 2011 (4) Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. PFCn7 PFCn6 PFCn5 PFCn4 PFCn3 PFCn2 PFCn1 PFCn0PFCn After reset: 00H R/W Alternate function 1 Alternate function 2 PFCnm Specification of alternate function (5) Port n function control expansion register (PFCEn) The PFCEn register specifies the alternate function of a port pin to be us ed if the pin has three or more alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. PFCn7 PFCn6 PFCn5 PFCn4 PFCn3 PFCn2 PFCn1 PFCn0 PFCEn7 PFCEn6 PFCEn5 PFCEn4 PFCEn3 PFCEn2 PFCEn1 PFCEn0 After reset: 00H R/W PFCEn PFCn Alternate function 1 Alternate function 2 Alternate function 3 Alternate function 4 PFCEnm Specification of alternate function PFCnm

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 115 of 1817 Sep 19, 2011 (6) Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in 1- bit units. PFn7 PFn6 PFn5 PFn4 PFn3 PFn2 PFn1 PFn0 Normal output (CMOS output) N-ch open-drain output PFnmNote Control of normal output/N-ch open-drain output PFn After reset: 00H R/W Note The PFnm bit of the PFn register is valid only when the PMnm bit of the PMn register is 0 (when the output mode is specified) in port mode (PMCnm bit = 0). When the PMnm bit is 1 (when the input mode is specified), the set value of the PFn register is invalid.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 116 of 1817 Sep 19, 2011 (7) Port setting Set a port as illustrated below. Figure 4-3. Setting of Each Register and Pin Function PFCEnm PFCnm PMCn register Output mode Input mode PMn register “0” “1” “0” “1” “0” “1” (a) (b) (c) (d) Alternate function (when two alternate functions are available) Port mode Alternate function 1 Alternate function 2 PFCn register Alternate function (when three or more alternate functions are available) Alternate function 1 Alternate function 2 Alternate function 3 Alternate function 4 PFCn register PFCEn register 0 (a) (b) (c) (d) Remark Set the alternate functions in the following sequence. <1> Set the PFCn and PFCEn registers. <2> Set the PMCn register. <3> Set the INTRn or INTFn register (to specify an external interrupt pin). If the PMCn register is set first, an unintende d function may be set while the PFCn and PFCEn registers are being set.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 117 of 1817 Sep 19, 2011

4.3.1 Port 0

Port 0 is 2-bit port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Table 4-6. Port 0 Alternate-Function Pins Pin No. Pin Name V850ES/ JH3-E V850ES/ JJ3-E Alternate-Function Pin Name I/O Remark P02 21 21 NMI Input P03 22 22 INTP00/ADTRG/EXCLK Input Can be specified as an N-ch open-drain output Caution The P02 and P03 pins have hysteresis characteri stics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. (1) Port 0 register (P0) Outputs 0. Outputs 1. P0n Output data control (in output mode) (n = 2, 3) After reset: 00H (output latch) R/W Address: FFFFF400H 0 0 0 0 P03 P02 0 0 76543210 (2) Port 0 mode register (PM0) Output mode Input mode PM0n I/O mode control (n = 2, 3) PM0 After reset: FFH R/W Address: FFFFF420H 1 1 1 1 PM03 PM02 1 1 76543210

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 118 of 1817 Sep 19, 2011 (3) Port 0 mode control register (PMC0) PMC0 I/O port INTP00 input/ADTRG input/EXCLK input PMC03 Specification of P03 pin operation mode I/O port NMI input PMC02 Specification of P02 pin operation mode After reset: 00H R/W Address: FFFFF440H 0 0 0 0 PMC03 PMC02 0 0 76543210 (4) Port 0 function control register (PFC0) PFC0 After reset: 00H R/W Address: FFFFF460H 0 0 0 0 PFC03 0 0 0 76543210 Remark For details of alternate function specification, see 4.3.1 (6) Port 0 alternate function specifications. (5) Port 0 function control expansion register (PFCE0) PFCE0 After reset: 00H R/W Address: FFFFF700H 0 0 0 0 PFCE03 0 0 0 76543210 Remark For details of alternate function specification, see 4.3.1 (6) Port 0 alternate function specifications. (6) Port 0 alternate function specifications PFCE03 PFC03 Specification of P03 pin alternate function 0 0 INTP00 input 0 1 ADTRG input 1 0 EXCLK input 1 1 Setting prohibited (7) Port 0 function register (PF0)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 119 of 1817 Sep 19, 2011 Normal output N-ch open-drain output PF0n Control of normal output or N-ch open-drain output (n = 2, 3) PF0 After reset: 00H R/W Address: FFFFFC60H 0 0 0 0 PF03 PF02 0 0 76543210

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 120 of 1817 Sep 19, 2011

4.3.2 Port 2

Port 2 is a 7-bit (V850ES/JH3-E)/8-bit (V850ES/JJ3-E) port for which I/O settings can be controlled in 1-bit units. Port 2 includes the following alternate-function pins. Table 4-7. Port 2 Alternate-Function Pins Pin No. Pin Name V850ES/ JH3-E V850ES/ JJ3-E Alternate-Function Pin Name I/O Remark P20 38 38 TIAB02/TOAB02/INTP01 I/O P21 39 39 TIAB00/TOAB00/RTCDIV/RTCCL I/O P22 40 40 TIAB01/TOAB01/RTC1HZ/INTP02 I/O P23 59 65 SIF1/TXDC1/SDA00/INTP03 I/O P24 62 68 SOF1/RXDC1/SCL00/INTP04 Input P25 63 69 SCKF1/TIAA30/TOAA30/UDMARQ0 I/O P26 64 70 TIAA31/TOAA31/INTP05/UDMAAK0 I/O P27 − 41 TIAB03/TOAB03/INTP21 I/O Can be specified as an N-ch open- drain output Caution The P20 to P27 pins have hysteresis characteristi cs in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. (1) Port 2 register (P2) (a) V850ES/JH3-E Outputs 0. Outputs 1. P2n Output data control (in output mode) (n = 0 to 6) After reset: 00H (output latch) R/W Address: FFFFF404H

0 P26 P25 P24 P23 P22 P21 P20

(b) V850ES/JJ3-E Outputs 0. Outputs 1. P2n Output data control (in output mode) (n = 0 to 7) After reset: 00H (output latch) R/W Address: FFFFF404H P27 P26 P25 P24 P23 P22 P21 P20 76543210

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 121 of 1817 Sep 19, 2011 (2) Port 2 mode register (PM2) (a) V850ES/JH3-E Output mode Input mode PM2n Output data control (n = 0 to 6) PM2 After reset: FFH R/W Address: FFFFF424H

1 PM26 PM25 PM24 PM23 PM22 PM21 PM20

(b) V850ES/JJ3-E Output mode Input mode PM2n Output data control (n = 0 to 7) PM2 After reset: FFH R/W Address: FFFFF424H PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 76543210

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 122 of 1817 Sep 19, 2011 (3) Port 2 mode control register (PMC2) (1/2) (a) V850ES/JH3-E PMC2 I/O port SCKF1 I/O/TIAA30 input/TOAA30 output/UDMARQ0 input PMC25 Specification of P25 pin operation mode I/O port TIAA31 input/TOAA31 output/INTP05 input/UDMAAK0 output PMC26 Specification of P26 pin operation mode I/O port SOF1 output/RXDC1 input/SCL00 I/O/INTP04 input PMC24 Specification of P24 pin operation mode I/O port SIF1 input/TXDC1 output/SDA00 I/O/INTP03 input PMC23 Specification of P23 pin operation mode I/O port TIAB01 input/TOAB01 output/RTC1HZ output/INTP02 input PMC22 Specification of P22 pin operation mode I/O port TIAB00 input/TOAB00 output/RTCDIV output/RTCCL output PMC21 Specification of P21 pin operation mode I/O port TIAB02 input/TOAB02 output/INTP01 input PMC20 Specification of P20 pin operation mode After reset: 00H R/W Address: FFFFF444H

0 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 123 of 1817 Sep 19, 2011 (2/2) (b) V850ES/JJ3-E PMC2 I/O port SCKF1 I/O/TIAA30 input/TOAA30 output/UDMARQ0 input PMC25 Specification of P25 pin operation mode I/O port TIAA31 input/TOAA31 output/INTP05 input/UDMAAK0 output PMC26 Specification of P26 pin operation mode I/O port SOF1 output/RXDC1 input/SCL00 I/O/INTP04 input PMC24 Specification of P24 pin operation mode I/O port SIF1 input/TXDC1 output/SDA00 I/O/INTP03 input PMC23 Specification of P23 pin operation mode I/O port TIAB01 input/TOAB01 output/RTC1HZ output/INTP02 input PMC22 Specification of P22 pin operation mode I/O port TIAB00 input/TOAB00 output/RTCDIV output/RTCCL output PMC21 Specification of P21 pin operation mode I/O port TIAB02 input/TOAB02 output/INTP01 input PMC20 Specification of P20 pin operation mode After reset: 00H R/W Address: FFFFF444H PMC27 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20 76543210 I/O port TIAB03 input/TOAB03 output/INTP21 input PMC27 Specification of P27 pin operation mode

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 124 of 1817 Sep 19, 2011 (4) Port 2 function control register (PFC2) (a) V850ES/JH3-E PFC2 After reset: 00H R/W Address: FFFFF464H

0 PFC26 PFC25 PFC24 PFC23 PFC22 PFC21 PFC20

(b) V850ES/JJ3-E PFC2 After reset: 00H R/W Address: FFFFF464H PFC27 PFC26 PFC25 PFC24 PFC23 PFC22 PFC21 PFC20 76543210 Remark For details of alternate function specification, see 4.3.2 (6) Port 2 alternate function specifications. (5) Port 2 function control expansion register (PFCE2) (a) V850ES/JH3-E PFCE2 After reset: 00H R/W Address: FFFFF704H

0 PFCE26 PFCE25 PFCE24 PFCE23 PFCE22 PFCE21 PFCE20

(b) V850ES/JJ3-E PFCE2 After reset: 00H R/W Address: FFFFF704H PFCE27 PFCE26 PFCE25 PFCE24 PFCE23 PFCE22 PFCE21 PFCE20 76543210 Remark For details of alternate function specification, see 4.3.2 (6) Port 2 alternate function specifications.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 125 of 1817 Sep 19, 2011 (6) Port 2 alternate function specifications PFCE27 PFC27 Specification of P27 pin alternate function (V850ES/JJ3-E only) 0 0 TIAB03 input 0 1 TOAB03 output 1 0 INTP21 input 1 1 Setting prohibited PFCE26 PFC26 Specification of P26 pin alternate function 0 0 TIAB31 input 0 1 TOAB31 output 1 0 INTP05 input 1 1 UDMAAK0 output PFCE25 PFC25 Specification of P25 pin alternate function 0 0 SCKF1 I/O 0 1 TIAA30 input 1 0 TOAA30 output 1 1 UDMARQ0 input PFCE24 PFC24 Specification of P24 pin alternate function 0 0 SOF1 output 0 1 RXDC1 input 1 0 SCL00 I/O 1 1 INTP04 input PFCE23 PFC23 Specification of P23 pin alternate function 0 0 SIF1 input 0 1 TXDC1 output 1 0 SDA00 I/O 1 1 INTP03 input PFCE22 PFC22 Specification of P22 pin alternate function 0 0 TIAB01 input 0 1 TOAB00 output 1 0 RTC1HZ output 1 1 INTP02 input PFCE21 PFC21 Specification of P21 pin alternate function 0 0 TIAB00 input 0 1 TOAB00 output 1 0 RTCDIV output 1 1 RTCCL output

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 126 of 1817 Sep 19, 2011 PFCE20 PFC20 Specification of P20 pin alternate function 0 0 TIAB02 input 0 1 TOAB02 output 1 0 INTP01 input 1 1 Setting prohibited (7) Port 2 function register (PF2) (a) V850ES/JH3-E Normal output N-ch open-drain output PF2n Control of normal output or N-ch open-drain output (n = 0 to 6) PF2 After reset: 00H R/W Address: FFFFFC64H

0 PF26 PF25 PF24 PF23 PF22 PF21 PF20

(b) V850ES/JJ3-E Normal output N-ch open-drain output PF2n Control of normal output or N-ch open-drain output (n = 0 to 7) PF2 After reset: 00H R/W Address: FFFFFC64H PF27 PF26 PF25 PF24 PF23 PF22 PF21 PF20 76543210

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 127 of 1817 Sep 19, 2011

4.3.3 Port 3

Port 3 is a 8-bit port that controls I/O in 1-bit units. Port 3 includes the following alternate-function pins. Table 4-8. Port 3 Alternate-Function Pins Pin No. Pin Name V850ES/ JH3-E V850ES/ JJ3-E Alternate-Function Pin Name I/O Remark P30 28 28 TXDC0/SIF2/TIAA00/TOAA00 I/O P31 29 29 RXDC0/SOF2/TIAA01/TOAA01 I/O P32 30 30 ASCKC0/SCKF2/TIAA10/TOAA10 I/O P33 31 31 SIF4/TXDB0/TIAA11/TOAA11 I/O P34 32 32 SOF4/RXDB0/TIAA20/TOAA20 I/O P35 33 33 SCKF4/TIAA21/TOAA21/TOAA1OFF /INTP06 I/O P36 36 36 TXDC2/SDA02/CTXD0 Note I/O P37 37 37 RXDC2/SCL02/CRXD0 Note I/O Can be specified as an N-ch open- drain output Note μPD70F3783, 70F3786 only Caution The P30 to P37 pins have hysteresis characteristi cs in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. (1) Port 3 register (P3) Outputs 0. Outputs 1. P3n Output data control (in output mode) (n = 0 to 7) After reset: 00H (output latch) R/W Address: FFFFF406H P37 P36 P35 P34 P33 P32 P31 P30 76543210 (2) Port 3 mode register (PM3) Output mode Input mode PM3n I/O mode control (n = 0 to 7) PM3 After reset: FFH R/W Address: FFFFF426H PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 76543210

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 128 of 1817 Sep 19, 2011 (3) Port 3 mode control register (PMC3) I/O port RXDC2 input/SCL02 I/O/CRXD0 inputNote PMC37 Specification of P37 pin operation mode I/O port TXDC2 output/SDA02 I/O/CTXD0 output Note PMC36 Specification of P36 pin operation mode PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30PMC3 After reset: 00H R/W Address: FFFFF446H I/O port SCKF4 I/O/TIAA21 input/TOAA21 output/TOAA1OFF input/INTP06 input PMC35 Specification of P35 pin operation mode I/O port SOF4 output/RXDB0 input/TIAA20 input/TOAA20 output PMC34 Specification of P34 pin operation mode I/O port SIF4 input/TXDB0 output/TIAA11 input/TOAA11 output PMC33 Specification of P33 pin operation mode I/O port ASCKA0 input/SCKF2 I/O/TIAA10 input/TOAA10 output PMC32 Specification of P32 pin operation mode I/O port RXDC0 input/SOF2 output/TIAA01 input/TOAA01 output PMC31 Specification of P31 pin operation mode I/O port TXDC0 output/SIF2 input/TIAA00 input/TOAA00 output PMC30 Specification of P30 pin operation mode Note μPD70F3783, 70F3786 only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 129 of 1817 Sep 19, 2011 (4) Port 3 function control register (PFC3) PFC37 PFC36 PFC35 PFC34 PFC33 PFC32 PFC31 PFC30PFC3 After reset: 00H R/W Address: FFFFF466H Remark For details of alternate function specification, see 4.3.3 (6) Port 3 alternate function specifications. (5) Port 3 function control expansion register (PFCE3) PFCE3 After reset: 00H R/W Address: FFFFF706H PFCE37Note PFCE36Note PFCE35 PFCE34 PFCE33 PFCE32 PFCE31 PFCE30 Note μPD70F3783, 70F3786 only Remark For details of alternate function specification, see 4.3.3 (6) Port 3 alternate function specifications. (6) Port 3 alternate function specifications PFCE37 Note PFC37 Specification of P37 pin alternate function 0 0 RXDC2 input 0 1 SCL02 I/O 1 0 CRXD0 input Note 1 1 Setting prohibited Note Note μPD70F3783, 70F3786 only PFCE36 Note PFC36 Specification of P36 pin alternate function 0 0 TXDC2 output 0 1 SDA02 I/O 1 0 CTXD0 output Note 1 1 Setting prohibited Note Note μPD70F3783, 70F3786 only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 130 of 1817 Sep 19, 2011 PFCE35 PFC35 Specification of P35 pin alternate function 0 0 SCKF4 I/O Note 1 0 1 TIAA21 input 1 0 TOAA21 output 1 1 TOAA1OFF input/INTP06 input Note 2 Notes 1. The SCKF4 function is assigned to the PDH5 pin as well as the P35 pin. When using the P35 pin for the SCKF4 function, do not specify the PDH5 pin to be used for this function. 2. TOAA1OFF and INTP09 are alternate functions. W hen using the pin as the TOAA1OFF pin, disable INTP09 pin edge detection, which is the alternate function. Also, when using the pin as the INTP09 pin, stop the high-impedance output controller. PFCE34 PFC34 Specification of P34 pin alternate function 0 0 SOF4 output Note 0 1 RXDB0 input 1 0 TIAA20 input 1 1 TOAA20 output Note The SOF4 function is assigned to the PDH4 pin as we ll as the P34 pin. When using the P34 pin for the SOF4 function, do not specify the PDH4 pin to be used for this function. PFCE33 PFC33 Specification of P33 pin alternate function 0 0 SIF4 input Note 0 1 TXDB0 output 1 0 TIAA11 input 1 1 TOAA11 output Note The SIF4 function is assigned to the PDH3 pin as well as the P33 pin. When using the P33 pin for the SIF4 function, do not specify the PDH3 pin to be used for this function. PFCE32 PFC32 Specification of P32 pin alternate function 0 0 ASCKC0 input 0 1 SCKF2 I/O 1 0 TIAA10 input 1 1 TOAA10 output PFCE31 PFC31 Specification of P31 pin alternate function 0 0 RXDC0 input 0 1 SOF2 input 1 0 TIAA01 input 1 1 TOAA01 output PFCE30 PFC30 Specification of P30 pin alternate function 0 0 TXDC0 output 0 1 SIF2 input 1 0 TIAA00 input 1 1 TOAA00 output

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 131 of 1817 Sep 19, 2011 (7) Port 3 function register (PF3) PF37 PF36 PF35 PF34 PF33 PF32 PF31 PF30 Normal output (CMOS output) N-ch open-drain output PF3n Control of normal output or N-ch open-drain output (n = 0 to 7) PF3 After reset: 00H R/W Address: FFFFFC66H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 132 of 1817 Sep 19, 2011

4.3.4 Port 4

Port 4 is a 6-bit (V850ES/JH3-E) and 9-bit (V850ES/JJ3-E) port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Table 4-9. Port 4 Alternate-Function Pins Pin No. Pin Name V850ES/ JH3-E V850ES/ JJ3-E Alternate-Function Pin Name I/O Remark P40 3 3 SIF0/TXDC3/SDA01/RTP00 I/O P41 4 4 SOF0/RXDC3/SCL01/RTP01 I/O Can be specified as an N-ch open-drain output P42 5 5 SCKF0/TIAA40/TOAA40/RTP02 I/O 6 − SIE0/TXDC4/RTP03/HLDAK I/O P43 − 6 SIE0/TXDC4/RTP03 I/O 7 − SOE0/RXDC4/RTP04/HLDRQ I/O P44 − 7 SOE0/RXDC4/RTP04 I/O P45 8 8 SCKE0/TIAA41/TOAA41/RTP05 I/O P46 − 128 SIF5/TXDC6/RTP06 I/O P47 − 129 SOF5/RXDC6/RTP07 I/O P48 − 130 SCKF5/INTP22 I/O Can be specified as an N-ch open-drain output Caution The P40 to P48 pins have hysteresis characteristi cs in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 133 of 1817 Sep 19, 2011 (1) Port 4 register (P4) (a) V850ES/JH3-E Outputs 0. Outputs 1. P4n Output data control (in output mode) (n = 0 to 5) P4 0 P45 P44 P43 P42 P41 P40 After reset: 00H (output latch) R/W Address: FFFFF408H (b) V850ES/JJ3-E Outputs 0. Outputs 1. P4n Output data control (in output mode) (n = 0 to 8) 0 0 0 0 0 0 P48 P47 P46 P45 P44 P43 P42 P41 P40 89101112131415 P4 (P4H) (P4L) After reset: 0000H (output latch) R/W Address: P4 FFFFF408H, P4L FFFFF408H, P4H FFFFF409H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 134 of 1817 Sep 19, 2011 (2) Port 4 mode register (PM4) (a) V850ES/JH3-E Output mode Input mode PM4n I/O mode control (n = 0 to 5) PM4 1 PM45 PM44 PM43 PM42 PM41 PM40 After reset: FFH R/W Address: FFFFF428H (b) V850ES/JJ3-E Output mode Input mode PM4n I/O mode control (n = 0 to 8) 1 1 1 1 1 1 PM48 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 89101112131415 PM4 (PM4H) (PM4L) After reset: FFFFH R/W Address: PM4 FFFFF428H, PM4L FFFFF428H, PM4H FFFFF429H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 135 of 1817 Sep 19, 2011 (3) Port 4 mode control register (PMC4) (1/2) (a) V850ES/JH3-E 0PMC4 0 PMC45 PMC44 PMC43 PMC42 PMC41 PMC40 I/O port SCKE0 I/O/TIAA41 input/TOAA41 output/RTP05 output PMC45 Specification of P45 pin operation mode I/O port SOE0 output/RXDC4 input/RTP04 output/HLDRQ input PMC44 Specification of P44 pin operation mode I/O port SIE0 input/TXDC4 output/RTP03 output/HLDAK output PMC43 Specification of P43 pin operation mode After reset: 00H R/W Address: FFFFF448H I/O port SCKF0 I/O/TIAA40 input/TOAA40 output/RTP02 output PMC42 Specification of P42 pin operation mode I/O port SOF0 output/RXDC3 input/SCL01 I/O/RTP01 output PMC41 Specification of P41 pin operation mode I/O port SIF0 input/TXDC3 output/SDA01 I/O/RTP00 output PMC40 Specification of P40 pin operation mode

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 136 of 1817 Sep 19, 2011 (2/2) (b) V850ES/JJ3-E I/O port SCKF5 I/O/INTP22 input PMC48 Specification of P48 pin operation mode 0 0 0 0 0 0 PMC48 PMC47 PMC46 PMC45 PMC44 PMC43 PMC42 PMC41 PMC40 89101112131415 PMC4 (PMC4H) (PMC4L) After reset: 0000H (output latch) R/W Address: PMC4 FFFFF448H, PMC4L FFFFF448H, PMC4H FFFFF449H I/O port SCKE0 I/O/TIAA41 input/TOAA41 output/RTP05 output PMC45 Specification of P45 pin operation mode I/O port SOE0 output/RXDC4 input/RTP04 PMC44 Specification of P44 pin operation mode I/O port SIE0 input/TXDC4 output/RTP03 output PMC43 Specification of P43 pin operation mode I/O port SOF5 output/RXDC6 input/RTP07 output PMC47 Specification of P47 pin operation mode I/O port SIF5 input/TXDC6 output/RTP06 output PMC46 Specification of P46 pin operation mode I/O port SCKF0 I/O/TIAA40 input/TOAA40 output/RTP02 output PMC42 Specification of P42 pin operation mode I/O port SOF0 output/RXDC3 input/SCL01 I/O/RTP01 output PMC41 Specification of P41 pin operation mode I/O port SIF0 input/TXDC3 output/SDA01 I/O/RTP00 output PMC40 Specification of P40 pin operation mode

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 137 of 1817 Sep 19, 2011 (4) Port 4 function control register (PFC4) (a) V850ES/JH3-E PFC4 After reset: 00H R/W Address: FFFFF468H 0 0 PFC45 PFC44 PFC43 PFC42 PFC41 PFC40 (b) V850ES/JJ3-E 0 0 0 0 0 0 0 PFC48 PFC47 PFC46 PFC45 PFC44 PFC43 PFC42 PFC41 PFC40 89101112131415 PFC4 (PFC4H) (PFC4L) After reset: 0000H R/W Address: PFC4 FFFFF468H, PFC4L FFFFF468H, PFC4H FFFFF469H Remarks 1. For details of alternate- function specification, see 4.3.4 (6) Port 4 alternate function specifications. 2. The PFC4 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PFC4 register as the PFC4H register and the lower 8 bits as the PFC4L register, the register can be read or written in 8-bit or 1-bit units. 3. To read/write bits 8 to 15 of the PFC4 regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PFC4H register. (5) Port 4 function control ex pansion register L (PFCE4L) (a) V850ES/JH3-E PFCE4L After reset: 00H R/W Address: FFFFF708H 0 0 PFCE45 PFCE44 PFCE43 PFCE42 PFCE41 PFCE40 (b) V850ES/JJ3-E PFCE4L After reset: 00H R/W Address: FFFFF708H PFCE47 PFCE46 PFCE45 PFCE44 PFCE43 PFCE42 PFCE41 PFCE40 Remark For details of alternate function specification, see 4.3.4 (6) Port 4 alternate function specifications.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 138 of 1817 Sep 19, 2011 (6) Port 4 alternate function specifications PFC48 Note Specification of P48 pin Note alternate function

0 SCKF5 I/O

1 INTP22 input

PFCE45 PFC45 Specification of P45 pin alternate function 0 0 SCKE0 I/O 0 1 TIAA41 input 1 0 TOAA41 output 1 1 RTP05 output PFCE44 PFC44 Specification of P44 pin alternate function 0 0 SOE0 output 0 1 RXDC4 input 1 0 RTP04 output 1 1 HLDRQ input Note Note V850ES/JH3-E only, setting prohibited in V850ES/JJ3-E PFCE43 PFC43 Specification of P44 pin alternate function 0 0 SIE0 input 0 1 TXDC4 output 1 0 RTP03 output 1 1 HLDAK output Note Note V850ES/JH3-E only, setting prohibited in V850ES/JJ3-E

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 139 of 1817 Sep 19, 2011 PFCE42 PFC42 Specification of P42 pin alternate function 0 0 SCKF0 I/O 0 1 TIAA40 input 1 0 TOAA40 output 1 1 RTP02 output PFCE41 PFC41 Specification of P41 pin alternate function 0 0 SOF0 output 0 1 RXDC3 input 1 0 SCL01 I/O 1 1 RTP01 output PFCE40 PFC40 Specification of P40 pin alternate function 0 0 SIF0 input 0 1 TXDC3 output 1 0 SDA01 I/O 1 1 RTP00 output

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 140 of 1817 Sep 19, 2011 (7) Port 4 function register (PF4) (a) V850ES/JH3-E Normal output (CMOS output) N-ch open-drain output PF4n Control of normal output or N-ch open-drain output (n = 0 to 2) PF4 0 0 0 0 PF42 PF41 PF40 After reset: 00H R/W Address: FFFFFC68H (b) V850ES/JJ3-E Normal output (CMOS output) N-ch open-drain output PF4n Control of normal output or N-ch open-drain output (n = 0 to 2, 6 to 8) 0 0 0 0 0 0 PF48 PF47 PF46 0 0 0 PF42 PF41 PF40 89101112131415 PF4 (PF4H) (PF4L) After reset: 0000H R/W Address: PF4 FFFFFC68H, PF4L FFFFFC68H, PF4H FFFFFC69H Remarks 1. The PF4 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PF4 register as the PF4H register and the lower 8 bits as the PF4L register, they can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PF4 regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PF4H register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 141 of 1817 Sep 19, 2011

4.3.5 Port 5

Port 5 is a 5-bit (V850ES/JH3-E)/10-bit (V850ES/JJ3-E) port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Table 4-10. Port 5 Alternate-Function Pins Pin No. Pin Name V850ES/ JH3-E V850ES/ JJ3-E Alternate-Function Pin Name I/O Remark P50 23 23 INTP07/DDI Note Input P51 24 24 INTP08/DDO Note I/O P52 25 25 INTP09/DCK Note Input P53 26 26 IINTP10/DMS Note Input P54 27 27 INTP11/DRST Note Input P55 − 42 SDA04/INTP23/UDMARQ1 I/O P56 − 43 SCL04/INTP24/UDMAAK1 I/O P57 − 62 SIF6/TXDC7 I/O P58 − 63 SOF6/RXDC7 I/O P59 − 64 SCKF6/INTP25 Input Can be specified as an N-ch open-drain output Note The DDI, DDO, DCK, DMS, and DRST pins are used for on-chip debugging. If on-chip debugging is not used, fix the P54/INTP11/D RST pin to low level between when the reset by the RESET pin is released and when the OCDM.OCDM0 bit is cleared (0). For details, see 4.5.3 Cautions on on-chip debug pins. Cautions 1. When the power is turn ed on, the P51 pin may output an undefined level temporarily even during reset. 2. The P50 to P59 pins have hysteresis characteri stics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 142 of 1817 Sep 19, 2011 (1) Port 5 register (P5) (a) V850ES/JH3-E Outputs 0. Outputs 1. P5n Output data control (in output mode) (n = 0 to 4) P5 0 0 P54 P53 P52 P51 P50 After reset: 00H (output latch) R/W Address: FFFFF40AH (b) V850ES/JJ3-E Outputs 0. Outputs 1. P5n Output data control (in output mode) (n = 0 to 9) 0 0 0 0 0 P59 P58 P57 P56 P55 P54 P53 P52 P51 P50 89101112131415 P5 (P5H) (P5L) After reset: 0000H (output latch) R/W Address: P5 FFFFF40AH, P5L FFFFF40AH, P5H FFFFF40BH Remarks 1. The P5 register can be read or written in 16-bit units. However, when using the higher 8 bits of the P5 register as the P5H register and the lower 8 bits as the P5L register, they can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the P5 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the P5H register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 143 of 1817 Sep 19, 2011 (2) Port 5 mode register (PM5) (a) V850ES/JH3-E Output mode Input mode PM5n I/O mode control (n = 0 to 4) PM5 1 1 PM54 PM53 PM52 PM51 PM50 After reset: FFH R/W Address: FFFFF42AH (b) V850ES/JJ3-E Output mode Input mode PM5n I/O mode control (n = 0 to 9) 1 1 1 1 1 PM59 PM58 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 89101112131415 PM5 (PM5H) (PM5L) After reset: FFFFH R/W Address: PM5 FFFFF42AH, PM5L FFFFF42AH, PM5H FFFFF42BH Remarks 1. The PM5 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PM5 register as the PM5H register and the lower 8 bits as the PM5L register, they can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PM5 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PM5H register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 144 of 1817 Sep 19, 2011 (3) Port 5 mode control register (PMC5) (1/2) (a) V850ES/JH3-E 0PMC5 0 0 PMC54 PMC53 PMC52 PMC51 PMC50 I/O port INTP11 input PMC54 Specification of P54 pin operation mode I/O port INTP10 input PMC53 Specification of P53 pin operation mode I/O port INTP09 input PMC52 Specification of P52 pin operation mode I/O port INTP08 input PMC51 Specification of P51 pin operation mode I/O port INTP07 input PMC50 Specification of P50 pin operation mode After reset: 00H R/W Address: FFFFF44AH

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 145 of 1817 Sep 19, 2011 (2/2) (b) V850ES/JJ3-E I/O port SCKF6 I/O/INTP25 input PMC59 Specification of P59 pin operation mode 0 0 0 0 0 PMC59 PMC58 PMC57 PMC56 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 89101112131415 PMC5 (PMC5H) (PMC5L) After reset: 0000H R/W Address: PMC5 FFFFF44AH, PMC5L FFFFF44AH, PMC5H FFFFF44BH I/O port SDA04 I/O/INTP23 input/UDMARQ1 input PMC56 Specification of P56 pin operation mode I/O port SCL04 I/O/INTP24 input/UDMAAK1 output PMC55 Specification of P55 pin operation mode I/O port SOF6 output/RXDC7 input PMC58 Specification of P58 pin operation mode I/O port SIF6 input/TXDC7 output PMC57 Specification of P57 pin operation mode I/O port INTP11 input PMC54 Specification of P54 pin operation mode I/O port INTP10 input PMC53 Specification of P53 pin operation mode I/O port INTP09 input PMC52 Specification of P52 pin operation mode I/O port INTP08 input PMC51 Specification of P51 pin operation mode I/O port INTP07 input PMC50 Specification of P50 pin operation mode Remarks 1. The PMC5 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PMC5 register as the PMC5H register and the lower 8 bits as the PMC5L register, they can be read or written in 8-bit or 1- bit units. 2. To read/write bits 8 to 15 of the PMC5 regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PMC5H register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 146 of 1817 Sep 19, 2011 (4) Port 5 function control register (PFC5) (V850ES/JJ3-E only) 0 0 0 0 0 0 PFC59 PFC58 PFC57 PFC56 PFC55 0 0 0 0 0 89101112131415 PFC5 (PFC5H) (PFC5L) After reset: 0000H R/W Address: PFC5 FFFFF46AH, PFC5L FFFFF46AH, PFC5H FFFFF46BH Remarks 1. For details of alternate f unction specification, see 4.3.5 (6) Port 5 alternate function specifications. 2. The PFC5 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PFC5 register as the PFC5H register and the lower 8 bits as the PFC5L register, they can be read or written in 8-bit or 1-bit units. 3. To read/write bits 8 to 15 of the PFC5 regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PFC5H register. (5) Port 5 function control expansion register L (PFCE5L) (V850ES/JJ3-E only) 0PFCE5L PFCE56 PFCE55 0 0 0 0 0 After reset: 00H R/W Address: FFFFF70AH Remark For details of alternate function specification, see 4.3.5 (6) Port 5 alternate function specifications. (6) Port 5 alternate function specifications (V850ES/JJ3-E only) PFC59 Specification of P59 pin alternate function

0 SCKF6 I/O

1 INTP25 input

PFC58 Specification of P58 pin alternate function

0 SOF6 output

1 RXDC7 input

PFC57 Specification of P57 pin alternate function

0 SIF6 input

1 TXDC7 output

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 147 of 1817 Sep 19, 2011 PFCE56 PFC56 Specification of P56 pin alternate function 0 0 SCL04 I/O 0 1 INTP24 input 1 0 UDMAAK1 output 1 1 Setting prohibited PFCE55 PFC55 Specification of P55 pin alternate function 0 0 SDA04 I/O 0 1 INTP23 input 1 0 UDMARQ1 input 1 1 Setting prohibited (7) Port 5 function register (PF5) (a) V850ES/JH3-E Normal output (CMOS output) N-ch open-drain output PF5n Control of normal output or N-ch open-drain output (n = 0 to 4) PF5 0 0 PF54 PF53 PF52 PF51 PF50 After reset: 00H R/W Address: FFFFFC6AH (b) V850ES/JJ3-E Normal output (CMOS output) N-ch open-drain output PF5n Control of normal output or N-ch open-drain output (n = 0 to 9) 0 0 0 0 0 PF59 PF58 PF57 PF56 PF55 PF54 PF53 PF52 PF51 PF50 89101112131415 PF5 (PF5H) (PF5L) After reset: 0000H R/W Address: PF5 FFFFFC6AH, PF5L FFFFFC6AH, PF5H FFFFFC6BH Remarks 1. The PF5 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PF5 register as the PF5H register and the lower 8 bits as the PF5L register, they can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PF5 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PF5H register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 148 of 1817 Sep 19, 2011

4.3.6 Port 7

Port 7 is a 10-bit (V850ES/JH3-E) and 12-bit (V850ES/JJ3-E) port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Table 4-11. Port 7 Alternate-Function Pins Pin No. Pin Name V850ES/ JH3-E V850ES/ JJ3-E Alternate-Function Pin Name I/O Remark P70 128 144 ANI0 Input P71 127 143 ANI1 Input P72 126 142 ANI2 Input P73 125 141 ANI3 Input P74 124 140 ANI4 Input P77 123 139 ANI5 Input P76 122 138 ANI6 Input P77 121 137 ANI7 Input P78 120 136 ANI8 Input P79 119 135 ANI9 Input P710 − 134 ANI10 Input P711 − 133 ANI11 Input

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 149 of 1817 Sep 19, 2011 (1) Port 7 register H, port 7 register L (P7H, P7L) (a) V850ES/JH3-E Outputs 0. Outputs 1. P7n Output data control (in output mode) (n = 0 to 9) P7H P7L After reset: 00H (output latch) R/W Address: P7L FFFFF40EH, P7H FFFFF40FH P77 P76 P75 P74 P73 P72 P71 P70 0 0 0 0 0 0 P79 P78 (b) V850ES/JJ3-E Outputs 0. Outputs 1. P7n Output data control (in output mode) (n = 0 to 11) P7H P7L After reset: 00H (output latch) R/W Address: P7L FFFFF40EH, P7H FFFFF40FH P77 P76 P75 P74 P73 P72 P71 P70 0 0 0 0 P711 P710 P79 P78 Caution Do not read or write the P7H and P7 L registers during A/D conversion (see 15.6 (4) Alternate I/O). Remark These registers cannot be accessed in 16-bit uni ts as the P7 register. They can be read or written in 8-bit or 1-bit units as the P7H and P7L registers.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 150 of 1817 Sep 19, 2011 (2) Port 7 mode register H, port 7 mode register L (PM7H, PM7L) (a) V850ES/JH3-E Output mode Input mode PM7n I/O mode control (n = 0 to 9) PM7H PM7L 1 1 1 1 1 PM79 PM78 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 After reset: FFH R/W Address: PM7L FFFFF42EH, PM7H FFFFF42FH (b) V850ES/JJ3-E Output mode Input mode PM7n I/O mode control (n = 0 to 11) PM7H PM7L 1 1 1 PM711 PM710 PM79 PM78 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 After reset: FFH R/W Address: PM7L FFFFF42EH, PM7H FFFFF42FH Caution When using the P7n pin as its alternate function (ANIn pin), set the PM7n bit to 1. Remark These registers cannot be accessed in 16-bit units as the PM7 register. They can be read or written in 8-bit or 1-bit units as the PM7H and PM7L registers.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 151 of 1817 Sep 19, 2011

4.3.7 Port 9

Port 9 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Table 4-12. Port 9 Alternate-Function Pins Pin No. Pin Name V850ES/ JH3-E V850ES/ JJ3-E Alternate-Function Pin Name I/O Remark P90 65 71 TOAB1T1/TOAB11/TIAB11/KR0 /INTP12/A0 I/O P91 66 72 TOAB1B1/TIAB10/KR1/TOAB10/A1 I/O P92 67 73 TOAB1T2/TOAB12/TIAB12/KR2 /INTP13/A2 I/O P93 68 74 TOAB1B2/TRGAB1/KR3/INTP14/A3 I/O P94 69 75 TOAB1T3/TOAB13/TIAB13/KR4 /INTP15/A4 I/O P95 70 76 TOAB1B3/EVTAB1/KR5/INTP16/A5 I/O P96 71 77 TECR0/TIT00/KR6/TOT00/A6 I/O P97 72 78 TENC00/TIT01/KR7/TOT01/A7 I/O P98 73 79 TENC01/INTP17/A8 I/O P99 74 80 SIE1/TXDC5/SDA03/A9 I/O P910 75 81 SOE1/RXDC5/SCL03/A10 I/O P911 76 82 SCKE1/TIAA50/TOAA50/A11 I/O P912 77 83 TOAB1OFF/INTP18/A12 I/O P913 78 84 SIF3/TXDB1/INTP19/A13 I/O P914 79 85 SOF3/RXDB1/INTP20/A14 I/O P915 80 86 SCKF3/TIAA51/TOAA51/A15 I/O Can be specified as an N-ch open- drain output Caution The P90 to P915 pins have hyst eresis characteristics in the input m ode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 152 of 1817 Sep 19, 2011 (1) Port 9 register (P9) P915 Outputs 0. Outputs 1. P9n Output data control (in output mode) (n = 0 to 15) P914 P913 P912 P911 P910 P99 P98 P97 P96 P95 P94 P93 P92 P91 P90 89101112131415 P9 (P9H) (P9L) After reset: 0000H (output latch) R/W Address: P9 FFFFF412H, P9L FFFFF412H, P9H FFFFF413H Remarks 1. The P9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the P9 register as the P9H register and the lower 8 bits as the P9L register, they can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the P9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the P9H register. (2) Port 9 mode register (PM9) PM97 Output mode Input mode PM9n I/O mode control (in output mode) (n = 0 to 15) PM96 PM95 PM94 PM93 PM92 PM91 PM90 PM915 PM914 PM913 PM912 PM911 PM910 PM99 PM98 89101112131415 PM9 (PM9H) (PM9L) After reset: FFFFH R/W Address: PM9 FFFFF432H, PM9L FFFFF432H, PM9H FFFFF433H Remarks 1. The PM9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PM9 register as the PM9H register and the lower 8 bits as the PM9L register, th ey can be read or written in 8-bit and 1-bit units. 2. To read/write bits 8 to 15 of the PM9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PM9H register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 153 of 1817 Sep 19, 2011 (3) Port 9 mode control register (PMC9) (1/2) I/O port SCKF3 I/O/TIAA51 input/TOAA51 output/A15 output PMC915 Specification of P915 pin operation mode PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90 PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98 89101112131415 I/O port SOF3 output/RXDB1 input/INTP20 input/A14 output PMC914 Specification of P914 pin operation mode I/O port SCKE1 I/O/TIAA50 input/TOAA50 output/A11 output PMC911 Specification of P911 pin operation mode I/O port SOE1 output/RXDC5 input/SCL03 I/O/A10 output PMC910 Specification of P910 pin operation mode I/O port SIE1 input/TXDC5 output/SDA03 I/O/A9 output PMC99 Specification of P99 pin operation mode I/O port SIF3 input/TXDB1 output/INTP19 input/A13 output PMC913 Specification of P913 pin operation mode I/O port TOAB1OFF input/INTP18 input/A12 output PMC912 Specification of P912 pin operation mode PMC9 (PMC9H) (PMC9L) After reset: 0000H R/W Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H I/O port TENC01 input/INTP17 input/A8 output PMC98 Specification of P98 pin operation mode Remarks 1. The PMC9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PMC9 register as the PMC9H register and the lower 8 bits as the PMC9L register, they can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PMC9 regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PMC9H register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 154 of 1817 Sep 19, 2011 (2/2) I/O port TENC00 input/TIT01 input/KR7 input/TOT01 output/A7 output PMC97 Specification of P97 pin operation mode I/O port TECR0 input/TIT00 input/KR06 input/TOT00 output/A6 output PMC96 Specification of P96 pin operation mode I/O port TOAB1B3 output/EVTAB1 input/KR5 input/INTP16 input/A5 output PMC95 Specification of P95 pin operation mode I/O port TOAB1T3 output/TOAB13 output/TIAB13 input/KR4 input/INTP15 input/A4 output PMC94 Specification of P94 pin operation mode I/O port TOAB1B2 output/TRGAB1 input/KR3 input/INTP14 input/A3 output PMC93 Specification of P93 pin operation mode I/O port TOAB1T2 output/TOAB12 output/TIAB12 input/KR2 input/INTP13 input/A2 output PMC92 Specification of P92 pin operation mode I/O port TOAB1B1 output/TIAB10 input/KR1 input/TOAB10 output/A1 output PMC91 Specification of P91 pin operation mode I/O port TOAB1T1 output/TOAB11 output/TIAB11 input/KR0 input/INTP12 input/A0 output PMC90 Specification of P90 pin operation mode Caution When using the A0 to A15 pins as the alternate functions of the P90 to P915 pins, be sure to set all 16 bits of the PMC9 register to FFFFH at once.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 155 of 1817 Sep 19, 2011 (4) Port 9 function control register (PFC9) Caution When performing separate ad dress bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after clearing the PFC9 register to FEFFH and the PFCE9 registers to EFFFH. PFC97 PFC96 PFC95 PFC94 PFC93 PFC92 PFC91 PFC90 PFC915 PFC914 PFC913 PFC912 PFC911 PFC910 PFC99 PFC98 89101112131415 After reset: 0000H R/W Address: PFC9 FFFFF472H, PFC9L FFFFF472H, PFC9H FFFFF473H PFC9 (PFC9H) (PFC9L) Remarks 1. For details of alternate f unction specification, see 4.3.7 (6) Port 9 alternate function specifications. 2. The PFC9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PFC9 register as the PFC9H register and the lower 8 bits as the PFC9L register, they can be read or written in 8-bit or 1-bit units. 3. To read/write bits 8 to 15 of the PFC9 regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PFC9H register. (5) Port 9 function control expansion register (PFCE9) Caution When performing separate ad dress bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after clearing the PFC9 register to FEFFH and the PFCE9 registers to 0000H. PFCE97 PFCE96 PFCE95 PFCE94 PFCE93 PFCE92 PFCE91 PFCE90 PFCE915 PFCE914 PFCE913 0 PFCE911 PFCE910 PFCE99 PFCE98 89101112131415 After reset: 0000H R/W Address: PFCE9 FFFFF712H, PFCE9L FFFFF712H, PFCE9H FFFFF713H PFCE9 (PFCE9H) (PFCE9L) Remarks 1. For details of alternate f unction specification, see 4.3.7 (6) Port 9 alternate function specifications. 2. The PFCE9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PFCE9 register as the PFCE9H register and the lower 8 bits as the PFCE9L register, they can be read or written in 8-bit or 1- bit units. 3. To read/write bits 8 to 15 of the PFCE9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PFCE9H register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 156 of 1817 Sep 19, 2011 (6) Port 9 alternate function specifications PFCE915 PFC915 Specification of P915 pin alternate function 0 0 SCKF3 I/O 0 1 TIAA51 input 1 0 TOAA51 output 1 1 A15 output PFCE914 PFC914 Specification of P914 pin alternate function 0 0 SOF3 output 0 1 RXDB1 input 1 0 INTP20 input 1 1 A14 output PFCE913 PFC913 Specification of P913 pin alternate function 0 0 SIF3 input 0 1 TXDB1 output 1 0 INTP19 input 1 1 A13 output PFC912 Specification of P912 pin alternate function

0 TOAB1OFF input/INTP18 input

1 A12 output

Caution TOAB1OFF and INTP18 are alternate functions of the P912 pin. When using the pin for the TOAB1OFF function, disable interrupt detection of INTP18, which is an alternate function (set the INTR9.INTR912 and INTF9.INTF912 bits to 0) . Also, when using the pin for the INTP18 function, disable edge detection of TOAB1OFF, which is an alternate function (set the HZA0CTL0. HZA0DCN0 and NZA0DCP0 bits to 00). PFCE911 PFC911 Specification of P911 pin alternate function 0 0 SCKE1 I/O 0 1 TIAA50 input 1 0 TOAA50 output 1 1 A11 output Caution The SCKE1 function is assigned to the PDH2 pi n as well as the P911 pin. When using the P911 pin for the SCKE1 function, do not specify the PDH2 pin to be used for this function. PFCE910 PFC910 Specification of P910 pin alternate function 0 0 SOE1 output 0 1 RXDC5 input 1 0 SCL03 I/O 1 1 A10 output

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 157 of 1817 Sep 19, 2011 PFCE99 PFC99 Specification of P99 pin alternate function 0 0 SIE1 input 0 1 TXDC5 output 1 0 SDA03 I/O 1 1 A9 output Caution The SIE1 function is assigned to the PDH0 pin as well as the P 99 pin. When using the P99 pin for the SIE1 function, do not set the PDH0 pin to be used for this function. PFCE98 PFC98 Specification of P98 pin alternate function 0 0 TENC01 input 0 1 INTP17 input 1 0 A8 output 1 1 Setting prohibited PFCE97 PFC97 Specification of P97 pin alternate function 0 0 TENC00 input 0 1 TIT01 input/KR7 input 1 0 TOT01 output 1 1 A7 output Caution KR7 and TIT01 are alternate functions. When using the pin fo r the TIT01 function, disable key return detection of KR7, which is the alternate function (set the KRM.KRM7 bit to 0). Also, when using the pin for the KR7 function, disable edge detection of TIT01, which is the alternate function (set the TTI0IOC1.TT0IS3 and TT0IS2 bits to 00). PFCE96 PFC96 Specification of P96 pin alternate function 0 0 TECR0 input 0 1 TIT00 input/KR6 input 1 0 TOT00 output 1 1 A6 output Caution KR6 and TIT00 are alternate functions. When using the pin fo r the TIT00 function, disable key return detection of KR6, which is the alternate function (set the KRM.KRM6 bit to 0). Also, when using the pin for the KR6 function, disable edge detection of TIT00, which is the alternate function (set the TTI0IOC1.TT0IS1 and TT0IS0 bits to 00). PFCE95 PFC95 Specification of P95 pin alternate function 0 0 TOAB1B3 output 0 1 EVTAB1 input/KR5 input 1 0 INTP16 input 1 1 A5 output Caution KR5 and EVTAB1 are alternate functions. Wh en using the pin for the EVTAB1 function, disable key return detection of KR5, which is the altern ate function (set the KRM.KRM5 bit to 0). Also, when using the pin for the KR5 function, disab le edge detection of EVTAB1, which is the alternate function (set the TAB1IOC2.TAB1EES1 and TAB1EES0 bits to 00).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 158 of 1817 Sep 19, 2011 PFCE94 PFC94 Specification of P94 pin alternate function 0 0 TOAB1T3 output/TOAB13 output 0 1 TIAB13 input/KR4 input 1 0 INTP15 input 1 1 A4 output Caution KR4 and TIAB13 are alternate functions. Wh en using the pin for the TIAB13 function, disable key return detection of KR4, which is the altern ate function (set the KRM.KRM4 bit to 0). Also, when using the pin for the KR4 function, disable edge detection of TIAB13, which is the alternate function (set the TAB1IOC1.TAB1IS7 and TAB1IS6 bits to 00). PFCE93 PFC93 Specification of P93 pin alternate function 0 0 TOAB1B2 output 0 1 TRGAB1 input/KR3 input 1 0 INTP14 input 1 1 A3 output Caution KR3 and TRGAB1 are alternate functions. Wh en using the pin for the TRGAB1 function, disable key return detection of KR3, which is the altern ate function (set the KRM.KRM3 bit to 0). Also, when using the pin for the KR3 function, disab le edge detection of TRGAB1, which is the alternate function (set the TAB1IOC2.TAB1ETS1 and TAB1ETS0 bits to 00). PFCE92 PFC92 Specification of P92 pin alternate function 0 0 TOAB1T2 output/TOAB12 output 0 1 TIAB12 input/KR2 input 1 0 INTP13 input 1 1 A2 output Caution KR2 and TIAB12 are alternate functions. Wh en using the pin for the TIAB12 function, disable key return detection of KR2, which is the altern ate function (set the KRM.KRM2 bit to 0). Also, when using the pin for the KR2 function, disable edge detection of TIAB12, which is the alternate function (set the TAB1IOC1.TAB1IS5 and TAB1IS4 bits to 00). PFCE91 PFC91 Specification of P91 pin alternate function 0 0 TOAB1B1 output 0 1 TIAB10 input/KR1 input 1 0 TOAB10 output 1 1 A1 output Caution KR1 and TIAB10 are alternate functions. Wh en using the pin for the TIAB10 function, disable key return detection of KR1, which is the altern ate function (set the KRM.KRM1 bit to 0). Also, when using the pin for the KR1 function, disable edge detection of TIAB10, which is the alternate function (set the TAB1IOC1.TAB1IS1 and TAB1IS0 bits to 00). PFCE90 PFC90 Specification of P90 pin alternate function 0 0 TOAB1T1 output/TOAB11 output 0 1 TIAB11 input/KR0 input 1 0 INTP12 input 1 1 A0 output Caution KR0 and TIAB11 are alternate functions. Wh en using the pin for the TIAB11 function, disable key return detection of KR0, which is the altern ate function (set the KRM.KRM0 bit to 0). Also, when using the pin for the KR0 function, disable edge detection of TIAB11, which is the alternate function (set the TAB1IOC1.TAB1IS3 and TAB1IS2 bits to 00).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 159 of 1817 Sep 19, 2011 (7) Port 9 function register (PF9) PF97 PF96 PF95 PF94 PF93 PF92 PF91 PF90 PF915 PF914 PF913 PF912 PF911 PF910 PF99 PF98 89101112131415 Normal output (CMOS output) N-ch open-drain output PF9n Control of normal output or N-ch open-drain output (n = 0 to 15) PF9 (PF9L) After reset: 0000H R/W Address: PF9 FFFFFC72H, PF9L FFFFFC72H Caution When output pins are pulled up to EV DD or higher, be sure to set the PF9n bit to 1. Remarks 1. The PF9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PF9 register as the PF9H register and the lower 8 bits as the PF9L register, they can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PF9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PF9H register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 160 of 1817 Sep 19, 2011

4.3.8 Port CM

Port CM is a 2-bit (V850ES/JH3-E)/4-bit (V850ES/JJ3-E) port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Table 4-13. Port CM Alternate-Function Pins Pin No. Pin Name V850ES/ JH3-E V850ES/ JJ3-E Alternate-Function Pin Name I/O Remark PCM0 86 92 WAIT Input PCM1 81 87 CLKOUT Output PCM2 − 119 HLDAK Output PCM3 − 120 HLDRQ Input (1) Port CM register (PCM) (a) V850ES/JH3-E Outputs 0. Outputs 1. PCMn Output data control (in output mode) (n = 0, 1) PCM 0 0 0 0 0 PCM1 PCM0 After reset: 00H (output latch) R/W Address: FFFFF00CH (b) V850ES/JJ3-E Outputs 0. Outputs 1. PCMn Output data control (in output mode) (n = 0 to 3) PCM 0 0 0 PCM3 PCM2 PCM1 PCM0 After reset: 00H (output latch) R/W Address: FFFFF00CH

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 161 of 1817 Sep 19, 2011 (2) Port CM mode register (PMCM) (a) V850ES/JH3-E Output mode Input mode PMCMn I/O mode control (n = 0, 1) PMCM 1 1 1 1 1 PMCM1 PMCM0 After reset: FFH R/W Address: FFFFF02CH (b) V850ES/JJ3-E Output mode Input mode PMCMn I/O mode control (n = 0 to 3) PMCM 1 1 1 PMCM3 PMCM2 PMCM1 PMCM0 After reset: FFH R/W Address: FFFFF02CH

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 162 of 1817 Sep 19, 2011 (3) Port CM mode control register (PMCCM) (a) V850ES/JH3-E 0PMCCM 0 0 0 0 0 PMCCM1 PMCCM0 I/O port CLKOUT output PMCCM1 Specification of PCM1 pin operation mode I/O port WAIT input PMCCM0 Specification of PCM0 pin operation mode After reset: 00H R/W Address: FFFFF04CH (b) V850ES/JJ3-E 0PMCCM 0 0 0 PMCCM3 PMCCM2 PMCCM1 PMCCM0 I/O port HLDRQ input PMCCM3 Specification of PCM3 pin operation mode I/O port HLDAK output PMCCM2 Specification of PCM2 pin operation mode I/O port CLKOUT output PMCCM1 Specification of PCM1 pin operation mode I/O port WAIT input PMCCM0 Specification of PCM0 pin operation mode After reset: 00H R/W Address: FFFFF04CH

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 163 of 1817 Sep 19, 2011

4.3.9 Port CS

Port CS is a 2-bit (V850ES/JH3-E)/3-bit (V850ES/JJ3-E) port for which I/O settings can be controlled in 1-bit units. Port CS includes the following alternate-function pins. Table 4-14. Port CM Alternate-Function Pins Pin No. Pin Name V850ES/ JH3-E V850ES/ JJ3-E Alternate-Function Pin Name I/O Remark PCS0 115 125 CS0 Output PCS2 116 126 CS2 Output PCS3 − 127 CS3 Output (1) Port CS register (PCS) (a) V850ES/JH3-E Outputs 0. Outputs 1. PCSn Output data control (in output mode) (n = 0, 2) PCS 0 0 0 0 PCS2 0 PCS0 After reset: 00H (output latch) R/W Address: FFFFF008H (b) V850ES/JJ3-E Outputs 0. Outputs 1. PCSn Output data control (in output mode) (n = 0, 2, 3) PCS 0 0 0 PCS3 PCS2 0 PCS0 After reset: 00H (output latch) R/W Address: FFFFF008H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 164 of 1817 Sep 19, 2011 (2) Port CS mode register (PMCS) (a) V850ES/JH3-E Output mode Input mode PMCSn I/O mode control (n = 0, 2) PMCS 1 1 1 1 PMCS2 1 PMCS0 After reset: FFH R/W Address: FFFFF028H (b) V850ES/JJ3-E Output mode Input mode PMCSn I/O mode control (n = 0, 2, 3) PMCS 1 1 1 PMCS3 PMCS2 1 PMCS0 After reset: FFH R/W Address: FFFFF028H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 165 of 1817 Sep 19, 2011 (3) Port CS mode control register (PMCCS) (a) V850ES/JH3-E 0PMCCS 0 0 0 0 PMCCS2 0 PMCCS0 I/O port CS2 output PMCCS2 Specification of PCS2 pin operation mode I/O port CS0 output PMCCS0 Specification of PCS0 pin operation mode After reset: 00H R/W Address: FFFFF048H (b) V850ES/JJ3-E 0PMCCS 0 0 0 PMCCS3 PMCCS2 0 PMCCS0 I/O port CS3 output PMCCS3 Specification of PCS3 pin operation mode I/O port CS2 output PMCCS2 Specification of PCS2 pin operation mode I/O port CS0 output PMCCS0 Specification of PCS0 pin operation mode After reset: 00H R/W Address: FFFFF048H

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4.3.10 Port CT

Port CT is a 4-bit port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Table 4-15. Port CT Alternate-Function Pins Pin No. Pin Name V850ES/ JH3-E V850ES/ JJ3-E Alternate-Function Pin Name I/O Remark PCT0 111 121 WR0 Output PCT1 112 122 WR1 Output PCT4 113 123 RD Output PCT6 114 124 ASTB Output (1) Port CT register (PCT) Outputs 0. Outputs 1. PCMn Output data control (in output mode) (n = 0, 1, 4, 6) PCT PCT6 0 PCT4 0 0 PCT1 PCT0 After reset: 00H (output latch) R/W Address: FFFFF00AH (2) Port CT mode register (PMCT) Output mode Input mode PMCTn I/O mode control (n = 0, 1, 4, 6) PMCT PMCT6 1 PMCT4 1 1 PMCT1 PMCT0 After reset: FFH R/W Address: FFFFF02AH

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 167 of 1817 Sep 19, 2011 (3) Port CT mode control register (PMCCT) 0PMCCT PMCCT6 0 PMCCT4 0 0 PMCCT1 PMCCT0 I/O port ASTB output PMCCT6 Specification of PCT6 pin operation mode I/O port RD output PMCCT4 Specification of PCT4 pin operation mode I/O port WR1 output PMCCT1 Specification of PCT1 pin operation mode I/O port WR0 output PMCCT0 Specification of PCT0 pin operation mode After reset: 00H R/W Address: FFFFF04AH

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4.3.11 Port DH

Port DH is an 6-bit (V850ES/JH3-E)/8-bit (V850ES/JJ3-E) port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Table 4-16. Port DH Alternate-Function Pins Pin No. Pin Name V850ES/ JH3-E V850ES/ JJ3-E Alternate-Function Pin Name I/O Remark PDH0 105 111 A16/SIE1 I/O PDH1 106 112 A17/SOE1 Output PDH2 107 113 A18/SCKE1 I/O PDH3 108 114 A19/SIF4/TXDB0 I/O PDH4 109 115 A20/SOF4/RXDB0 I/O PDH5 110 116 A21/SCKF4 I/O PDH6 − 117 A22 Output PDH7 − 118 A23 Output

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 169 of 1817 Sep 19, 2011 (1) Port DH register (PDH) (a) V850ES/JH3-E Outputs 0. Outputs 1. PDHn Output data control (in output mode) (n = 0 to 5) PDH After reset: 00H (output latch) R/W Address: FFFFF006H 0 0 PDH5 PDH4 PDH3 PDH2 PDH1 PDH0 (b) V850ES/JJ3-E Outputs 0. Outputs 1. PDHn Output data control (in output mode) (n = 0 to 7) PDH After reset: 00H (output latch) R/W Address: FFFFF006H PDH7 PDH6 PDH5 PDH4 PDH3 PDH2 PDH1 PDH0

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 170 of 1817 Sep 19, 2011 (2) Port DH mode register (PMDH) (a) V850ES/JH3-E Output mode Input mode PMDHn I/O mode control (n = 0 to 5)

1 PMDH5 PMDH4 PMDH3 PMDH2 PMDH1 PMDH0

After reset: FFH R/W Address: FFFFF026H PMDH (b) V850ES/JJ3-E PMDH7 Output mode Input mode PMDHn I/O mode control (n = 0 to 7) PMDH6 PMDH5 PMDH4 PMDH3 PMDH2 PMDH1 PMDH0 After reset: FFH R/W Address: FFFFF026H PMDH

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 171 of 1817 Sep 19, 2011 (3) Port DH mode control register (PMCDH) (1/2) (a) V850ES/JH3-E 0 0 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 After reset: 00H R/W Address: FFFFF046H I/O port A21 output/SCKF4 I/O PMCDH5 Specification of PDH5 pin operation mode I/O port A20 output/SOF4 output/RXDB0 input PMCDH4 Specification of PDH4 pin operation mode I/O port A19 output/SIF4 input/TXDB0 output PMCDH3 Specification of PDH3 pin operation mode I/O port A18 output/SCKE1 I/O PMCDH2 Specification of PDH2 pin operation mode I/O port A17 output/SOE1 output PMCDH1 Specification of PDH1 pin operation mode I/O port A16 output/SIE1 input PMCDH0 Specification of PDH0 pin operation mode PMCDH

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 172 of 1817 Sep 19, 2011 (2/2) (b) V850ES/JJ3-E I/O port A23 output PMCDH7 Specification of PDH7 pin operation mode PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 After reset: 00H R/W Address: FFFFF046H I/O port A22 output PMCDH6 Specification of PDH6 pin operation mode I/O port A21 output/SCKF4 I/O PMCDH5 Specification of PDH5 pin operation mode I/O port A20 output/SOF4 output/RXDB0 input PMCDH4 Specification of PDH4 pin operation mode I/O port A19 output/SIF4 input/TXDB0 output PMCDH3 Specification of PDH3 pin operation mode I/O port A18 output/SCKE1 I/O PMCDH2 Specification of PDH2 pin operation mode I/O port A17 output/SOE1 output PMCDH1 Specification of PDH1 pin operation mode I/O port A16 output/SIE1 input PMCDH0 Specification of PDH0 pin operation mode PMCDH

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 173 of 1817 Sep 19, 2011 (4) Port DH function control register (PFCDH) PFCDH After reset: 00H R/W Address: FFFFF056H 0 0 PFCDH5 PFCDH4 PFCDH3 PFCDH2 PFCDH1 PFCDH0 76543210 Remark For details of alternate-f unction specification, see 4.3.11 (6) Port DH alternate function specifications. (5) Port DH function control ex pansion register (PFCEDH) PFCEDH After reset: 00H R/W Address: FFFFF726H 0 0 0 PFCEDH4PFCEDH3 0 0 0 76543210 Remark For details of alternate f unction specification, see 4.3.11 (6) Port DH alternate function specifications. (6) Port DH alternate function specifications PFCDH5 Specification of PDH5 pin alternate function

0 A21 output

1 SCKF4 I/O

Caution The SCKF4 function is assi gned to the PDH5 pin as well as the P35 pin. When using the PDH5 pin for the SCKF4 function, do not set the P35 pin to be used for this function. PFCEDH4 PFCDH4 Specification of PDH4 pin alternate function 0 0 A20 output 0 1 SOF4 output 1 0 RXDB0 input 1 1 Setting prohibited Caution The SOF4/RXDB0 function is assigned to the PDH4 pin as well as the P34 pin. When using the PDH4 pin for the SOF4/RXDB0 function, do not set the P34 pin to be used for this function. PFCEDH3 PFCDH3 Specification of PDH3 pin alternate function 0 0 A19 output 0 1 SIF4 input 1 0 TXDB0 output 1 1 Setting prohibited Caution The SIF4/TXDB0 function is assigned to the P DH3 pin as well as the P33 pin. When using the PDH3 pin for the SIF4/TXDB0 function, do not set the P33 pin to be used for this function.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 174 of 1817 Sep 19, 2011 PFCDH2 Specification of PDH2 pin alternate function

0 A18 output

1 SCKE1 I/O

Caution The SCKE1 function is assi gned to the PDH2 pin as well as the P911 pin. When using the PDH2 pin for the SCKE1 function, do not set the P911 pin to be used for this function. PFCDH1 Specification of PDH1 pin alternate function

0 A17 output

1 SOE1 output

Caution The SOE1 function is assigned to the PDH1 pin as well as the P910 pin. When using the PDH1 pin for the SOE1 function, do not set the P910 pin to be used for this function. PFCDH0 Specification of PDH0 pin alternate function

0 A16 output

1 SIE1 input

Caution The SIE1 function is assigned to the PDH0 pi n as well as the P99 pin. When using the PDH0 pin for the SIE1 function, do not set the P99 pin to be used for this function.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 175 of 1817 Sep 19, 2011

4.3.12 Port DL

Port DL is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Table 4-17. Port DL Alternate-Function Pins Pin No. Pin Name V850ES/ JH3-E V850ES/ JJ3-E Alternate-Function Pin Name I/O Remark PDL0 87 93 AD0 I/O PDL1 88 94 AD1 I/O PDL2 89 95 AD2 I/O PDL3 90 96 AD3 I/O PDL4 91 97 AD4 I/O PDL5 92 98 AD5/FLMD1 Note I/O PDL6 93 99 AD6 I/O PDL7 94 100 AD7 I/O PDL8 95 101 AD8 I/O PDL9 96 102 AD9 I/O PDL10 97 103 AD10 I/O PDL11 98 104 AD11 I/O PDL12 99 105 AD12 I/O PDL13 100 106 AD13 I/O PDL14 103 109 AD14 I/O PDL15 104 110 AD15 I/O Note Since this pin is set in the flash memory progra mming mode, it does not need to be manipulated with the port control register. For details, see CHAPTER 33 FLASH MEMORY.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 176 of 1817 Sep 19, 2011 (1) Port DL register (PDL) PDL15 Outputs 0. Outputs 1. PDLn Output data control (in output mode) (n = 0 to 15) PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 89101112131415 PDL (PDLH) (PDLL) After reset: 0000H (output latch) R/W Address: PDL FFFFF004H, PDLL FFFFF004H, PDLH FFFFF005H Remarks 1. The PDL register can be read or written in 16-bit units. However, when using the higher 8 bits of the PDL register as the PDLH register and the lower 8 bits as the PDLL register, they can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PDL regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PDLH register. (2) Port DL mode register (PMDL) PMDL7 Output mode Input mode PMDLn I/O mode control (n = 0 to 15) PMDL6 PMDL5 PMDL4 PMDL3 PMDL2 PMDL1 PMDL0 PMDL15 PMDL14 PMDL13 PMDL12 PMDL11 PMDL10 PMDL9 PMDL8 89101112131415 PMDL (PMDLH) (PMDLL) After reset: FFFFH R/W Address: PMDL FFFFF024H, PMDLL FFFFF024H, PMDLH FFFFF025H Remarks 1. The PMDL register can be read or written in 16-bit units. However, when using the higher 8 bits of the PMDL register as the PMDLH register and the lower 8 bits as the PMDLL register, they can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PMDL regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PMDLH register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 177 of 1817 Sep 19, 2011 (3) Port DL mode control register (PMCDL) I/O port ADn I/O (address/data bus I/O) PMCDLn Specification of PDLn pin operation mode (n = 0 to 15) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 89101112131415 PMCDL (PMCDLH) (PMCDLL) After reset: 0000H R/W Address: PMCDL FFFFF044H, PMCDLL FFFFF044H, PMCDLH FFFFF045H Remarks 1. The PMCDL register can be read or written in 16-bit units. However, when using the higher 8 bits of the PMCDL register as the PMCDLH register and the lower 8 bits as the PMCD LL register, they can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PMCDL regi ster in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PMCDLH register.

4.4 Port Register Settings When Alternate Function Is Used

Table 4-18 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each pin.

R01UH0290EJ0300 Rev.3.00 Page 178 of 1817 Sep 19, 2011 V850ES/JJ3-E, V850ES/JH3-E C H A P T E R 4 P O R T F U N C T I O N S Table 4-18. Using Port Pin as Alternate-Function Pin (1/13) Alternate Function Pin Name Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register Other Bits (Registers) P02 NMI Input P02 = Setting not required PM02 = Setting not required PMC02 = 1 − − INTP00 Input P03 = Setting not required PM03 = Setting not required PMC03 = 1 PFCE03 = 0 PFC03 = 0 ADTRG Input P03 = Setting not required PM03 = Setting not required PMC03 = 1 PFCE03 = 0 PFC03 = 1 P03 EXCLK Input P03 = Setting not required PM03 = Setting not required PMC03 = 1 PFCE03 = 1 PFC03 = 0 TIAB02 Input P20 = Setting not required PM20 = Setting not required PMC20 = 1 PFCE20 = 0 PFC20 = 0 TOAB03 Output P20 = Setting not required PM20 = Setting not required PMC20 = 1 PFCE20 = 0 PFC20 = 1 P20 INTP01 Input P20 = Setting not required PM20 = Setting not required PMC20 = 1 PFCE20 = 1 PFC20 = 0 TIAB00 Input P21 = Setting not required PM21 = Setting not required PMC21= 1 PFCE21 = 0 PFC21 = 0 TOAB00 Output P21 = Setting not required PM21 = Setting not required PMC21= 1 PFCE21 = 0 PFC21 = 1 RTCDIV Output P21 = Setting not required PM21 = Setting not required PMC21= 1 PFCE21 = 1 PFC21 = 0 P21 RTCCL Output P21 = Setting not required PM21 = Setting not required PMC21= 1 PFCE21 = 1 PFC21 = 1 TIAB01 Input P22 = Setting not required PM22 = Setting not required PMC22= 1 PFCE22 = 0 PFC22 = 0 TOAB00 Output P22 = Setting not required PM22 = Setting not required PMC22= 1 PFCE22 = 0 PFC22 = 1 RTC1HZ Output P22 = Setting not required PM22 = Setting not required PMC22= 1 PFCE22 = 1 PFC22 = 0 P22 INTP02 Input P22 = Setting not required PM22 = Setting not required PMC22= 1 PFCE22 = 1 PFC22 = 1 SIF1 Input P23 = Setting not required PM23 = Setting not required PMC23= 1 PFCE23 = 0 PFC23 = 0 TXDC1 Output P23 = Setting not required PM23 = Setting not required PMC23= 1 PFCE23 = 0 PFC23 = 1 SDA00 I/O P23 = Setting not required PM23 = Setting not required PMC23= 1 PFCE23 = 1 PFC23 = 0 PF23 (PF2) = 1 P23 INTP03 Input P23 = Setting not required PM23 = Setting not required PMC23= 1 PFCE23 = 1 PFC23 = 1 SOF1 Output P24 = Setting not required PM24 = Setting not required PMC24= 1 PFCE24 = 0 PFC24 = 0 RXDC1 Input P24 = Setting not required PM24 = Setting not required PMC24= 1 PFCE24 = 0 PFC24 = 1 SCL00 I/O P24 = Setting not required PM24 = Setting not required PMC24= 1 PFCE24 = 1 PFC24 = 0 PF24 (PF2)= 1 P24 INTP04 Input P24 = Setting not required PM24 = Setting not required PMC24= 1 PFCE24 = 1 PFC24 = 1

R01UH0290EJ0300 Rev.3.00 Page 179 of 1817 Sep 19, 2011 V850ES/JJ3-E, V850ES/JH3-E C H A P T E R 4 P O R T F U N C T I O N S Table 4-18. Using Port Pin as Alternate-Function Pin (2/13) Alternate Function Pin Name Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register Other Bits (Registers) SCKF1 I/O P25 = Setting not required PM25 = Setting not required PMC25= 1 PFCE25 = 0 PFC25 = 0 TIAB30 Input P25 = Setting not required PM25 = Setting not required PMC25= 1 PFCE25 = 0 PFC25 = 1 TOAB30 Output P25 = Setting not required PM25 = Setting not required PMC25= 1 PFCE25 = 1 PFC25 = 0 P25 UDMARQ0 Input P25 = Setting not required PM25 = Setting not required PMC25= 1 PFCE25 = 1 PFC25 = 1 TIAB31 Input P26 = Setting not required PM26 = Setting not required PMC26= 1 PFCE26 = 0 PFC26 = 0 TOAB31 Output P26 = Setting not required PM26 = Setting not required PMC26= 1 PFCE26 = 0 PFC26 = 1 INTP05 Input P26 = Setting not required PM26 = Setting not required PMC26= 1 PFCE26 = 1 PFC26 = 0 P26 UDMAAK0 Output P26 = Setting not required PM26 = Setting not required PMC26= 1 PFCE26 = 1 PFC26 = 1 TIAB03 Input P27 = Setting not required PM27 = Setting not required PMC27= 1 PFCE27 = 0 PFC27 = 0 TOAB03 Output P27 = Setting not required PM27 = Setting not required PMC27= 1 PFCE27 = 0 PFC27 = 1 P27 Note INTP21 Input P27 = Setting not required PM27 = Setting not required PMC27= 1 PFCE27 = 1 PFC27 = 0 TXDC0 Output P30 = Setting not required PM30 = Setting not required PMC30= 1 PFCE30 = 0 PFC30 = 0 SIF2 Input P30 = Setting not required PM30 = Setting not required PMC30= 1 PFCE30 = 0 PFC30 = 1 INTP05 Input P30 = Setting not required PM30 = Setting not required PMC30= 1 PFCE30 = 1 PFC30 = 0 P30 UDMAAK0 Output P30 = Setting not required PM30 = Setting not required PMC30= 1 PFCE30 = 1 PFC30 = 1 RXDC0 Input P31 = Setting not required PM31 = Setting not required PMC31= 1 PFCE31 = 0 PFC31 = 0 SOF2 Output P31 = Setting not required PM31 = Setting not required PMC31= 1 PFCE31 = 0 PFC31 = 1 TIAA01 Input P31 = Setting not required PM31 = Setting not required PMC31= 1 PFCE31 = 1 PFC31 = 0 P31 TOAA01 Output P31 = Setting not required PM31 = Setting not required PMC31= 1 PFCE31 = 1 PFC31 = 1 ASCKC0 I/O P32 = Setting not required PM32 = Setting not required PMC32= 1 PFCE32 = 0 PFC32 = 0 SCKF2 I/O P32 = Setting not required PM32 = Setting not required PMC32= 1 PFCE32 = 0 PFC32 = 1 TIAA10 Input P32 = Setting not required PM32 = Setting not required PMC32= 1 PFCE32 = 1 PFC32 = 0 P32 TOAA10 Output P32 = Setting not required PM32 = Setting not required PMC32= 1 PFCE32 = 1 PFC32 = 1

R01UH0290EJ0300 Rev.3.00 Page 180 of 1817 Sep 19, 2011 V850ES/JJ3-E, V850ES/JH3-E C H A P T E R 4 P O R T F U N C T I O N S Table 4-18. Using Port Pin as Alternate-Function Pin (3/13) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register Other Bits (Registers) SIF4 Note 1 Input P33 = Setting not required PM33 = Setting not required PMC33= 1 PFCE33 = 0 PFC33 = 0 TXDB0 Output P33 = Setting not required PM33 = Setting not required PMC33= 1 PFCE33 = 0 PFC33 = 1 TIAA11 Input P33 = Setting not required PM33 = Setting not required PMC33= 1 PFCE33 = 1 PFC33 = 0 P33 TOAA11 Output P33 = Setting not required PM33 = Setting not required PMC33= 1 PFCE33 = 1 PFC33 = 1 SOF4 Note 2 Output P34 = Setting not required PM34 = Setting not required PMC34 = 1 PFCE34 = 0 PFC34 = 0 RXDB0 Input P34 = Setting not required PM34 = Setting not required PMC34 = 1 PFCE34 = 0 PFC34 = 1 TIAA20 Input P34 = Setting not required PM34 = Setting not required PMC34 = 1 PFCE34 = 1 PFC34 = 0 P34 TOAA20 Output P34 = Setting not required PM34 = Setting not required PMC34 = 1 PFCE34 = 1 PFC34 = 1 SCKF4 Note 3 I/O P35 = Setting not required PM35 = Setting not required PMC35 = 1 PFCE35 = 0 PFC35 = 0 TIAA21 Input P35 = Setting not required PM35 = Setting not required PMC35 = 1 PFCE35 = 0 PFC35 = 1 TOAA21 Output P35 = Setting not required PM35 = Setting not required PMC35 = 1 PFCE35 = 1 PFC35 = 0 TOAA1OFF Note 4 Input P35 = Setting not required PM35 = Setting not required PMC35 = 1 PFCE35 = 1 PFC35 = 1 P35 INTP06 Note 4 Input P35 = Setting not required PM35 = Setting not required PMC35 = 1 PFCE35 = 1 PFC35 = 1 TXDC2 Output P36 = Setting not required PM36 = Setting not required PMC36 = 1 PFCE36 = 0 PFC36 = 0 SDA02 I/O P36 = Setting not required PM36 = Setting not required PMC36 = 1 PFCE36 = 0 PFC36 = 1 PF36 (PF3) = 1 P36 CTXD0 Note 5 Input P36 = Setting not required PM36 = Setting not required PMC36 = 1 PFCE36 = 1 PFC36 = 0 RXDC2 Input P37 = Setting not required PM37 = Setting not required PMC37 = 1 PFCE37 = 0 PFC37 = 0 SCL02 I/O P37 = Setting not required PM37 = Setting not required PMC37 = 1 PFCE37 = 0 PFC37 = 1 PF37 (PF3) = 1 P37 CRXD0 Note 5 Input P37 = Setting not required PM37 = Setting not required PMC37 = 1 PFCE37 = 1 PFC37 = 0 Notes 1. The SIF4 function is assigned to the PDH3 pin as well as the P33 pin. When using t he P33 pin for the SIF4 function, do not set the PDH3 pin to be used for this function. 2. The SOF4 function is assigned to the PDH4 pin as well as the P34 pin. When using the P34 pin for the SOF4 function, do not set the PDH4 pin to be used for this function. 3. The SCKF4 function is assigned to the PDH5 pin as well as the P35 pin. When using t he P35 pin for the SCKF4 function, do not set the PDH5 pin to be used for this function. 4. TOAA1OFF and INTP09 are alternate functions. When using the pi n for the TOAA1OFF function, disable edge detection of INTP09, which is the alternate function. Also, when using the pin for the INTP09 function, stop the high-impedance output controller. μPD70F3783 and 70F3786 only

R01UH0290EJ0300 Rev.3.00 Page 181 of 1817 Sep 19, 2011 V850ES/JJ3-E, V850ES/JH3-E C H A P T E R 4 P O R T F U N C T I O N S Table 4-18. Using Port Pin as Alternate-Function Pin (4/13) Alternate Function Pin Name Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register Other Bits (Registers) SIF0 Input P40 = Setting not required PM40 = Setting not required PMC40 = 1 PFCE40 = 0 PFC40 = 0 TXDC3 Output P40 = Setting not required PM40 = Setting not required PMC40 = 1 PFCE40 = 0 PFC40 = 1 SDA01 I/O P40 = Setting not required PM40 = Setting not required PMC40 = 1 PFCE40 = 1 PFC40 = 0 PF40 (PF4) = 1 P40 RTP00 Output P40 = Setting not required PM40 = Setting not required PMC40 = 1 PFCE40 = 1 PFC40 = 1 SOF0 Output P41 = Setting not required PM41 = Setting not required PMC41 = 1 PFCE41 = 0 PFC41 = 0 RXDC3 Input P41 = Setting not required PM41 = Setting not required PMC41 = 1 PFCE41 = 0 PFC41 = 1 SCL01 I/O P41 = Setting not required PM41 = Setting not required PMC41 = 1 PFCE41 = 1 PFC41 = 0 PF41 (PF4) = 1 P41 RTP01 Output P41 = Setting not required PM41 = Setting not required PMC41 = 1 PFCE41 = 1 PFC41 = 1 SCKF0 I/O P42 = Setting not required PM42 = Setting not required PMC42 = 1 PFCE42 = 0 PFC42 = 0 TIAA40 Input P42 = Setting not required PM42 = Setting not required PMC42 = 1 PFCE42 = 0 PFC42 = 1 TOAA40 Output P42 = Setting not required PM42 = Setting not required PMC42 = 1 PFCE42 = 1 PFC42 = 0 P42 RTP02 Output P42 = Setting not required PM42 = Setting not required PMC42 = 1 PFCE42 = 1 PFC42 = 1 SIE0 Input P43 = Setting not required PM43 = Setting not required PMC43 = 1 PFCE43 = 0 PFC43 = 0 TXDC4 Output P43 = Setting not required PM43 = Setting not required PMC43 = 1 PFCE43 = 0 PFC43 = 1 RTP03 Output P43 = Setting not required PM43 = Setting not required PMC43 = 1 PFCE43 = 1 PFC43 = 0 P43 HLDAK Note Output P43 = Setting not required PM43 = Setting not required PMC43 = 1 PFCE43 = 1 PFC43 = 1 SOE0 Output P44 = Setting not required PM44 = Setting not required PMC44 = 1 PFCE44 = 0 PFC44 = 0 RXDC4 Input P44 = Setting not required PM44 = Setting not required PMC44 = 1 PFCE44 = 0 PFC44 = 1 RTP04 Output P44 = Setting not required PM44 = Setting not required PMC44 = 1 PFCE44 = 1 PFC44 = 0 P44 HLDRQ Note Output P44 = Setting not required PM44 = Setting not required PMC44 = 1 PFCE44 = 1 PFC44 = 1 SCKE0 Output P45 = Setting not required PM45 = Setting not required PMC45 = 1 PFCE45 = 0 PFC45 = 0 TIAA41 Input P45 = Setting not required PM45 = Setting not required PMC45 = 1 PFCE45 = 0 PFC45 = 1 TOAA41 Output P45 = Setting not required PM45 = Setting not required PMC45 = 1 PFCE45 = 1 PFC45 = 0 P45 RTP05 Output P45 = Setting not required PM45 = Setting not required PMC45 = 1 PFCE45 = 1 PFC45 = 1 Note V850ES/JH3-E only

R01UH0290EJ0300 Rev.3.00 Page 182 of 1817 Sep 19, 2011 V850ES/JJ3-E, V850ES/JH3-E C H A P T E R 4 P O R T F U N C T I O N S Table 4-18. Using Port Pin as Alternate-Function Pin (5/13) Alternate Function Pin Name Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register Other Bits (Registers) SIF5 Input P46 = Setting not required PM46 = Setting not required PMC46 = 1 PFCE46 = 0 PFC46 = 0 TXDC6 Output P46 = Setting not required PM46 = Setting not required PMC46 = 1 PFCE46 = 0 PFC46 = 1 P46 Note RTP06 Output P46 = Setting not required PM46 = Setting not required PMC46 = 1 PFCE46 = 1 PFC46 = 0 SOF5 Output P47 = Setting not required PM47 = Setting not required PMC47 = 1 PFCE47 = 0 PFC47 = 0 RXDC6 Input P47 = Setting not required PM47 = Setting not required PMC47 = 1 PFCE47 = 0 PFC47 = 1 P47 Note RTP07 Output P47 = Setting not required PM47 = Setting not required PMC47 = 1 PFCE47 = 1 PFC47 = 0 SCKF5 I/O P48 = Setting not required PM48 = Setting not required PMC48 = 1 − PFC48 = 0 P48 Note INTP22 Input P48 = Setting not required PM48 = Setting not required PMC48 = 1 − PFC48 = 1 INTP07 Input P50 = Setting not required PM50 = Setting not required PMC50 = 1 − − P50 DDI Input P50 = Setting not required PM50 = Setting not required PMC50 = Setting not required − − OCDM0 (OCDM) = 1 INTP08 Input P51 = Setting not required PM51 = Setting not required PMC51 = 1 − − P51 DDO Output P51 = Setting not required PM51 = Setting not required PMC51 = Setting not required − − OCDM0 (OCDM) = 1 INTP09 Input P52 = Setting not required PM52 = Setting not required PMC52 = 1 − − P52 DCK Input P52 = Setting not required PM52 = Setting not required PMC52 = Setting not required − − OCDM0 (OCDM) = 1 INTP10 Input P53 = Setting not required PM53 = Setting not required PMC53 = 1 − − P53 DMS Input P53 = Setting not required PM53 = Setting not required PMC53 = Setting not required − − OCDM0 (OCDM) = 1 INTP11 Input P54 = Setting not required PM54 = Setting not required PMC54 = 1 − − P54 DRST Input P54 = Setting not required PM54 = Setting not required PMC54 = Setting not required − − OCDM0 (OCDM) = 1 SDA04 I/O P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 0 PFC55 = 0 PF55 (PF5) = 1 INTP23 Input P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 0 PFC55 = 0 P55 Note UDMARQ1 Input P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 0 PFC55 = 1 Note V850ES/JJ3-E only

R01UH0290EJ0300 Rev.3.00 Page 183 of 1817 Sep 19, 2011 V850ES/JJ3-E, V850ES/JH3-E C H A P T E R 4 P O R T F U N C T I O N S Table 4-18. Using Port Pin as Alternate-Function Pin (6/13) Alternate Function Pin Name Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register Other Bits (Registers) SCL04 I/O P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 0 PFC55 = 0 PF55 (PF5) = 1 INTP24 Input P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 0 PFC55 = 1 P56 Note UDMAAK1 Output P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 1 PFC55 = 1 SIF6 Input P57 = Setting not required PM57 = Setting not required PMC57 = 1 − PFC57 = 0 P57 Note TXDC7 Output P57 = Setting not required PM57 = Setting not required PMC57 = 1 − PFC57 = 1 SOF6 Output P58 = Setting not required PM58 = Setting not required PMC58 = 1 − PFC58 = 0 P58 Note RXDC7 Input P58 = Setting not required PM58 = Setting not required PMC58 = 1 − PFC58 = 1 SCKF6 I/O P59 = Setting not required PM59 = Setting not required PMC59 = 1 − PFC59 = 0 P59 Note INTP25 Input P59 = Setting not required PM59 = Setting not required PMC59 = 1 − PFC59 = 1 P70 ANI0 Input P70 = Setting not required PM70 = 1 − − − P71 ANI1 Input P71 = Setting not required PM71 = 1 − − − P72 ANI2 Input P72 = Setting not required PM72 = 1 − − − P73 ANI3 Input P73 = Setting not required PM73 = 1 − − − P74 ANI4 Input P74 = Setting not required PM74 = 1 − − − P75 ANI5 Input P75 = Setting not required PM75 = 1 − − − P76 ANI6 Input P76 = Setting not required PM76 = 1 − − − P77 ANI7 Input P77 = Setting not required PM77 = 1 − − − P78 ANI8 Input P78 = Setting not required PM78 = 1 − − − P79 ANI9 Input P79 = Setting not required PM79 = 1 − − − P710 Note ANI10 Input P710 = Setting not required PM710 = 1 − − − P711 Note ANI11 Input P711 = Setting not required PM711 = 1 − − − Note V850ES/JJ3-E only

R01UH0290EJ0300 Rev.3.00 Page 184 of 1817 Sep 19, 2011 V850ES/JJ3-E, V850ES/JH3-E C H A P T E R 4 P O R T F U N C T I O N S Table 4-18. Using Port Pin as Alternate-Function Pin (7/13) Alternate Function Pin Name Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register Other Bits (Registers) TOAB1T1 Output P90 = Setting not required PM90 = Setting not required PMC90 = 1 PFCE90 = 0 PFC90 = 0 TOAB11 Output P90 = Setting not required PM90 = Setting not required PMC90 = 1 PFCE90 = 0 PFC90 = 0 TIAB11 Note 1 Input P90 = Setting not required PM90 = Setting not required PMC90 = 1 PFCE90 = 0 PFC90 = 1 KRM0 (KRM) = 0 KR0 Note 1 Input P90 = Setting not required PM90 = Setting not required PMC90 = 1 PFCE90 = 0 PFC90 = 1 TAB1TIS3, TAB1TIS2 (TAB1I0C1) = 0 INTP12 Input P90 = Setting not required PM90 = Setting not required PMC90 = 1 PFCE90 = 1 PFC90 = 0 P90 Note 2 Output P90 = Setting not required PM90 = Setting not required PMC90 = 1 PFCE90 = 1 PFC90 = 1 TOAB1B1 Output P91 = Setting not required PM91 = Setting not required PMC91 = 1 PFCE91 = 0 PFC91 = 0 TIAB10 Note 3 Input P91 = Setting not required PM91 = Setting not required PMC91 = 1 PFCE91 = 0 PFC91 = 1 KRM1 (KRM) = 0 KR1 Note 3 Input P91 = Setting not required PM91 = Setting not required PMC91 = 1 PFCE91 = 0 PFC91 = 1 TAB1TIS1, TAB1TIS0 (TAB1I0C1) = 0 TOAB10 Output P91 = Setting not required PM91 = Setting not required PMC91 = 1 PFCE91 = 1 PFC91 = 0 PF91 (PF9) = 1 P91 Note 2 Output P91 = Setting not required PM91 = Setting not required PMC91 = 1 PFCE91 = 1 PFC91 = 1 TOAB1T2 Output P92 = Setting not required PM92 = Setting not required PMC92 = 1 PFCE92 = 0 PFC92 = 0 TOAB12 Output P92 = Setting not required PM92 = Setting not required PMC92 = 1 PFCE92 = 0 PFC92 = 0 TIAB12 Note 4 Input P92 = Setting not required PM92 = Setting not required PMC92 = 1 PFCE92 = 0 PFC92 = 1 KRM2 (KRM) = 0 KR2 Note 4 Input P92 = Setting not required PM92 = Setting not required PMC92 = 1 PFCE92 = 0 PFC92 = 1 TAB1TIS5, TAB1TIS4 (TAB1I0C1) = 0 INTP13 Input P92 = Setting not required PM92 = Setting not required PMC92 = 1 PFCE92 = 1 PFC92 = 0 P92 Note 1 Output P92 = Setting not required PM92 = Setting not required PMC92 = 1 PFCE92 = 1 PFC92 = 1 Notes 1. KR0 and TIAB11 are alternate functions. W hen using the pin for the TIAB11 function, di sable key return detection of KR0, which is the alternate function (set the KRM.KRM0 bit to 0). Also, when using the pin for the KR0 func tion, disable edge detection of TIAB11, which is the alternate function (set the TAB1IOC1.TAB1IS3 and TAB1IS2 bits to 00). 2. When using as the A0 to A15 pins, be sure to set all 16 bits of the PMC9 register to FFFFH at once. 3. KR1 and TIAB10 are alternate functions. W hen using the pin for the TIAB10 function, di sable key return detection of KR1, which is the alternate function (set the KRM.KRM1 bit to 0). Also, when using the pin for the KR1 func tion, disable edge detection of TIAB10, which is the alternate function (set the TAB1IOC1.TAB1IS1 and TAB1IS0 bits to 00). 4. KR2 and TIAB12 are alternate functions. W hen using the pin for the TIAB12 function, di sable key return detection of KR2, which is the alternate function (set the KRM.KRM2 bit to 0). Also, when using the pin for the KR2 func tion, disable edge detection of TIAB12, which is the alternate function (set the TAB1IOC1.TAB1IS5 and TAB1IS4 bits to 00).

R01UH0290EJ0300 Rev.3.00 Page 185 of 1817 Sep 19, 2011 V850ES/JJ3-E, V850ES/JH3-E C H A P T E R 4 P O R T F U N C T I O N S Table 4-18. Using Port Pin as Alternate-Function Pin (8/13) Alternate Function Pin Name Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register Other Bits (Registers) TOAB1B2 Output P93 = Setting not required PM93 = Setting not required PMC93 = 1 PFCE93 = 0 PFC93 = 0 TRGAB1 Note 1 Input P93 = Setting not required PM93 = Setting not required PMC93 = 1 PFCE93 = 0 PFC93 = 1 KRM3 (KRM) = 0 KR3 Note 1 Input P93 = Setting not required PM93 = Setting not required PMC93 = 1 PFCE93 = 0 PFC93 = 1 TAB1ETS1, TAB1ETS0 (TAB1I0C1) = 0 INTP14 Input P93 = Setting not required PM93 = Setting not required PMC93 = 1 PFCE93 = 1 PFC93 = 0 P93 Note 2 Output P93 = Setting not required PM93 = Setting not required PMC93 = 1 PFCE93 = 1 PFC93 = 1 TOAB1T3 Output P94 = Setting not required PM94 = Setting not required PMC94 = 1 PFCE94 = 0 PFC94 = 0 TOAB13 Output P94 = Setting not required PM94 = Setting not required PMC94 = 1 PFCE94 = 0 PFC94 = 0 TIAB13 Note 3 Input P94 = Setting not required PM94 = Setting not required PMC94 = 1 PFCE94 = 0 PFC94 = 1 KRM2 (KRM) = 0 KR 4Note 3 Input P94 = Setting not required PM94 = Setting not required PMC94 = 1 PFCE94 = 0 PFC94 = 1 TAB1TIS7, TAB1TIS6 (TAB1I0C1) = 0 INTP15 Input P94 = Setting not required PM94 = Setting not required PMC94 = 1 PFCE94 = 1 PFC94 = 0 P94 Note 2 Output P94 = Setting not required PM94 = Setting not required PMC94 = 1 PFCE94 = 1 PFC94 = 1 TOAB1B3 Output P95 = Setting not required PM95 = Setting not required PMC95 = 1 PFCE95 = 0 PFC95 = 0 EVTAB1 Note 4 Input P95 = Setting not required PM95 = Setting not required PMC95 = 1 PFCE95 = 0 PFC95 = 1 KRM5 (KRM) = 0 KR5 Note 4 Input P95 = Setting not required PM95 = Setting not required PMC95 = 1 PFCE95 = 0 PFC95 = 1 TAB1EES1, TAB1EES0 (TAB1I0C1) = 0 INTP16 Input P95 = Setting not required PM95 = Setting not required PMC95 = 1 PFCE95 = 1 PFC95 = 0 P95 Note 2 Output P95 = Setting not required PM95 = Setting not required PMC95 = 1 PFCE95 = 1 PFC95 = 1 Notes 1. KR3 and TRGAB1 are alternate functions. When using the pin for the TRGAB1 function, disable key return detection of KR3, which is the alternate function (set the KRM.KRM3 bit to 0). Also, when using the pin for the KR3 functi on, disable edge detection of TRGAB1, which is the alternate fu nction (set the TAB1IOC2.TAB1ETS1 and TAB1ETS0 bits to 00). 2. When using as the A0 to A15 pins, be sure to set all 16 bits of the PMC9 register to FFFFH at once. 3. KR4 and TIAB13 are alternate functions. W hen using the pin for the TIAB13 function, di sable key return detection of KR4, which is the alternate function (set the KRM.KRM4 bit to 0). Also, when using the pin for the KR4 func tion, disable edge detection of TIAB13, which is the alternate function (set the TAB1IOC1.TAB1IS7 and TAB1IS6 bits to 00). 4. KR5 and EVTAB1 are alternate functions. When using the pin for t he EVTAB1 function, disable key return detection of KR5, which is the alternate function (set the KRM.KRM5 bit to 0). Also, when using the pin for the KR5 functi on, disable edge detection of EV TAB1, which is the alternate fu nction (set the TAB1IOC2.TAB1EES1 and TAB1EES0 bits to 00).

R01UH0290EJ0300 Rev.3.00 Page 186 of 1817 Sep 19, 2011 V850ES/JJ3-E, V850ES/JH3-E C H A P T E R 4 P O R T F U N C T I O N S Table 4-18. Using Port Pin as Alternate-Function Pin (9/13) Alternate Function Pin Name Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register Other Bits (Registers) TECR0 Input P96 = Setting not required PM96 = Setting not required PMC96 = 1 PFCE96 = 0 PFC96 = 0 TIT00 Note 1 Input P96 = Setting not required PM96 = Setting not required PMC96 = 1 PFCE96 = 1 PFC96 = 0 KRM6 (KRM) = 0 KR6 Note 1 Input P96 = Setting not required PM96 = Setting not required PMC96 = 1 PFCE96 = 1 PFC96 = 0 TT0IS1, TT0IS0 (TTI0IOC1) = 0 TOT00 Output P96 = Setting not required PM96 = Setting not required PMC96 = 1 PFCE96 = 1 PFC96 = 0 P96 Note 2 Output P96 = Setting not required PM96 = Setting not required PMC96 = 1 PFCE96 = 1 PFC96 = 1 Note 2 TENC00 Input P97 = Setting not required PM97 = Setting not required PMC97 = 1 PFCE97 = 0 PFC97 = 0 TIT01 Note 3 Input P97 = Setting not required PM97 = Setting not required PMC97 = 1 PFCE97 = 0 PFC97 = 1 KRM7 (KRM) = 0 KR7 Note 3 Input P97 = Setting not required PM97 = Setting not required PMC97 = 1 PFCE97 = 0 PFC97 = 1 TT0IS3, TT0IS2 (TTI0IOC1) = 0 TOT01 Output P97 = Setting not required PM97 = Setting not required PMC97 = 1 PFCE97 = 1 PFC97 = 0 P97 Note 2 Output P97 = Setting not required PM97 = Setting not required PMC97 = 1 PFCE97 = 1 PFC97 = 1 TENC01 Input P98 = Setting not required PM98 = Setting not required PMC98 = 1 PFCE98 = 0 PFC98 = 0 INTP17 Input P98 = Setting not required PM98 = Setting not required PMC98 = 1 PFCE98 = 0 PFC98 = 1 P98 Note 2 Output P98 = Setting not required PM98 = Setting not required PMC98 = 1 PFCE98 = 1 PFC98 = 0 SIE1 Note 4 Input P99 = Setting not required PM99 = Setting not required PMC99 = 1 PFCE99 = 0 PFC99 = 0 TXDC5 Output P99 = Setting not required PM99 = Setting not required PMC99 = 1 PFCE99 = 0 PFC99 = 1 SDA03 I/O P99 = Setting not required PM99 = Setting not required PMC99 = 1 PFCE99 = 1 PFC99 = 0 P99 Note 2 Output P99 = Setting not required PM99 = Setting not required PMC99 = 1 PFCE99 = 1 PFC99 = 1 Notes 1. KR6 and TIT00 are alternate functions. W hen using the pin for the TIT 00 function, disable key return detection of KR6, which is the alternate function (set the KRM.KRM6 bit to 0). Also, when using the pin for the KR6 functi on, disable edge detection of TIT00, which is the alternate function (set the TTI0IOC1.TT0IS1 and TT0IS0 bits to 00). 2. When using as the A0 to A15 pins, be sure to set all 16 bits of the PMC9 register to FFFFH at once. 3. KR7 and TIT01 are alternate functions. W hen using the pin for the TIT 01 function, disable key return detection of KR7, which is the alternate function (set the KRM.KRM7 bit to 0). Also, when using the pin for the KR7 functi on, disable edge detection of TIT01, which is the alternate function (set the TTI0IOC1.TT0IS3 and TT0IS2 bits to 00). 4. The SIE1 function is assigned to the PDH0 pin as well as the P99 pin. When using t he P99 pin for the SIE1 function, do not specify the PDH0 pin to be used for this function.

R01UH0290EJ0300 Rev.3.00 Page 187 of 1817 Sep 19, 2011 V850ES/JJ3-E, V850ES/JH3-E C H A P T E R 4 P O R T F U N C T I O N S Table 4-18. Using Port Pin as Alternate-Function Pin (10/13) Alternate Function Pin Name Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register Other Bits (Registers) SOE1 Output P910 = Setting not required PM910 = Setting not required PMC910 = 1 PFCE910 = 0 PFC910 = 0 RXDC5 Output P910 = Setting not required PM910 = Setting not required PMC910 = 1 PFCE910 = 0 PFC910 = 1 SCL03 I/O P910 = Setting not required PM910 = Setting not required PMC910 = 1 PFCE910 = 1 PFC910 = 0 PF910 (PF9) = 1 P910 A10 Note 1 Output P910 = Setting not required PM910 = Setting not required PMC910 = 1 PFCE910 = 1 PFC910 = 1 SCKE1 Note 2 I/O P911 = Setting not required PM911 = Setting not required PMC911 = 1 PFCE911 = 0 PFC911 = 0 TIAA50 Input P911 = Setting not required PM911 = Setting not required PMC911 = 1 PFCE911 = 0 PFC911 = 1 TOAA50 Output P911 = Setting not required PM911 = Setting not required PMC911 = 1 PFCE911 = 1 PFC911 = 0 P911 A11 Note 1 Output P911 = Setting not required PM911 = Setting not required PMC911 = 1 PFCE911 = 1 PFC911 = 1 TOAB1OFF Note 3 Input P912 = Setting not required PM912 = Setting not required PMC912 = 1 − PFC912 = 0 INTR912 (INTR9) = 0, INTF912 (INTF9) = 0 INTP18 Note 3 Input P912 = Setting not required PM912 = Setting not required PMC912 = 1 − PFC912 = 0 HZA0DCN0, NZA0DCP0 (HZA0CTL0) = 00 P912 A12 Note 1 Output P912 = Setting not required PM912 = Setting not required PMC912 = 1 − PFC912 = 1 SIF3 Input P913 = Setting not required PM913 = Setting not required PMC913 = 1 PFCE913 = 0 PFC913 = 0 TXDB1 Output P913 = Setting not required PM913 = Setting not required PMC913 = 1 PFCE913 = 0 PFC913 = 1 INTP19 Input P913 = Setting not required PM913 = Setting not required PMC913 = 1 PFCE913 = 1 PFC913 = 0 P913 A13 Note 1 Output P913 = Setting not required PM913 = Setting not required PMC913 = 1 PFCE913 = 1 PFC913 = 1 SOF3 Output P914 = Setting not required PM914 = Setting not required PMC914 = 1 PFCE914 = 0 PFC914 = 0 RXDB1 Input P914 = Setting not required PM914 = Setting not required PMC914 = 1 PFCE914 = 0 PFC914 = 1 INTP20 Input P914 = Setting not required PM914 = Setting not required PMC914 = 1 PFCE914 = 1 PFC914 = 0 P914 A14 Note 1 Output P914 = Setting not required PM914 = Setting not required PMC914 = 1 PFCE914 = 1 PFC914 = 1 Notes 1. When using as the A0 to A15 pins, be sure to set all 16 bits of the PMC9 register to FFFFH at once. 2. The SCKE1 function is assigned to the PDH2 pin as well as the P911 pin. When using the P911 pin for the SCKE1 function, do no t set the PDH2 pin to be used for this function. 3. TOAB1OFF and INTP18 are alternate functions. When using the pin for the TOAB1OFF function, disable interrupt detection of INT P18 , which is the alternate function (set the INTR9.INTR912 and INTF9.INTF912 bits to 0). Also , when using the pin for the INTP18 function, disable edge d etection of TOAB1OFF , which is the alternate function (set the HZA0CTL0. HZA0DCN0 and NZA0DCP0 bits to 00).

R01UH0290EJ0300 Rev.3.00 Page 188 of 1817 Sep 19, 2011 V850ES/JJ3-E, V850ES/JH3-E C H A P T E R 4 P O R T F U N C T I O N S Table 4-18. Using Port Pin as Alternate-Function Pin (11/13) Alternate Function Pin Name Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register Other Bits (Registers) SCKF3 I/O P915 = Setting not required PM915 = Setting not required PMC915 = 1 PFCE915 = 0 PFC915 = 0 TIAA50 Input P915 = Setting not required PM915 = Setting not required PMC915 = 1 PFCE915 = 0 PFC915 = 1 TOAA0 Output P915 = Setting not required PM915 = Setting not required PMC915 = 1 PFCE915 = 1 PFC915 = 0 P915 A15 Note 1 Output P915 = Setting not required PM915 = Setting not required PMC915 = 1 PFCE915 = 1 PFC915 = 1 PCM0 WAIT Input PCM0 = Setting not required PMCM0 = Setting not required PMCCM0 = 1 − − PCM1 CLKOUT Output PCM1 = Setting not required PMCM1 = Setting not required PMCCM1 = 1 − − PCM2 HLDAK Note 2 Output PCM2 = Setting not required PMCM2 = Setting not required PMCCM2 = 1 − − PCM3 HLDRQ Note 2 Input PCM3 = Setting not required PMCM3 = Setting not required PMCCM3 = 1 − − PCS0 CS0 Output PCS0 = Setting not required PMCS0 = Setting not required PMCCS0 = 1 − − PCS2 CS2 Output PCS2 = Setting not required PMCS2 = Setting not required PMCCS2 = 1 − − PCS3 CS3 Note 2 Output PCS3 = Setting not required PMCS3 = Setting not required PMCCS3 = 1 − − PCT0 WR0 Output PCT0 = Setting not required PMCT0 = Setting not required PMCCT0 = 1 − − PCT1 WR1 Output PCT1 = Setting not required PMCT1 = Setting not required PMCCT1 = 1 − − PCT4 RD Output PCT4 = Setting not required PMCT4 = Setting not required PMCCT4 = 1 − − PCT6 ASTB Output PCT6 = Setting not required PMCT6 = Setting not required PMCCT6 = 1 − − A16 Output PDH0 = Setting not required PMDH0 = Setting not required PMCDH0 = 1 − FECDH0 = 0 PDH0 SIE1 Note 3 Input PDH0 = Setting not required PMDH0 = Setting not required PMCDH0 = 1 − FECDH0 = 1 A17 Output PDH1 = Setting not required PMDH1 = Setting not required PMCDH1 = 1 − FECDH1 = 0 PDH1 SOE1 Note 4 Output PDH1 = Setting not required PMDH1 = Setting not required PMCDH1 = 1 − FECDH1 = 1 A18 Output PDH2 = Setting not required PMDH2 = Setting not required PMCDH2 = 1 − FECDH2 = 0 PDH2 SCKE1 I/O PDH2 = Setting not required PMDH2 = Setting not required PMCDH2 = 1 − FECDH2 = 1 Notes 1. When using as the A0 to A15 pins, be sure to set all 16 bits of the PMC9 register to FFFFH at once. 2. V850ES/JJ3-E only 3. The SIE1 function is assigned to the PDH0 pin as well as the P99 pin. When using the PDH0 pin for the SIE1 function, do not s et the P99 pin to be used for this function. 4. The SOE1 function is assigned to the PDH1 pin as well as the P910 pin. When using the PDH1 pi n for the SOE1 function, do not set the P910 pin to be used for this function. 5. The SCKE1 function is assigned to the PDH2 pin as well as the P911 pin. When using the PDH2 pin for the SCKE1 function, do no t set the P911 pin to be used for this function.

R01UH0290EJ0300 Rev.3.00 Page 189 of 1817 Sep 19, 2011 V850ES/JJ3-E, V850ES/JH3-E C H A P T E R 4 P O R T F U N C T I O N S Table 4-18. Using Port Pin as Alternate-Function Pin (12/13) Alternate Function Pin Name Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register Other Bits (Registers) A19 Output PDH3 = Setting not required PMDH3 = Setting not required PMCDH3 = 1 FECEDH3 = 0 FECDH3 = 0 SIF4 Note 1 Input PDH3 = Setting not required PMDH3 = Setting not required PMCDH3 = 1 FECEDH3 = 0 FECDH3 = 1 PDH3 TXDB0 Note 1 Output PDH3 = Setting not required PMDH3 = Setting not required PMCDH3 = 1 FECEDH3 = 1 FECDH3 = 0 A20 Output PDH4 = Setting not required PMDH4 = Setting not required PMCDH4 = 1 FECEDH4 = 0 FECDH4 = 0 SOF4 Note 2 Output PDH4 = Setting not required PMDH4 = Setting not required PMCDH4 = 1 FECEDH4 = 0 FECDH4 = 1 PDH4 RXDB0 Note 2 Input PDH4 = Setting not required PMDH4 = Setting not required PMCDH4 = 1 FECEDH4 = 1 FECDH4 = 0 A21 Output PDH5 = Setting not required PMDH5 = Setting not required PMCDH5 = 1 − FECDH5 = 0 PDH5 SCKF4 Note 3 I/O PDH5 = Setting not required PMDH5 = Setting not required PMCDH5 = 1 − FECDH5 = 1 PDH6 A22 Note 4 Output PDH6 = Setting not required PMDH6 = Setting not required PMCDH6 = 1 − − PDH7 A23 Note 4 Output PDH7 = Setting not required PMDH7 = Setting not required PMCDH7 = 1 − − PDL0 AD0 I/O PDL0 = Setting not required PMDL0 = Setting not required PMCDL0 = 1 − − PDL1 AD1 I/O PDL1 = Setting not required PMDL1 = Setting not required PMCDL1 = 1 − − PDL2 AD2 I/O PDL2 = Setting not required PMDL2 = Setting not required PMCDL2 = 1 − − PDL3 AD3 I/O PDL3 = Setting not required PMDL3 = Setting not required PMCDL3 = 1 − − PDL4 AD4 I/O PDL4 = Setting not required PMDL4 = Setting not required PMCDL4 = 1 − − Notes 1. The SIF4/TXDB0 function is assigned to the PDH3 pin as well as the P33 pin. When usi ng the PDH3 pin for the SIF4/TXDB0 function, do not set the P33 pin to be used for this function. 2. The SOF4/RXDB0 function is assigned to the PDH4 pin as well as the P34 pin. When using the PDH4 pin for the SOF4/RXDB0 functi on, do not set the P34 pin to be used for this function. 3. The SCKF4 function is assigned to the PDH5 pin as well as the P35 pin. When using the PDH5 pin for the SCKF4 function, do not set the P35 pin to be used for this function. 4. V850ES/JJ3-E only

R01UH0290EJ0300 Rev.3.00 Page 190 of 1817 Sep 19, 2011 V850ES/JJ3-E, V850ES/JH3-E C H A P T E R 4 P O R T F U N C T I O N S Table 4-18. Using Port Pin as Alternate-Function Pin (13/13) Alternate Function Pin Name Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register Other Bits (Registers) AD5 I/O PDL5 = Setting not required PMDL5 = Setting not required PMCDL5 = 1 − − PDL5 FLMD1 Note Input PDL5 = Setting not required PMDL5 = Setting not required PMCDL5 = Setting not required − − PDL6 AD6 I/O PDL6 = Setting not required PMDL6 = Setting not required PMCDL6 = 1 − − PDL7 AD7 I/O PDL7 = Setting not required PMDL7 = Setting not required PMCDL7 = 1 − − PDL8 AD8 I/O PDL8 = Setting not required PMDL8 = Setting not required PMCDL8 = 1 − − PDL9 AD9 I/O PDL9 = Setting not required PMDL9 = Setting not required PMCDL9 = 1 − − PDL10 AD10 I/O PDL10 = Setting not required PMDL10 = Setting not required PMCDL10 = 1 − − PDL11 AD11 I/O PDL11 = Setting not required PMDL11 = Setting not required PMCDL11 = 1 − − PDL12 AD12 I/O PDL12 = Setting not required PMDL12 = Setting not required PMCDL12 = 1 − − PDL13 AD13 I/O PDL13 = Setting not required PMDL13 = Setting not required PMCDL13 = 1 − − PDL14 AD14 I/O PDL14 = Setting not required PMDL14 = Setting not required PMCDL14 = 1 − − PDL15 AD15 I/O PDL15 = Setting not required PMDL15 = Setting not required PMCDL15 = 1 − − Note Since this pin is set in the flash memory programming mode, it does not need to be manipulated using the port control register. For details, see CHAPTER 33 FLASH MEMORY.

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4.5 Cautions

4.5.1 Cautions on setting port pins

(1) In the V850ES/JH3-E and V850ES/JJ3-E, the general-purpose port functions share pins with several peripheral function I/O pins. Switch between the general-purpose port ( port mode) and the peripheral function I/O pin (alternate-function mode) by setting the PMCn register. Note the following cautions with regards to this register setting sequence. (a) Cautions on switching from por t mode to alternate-function mode Switch from the port mode to alternate-function mode in the following order. <1> Set the PFn register Note 1 : N-ch open-drain setting <2> Set the PFCn and PFCEn registers: Alternate-function selection <3> Set the corresponding bit of the PMCn register to 1: Switch to alternate-function mode <4> Set the INTRn and INTFn registers Note 2 : External interrupt setting If the PMCn register is set first, note that unexpected operations may occur at t hat moment or depending on the change of the pin states in accordance with the setting of the PFn, PFCn, and PFCEn registers. A concrete example is shown in [Example] below. Notes 1. N-ch open-drain output pin only 2. Only when the external in terrupt function is selected Caution Regardless of the port mode /alternate-function mode, the Pn re gister is read and written as follows.

• Pn register read: Read the port output latch value (when PMn.PMnm bit = 0), or read the pin states (PMn.PMnm bit = 1).
• Pn register write: Write to the port output latch [Example] SCL01 pin setting example The SCL01 pin is used alternately as the P41/SOF0 pin. Select the valid pin function using the PMC4, PFC4, and PF4 registers. PMC41 Bit PFC41 Bit PF41 Bit Valid Pin Function 0 don’t care 1 P41 (in output port mode, N-ch open-drain output) 0 1 SOF0 output (N-ch open-drain output) 1 1 1 SCL01 I/O (N-ch open-drain output)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 4 PORT FUNCTIONS R01UH0290EJ0300 Rev.3.00 Page 192 of 1817 Sep 19, 2011 The setting procedure that may caus e malfunction on switching from the P41 pin to the SCL01 pin is shown below. Setting Procedure Setting Contents Pin State Pin Level <1> Initial value (PMC41 bit = 0, PFC41 bit = 0, PF41 bit = 0) Port mode (input) Hi-Z <2> PMC41 bit ← 1 SOF0 output Low level (high level depending on the CSIF0 setting) <3> PFC41 bit ← 1 SCL01 I/O High level (CMOS output) <4> PF41 bit ← 1 SCL01 I/O Hi-Z (N-ch open-drain output) In <2>, I C communication may be affected since the alternate-function SOF0 output is output to the pin. In the CMOS output period of <2> or <3>, unnecessary current may be generated. (b) Cautions on alternate-function mode (input) The signal input to the alternate-function block is low level when the PMCn.PMCnm bit is 0 due to the AND output of the PMCn register set va lue and the pin level. Thus, depending on the port setting and alternate- function operation enable timing, unexpected operations ma y occur. Therefore, switch between the port mode and alternate-function mode in the following sequence.

• To switch from port mode to alternate-function mode (input) Set the pins to the alternate-function mode using the PMCn register and then enab le the alternate-function operation.
• To switch from alternate-function mode (input) to port mode Stop the alternate-function operation and then switch the pins to the port mode. Concrete examples are shown in [Example 1] and [Example 2]. [Example 1] Switching from general-purpose port (P02) to external interrupt pin (NMI) When the P02/NMI pin is pulled up as shown in Fi gure 4-4 and the rising edge is specified by the NMI pin edge detection setting, even though a high level is input continuously to the NMI pin when switching from the P02 pin to the an NMI pin (PMC02 bit = 0 → 1), this is detected as a rising edge as if a low level changed to a high level, and an NMI interrupt occurs. To avoid this, set the NMI pin’s valid edge after switching from the P02 pin to the NMI pin.

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4.5.2 Cautions on bit manipulation instruction for port n register (Pn)

When a 1-bit manipulation instruction is executed on a port t hat provides both input and out put functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. <Example> When the P90 pin is an output port, the P91 to P 97 pins are input ports (all pi n statuses are high level), and the value of the port latch is 00H, if the output of the P90 pin is changed from low level to high level via a bit manipulation instruction, the value of the port latch is FFH. Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A bit manipulation instruction is executed in t he following order in the V850ES/JH3-E and V850ES/JJ3-E. <1> The Pn register is read in 8-bit units. <2> The targeted bit is manipulated. <3> The Pn register is written in 8-bit units. In step <1>, the value of the output latch (0) of the P90 pin, which is an output port, is read, while the pin statuses of the P91 to P97 pins, wh ich are input ports, are read. If t he pin statuses of the P91 to P97 pins are high level at this time, the read value is FEH. The value is changed to FFH by the manipulation in <2>. FFH is written to the output la tch by the manipulation in <3>. Figure 4-6. Bit Manipulation Instruction (P90 Pin) Bit manipulation instruction (set1 0, P9L[r0]) is executed for P90 bit. P90 P91 to P97 Port 9L latch 00000000 P90 P91 to P97 11111111 Low-level output Pin status: High level High-level output Pin status: High level Port 9L latch Bit manipulation instruction for P90 bit <1> P9L register is read in 8-bit units.  In the case of P90, an output port, the value of the port latch (0) is read.  In the case of P91 to P97, input ports, the pin status (1) is read. <2> Set (1) P90 bit. <3> Write the results of <2> to the output latch of P9L register in 8-bit units.

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4.5.3 Cautions on on-chip debug pins (V850ES/JH3-E only)

The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P54 /INTP11/DRST pin is initialized to function as an on-chip debug pin (DRST). If a high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can be used. The following action must be taken if on-chip debugging is not used.

• Clear the OCDM0 bit of the OCDM register (special register) (0) At this time, fix the P54/INTP11/DRST pin to low level from when reset by the RESET pin is released until the above action is taken. If a high level is input to the DRST pin before the above acti on is taken, it may cause a malfunction (CPU deadlock). Handle the P54 pin with the utmost care. Caution After reset by the WDT2RES signal, clock m onitor (CLM), or low-voltage detector (LVI), the P54/INTP11/DRST pin is not initialized to functi on as an on-chip debug pin (DRST). The OCDM register holds the current value.

4.5.4 Cautions on P54/INTP11/DRST pin

The P54/INTP11/DRST pin has an internal pull-down resistor (30 k Ω TYP.). After a reset by the RESET pin, a pull- down resistor is connected. The pull-down resistor is disconnected when the OCDM0 bit is cleared (0).

4.5.5 Cautions on P51 pin when power is turned on

When the power is turned on, the following pins may output an undefined level temporarily even during reset.

• P51/INTP08/DDO pin

4.5.6 Hysteresis characteristics

In port mode, the following port pins do not have hysteresis characteristics. P02, P03 P20 to P27 P30 to P37 P40 to P48 P50 to P59 P60 to P65 P90 to P915

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 5 BUS CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 196 of 1817 Sep 19, 2011 CHAPTER 5 BUS CONTROL FUNCTION The V850ES/JH3-E and V850ES/JJ3-E are provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected.

5.1 Features

Output is selectable from multiplexed bus output with a minimum of 3 bus cycles and separate bus output 8-bit/16-bit data bus selectable Wait function

• Programmable wait function of up to 7 states
• External wait function using WAIT pin Idle state function Bus hold function

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5.2 Bus Control Pins

The pins used to connect an external device are listed in the table below. Table 5-1. Bus Control Pins (Multiplexed Bus) Bus Control Pin Alternate-Function Pin I/O Function AD0 to AD15 PDL0 to PDL15 I/O Address/data bus A16 to A23 Note 1 PDH0 to PDH7 Output Address bus WAIT PCM0 Input External wait control CLKOUT PCM1 Output Internal system clock WR0, WR1 PCT0, PCT1 Output Write strobe signal RD PCT4 Output Read strobe signal ASTB PCT6 Output Address strobe signal HLDRQ P44 Note 2 PCM3 Note 3 Input HLDAK P43 Note 2 PCM2 Note 3 Output Bus hold control CS0, CS2, CS3 Note 2 PCS0, PCS2, PCS3 Output Chip select Notes 1. V850ES/JJ3-E only. A16 to A21 pins are used for the V850ES/JH3-E. 2. V850ES/JH3-E only 3. V850ES/JJ3-E only Table 5-2. Bus Control Pins (Separate Bus) Bus Control Pin Alternate-Function Pin I/O Function AD0 to AD15 PDL0 to PDL15 I/O Data bus A0 to A15 P90 to P915 Output Address bus A16 to A23 Note 1 PDH0 to PDH7 Output Address bus WAIT PCM0 Input External wait control CLKOUT PCM1 Output Internal system clock WR0, WR1 PCT0, PCT1 Output Write strobe signal RD PCT4 Output Read strobe signal HLDRQ P44 Note 2 PCM3 Note 3 Input HLDAK P43 Note 2 PCM2 Note 3 Output Bus hold control CS0, CS2, CS3 Note 3 PCS0, PCS2, PCS3 Output Chip select Notes 1. V850ES/JJ3-E only. The A16 to A21 pins are used in the V850ES/JH3-E. 2. V850ES/JH3-E only 3. V850ES/JJ3-E only

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5.2.1 Pin status when internal ROM, intern al RAM, or on-chip peripheral I/O is accessed

When the internal ROM, internal RAM, or on-chip peripheral I/O are accessed, the status of each pin is as follows. Table 5-3. Pin Statuses When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed Separate Bus Mode Multiplexed Bus Mode Bus Control Pin Internal ROM/RAM Peripheral I/O Internal ROM/RAM Peripheral I/O Address/data bus (AD15 to AD0) Undefined Undefined Undefined Undefined Address bus (A23 to A16) Undefined Undefined (Address output during access) Undefined Undefined (Address output during access) Address bus (A15 to A0) Undefined Undefined (Address output during access) Undefined Undefined (Address output during access) Control signal Inactive Inac tive Inactive Inactive Caution When a write access is perfo rmed to the internal ROM area, addr ess, data, and control signals are activated in the same way as access to the external memory area.

5.2.2 Pin status in each operation mode

For the pin status of the V850ES/JH3-E and V850ES/JJ3-E in each operation mode, see 2.2 Pin States.

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5.3 Memory Block Function

The 16 MB external memory space is divided into memory blocks of 2 MB, 4 MB, and 8 MB from the lowest of the memory space. The programmable wait function and bus cycle operation mode for eac h of these blocks can be independently controlled in one-block units. Figure 5-1. Data Memory Map: Physical Address CS3 CS2 CS0 (CS1Note 2) (80 KB) Use prohibited Use prohibitedNote 3 Programmable peripheral I/O areaNote 4 or use prohibitedNote 5 External memory areaNote 1 (8 MB) External memory area (4 MB) USB function/ Ethernet/ used area (2 MB) Internal ROM areaNote 6 (1 MB) External memory area (1 MB) Internal RAM area (60 KB) On-chip peripheral I/O area (4 KB) 03FFFFFFH 03FEC000H 03FEBFFFH 01000000H 00FFFFFFH 00800000H 007FFFFFH 00400000H 003FFFFFH 00200000H 001FFFFFH 00000000H 03FFFFFFH 001FFFFFH 00100000H 000FFFFFH 00000000H 03FFF000H 03FFEFFFH 03FF0000H 03FEFFFFH 03FEF000H 03FEEFFFH 03FEC000H Notes 1. Use of this area is allowed only when using t he V850ES/JJ3-E. When using the V850ES/JH3-E, this area cannot be used. 2. CS1 is not provided as an external signal of the V850ES/Jx3-E; it is used internally as a chip select signal for the USB and Ethernet. 3. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because these addresses are in the same area as the on-chip peripheral I/O area. 4. Only the programmable peripheral I/O area is s een as images of 256 MB each in the 4 GB address space. 5. In the CAN controller vers ion, addresses 03FEC000H to 03FEEFFFH are assigned as a programmable peripheral I/O area in addresses 03FEC000H to 03FECBFFH. Use of these addresses in a version without a CAN controller is prohibited. 6. This area is used as an external memory area when data write access to this area is executed.

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5.4 Bus Access

5.4.1 Number of clocks for access

The following table shows the number of basic clocks required for accessing each resource. External Memory (16 Bits)Area (Bus Width) Bus Cycle Type Internal ROM (32 Bits) Internal RAM (32 Bits) Multiplexed Separate Instruction fetch (normal access) 1 1 Note 3 + n Instruction fetch (branch) 3 2 Note 3 + n Operand data access 5 1 3 + n Note Increases by 1 if a conflict with a data access occurs. Remark Unit: Clocks/access

5.4.2 Bus size setting function

Each external memory area selected by memory block CSn can be set by using the BSC register. However, the bus size can be set to 8 bits and 16 bits only. The external memory area of the V850ES/JH3-E is selected by using CS0 and CS2, and the external memory area of the V850ES/JJ3-E is selected by using CS0, CS2 and CS3. (1) Bus size configuration register (BSC) The BSC register can be read or written in 16-bit units. Reset sets this register to 5555H. Caution Write to the BSC register after reset, and then do not change the set values. Also, do not access an external memory area until the initial settings of the BSC register are complete. After reset: 5555H R/W Address: FFFFF066H BSn0 8 bits 16 bits BSC 1 BS30 Note BS20 BS00 8910111213 Data bus width of memory block CSn space (n = 0, 2, 3) 1415 1234567 0 CS0CS3 CS2 Note V850ES/JJ3-E only. Be sure to set this bit to 1 in the V850ES/JH3-E. Caution Be sure to set bits 14, 12, 10, 8, and 2 to “1”, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to “0”.

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5.4.3 Access by bus size

The V850ES/JH3-E and V850ES/JJ3-E access the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows.

• The bus size of the on-chip peripheral I/O is fixed to 16 bits.
• The bus size of the external memory is selectable from 8 bits or 16 bits (by using the BSC register). The operation when each of the above is accessed is described below. All data is accessed starting from the lower side. The V850ES/JH3-E and V850ES/JJ3-E support only the little-endian format. Figure 5-2. Little-Endian Address in Word 000BH 000AH 0009H 0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 0000H 31 24 23 16 15 8 7 0 (1) Data space The V850ES/JH3-E and V850ES/JJ3-E have an address misalign function. With this function, data can be placed at all addresses, re gardless of the format of the data (word data or halfword data). However, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (a) Halfword-length data access A byte-length bus cycle is generated twice if the least significant bit of the address is 1. (b) Word-length data access (i) A byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (ii) A halfword-length bus cycle is generated twic e if the lower 2 bits of the address are 10.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 5 BUS CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 202 of 1817 Sep 19, 2011 (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Byte data External data bus Address 2n + 1 Address Byte data External data bus (b) 8-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Byte data External data bus 2n + 1 Address Byte data External data bus

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 5 BUS CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 203 of 1817 Sep 19, 2011 (3) Halfword access (16 bits) (a) 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address 2n + 1 Halfword data External data bus First access Second access 2n + 2 Halfword data External data bus Address Halfword data External data bus Address 2n + 1 (b) 8-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) First access Second access

8 Address

Halfword data External data bus Halfword data External data bus First access Second access 2n + 22n + 1 Address Address Halfword data External data bus Halfword data External data bus

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 5 BUS CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 204 of 1817 Sep 19, 2011 (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Second access 4n + 1 4n + 2 4n + 3 Word data External data bus Address Word data External data bus Address <2> Access to address (4n + 1) First access Second access Third access 4n + 1 4n + 2 4n + 3 4n + 4 Word data External data bus Address Word data External data bus Address Word data External data bus Address

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 5 BUS CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 205 of 1817 Sep 19, 2011 (a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access 4n + 2 4n + 3 4n + 4 4n + 5 Word data External data bus Address Word data External data bus Address <4> Access to address (4n + 3) First access Second access Third access 4n + 3 4n + 4 4n + 5 4n + 6 Word data External data bus Address Word data External data bus Address Word data External data bus Address

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 5 BUS CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 206 of 1817 Sep 19, 2011 (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Second access Third access Fourth access 4n + 1 4n + 2 4n + 3 Word data External data bus Address Word data External data bus Address Word data External data bus Address Word data External data bus Address <2> Access to address (4n + 1) First access Second access Third access Fourth access 4n + 1 4n + 2 4n + 3 4n + 4 Word data External data bus Address Word data External data bus Address Word data External data bus Address Word data External data bus Address

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 5 BUS CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 207 of 1817 Sep 19, 2011 (b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Third access Fourth access Word data External data bus Address Word data External data bus Address Word data External data bus Address Word data External data bus Address 4n + 2 4n + 3 4n + 4 4n + 5 <4> Access to address (4n + 3) First access Second access Third access Fourth access 4n + 3 4n + 4 4n + 5 4n + 6 Word data External data bus Address Word data External data bus Address Word data External data bus Address Word data External data bus Address

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5.5 Wait Function

5.5.1 Programmable wait function

(1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each CS space. The number of wait states can be programmed by using the DWC0 register. Immediately after system reset, 7 data wait states are inserted for all the blocks. The DWC0 register can be read or written in 16-bit units. Reset sets this register to 7777H. Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are always accessed without a wait state. The on-ch ip peripheral I/O area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. Write to the DWC0 register after reset, an d then do not change the set values. Also, do not access an external memory area until the initial settings of the DWC0 register are complete. After reset: 7777H R/W Address: FFFFF484H DWn2 DWn1 DWn0 None DWC0 DW32 Note1 DW12Note2 DW31Note1 DW11Note2 DW30Note1 DW10Note2 DW22 DW02 DW21 DW01 DW20 DW00 8910111213 Number of wait states inserted in CSn space (n = 0 to 3) 1415 1234567 0 CS0 CS3 CS2 Notes 1. V850ES/JJ3-E only. Be sure to set 1 in the V850ES/JH3-E. 2. The DW12 to DW10 bits set wait of access to the USB function area. It is recommended to set the DW12 to DW10 bits to 001B (1 wait). Caution Be sure to set bits 15, 11, 7, and 3 to “0”.

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5.5.2 External wait function

To synchronize an extremely slow external memory, I/O, or asynchronous system, any num ber of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). When the PCM0 pin is set to its alternate function, the external wait function is enabled. Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the external wait function, in the same manner as the programmable wait function. The WAIT signal can be input asynchronously to CLKOUT, and is sampled at the falling edge of the clock in the T2 and TW states of the bus cycle in the multiple xed bus mode. In the separate bus mode, it is sampled at the rising edge of the clock immediately after the T1 and TW states of the bus cycle. If the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all.

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5.5.3 Relationship between programm able wait and external wait

Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT pin. Wait control Programmable wait Wait via WAIT pin For example, if the timing of the programmable wait and the WAIT pin signal is as illustrated below, three wait states will be inserted in the bus cycle. Figure 5-3. Inserting Wait Example CLKOUT T1 T2 TW TW TW T3 WAIT pin Wait via WAIT pin Programmable wait Wait control Remark The circles indicate the sampling timing.

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5.5.4 Programmable address wait function

Address-setup or address-hold waits to be inserted in each bus cycle can be se t by using the AWC register. Address wait insertion is set for each chip select area (CS0, CS2, CS3). If an address setup wait is inserted, it s eems that the high-clock period of the T1 state is extended by 1 clock. If an address-hold wait is inserted, it seems that the low-clock period of the T1 state is extended by 1 clock. (1) Address wait control register (AWC) The AWC register can be read or written in 16-bit units. Reset sets this register to FFFFH. Cautions 1. Address-setup wait and address-hold wait cycles are not inserted when the internal ROM area, internal RAM area, and on-chip peripheral I/O areas are accessed. 2. Write to the AWC register after reset, and then do not change the set values. Also, do not access an external memory area until the initial settings of the AWC register are complete. After reset: FFFFH R/W Address: FFFFF488H AHW3Note1 AHWn Not inserted Inserted AWC 1 ASW3Note1 AHW2 ASW2 AHW1Note2 ASW1Note2 AHW0 ASW0 8910111213 Specifies insertion of address-hold wait (n = 0, 2, 3) 1415 1234567 0 ASWn Not inserted Inserted Specifies insertion of address-setup wait (n = 0, 2, 3) CS0CS3 CS2 Notes 1. V850ES/JJ3-E only. Be sure to set 1 in the V850ES/JH3-E. 2. It is recommended to clear the AHW1 bit and the ASW1 bit to 0. Caution Be sure to set bits 15 to 8 to “1”.

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5.6 Idle State Insertion Function

To facilitate interfacing with low-speed memories, one idle state (TI) can be insert ed after the T3 state in the bus cycle that is executed for each space selected by the chip select. By inserting an idle state, the data output float delay time of the memory can be secured during read access (an idle state cannot be inserted during write access). Whether the idle state is to be inserted can be programmed by using the BCC register. An idle state is inserted for all the areas immediately after system reset. (1) Bus cycle control register (BCC) The BCC register can be read or written in 16-bit units. Reset sets this register to AAAAH. Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle state insertion. 2. Write to the BCC register after reset, and th en do not change the set values. Also, do not access an external memory area until the initial settings of the BCC register are complete. After reset: AAAAH R/W Address: FFFFF48AH BC31Note1 BCn1 Not inserted Inserted BCC 0 BC21 BC11Note2 BC01 8910111213 Specifies insertion of idle state (n = 0 to 3) 1415 1234567 0 CS3 CS2 CS0 Notes1. V850ES/JJ3-E only. Be sure to set 1 in the V850ES/JH3-E. 2. It is recommended to clear the BC11 bit to 0. Caution Be sure to set bits 15, 13, 11 and 9 to “1”, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to “0”.

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5.7 Bus Hold Function

5.7.1 Functional outline

The HLDRQ and HLDAK functions are valid if the P43 Note 1 , P44 Note 1 , PCM2 Note 2 , and PCM3 Note 2 pins are set to their alternate function. When the HLDRQ pin is asserted (low level), indicating th at another bus master has requested bus mastership, the external address/data bus goes into a hi gh-impedance state and is released (bus hold status). If the request for the bus mastership is cleared and the HLDRQ pin is deasserted (high level), driving these pins is started again. During the bus hold period, execution of the program in th e internal ROM and internal RAM is continued until an on- chip peripheral I/O register or the external memory is accessed. The bus hold status is indicated by assertion of the HLDAK pin (low leve l). The bus hold function enables the configuration of multi-processor type systems in which two or more bus masters exist. Note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing function or a bit manipulation instruction. Notes 1. V850ES/JH3-E 2. V850ES/JJ3-E Status Data Bus Width Access Type Timing at Which Bus Hold Request Is Not Acknowledged Word access to even address Between first and second access Between first and second access Word access to odd address Between second and third access 16 bits Halfword access to odd address Between first and second access Between first and second access Between second and third access Word access Between third and fourth access CPU bus lock 8 bits Halfword access Between first and second access Read-modify-write access of bit manipulation instruction − − Between read access and write access

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5.7.2 Bus hold procedure

The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited <3> End of current bus cycle <4> Shift to bus idle status <5> HLDAK = 0 <6> HLDRQ = 1 acknowledged <7> HLDAK = 1 <8> Bus cycle start request inhibition released <9> Bus cycle starts Normal status Bus hold status Normal status HLDAK (output) HLDRQ (input)

5.7.3 Operation in power save mode

Because the internal system clock is stopped in the STOP , IDLE1, and IDLE2 modes, the bus hold status is not entered even if the HLDRQ pin is asserted. In the HALT mode, the HLDAK pin is asserted as soon as the HLDRQ pin has been asse rted, and the bus hold status is entered. When the HLDRQ pin is la ter deasserted, the HLDAK pin is also deasserted, and the bus hold status is cleared.

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5.8 Bus Priority

Bus hold, DMA transfer, operand data accesses, instructi on fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. Bus hold has the highest priority, followed by DMA transfe r, operand data access, instruction fetch (branch), and instruction fetch (successive). An instruction fetch may be inserted between the read access and write access in a read-modify-write access. If an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. Table 5-4. Bus Priority Priority External Bus Cycle Bus Master Bus hold External device DMA transfer DMAC Operand data access CPU Instruction fetch (branch) CPU High Low Instruction fetch (successive) CPU

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5.9 Bus Timing

Figure 5-4. Multiplexed/Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) A1 A2 A3D1 D2 A3A2A1 T1 T2 T3 T1 T2 TW TW T3 TI T1 CLKOUT A23 to A0Note 1 ASTB CS3, CS2, CS0Notes 2, 3 WAIT AD15 to AD0 RD AD15 to AD8 AD7 to AD0 Hi-Z Hi-Z Active Active Odd Address Even Address8-bit Access Programmable wait External wait Idle state Notes 1. V850ES/JJ3-E only. The A21 to A0 pins are used in the V850ES/JH3-E. 2. V850ES/JJ3-E only. The CS2 and CS0 pins are used in the V850ES/JH3-E. 3. Only the CS space subject to access is active. Remark The broken lines indicate high impedance. Figure 5-5. Multiplexed/Separate Bus Read Timing (Bus Size: 8 Bits) A1 A2 A3D1 D2 A3A2A1 T1 T2 T3 T1 T2 TW TW T3 TI T1 CLKOUT A23 to A0Note 1, AD15 to AD8 ASTB WAIT AD7 to AD0 RD CS3, CS2, CS0Notes 2, 3 Programmable wait External wait Idle state Notes 1. V850ES/JJ3-E only. The A21 to A0 pins are used in the V850ES/JH3-E. 2. V850ES/JJ3-E only. The CS2 and CS0 pins are used in the V850ES/JH3-E. 3. Only the CS space subject to access is active. Remark The broken lines indicate high impedance.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 5 BUS CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 218 of 1817 Sep 19, 2011 Figure 5-8. Multiplexed/Separate Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access) A2UndefinedUndefined Undefined T2 T3 TI Note 1 TH TH TH TH TI Note 1 T1 T2 T3 CLKOUT HLDRQ HLDAK A23 to A0Note 2 ASTB AD15 to AD0 RD A2 D2 1111 1111CS3, CS2, CS0Notes 3, 4 Undefined Notes 1. This idle state (TI) does not de pend on the BCC register settings. 2. V850ES/JJ3-E only. The A21 to A0 pins are used in the V850ES/JH3-E. 3. V850ES/JJ3-E only. The CS2 and CS0 pins are used in the V850ES/JH3-E. 4. Only the CS space subject to access is active. Remarks 1. See Table 2-2 for the pin statuses in the bus hold mode. 2. The broken lines indicate the high-impedance state.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 6 CLOCK GENERATION FUNCTION R01UH0290EJ0300 Rev.3.00 Page 219 of 1817 Sep 19, 2011 CHAPTER 6 CLOCK GENERATION FUNCTION

6.1 Overview

The following clock generation functions are available. Main clock oscillator

• In clock-through mode f X = 3.0 to 6.25 MHz (fXX = 3.0 to 6.25 MHz)
• In PLL mode f X = 3.0 to 6.25 MHz (×8: fXX = 24 to 50 MHz) Subclock oscillator
• f XT = 32.768 kHz Multiply ( ×8) function by PLL (Phase Locked Loop)
• Clock-through mode/PLL mode selectable Internal oscillator
• f R = 220 kHz (TYP.) Internal system clock generation
• 7 steps (f XX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT) Peripheral clock generation Clock output function Remark f X: Main clock oscillation frequency f XX: Main clock frequency f XT: Subclock frequency f R: Internal oscillation clock frequency

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6.2 Configuration

Figure 6-1. Clock Generator CLKOUT EXCLK fXX/32 fXX/16 fXX/8 fXX/4 fXX/2 fXX fCPU fCLK fXTfXT fR Selector Selector Selector FRC bit MFRC bit SELPLL bit PLLON bit CLS, CK3 bits CK2 to CK0 bits UCKSEL bit STOP mode Subclock oscillator RTC clock, WDT clock RTC clock Port CM Prescaler 1 Prescaler 2IDLE control HALT mode CPU clock Peripheral clock (Including clock for Ethernet) USB clock WDT clock, TMM clock Internal system clock Prescaler 3 Main clock oscillator Main clock oscillator stop control RSTOP bit Internal oscillator 1/8 divider XT1 XT2 IDLE mode PLL f XXfX IDLE control Selector Selector HALT control Remark f X: Main clock oscillation frequency f XX: Main clock frequency f CLK: Internal system clock frequency f XT: Subclock frequency f CPU: CPU clock frequency f R: Internal oscillation clock frequency

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 6 CLOCK GENERATION FUNCTION R01UH0290EJ0300 Rev.3.00 Page 221 of 1817 Sep 19, 2011 (1) Main clock oscillator The main clock oscillator oscillates the following frequencies (fX).

• In clock-through mode f X = 3.0 to 6.25 MHz
• In PLL mode f X = 3.0 to 6.25 MHz (×8) (2) Subclock oscillator The sub-resonator oscillates a frequency of 32.768 kHz (fXT). (3) Main clock oscillator stop control This circuit generates a control signal that stops oscillation of the main clock oscillator. Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only when the PCC.CLS bit = 1). (4) Internal oscillator Oscillates a frequency (fR) of 220 kHz (TYP.). (5) Prescaler 1 This prescaler generates the clock (f XX to f XX/1,024) to be supplied to the follo wing on-chip peripheral functions: TAA, TAB, TMM, TMT, CSIE, CSIF, UARTB, UARTC, I C, CAN, ADC, WDT2, Ethernet controller (6) Prescaler 2 This circuit divides the main clock (fXX). The clock generated by prescaler 2 (f XX to f XX/32) is supplied to the selector that generates the CPU clock (f CPU) and internal system clock (fCLK). fCLK is the clock supplied to the INTC, ROM, and RAM blocks, and can be output from the CLKOUT pin. (7) Prescaler 3 This circuit divides the clock generated by the main clock oscillator (f X) to a specific frequency (32.768 kHz) and supplies that clock to the real-time counter (RTC) block. (8) PLL This circuit multiplies the clock generated by the main clock oscillator (fX) by 8. It operates in two modes: clock-through mode in which f X is output as is, and PLL mode in which a multiplied clock is output. These modes can be selected by using the PLLCTL.SELPLL bit.

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6.3 Registers

(1) Processor clock control register (PCC) The PCC register is a special register. Data can be wri tten to this register only in combination of specific sequences (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 6 CLOCK GENERATION FUNCTION R01UH0290EJ0300 Rev.3.00 Page 223 of 1817 Sep 19, 2011 FRC Used Not used FRC Use of subclock on-chip feedback resistor PCC MCK MFRC CLS Note CK3 CK2 CK1 CK0 Oscillation enabled Oscillation stopped MCK Main clock oscillator control Used Not used MFRC Use of main clock on-chip feedback resistor After reset: 03H R/W Address: FFFFF828H Main clock operation Subclock operation CLS Note Status of CPU clock (f CPU) Even if the MCK bit is set (1) while the system is operating with the main clock as the CPU clock, the operation of the main clock does not stop. It stops after the CPU clock has been changed to the subclock. Before setting the MCK bit from 0 to 1, stop the on-chip peripheral functions operating with the main clock. When the main clock is stopped and the device is operating with the subclock, clear (0) the MCK bit and secure the oscillation stabilization time by software before switching the CPU clock to the main clock or operating the on-chip peripheral functions. fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 Setting prohibited fXT CK2 Clock selection (f CLK/fCPU)CK1 CK0 CK3 Note The CLS bit is a read-only bit. Cautions 1. Do not change the CPU clock (by us ing the CK3 to CK0 bits) while CLKOUT is being output. 2. Use a bit manipulation instruction to ma nipulate the CK3 bit. When using an 8-bit manipulation instruction, do not change the set values of the CK2 to CK0 bits. Remark ×: don't care

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 6 CLOCK GENERATION FUNCTION R01UH0290EJ0300 Rev.3.00 Page 224 of 1817 Sep 19, 2011 (a) Example of setting main clock operation → subclock operation <1> CK3 bit ← 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <2> Subclock operation: Read the CLS bit to check if s ubclock operation has started. It takes the following time after the CK3 bit is set until subclock operation is started. Max.: 1/f XT (1/subclock frequency) <3> MCK bit ← 1: Set the MCK bit to 1 only when stopping the main clock. Cautions 1. When stopping the main clock, stop th e PLL. Also stop the op erations of the on-chip peripheral functions operating with the main clock. 2. If the following conditions are not satisf ied, change the CK2 to CK0 bits so that the conditions are satisfied, then change to the subclock operation mode. Internal system clock (f CLK) > Subclock (fXT: 32.768 kHz) × 4 Remark Internal system clock (f CLK): Clock generated from the main clock (f XX) by setting the CK2 to CK0 bits [Description example] _DMA_DISABLE: clrl 0, DCHCn[r0] -- DMA operation disabled. n = 0 to 3 st.b r0, PRCMD[r0] set1 3, PCC[r0] -- CK3 bit ← 1 <2> _CHECK_CLS : tst1 4, PCC[r0] -- Wait until subclock operation starts. bz _CHECK_CLS st.b r0, PRCMD[r0] set1 6, PCC[r0] -- MCK bit ← 1, main clock is stopped. _DMA_ENABLE: setl 0, DCHCn[r0] -- DMA operation enabled. n = 0 to 3 Remark The description above is simply an example. Note that in <2> above, the CLS bit is read in a closed loop.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 6 CLOCK GENERATION FUNCTION R01UH0290EJ0300 Rev.3.00 Page 225 of 1817 Sep 19, 2011 (b) Example of setting subclock operation → main clock operation <1> MCK bit ← 0: Main clock starts oscillating <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses. <3> CK3 bit ← 0: Use of a bit manipulation instructi on is recommended. Do not change the CK2 to CK0 bits. <4> Main clock operation: It takes the following time af ter the CK3 bit is set until main clock operation is started. Max.: 1/f XT (1/subclock frequency) Therefore, insert one NO P instruction immediately after setting the CK3 bit to 0 or read the CLS bit to check if main clock operation has started. Caution Enable operation of the on -chip peripheral functions operating with the main clock only after the oscillation of the main clock stabilizes. If their operations are enabled before the lapse of the oscillation stabilization time, a malfunction may occur. [Description example] _DMA_DISABLE: clrl 0, DCHCn[r0] -- DMA operation disabled. n = 0 to 3 st.b r0, PRCMD[r0] -- Release of protection of special registers clr1 6, PCC[r0] -- Main clock starts oscillating. <2> movea 0x55, r0, r11 -- Wait for oscillation stabilization time. _WAIT_OST : nop nop nop addi -1, r11, r11 cmp r0, r11 bne _WAIT_OST <3> st.b r0, PRCMD[r0] clr1 3, PCC[r0] -- CK3 ← 0 <4> _CHECK_CLS : tst1 4, PCC[r0] -- Wait until main clock operation starts. bnz _CHECK_CLS _DMA_ENABLE: setl 0, DCHCn[r0] -- DMA operation enabled. n = 0 to 3 Remark The description above is simply an example. Note that in <4> above, the CLS bit is read in a closed loop.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 6 CLOCK GENERATION FUNCTION R01UH0290EJ0300 Rev.3.00 Page 226 of 1817 Sep 19, 2011 (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. 0RCM 0 0 0 00 0 RSTOP Internal oscillator oscillation Internal oscillator stopped RSTOP Oscillation/stop of internal oscillator After reset: 00H R/W Address: FFFFF80CH < > Cautions 1. The internal oscilla tor cannot be stopped while the CPU is operating on the internal oscillation clock (CCLS.CCLSF bit = 1). Do not set the RSTOP bit to 1. 2. The internal oscillator oscillates if the CCLS.CCLSF bit is set to 1 (when WDT overflow occurs during oscillation stabilization) even when the RSTOP bit is set to 1. At this time, the RSTOP bit remains being set to 1. (3) CPU operation clock status register (CCLS) The CCLS register indicates the status of the CPU operation clock. This register is read-only, in 8-bit or 1-bit units. Reset sets this register to 00H. 0CCLS 0 0 0 0 0 0 CCLSF After reset: 00HNote R Address: FFFFF82EH Operating on main clock (fX) or subclock (fXT). Operating on internal oscillation clock (fR). CCLSF CPU operation clock status Note If WDT overflow occurs during oscillation stabilization after a reset is released, the CCLSF bit is set to 1 and the reset value is 01H.

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6.4 Operation

6.4.1 Operation of each clock

The following table shows the operation status of each clock. Table 6-1. Operation Status of Each Clock PCC Register CLK Bit = 0, MCK Bit = 0 CLS Bit = 1, MCK Bit = 0 CLS Bit = 1, MCK Bit = 1 Register Setting and Operation Status Target Clock During Reset During Oscillation Stabilization Time Count HALT Mode IDLE1, IDLE2 Mode STOP Mode Subclock Mode Sub-IDLE Mode Subclock Mode Sub-IDLE Mode Main clock oscillator (fX) × × × × Subclock oscillator (fXT) Internal system clock (fCLK) × × × × × × Main clock (in PLL mode, fXX) × Note × × × × Peripheral clock (fXX to fXX/1,024) × × × × × × × WT clock (main) × × × × WT clock (sub) WDT2 clock (internal oscillation) × WDT2 clock (sub) Note Lockup time Remark : Operable ×: Stopped

6.4.2 Clock output function

The clock output function is used to output the internal system clock (fCLK) from the CLKOUT pin. The internal system clock (fCLK) is selected by using the PCC.CK3 to PCC.CK0 bits. The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the control register of port CM. The status of the CLKOUT pin is the same as the internal system clo ck in Table 6-1 and the pin can output the clock when it is in the operable status. It outputs a low level in the stopped status. However, t he CLKOUT pin is in the port mode (PCM1 pin: input mode) after reset and until it is set in the output mode. Therefore, the status of the pin is Hi-Z.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 6 CLOCK GENERATION FUNCTION R01UH0290EJ0300 Rev.3.00 Page 228 of 1817 Sep 19, 2011

6.5 PLL Function

6.5.1 Overview

In the V850ES/JH3-E and V850ES/JJ3-E, an operating clock that is 8 times higher than the oscillation frequency output by the PLL function or the clock-through mode can be select ed as the operating clock of the CPU and on-chip peripheral functions. When PLL function is used (×8): Input clock = 3.0 to 6.25 MHz (output: 24 to 50 MHz) Clock-through mode: Input clock = 3.0 to 6.25 MHz (output: 3.0 to 6.25 MHz)

6.5.2 Registers

(1) PLL control register (PLLCTL) The PLLCTL register is an 8-bit register that controls the PLL function. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H. 0PLLCTL 0 0 0 00 SELPLL PLLON PLL stopped PLL operating (After PLL operation starts, a lockup time is required for frequency stabilization) PLLON PLL operation stop register Clock-through mode PLL mode SELPLL CPU operation clock selection register After reset: 01H R/W Address: FFFFF82CH < > < > Cautions 1. When the PLLON bit is cleared to 0, the SELPLL bit is automatical ly cleared to 0 (clock- through mode). 2. The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If not (unlocked), "0" is written to the SELPLL bit if data is written to it.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 6 CLOCK GENERATION FUNCTION R01UH0290EJ0300 Rev.3.00 Page 229 of 1817 Sep 19, 2011 (2) Clock control register (CKC) The CKC register is a special register. Data can be wri tten to this register only in a combination of specific sequence (see 3.4.8 Special registers). The CKC register controls the internal system clock in the PLL mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 0AH. 0CKC 0 0 0 1 0 1 CKDIV0 After reset: 0AH R/W Address: FFFFF822H Setting prohibited fXX = 8 × fX (fX = 3.0 to 6.25 MHz) CKDIV0 Internal system clock (f XX) in PLL mode Caution 1. Be sure to set the CKC re gister to 0BH. When setting this register to a value other than 0BH or leaving it set to its initial value without setting it to 0BH, enabling PLL operation (PLLCTL.SELPLL = 1) is prohibited. 2. Be sure to set bits 3 and 1 to ‘‘ 1’’ and clear bits 7 to 4 and 2 to ‘‘0’’. Remark Both the CPU clock and peripheral clock are divided by the CKC register, but only the CPU clock is divided by the PCC register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 6 CLOCK GENERATION FUNCTION R01UH0290EJ0300 Rev.3.00 Page 230 of 1817 Sep 19, 2011 (3) Lock register (LOCKR) Phase lock occurs at a given frequency following power application or immediately after the STOP mode is released, and the time required for stabilization is the lo ckup time (frequency stabilization time). This state until stabilization is called the lockup status, and the stabilized state is called the locked status. The LOCKR register includes a LOCK bit that reflects the PLL frequency stabilization status. This register is read-only, in 8-bit or 1-bit units. Reset sets this register to 00H. 0LOCKR 0 0 0 00 0 LOCK Locked status Unlocked status LOCK PLL lock status check After reset: 00H R Address: FFFFF824H < > Caution The LOCK register does not re flect the lock status of the PL L in real time. The set/clear conditions are as follows. [Set conditions]

• Upon system reset Note
• In IDLE2 or STOP mode
• Upon setting of PLL stop (clearing of PLLCTL.PLLON bit to 0)
• Upon stopping main clock and using CPU with subc lock (setting of PCC.CK3 bit to 1 and setting of PCC.MCK bit to 1) Note This register is set to 01H by reset and cleared to 00H after the reset has been released and the oscillation stabilization time has elapsed. [Clear conditions]
• Upon overflow of oscillation stabilization time fo llowing reset release (OSTS register default time (see 27.2 (3) Oscillation stabilization time select register (OSTS)))
• Upon oscillation stabilization timer overflow (tim e set by OSTS register) following STOP mode release, when the STOP mode was set in the PLL operating status
• Upon PLL lockup time timer overflow (time set by PLLS register) when the PLLCTL.PLLON bit is changed from 0 to 1
• After the setup time inserted upon release of the ID LE2 mode is released (time set by the OSTS register) when the IDLE2 mode is set during PLL operation.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 6 CLOCK GENERATION FUNCTION R01UH0290EJ0300 Rev.3.00 Page 231 of 1817 Sep 19, 2011 (4) PLL lockup time specification register (PLLS) The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed from 0 to 1. This register can be read or written in 8-bit units. Reset sets this register to 03H. 210/fX 211/fX 212/fX 213/fX (default value) PLLS1 PLLS0 Selection of PLL lockup time PLLS 0 0 0 0 0 PLLS1 PLLS0 After reset: 03H R/W Address: FFFFF6C1H Cautions 1. Set so that the lockup time is 800 μs or longer. 2. Do not change the PLLS register setting during the lockup period.

6.5.3 Usage

(1) When PLL is used

• After the reset signal has been released, the PLL o perates (PLLCTL.PLLON bit = 1), but because the default mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1).
• To enable PLL operation, first set the PLLON bit to 1, and then set the SELPLL bit to 1 after the LOCKR.LOCK bit = 0. To stop the PLL, first select the clock-through mode (SELPLL bit = 0), wait for 8 clocks or more, and then stop the PLL (PLLON bit = 0).
• The PLL stops during transition to the IDLE2 or STOP mode regardless of the setting and is restored from the IDLE2 or STOP mode to the status before transition. The time required for restoration is as follows. (a) When transiting to the IDLE2 or ST OP mode from the clock through mode
• STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (min.) or longer.
• IDLE2 mode: Set the OSTS register so that the setup time is 350 μs (min.) or longer. (b) When transiting to the IDLE 2 or STOP m ode while remaining in the PLL operation mode
• STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (min.) or longer.
• IDLE2 mode: Set the OSTS register so that the setup time is 800 μs (min.) or longer. When transiting to the IDLE1 mode, the PLL does not stop. Stop the PLL if necessary. (2) When PLL is not used
• The clock-through mode (SELPLL bit = 0) is selected a fter the reset signal has been released, but the PLL is operating (PLLON bit = 1) and must therefore be stopped (PLLON bit = 0).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 232 of 1817 Sep 19, 2011 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) Timer AA (TAA) is 16-bit timer/event counter. The V850ES/JH3-E and V850ES/JJ3-E have TAA0 to TAA5.

7.1 Overview

An overview of TAAn is shown below.

• Clock selection: 8 ways
• Capture/trigger input pins: 2
• External event count input pins Note : 1
• External trigger input pin Note : 1
• Timer/counter: 1
• Capture/compare registers: 2 (32-bit capture timer function available by using a cascade connection of TAA0 and TAA1, TAA2 and TAA3.)
• Capture/compare match interrupt request signals: 2
• Timer output pins: 2 Note External event count input pins and external trigger input pins are alternately used as capture/trigger input pins (TIAAn0). Remark n = 0 to 5

7.2 Functions

TAAn has the following functions.

• Interval timer
• External event counter
• External trigger pulse output
• One-shot pulse output
• PWM output
• Free-running timer
• Pulse width measurement
• Timer-tuned function
• Simultaneous-start function

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7.3 Configuration

TAAn includes the following hardware. Table 7-1. Configuration of TAAn Item Configuration Registers 16-bit counter TAAn capture/compare registers 0, 1 (TAAnCCR0, TAAnCCR1) TAAn counter read buffer register (TAAnCNT) CCR0, CCR1 buffer registers TAAn control registers 0, 1 (TAAnCTL0, TAAnCTL1) TAAn I/O control registers 0 to 2, 4 (TAAnIOC0 to TAAnIOC2, TAAnIOC4) TAAn option registers 0, 1 (TAAnOPT0, TAAnOPT1) TAA noise elimination control register (TANFC) Timer inputs Note 1 2 (TIAAn0 Note 2 , TIAAn1 pins) Timer outputs Note 1 2 (TOAAn0, TOAAn1 pins) Notes 1. When using the functions of the TIAA n0, TIAAn1, TOAAn0, and TOAAn1 pins, see Table 4-18 Using Port Pin as Alternate-Function Pin. 2. The TIAAn0 pin functions alternat ely as a capture trigger input signal, external event count input signal, and external trigger input signal. Remark n = 0 to 5 Figure 7-1. Block Diagram of TAAn Selector Internal bus Internal bus Selector Edge detector CCR0 buffer register CCR1 buffer register TAAnCCR0 TAAnCCR1 16-bit counter TAAnCNT INTTAAnOV INTTAAnCC0 INTTAAnCC1 Output controller Clear TOAAn0 TOAAn1 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 TIAAn0 TIAAn1 Note Note TAA2, TAA3, TAA5: fXX/2, fXX/4, fXX/8, fXX/16, fXX/64, fXX/256, fXX/512, fXX/1024. Remark f XX: Main clock frequency n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 234 of 1817 Sep 19, 2011 (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TAAnCNT register. When the TAAnCTL0.TAAnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TAAnCNT register is read at this time, 0000H is read. Reset sets the TAAnCE bit to 0. Therefore, the 16-bit counter is set to FFFFH. (2) CCR0 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TAAnCCR0 register is used as a compare regist er, the value written to the TAAnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTAAnCC0) is generated. The CCR0 buffer register cannot be read or written directly. Reset clears the TAAnCCR0 register to 0000H. Therefore, the CCR0 buffer register is cleared to 0000H. (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TAAnCCR1 register is used as a compare regist er, the value written to the TAAnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTAAnCC1) is generated. The CCR1 buffer register cannot be read or written directly. Reset clears the TAAnCCR1 register to 0000H. Therefore, the CCR1 buffer register is cleared to 0000H. (4) Edge detector This circuit detects the valid edges input to the TIAAn0 and TIAAn1 pins. No edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the TAAnIOC1 and TAAnIOC2 registers. (5) Output controller This circuit controls the output of the TOAAn0 and TOAAn1 pins. The outputs of the TOAAn0 and TOAAn1 pins are controlled by the TAAnIOC0 register. (6) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock. Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 235 of 1817 Sep 19, 2011

7.3.1 Pin configuration

The timer inputs and outputs that configur e TAAn are shared with the following ports. The port functions must be set when using each pin (see Table 4-18 Using Port Pin as Alternate-Function Pin). Table 7-2 Pin Configuration Channel Port Timer AA Input Timer AA Output Other Alternate Function P30 TIAA00 Note TOAA00 TXDC0/SIF2 TAA0 P31 TIAA01 TOAA01 RXDC0/SOF2 P32 TIAA10 Note TOAA10 ASCKC0/SCKF2 TAA1 P33 TIAA11 TOAA11 SIF4/TXDB0 P34 TIAA20 Note TOAA20 SOF4/RXDB0 TAA2 P35 TIAA21 TOAA21 SCKF4/TOAA1OFF/INTP06 P25 TIAA30 Note TOAA30 SCKF1/UDMARQ0 TAA3 P26 TIAA31 TOAA31 INTP05/UDMAAK0 P42 TIAA40 Note TOAA40 SCKF0/RTP02 TAA4 P45 TIAA41 TOAA41 SCKE0/RTP05 P911 TIAA50 Note TOAA50 SCKE1/A11 TAA5 P915 TIAA51 TOAA51 SCKF3/A15 Note The TAAn0 pin functions alternately as a capture trigger input function, external event input function, and external trigger input function. Remark n = 0 to 5

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7.4 Registers

The registers that control TAAn are as follows.

• TAAn control register 0 (TAAnCTL0)
• TAAn control register 1 (TAAnCTL1)
• TAAn I/O control register 0 (TAAnIOC0)
• TAAn I/O control register 1 (TAAnIOC1)
• TAAn I/O control register 2 (TAAnIOC2)
• TAAn I/O control register 4 (TAAnIOC4)
• TAAn option register 0 (TAAnOPT0)
• TAAn option register 1 (TAAnOPT1)
• TAAn capture/compare register 0 (TAAnCCR0)
• TAAn capture/compare register 1 (TAAnCCR1)
• TAAn counter read buffer register (TAAnCNT)
• TAA noise elimination control register (TANFC) Remarks 1. When using the functions of the TIAA n0, TIAAn1, TOAAn0, and TOAAn1 pins, see Table 4-18 Using Port Pin as Alternate-Function Pin. 2. n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 237 of 1817 Sep 19, 2011 (1) TAAn control register 0 (TAAnCTL0) The TAAnCTL0 register is an 8-bit register that controls the operation of TAAn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TAAnCTL0 register by software. TAAnCE TAAn operation disabled (TAAn reset asynchronouslyNote ). TAAn operation enabled. TAAn operation started. TAAnCE TAAn operation control TAAnCTL0 (n = 0 to 5) 00 00 TAAnCKS2 TAAnCKS1 TAAnCKS0 65 43 21 After reset: 00H R/W Address: TAA0CTL0 FFFFF630H, TAA1CTL0 FFFFF640H, TAA2CTL0 FFFFF650H, TAA3CTL0 FFFFF660H, TAA4CTL0 FFFFF670H, TAA5CTL0 FFFFF680H <7> fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 (20.0 ns) (40.0 ns) (80.0 ns) (160.0 ns) (320.0 ns) (640.0 ns) (1.28 s) (2.56 s) f XX/2 fXX/4 fXX/8 fXX/16 fXX/64 fXX/256 fXX/512 fXX/1024 (40.0 ns) (80.0 ns) (160.0 ns) (320.0 ns) (1.28 s) (5.12 s) (10.24 s) (20.48 s) TAAnCKS2 Internal count clock selection TAAnCKS1 TAAnCKS0 μμ μ μ μμ Note TAAnOPT0.TAAnOVF bit, 16-bit counter, timer output (TOAAn0, TOAAn1 pins) Cautions 1. Set the TAAnCKS2 to TAAnCKS 0 bits when the TAAnCE bit = 0. When the value of the TAAnCE bit is changed from 0 to 1, the TAAnCKS2 to TAAnCKS0 bits can be set simultaneously. 2. Be sure to set bits 3 to 6 to “0”. Remark f XX: Main clock frequency The values in parentheses indicate the cycles when f XX = 50 MHz.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 238 of 1817 Sep 19, 2011 (2) TAAn control register 1 (TAAnCTL1) The TAAnCTL1 register is an 8-bit register that controls the operation of TAAn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) TAAnEST Software trigger control (n = 0 to 5) After reset: 00H R/W Address: Generates a valid signal for external trigger input.

• In one-shot pulse output mode: A one-shot pulse is output with writing 1 to the TAAnEST bit as the trigger.
• In external trigger pulse output mode: A PWM waveform is output with writing 1 to the TAAnEST bit as the trigger. Tuned operation mode enable control (n = 0, 2, 4, 5) Tuned-operation function (specification of slave operation) Simultaneous-start function (specification of slave timer) Independent operation mode (asynchronous operation mode) Setting prohibited For the tuned-operation function, see 7.6 Timer-Tuned Operation Function. For the simultaneous-start function, see 7.7 Simultaneous-Start Function. TAA0SYETAA0CTL1 TAA0EST TAA0EEETAA0SYM 0 TAA0MD2 TAA0MD1 TAA0MD0 TAA2SYETAA2CTL1 TAA2EST TAA2EEETAA2SYM 0 TAA2MD2 TAA2MD1 TAA2MD0 TAA5SYETAA5CTL1 TAA5EST TAA5EEETAA5SYM 0 TAA5MD2 TAA5MD1 TAA5MD0 0TAA1CTL1 TAA1EST TAA1EEE 0 0 TAA1MD2 TAA1MD1 TAA1MD0 TAA4SYETAA4CTL1 TAA4EST TAA4EEETAA4SYM 0 TAA4MD2 TAA4MD1 TAA4MD0 0TAA3CTL1 TAA3EST TAA3EEE 0 0 TAA3MD2 TAA3MD1 TAA3MD0 <6> 4 3 1 TAA0CTL1 FFFFF631H, TAA1CTL1 FFFFF641H, TAA2CTL1 FFFFF651H, TAA3CTL1 FFFFF661H, TAA4CTL1 FFFFF671H, TAA5CTL1 FFFFF681H 7 02 TAAnSYE TAA1 Master timer Slave timer TAA3 TAB0 TAB1 TAA0 TAA2 TAA5 TAA4 TAAnSYM These bits can be set only for the slave timer (setting them for the master timer is prohibited). The relationship between the master timer and slave timer is as follows. <5> Cautions 1. The TAAnEST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode . In any other mode, writing 1 to this bit is ignored. 2. Be sure to clear the sections of the TAAnCTL1 register of each channel, where 0 is specified, to 0.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 239 of 1817 Sep 19, 2011 (2/2) Disables operation with external event count input. (Performs counting with the count clock selected by the TAAnCTL0.TAAnCK0 to TAAnCK2 bits.) TAAnEEE Count clock selection The TAAnEEE bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. Interval timer mode External event count mode External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode Setting prohibited TAAnMD2 Timer mode selection TAAnMD1 TAAnMD0 Enables operation with external event count input. (Performs counting at every valid edge of the external event count input signal.) Cautions 1. External event count input is selected in the external event count mode regardless of the value of the TAAnEEE bit. 2. Set the TAAnEEE and TAAnMD 2 to TAAnMD0 bits when the TAAnCTL0.TAAnCE bit = 0. (The sam e value can be written when the TAAnCE bit = 1.) The operation is not guaranteed when rewriting is performed with the TAAnCE bit = 1. If rewriting was mistakenly performed, clear the TAAnCE bit to 0 an d then set the bits again (n = 0 to 5).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 240 of 1817 Sep 19, 2011 (3) TAAn I/O control register 0 (TAAnIOC0) The TAAnIOC0 register is an 8-bit register that controls the timer output (TOAAn0, TOAAn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. TAAnOL1 TOAAn1 pin output level settingNote TOAAn1 pin output starts at high level TOAAn1 pin output starts at low level TAAnIOC0 (n = 0 to 5) 0 0 0 TAAnOL1 TAAnOE1 TAAnOL0 TAAnOE0 65 43 < 2 > 1 After reset: 00H R/W Address: TAA0IOC0 FFFFF632H, TAA1IOC0 FFFFF642H, TAA2IOC0 FFFFF652H, TAA3IOC0 FFFFF662H, TAA4IOC0 FFFFF672H, TAA5IOC0 FFFFF682H TAAnOE1 TOAAn1 pin output setting Timer output disabled

• When TAAnOL1 bit = 0: Low level is output from the TOAAn1 pin
• When TAAnOL1 bit = 1: High level is output from the TOAAn1 pin TAAnOL0 TOAAn0 pin output level settingNote TOAAn0 pin output starts at high level TOAAn0 pin output starts at low level TAAnOE0 TOAAn0 pin output setting Timer output disabled
• When TAAnOL0 bit = 0: Low level is output from the TOAAn0 pin
• When TAAnOL0 bit = 1: High level is output from the TOAAn0 pin 7 <0> Timer output enabled (a square wave is output from the TOAAn1 pin). Timer output enabled (a square wave is output from the TOAAn0 pin). Note The output level of t he timer output pin (TOAAnm) specified by the TAAnOLm bit is shown below. TAAnCE bit TOAAnm pin output 16-bit counter
• When TAAnOLm bit = 0 TAAnCE bit TOAAnm pin output 16-bit counter
• When TAAnOLm bit = 1 Cautions 1. Rewrite the TAAnOL1, TAAnOE1, TAAnOL0, and TAAnOE0 bits when the TAAnCTL0.TAAnCE bit = 0. (The same value can be written when the TAAnCE bit = 1.) If rewriting was mistakenly performed, clear the TAAnCE bit to 0 and then set the bits again. 2. Even if the TAAnOLm bit is manipulated when the TAAnCE and TAAnOEm bits are 0, the TOAAnm pin output level varies. Remark m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 241 of 1817 Sep 19, 2011 (4) TAAn I/O control register 1 (TAAnIOC1) The TAAnIOC1 register is an 8-bit register that controls th e valid edge of the capture tr igger input signals (TIAAn0, TIAAn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. TAAnIS3 TAAnIS2 Capture trigger input signal (TIAAn1 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges TAAnIOC1 (n = 0 to 5) 0 0 0 TAAnIS3 TAAnIS2 TAAnIS1 TAAnIS0 65 43 21 After reset: 00H R/W Address: TAA0IOC1 FFFFF633H, TAA1IOC1 FFFFF643H, TAA2IOC1 FFFFF653H, TAA3IOC1 FFFFF663H, TAA4IOC1 FFFFF673H, TAA5IOC1 FFFFF683H TAAnIS1 TAAnIS0 Capture trigger input signal (TIAAn0 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges 7 0 Cautions 1. Rewrite the TAAnIS 3 to TAAnIS0 bits when the TAAnCTL0.TAAnCE bit = 0. (The same value can be written when the TAAnCE bit = 1.) If rewriting was mistakenly performed, clear the TAAnCE bit to 0 and then set the bits again. 2. The TAAnIS3 to TAAnIS0 bi ts are valid only in the free- running timer mode and the pulse width measurement mode. In all other modes, a capture operation is not performed.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 242 of 1817 Sep 19, 2011 (5) TAAn I/O control register 2 (TAAnIOC2) The TAAnIOC2 register is an 8-bit regi ster that controls the va lid edge of the external event count input signal (TIAAn0 pin) and external trigger input signal (TIAAn0 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. TAAnEES1 TAAnEES0 External event count input signal (TIAAn0 pin) valid edge setting No edge detection (external event count invalid) Detection of rising edge Detection of falling edge Detection of both edges TAAnIOC2 (n = 0 to 5) 00 0 TAAnEES1TAAnEES0 TAAnETS1 TAAnETS0 65 43 21 After reset: 00H R/W Address: TAA0IOC2 FFFFF634H, TAA1IOC2 FFFFF644H, TAA2IOC2 FFFFF654H, TAA3IOC2 FFFFF664H. TAA4IOC2 FFFFF674H, TAA5IOC2 FFFFF684H TAAnETS1 TAAnETS0 External trigger input signal (TIAAn0 pin) valid edge setting No edge detection (external trigger invalid) Detection of rising edge Detection of falling edge Detection of both edges 7 0 Cautions 1. Rewrite the T AAnEES1, TAAnEES0, TAAnETS1, and TAAnETS0 bits when the TAAnCTL0.TAAnCE bit = 0. (The same value can be written when the TAAnCE bit = 1.) If rewriting was mistakenly performed, clear the TAAnCE bit to 0 and then set the bits again. 2. The TAAnEES1 and TAAnEES0 bits are valid only when the TAAnCTL1.TAAnEEE bit = 1 or when the external event count mode (TAAnCTL1.TAAnMD2 to TAAnCTL1.TAAnMD0 bits = 001) has been set. 3. The TAAnETS1 and TAAnETS0 bits are valid only when the external trigger pulse output mode (TAAnCTL1.TAAnMD2 to TAAnCTL1.TAAnMD0 bits = 010) or the one-shot pulse output mode (TAAnCTL1.TAAnMD2 to TAAnCTL1.TAAnMD0 = 011) is set.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 243 of 1817 Sep 19, 2011 (6) TAAn I/O control register 4 (TAAnIOC4) The TAAnIOC4 register is an 8-bit register that controls the timer output. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. This register is not reset by stopping the timer operation (TAAnCTL0.TAAnCE = 0). Cautions 1. Accessing the TAAnIOC4 register is prohibi ted in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock 2. The TAAnIOC4 register can be set only in the interval timer mode and free-running timer mode. Be sure to set the TAAnIOC4 register to 00H in all other modes (for details of the mode setting, see 7.4 (2) TAAn control register 1 (TAAnCTL1)). The TAAnIOC4 register setting is invalid if the TAAnCCR0 and TAAnCCR1 registers are set to the capture functi on, even if the free-running timer mode is set. TAAnOS1 TAAnOR1 TAAnIOC4 (n = 0 to 5) 0 0 0 TAAnOS1 TAAnOR1 TAAnOS0 TAAnOR0 65 4 3 21 TAA0IOC4 FFFFF63CH, TAA1IOC4 FFFFF64CH, TAA2IOC4 FFFFF65CH, TAA3IOC4 FFFFF66CH, TAA4IOC4 FFFFF67CH, TAA5IOC4 FFFFF68CH TAAnOS0 TAAnOR0 7 0 After reset: 00H R/W Address: Toggle control of TIAAn1 pin No request. Normal toggle operation. Reset request Fix to inactive level upon next match between value of 16-bit counter and value of TAAnCCR1 register. Set request Fix to active level upon next match between value of 16-bit counter and value of TAAnCCR1 register. Keep request Keep current output level. Toggle control of TIAAn0 No request. Normal toggle operation. Reset request Fix to inactive level upon next match between value of 16-bit counter and value of TAAnCCR0 register. Set request Fix to active level upon next match between value of 16-bit counter and value of TAAnCCR0 register. Keep request Keep current output level.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 244 of 1817 Sep 19, 2011 (7) TAAn option register 0 (TAAnOPT0) The TAAnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. TAAnCCS1 TAAnCCR1 register capture/compare selection The TAAnCCS1 bit setting is valid only in the free-running timer mode. Compare register selected Capture register selected TAAnOPT0 (n = 0 to 5) TAAnCCS1TAAnCCS0 0 0 0 TAAnOVF 65 43 21 After reset: 00H R/W Address: TAA0OPT0 FFFFF635H, TAA1OPT0 FFFFF645H, TAA2OPT0 FFFFF655H, TAA3OPT0 FFFFF665H, TAA4OPT0 FFFFF675H, TAA5OPT0 FFFFF685H TAAnCCS0 TAAnCCR0 register capture/compare selection The TAAnCCS0 bit setting is valid only in the free-running timer mode. Compare register selected Capture register selected TAAnOVF Set (1) Reset (0) TAAn overflow detection flag

• The TAAnOVF bit is set to 1 when the 16-bit counter count value overflows from FFFFH to 0000H in the free-running timer mode or the pulse width measurement mode.  An interrupt request signal (INTTAAnOV) is generated at the same time that the TAAnOVF bit is set to 1. The INTTAAnOV signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode.  The TAAnOVF bit is not cleared even when the TAAnOVF bit or the TAAnOPT0 register are read when the TAAnOVF bit = 1.  The TAAnOVF bit can be both read and written, but the TAAnOVF bit cannot be set to 1 by software. Writing 1 has no influence on the operation of TAAn. Overflow occurred 0 written to TAAnOVF bit or TAAnCTL0.TAAnCE bit = 0 7 <0> Cautions 1. Rewrite the TAAnCCS 1 and TAAnCCS0 bits when the TAAnCE bit = 0. (The same value can be written when the TAAnCE bit = 1.) If rewriting was mistakenly performed, clear the TAAnCE bit to 0 and then set the bits again. 2. Be sure to set bits 1 to 3, 6, and 7 to “0”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 245 of 1817 Sep 19, 2011 (8) TAAn option register 1 (TAAnOPT1) The TAAnOPT1 register is an 8-bit r egister that controls the 32-bit capt ure function realized by a cascade connection. Rewriting this register is prohibited while the timer is operating (TAAnCTL0.TAAnCE = 1). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. TAAnCSE TAAnCSE Cascade control Individual operation or operation as lower side of cascade function Operation as higher side of cascade function TAAnOPT1 (n = 0, 2) 00 00 000 65 43 21 TAA0OPT1 FFFFF63DH, TAA2OPT1 FFFFF65DH 7 0 After reset: 00H R/W Address: Cautions 1. Cascade connection a nd timer-tuned operation cannot be used together. Be sure to set TAAnCTL1.TAAnSYE to 0 for a cascade connection. 2. For a cascade connecti on, set the free-running timer mode and use the TAAnCCR0 and TAAnCCR1 registers as capture registers. For details of cascade c onnection, see 7.8 Cascade Connection.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 246 of 1817 Sep 19, 2011 (9) TAAn capture/compare register 0 (TAAnCCR0) The TAAnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capt ure register or a compare register only in the free-running timer mode, depending on the setting of the TAAnOPT0.TAAnCCS0 bit. In the pulse width measurement mode, the TAAnCCR0 register can be used only as a capture register. In an y other mode, this register can be used only as a compare register. The TAAnCCR0 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TAAnCCR0 register is prohibite d in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock TAAnCCR0 (n = 0 to 5) 12 10 8 6 4 2 After reset: 0000H R/W Address: TAA0CCR0 FFFFF636H, TAA1CCR0 FFFFF646H, TAA2CCR0 FFFFF656H, TAA3CCR0 FFFFF666H, TAA4CCR0 FFFFF676H, TAA5CCR0 FFFFF686H 14 013 11 9 7 5 315 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 247 of 1817 Sep 19, 2011 (a) Function as compare register The TAAnCCR0 register can be rewritten even when the TAAnCTL0.TAAnCE bit = 1. The set value of the TAAnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16- bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTAAnCC0) is generated. If TOAAn0 pin output is enabled at this time , the output of the TOAAn0 pin is inverted. When the TAAnCCR0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse out put mode, or PWM output mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register. (b) Function as capture register When the TAAnCCR0 register is used as a capture register in the free-runni ng timer mode, the count value of the 16-bit counter is stored in the TAAnCCR0 register if the valid edge of the captur e trigger input pin (TIAAn0 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TAAnCCR0 register and the 16-bit counter is cleared (000 0H) if the valid edge of the capture trigger input pin (TIAAn0) is detected. Even if the capture operation and reading the TAAnCCR0 register conflict, the correct value of the TAAnCCR0 register can be read. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 7-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register −

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 248 of 1817 Sep 19, 2011 (10) TAAn capture/compare register 1 (TAAnCCR1) The TAAnCCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capt ure register or a compare register only in the free-running timer mode, depending on the setting of the TAAnOPT0.TAAnCCS1 bi t. In the pulse width measurement mode, the TAAnCCR1 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TAAnCCR1 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TAAnCCR1 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock TAAnCCR1 (n = 0 to 5) 12 10 8 6 4 2 After reset: 0000H R/W Address: TAA0CCR1 FFFFF638H, TAA1CCR1 FFFFF648H, TAA2CCR1 FFFFF658H, TAA3CCR1 FFFFF668H, TAA4CCR1 FFFFF678H, TAA5CCR1 FFFFF688H 14 013 11 9 7 5 315 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 249 of 1817 Sep 19, 2011 (a) Function as compare register The TAAnCCR1 register can be rewritten even when the TAAnCTL0.TAAnCE bit = 1. The set value of the TAAnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16- bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTAAnCC1) is generated. If TOAAn1 pin output is enabled at this time , the output of the TOAAn1 pin is inverted. (b) Function as capture register When the TAAnCCR1 register is used as a capture register in the free-runni ng timer mode, the count value of the 16-bit counter is stored in the TAAnCCR1 register if the valid edge of the captur e trigger input pin (TIAAn1 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TAAnCCR1 register and the 16-bit counter is cleared (000 0H) if the valid edge of the capture trigger input pin (TIAAn1) is detected. Even if the capture operation and reading the TAAnCCR1 register conflict, the correct value of the TAAnCCR1 register can be read. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 7-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register −

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 250 of 1817 Sep 19, 2011 (11) TAAn counter read buffer register (TAAnCNT) The TAAnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TAAnCTL0.TAAnCE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units. The value of the TAAnCNT register is cleared to 0000H when the TAAnCE bit = 0. If the TAAnCNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. Reset clears the TAAnCE bit to 0. Therefore, the value of the TAAnCNT register is cleared to 0000H. Caution Accessing the TAAnCNT register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock TAAnCNT (n = 0 to 5) 12 10 8 6 4 2 After reset: 0000H R Address: TAA0CNT FFFFF63AH, TAA1CNT FFFFF64AH, TAA2CNT FFFFF65AH, TAA3CNT FFFFF66AH, TAA4CNT FFFFF67AH, TAA5CNT FFFFF68AH 14 013 11 9 7 5 315 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 251 of 1817 Sep 19, 2011 (12) Noise elimination control register (TANFCn) Digital noise elimination can be selected for the TIAAn0 and TIAAn1 pins. The noise elimination setting is selected using the TANFCn register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among f XX and fXX/4. Sampling is performed 3 times. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution Time equal to the sampling clock × 3 clocks is required until th e digital noise eliminator is initialized after the sampling clock has been changed. If the valid edge of TIAAn0 and TIAAn1 is input after the sampling clock has been change d and before the time of the sampling clock × 3 clocks passes, therefore, an interrupt request si gnal may be generated. Therefore, when using the external trigger function, th e external event function, and the capture trigger function of TAAn, enable TAAn operation after the time of the sampling clock × 3 clocks has elapsed. Remark n = 0 to 5 TANFENnTANFCn (n = 0 to 5) 0 0 0 0 0 0 TANFCn0 fXX fXX/4 TANFCn0 Digital sampling clock After reset: 00H R/W Address: TANFC0 FFFFF5A0H, TANFC1 FFFFF5A2H, TANFC2 FFFFF5A4H, TANFC3 FFFFF5A6H, TANFC4 FFFFF5A8H, TANFC5 FFFFF5AAH Does not perform digital noise elimination Performs digital noise elimination TANFENn Setting of digital noise elimination < > Remarks 1. Since sampling is performed 3 times, the noise width for reliably eliminating noise is 2 sampling clocks. 2. In the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is generated if noise synchronized with the sampling clock is input.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 252 of 1817 Sep 19, 2011 A timing example of noise elimination performed by the timer AA input pin digital filter is shown Figure 7-2. Figure 7-2. Example of Digital Noise Elimination Timing Noise elimination clock Input signal Internal signal 3 clocks Sampling 3 times 3 clocks1 clock 1 clock 2 clocks 2 clocks Sampling 3 times Remark If there are two or fewer noise elimination cloc ks while the TIAAn0 or TIAAn1 input signal is high level (or low level), that input signal is eliminated as noise. If it is sampled three times or more, the edge is detected as a valid input (n = 0 to 5).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 253 of 1817 Sep 19, 2011

7.5 Operation

TAAn can perform the following operations. Operation TAAnCTL1.TAAnEST Bit (Software Trigger Bit) TIAAn0 Pin (External Trigger Input) Capture/Compare Register Setting Compare Register Write Interval timer mode Invalid Invalid Compare only Anytime write External event count mode Note 1 Invalid Invalid Compare only Anytime write External trigger pulse output mode Note 2 Valid Valid Compare only Batch write One-shot pulse output mode Note 2 Valid Valid Compare only Anytime write PWM output mode Invalid Invalid Compare only Batch write Free-running timer mode Invalid Invalid Switching enabled Anytime write Pulse width measurement mode Note 2 Invalid Invalid Capture only Not applicable Notes 1. To use the external event count mode , specify that the valid edge of the TI AAn0 pin capture trigger input is not detected (by clearing the TAAnIOC1.TAAnIS1 and TAAnIOC1.TAAnIS0 bits to “00”). 2. When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the TAAnCTL1.TAAnEEE bit to 0). Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 254 of 1817 Sep 19, 2011 (1) Anytime write and batch write With TAAn, the TAAnCCR0 and TAAnCCR1 registers can be rewritten during timer operation (TAAnCTL0.TAAnCE bit = 1), but the write method (anytime write, batch wr ite) of the CCR0 and CCR1 buffer registers differs depending on the mode. (a) Anytime write In this mode, data is transferred at any time from the TAAnCCR0 and TAAnCCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. Remark n = 0 to 5 Figure 7-3. Example of Basic Anytime Write Operation Flowchart (Interval Timer Mode of TAA0) START Initial settings

• Set values to TAACCRm register
• Timer operation enable (TAA0CE bit = 1) →Transfer values of TAA0CCRm register to CCRm buffer register Timer operation
• Match between 16-bit counter and CCR1 buffer registerNote
• Match between 16-bit counter and CCR0 buffer register
• 16-bit counter clear & start INTTAA0CC1 signal output TAA0CCRm register rewrite → Transfer to CCRm buffer register INTTAA0CC0 signal output Note The 16-bit counter is not cleared upon a match between the 16-bit counter value and the CCR1 buffer register value. It is cleared upon a match between the 16-bit counter value and the CCR0 buffer register value. Remark m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 255 of 1817 Sep 19, 2011 Figure 7-4. Example of Anytime Write Timing (Interval Timer Mode of TAA0) D01 D01 D01 D010000H TAA0CE bit = 1 D02 D02 D11 D11 D11 D12 D12 D12 D02 D110000H D12 16-bit counter TAA0CCR0 register TAA0CCR1 register INTTAA0C0 signal INTTAA0CC1 signal CCR0 buffer register CCR1 buffer register 0000H FFFFH Remark D 01, D02: Set values of TAA0CCR0 register D 11, D12: Set values of TAA0CCR1 register

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 256 of 1817 Sep 19, 2011 (b) Batch write In this mode, data is transferred all at once from the TAAnCCR0 and TAAnCCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. This da ta is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counte r. Transfer is enabled by writing to the TAAnCCR1 register. Whether to enable or disable the next transfe r timing is controlled by writ ing or not writing to the TAAnCCR1 register. In order for the set value when the TAAnCCR0 and TAAnCCR1 registers are rewritten to become the 16-bit counter comparison value (in other words, in order fo r this value to be transferred to the CCR0 and CCR1 buffer registers), it is necessary to rewrite the TAAn CCR0 register and then write to the TAAnCCR1 register before the 16-bit counter value and the CCR0 buffer re gister value match. Ther efore, the values of the TAAnCCR0 and TAAnCCR1 registers are transferred to the CCR0 and CCR1 buffer registers upon a match between the count value of the 16-bit counter and the va lue of the CCR0 buffer register. Thus even when wishing only to rewrite the value of the TAAnCCR0 register, also write the same value (same as preset value of the TAAnCCR1 register) to the TAAnCCR1 register. Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 257 of 1817 Sep 19, 2011 Figure 7-5. Example of Basic Batch Write Operation Flowchart (PWM Output Mode of TAA0) START Initial settings Set values to TAA0CCRm register Enable timer operation (TAA0CE bit = 1) Transfer values of TAA0CCRm register to CCRm buffer register Timer operation Match between 16-bit counter and CCR1 buffer registerNote Match between 16-bit counter and CCR0 buffer register 16-bit counter clear & start Transfer of values of TAA0CCRm register to CCRm buffer register INTTAA0CC1 signal output TAA0CCR0 register rewrite TAA0CCR1 register rewrite INTTAA0CC0 signal output Batch write enable Note The 16-bit counter is not cleared upon a matc h between the 16-bit counter value and the CCR1 buffer register value. It is cleared upon a match between the 16-bit counter value and the CCR0 buffer register value. Caution Writing to the TAA0CCR1 register includ es enabling of batch write. Thus, rewrite the TAA0CCR1 register after rewriting the TAA0CCR0 register. Remark m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 258 of 1817 Sep 19, 2011 Figure 7-6. Timing of Batch Write (Interval Timer Mode of TAA0) D01 D01 D02 D03 0000H D 01 D11 D12 D12 0000H D 11 TAA0CE bit = 1 Note 1 D02 D02 D03 D11 D12D12D12D1216-bit counter TAA0CCR0 register TAA0CCR1 register INTTAA0CC0 signal INTTAA0CC1 signal TOAA01 pin output TOAA00 pin output CCR0 buffer register CCR1 buffer register Note 1 Note 1 Note 1Same value write D02 D12 0000H D03 D12 Note 2 Note 3 FFFFH Notes 1. Because the TAA0CCR1 register was not rewritten, D 03 is not transferred. 2. Because the TAA0CCR1 register has been written (D 12), data is transferred to the CCR1 buffer register upon a match between the value of the 16-bit counter and the value of the TAA0CCR0 register (D01). 3. Because the TAA0CCR1 register has been written (D 12), data is transferred to the CCR1 buffer register upon a match between the value of the 16-bit counter and the value of the TAA0CCR0 register (D02). Remark D 01, D02, D03: Set values of TAA0CCR0 register D 11, D12: Set values of TAA0CCR1 register

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 259 of 1817 Sep 19, 2011

7.5.1 Interval timer mode (T AAnMD2 to TAAnMD0 bits = 000)

In the interval timer mode, an interrupt request signal (INTTAAnCC0) is generated at any interval if the TAAnCTL0.TAAnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOAAn0 pin. Usually, the TAAnCCR1 register is not used in the interval timer mode. Figure 7-7. Configuration of Interval Timer 16-bit counter Output controller CCR0 buffer registerTAAnCE bit TAAnCCR0 register Count clock selection Clear Match signal TOAAn0 pin INTTAAnCC0 signal Remark n = 0 to 5 Figure 7-8. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register TOAAn0 pin output INTTAAnCC0 signal D0 D0 D0 D0 Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 260 of 1817 Sep 19, 2011 When the TAAnCE bit is set to 1, the value of the 16-bi t counter is cleared from FFFFH to 0000H in synchronization with the count clock, and t he counter starts counting. At this time, the out put of the TOAAn0 pin is inverted. Additionally, the set value of the TAAnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, the output of the TOAAn0 pin is inverted, and a compare match interrupt request signal (INTTAAnCC0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TAAnCCR0 register + 1) × Count clock cycle Remark n = 0 to 5 Figure 7-9. Register Settings for Interval Timer Mode Operation (1/2) (a) TAAn control register 0 (TAAnCTL0) 0/1 0 0 0 0 TAAnCTL0 Select count clock 0: Stops counting 1: Enables counting 0/1 0/1 0/1 TAAnCKS2 TAAnCKS1 TAAnCKS0TAAnCE (b) TAAn control register 1 (TAAnCTL1) 0 0 0/1 Note 00 TAAnCTL1 0, 0, 0: Interval timer mode 0: Operates on count clock selected by TAAnCKS0 to TAAnCKS2 bits 1: Counts with external event count input signal 000 TAAnMD2 TAAnMD1 TAAnMD0TAAnEEETAAnEST Note This bit can be set to 1 only when the interrupt request signals (INTTAAnCC0 and INTTAAnCC1) are masked by the interrupt mask flags (TAAnCCMK0 and TAAnCCMK1) and timer output (TOAAn1) is performed. However, set the TAAnCCR0 and TAAnCCR1 registers to the same value (see 7.5.1 (2) (d) Operation of TAAnCCR1 register). Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 261 of 1817 Sep 19, 2011 Figure 7-9. Register Settings for Interval Timer Mode Operation (2/2) (c) TAAn I/O control register 0 (TAAnIOC0) 0 0 0 0 0/1 TAAnIOC0 0: Disables TOAAn0 pin output 1: Enables TOAAn0 pin output Setting of output level with operation of TOAAn0 pin disabled 0: Low level 1: High level 0: Disables TOAAn1 pin output 1: Enables TOAAn1 pin output Setting of output level with operation of TOAAn1 pin disabled 0: Low level 1: High level 0/1 0/1 0/1 TAAnOE1 TAAnOL0 TAAnOE0TAAnOL1 (d) TAAn counter read buffer register (TAAnCNT) By reading the TAAnCNT register, the count value of the 16-bit counter can be read. (e) TAAn capture/compare register 0 (TAAnCCR0) If the TAAnCCR0 register is set to D0, the interval is as follows. Interval = (D0 + 1) × Count clock cycle (f) TAAn capture/compare register 1 (TAAnCCR1) Usually, the TAAnCCR1 register is not used in the in terval timer mode. However, the set value of the TAAnCCR1 register is transferred to the CCR1 buffer register. A compare match interrupt request signal (INTTAAnCC1) is generated when the count value of t he 16-bit counter matches the value of the CCR1 buffer register. Therefore, mask the interrupt request by using the corresponding interrupt mask flag (TAAnCCMK1). Remarks 1. TAAn I/O control register 1 (TAAnIOC1), TAAn I/O control register 2 (TAAnIOC2), and TAAn option register 0 (TAAnOPT0) are not used in the interval timer mode. 2. n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 262 of 1817 Sep 19, 2011 (1) Interval timer mode operation flow Figure 7-10. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register TOAAn0 pin output INTTAAnCC0 signal D0 D0 D0 <1> <2> TAAnCE bit = 1 TAAnCE bit = 0 Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC0 register, TAAnCCR0 register Initial setting of these registers is performed before setting the TAAnCE bit to 1. The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting has been started (TAAnCE bit = 1). The counter is initialized and counting is stopped by clearing the TAAnCE bit to 0. START STOP <1> Count operation start flow <2> Count operation stop flow Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 263 of 1817 Sep 19, 2011 (2) Interval timer mode operation timing (a) Operation if TAAnCCR0 register is set to 0000H If the TAAnCCR0 register is set to 0000H, the IN TTAAnCC0 signal is generated at each count clock subsequent to the first count clock, and the output of the TOAAn0 pin is inverted. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter TAAnCE bit TAAnCCR0 register TOAAn0 pin output INTTAAnCC0 signal 0000H Interval time Count clock cycle Interval time Count clock cycle FFFFH 0000H 0000H 0000H 0000H Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 264 of 1817 Sep 19, 2011 (b) Operation if TAAnCCR0 register is set to FFFFH If the TAAnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing . The INTTAAnCC0 signal is generated and the output of the TOAAn0 pin is inverted. At this time, an overflow interrupt request signal (INTTAAnOV) is not generated, nor is the overflow flag (TAAnOPT0.TAAnOVF bit) set to 1. FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register TOAAn0 pin output INTTAAnCC0 signal FFFFH Interval time 10000H × count clock cycle Interval time 10000H × count clock cycle Interval time 10000H × count clock cycle Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 265 of 1817 Sep 19, 2011 (c) Notes on rewriting TAAnCCR0 register To change the value of the TAAnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TAAnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register TAAnOL0 bit TOAAn0 pin output INTTAAnCC0 signal D1 D2 D1 D1 D2D2 D2 L Interval time (1) Interval time (NG) Interval time (2) Remarks 1. Interval time (1): (D 1 + 1) × Count clock cycle Interval time (NG): (10000H + D 2 + 1) × Count clock cycle Interval time (2): (D 2 + 1) × Count clock cycle 2. n = 0 to 5 If the value of the TAAnCCR0 register is changed from D 1 to D 2 while the count value is greater than D 2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TAAnCCR0 register has been rewritten. Consequently, the value of the 16-bit counter that is compared is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D 2, the INTTAAnCC0 signal is generated and the output of the TOAAn0 pin is inverted. Therefore, the INTTAAnCC0 signal may not be generated at the interval time “(D 1 + 1) × Count clock cycle” or “(D2 + 1) × Count clock cycle” as originally expected, but may be generated at an interval of “(10000H + D2 + 1) × Count clock period”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 266 of 1817 Sep 19, 2011 (d) Operation of TAAnCCR1 register Figure 7-11. Configuration of TAAnCCR1 Register CCR0 buffer register TAAnCCR0 register TAAnCCR1 register CCR1 buffer register TOAAn0 pin INTTAAnCC0 signal TOAAn1 pin INTTAAnCC1 signal 16-bit counter Output controller TAAnCE bit Count clock selection Clear Match signal Output controller Match signal Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 267 of 1817 Sep 19, 2011 If the set value of the TAAnCCR1 register is less than the set value of the TAAnCCR0 register, the INTTAAnCC1 signal is generated once per cycle. At the same time, the output of the TOAAn1 pin is inverted. The TOAAn1 pin outputs a square wave with the same cycle as that output by the TOAAn0 pin. Figure 7-12. Timing Chart When D01 ≥ D11 FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register TOAAn0 pin output INTTAAnCC0 signal TAAnCCR1 register TOAAn1 pin output INTTAAnCC1 signal D01 D11 D01 D11 D11 D11 D11 D01 D01 D01 Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 268 of 1817 Sep 19, 2011 If the set value of the TAAnCCR1 register is greater than the set value of the T AAnCCR0 register, the count value of the 16-bit counter does not match the value of the TAAn CCR1 register. Consequently, the INTTAAnCC1 signal is not generated, nor is the output of the TOAAn1 pin changed. Figure 7-13. Timing Chart When D01 < D11 FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register TOAAn0 pin output INTTAAnCC0 signal TAAnCCR1 register TOAAn1 pin output INTTAAnCC1 signal D01 D11 D01 D01 D01 D01 L Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 269 of 1817 Sep 19, 2011

7.5.2 External event count mode (TAAnMD2 to TAAnMD0 bits = 001)

In the external event count mode, the valid edge of the external event count input is counted when the TAAnCTL0.TAAnCE bit is set to 1, and an interrupt request signal (INTTAAnCC0) is generated each time the specified number of edges have been counted. The TOAAn0 pin cannot be used. Usually, the TAAnCCR1 register is not used in the external event count mode. Figure 7-14. Configuration in External Event Count Mode 16-bit counter CCR0 buffer registerTAAnCE bit TAAnCCR0 register Edge detector Clear Match signal INTTAAnCC0 signal TIAAn0 pin (external event count input) Remark n = 0 to 5 Figure 7-15. Basic Timing in External Event Count Mode FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register INTTAAnCC0 signal D0 D0 D0 16-bit counter TAAnCCR0 register INTTAAnCC0 signal External event count input (TIAAn0 pin input) External event count interval 0 + 1) D0 − 1D 0 0000 0001 External event count interval 0 + 1) External event count interval 0 + 1) Remarks 1. This figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input. 2. n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 270 of 1817 Sep 19, 2011 When the TAAnCE bit is set to 1, the value of the 16-bit c ounter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is dete cted. Additionally, the set value of the TAAnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTAAnCC0) is generated. The INTTAAnCC0 signal is generated each time the valid edge of the external event count input has been detected (set value of TAAnCCR0 register + 1) times. Figure 7-16. Register Setting for Operation in External Event Count Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) 0/1 0 0 0 0 TAAnCTL0 0: Stops counting 1: Enables counting 000 TAAnCKS2 TAAnCKS1 TAAnCKS0TAAnCE (b) TAAn control register 1 (TAAnCTL1) 0000 0 TAAnCTL1 0, 0, 1: External event count mode 001 TAAnMD2 TAAnMD1 TAAnMD0TAAnEEETAAnEST (c) TAAn I/O control register 0 (TAAnIOC0) 0000 0 TAAnIOC0 0: Disables TOAAn0 pin output 0: Disables TOAAn1 pin output 000 TAAnOE1 TAAnOL0 TAAnOE0TAAnOL1 (d) TAAn I/O control register 2 (TAAnIOC2) 0 0 0 0 0/1 TAAnIOC2 Select valid edge of external event count input 0/1 0 0 TAAnEES0 TAAnETS1 TAAnETS0TAAnEES1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 271 of 1817 Sep 19, 2011 Figure 7-16. Register Setting for Operation in External Event Count Mode (2/2) (e) TAAn counter read buffer register (TAAnCNT) The count value of the 16-bit counter can be read by reading the TAAnCNT register. (f) TAAn capture/compare register 0 (TAAnCCR0) If D0 is set to the TAAnCCR0 register, the counter is cleared and a compare match interrupt request signal (INTTAAnCC0) is generated when the number of external event counts reaches (D0 + 1). (g) TAAn capture/compare register 1 (TAAnCCR1) Usually, the TAAnCCR1 register is not used in the external event count mode. However, the set value of the TAAnCCR1 register is transferred to the CCR1 buff er register. When the count value of the 16-bit counter matches the value of the CCR1 buffer re gister, a compare match interrupt request signal (INTTAAnCC1) is generated. Therefore, mask the interrupt signal by using the interrupt mask flag (TAAnCCMK1). Caution When an external clock is used as the count clock, the external clock can be input only from the TIAAn0 pin. At this time, set the TAAnIOC1.TAAnIS1 and TAAnIOC1.TAAnIS0 bits to 00 (capture trigger input (TIAAn0 pin): no edge detection). Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are not used in the external event count mode. 2. n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 272 of 1817 Sep 19, 2011 (1) External event count mode operation flow Figure 7-17. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register INTTAAnCC0 signal D0 D0 D0 <1> <2> TAAnCE bit = 1 TAAnCE bit = 0 Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC0 register, TAAnIOC2 register, TAAnCCR0 register Initial setting of these registers is performed before setting the TAAnCE bit to 1. The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting has been started (TAAnCE bit = 1). The counter is initialized and counting is stopped by clearing the TAAnCE bit to 0. START STOP <1> Count operation start flow <2> Count operation stop flow Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 273 of 1817 Sep 19, 2011 (2) Operation timing in external event count mode Cautions 1. In the external event count mode , do not set the TAAnCCR0 register to 0000H. 2. In the external event count mode, use of th e timer output is disabled. If performing timer output using external event count input, set th e interval timer mode, and select the operation of the count clock to be enabled by the ex ternal event count inpu t (TAAnCTL1.TAAnMD2 to TAAnCTL1.TAAnMD0 bits = 000, TAAnCTL1.TAAnEEE bit = 1). (a) Operation if TAAnCCR0 register is set to FFFFH If the TAAnCCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of the external event count signal has been detected. The 16-b it counter is cleared to 0000H in synchronization with the next count-up timing, and the INTTAAnCC0 signal is generated. At this time, the TAAnOPT0.TAAnOVF bit is not set. FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register INTTAAnCC0 signal FFFFH External event count signal interval External event count signal interval External event count signal interval Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 274 of 1817 Sep 19, 2011 (b) Notes on rewriting the TAAnCCR0 register To change the value of the TAAnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TAAnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register INTTAAnCC0 signal D1 D2 D1 D1 D2D2 D2 External event count signal interval (1) 1 + 1) External event count signal interval (NG) (10000H + D 2 + 1) External event count signal interval (2) 2 + 1) Remark n = 0 to 5 If the value of the TAAnCCR0 register is changed from D 1 to D 2 while the count value is greater than D 2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TAAnCCR0 register has been rewritten. Consequently, the value that is compared with the 16-bit counter is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D 2, the INTTAAnCC0 signal is generated. Therefore, the INTTAAnCC0 signal may not be generated at the valid edge count of “(D1 + 1) times” or “(D2 + 1) times” as originally expected, but may be generated at the valid edge count of “(10000H + D2 + 1) times”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 276 of 1817 Sep 19, 2011 If the set value of the TAAnCCR1 register is greate r than the set value of the TAAnCCR0 register, the INTTAAnCC1 signal is not generated because the count value of the 16-bit counter and the value of the TAAnCCR1 register do not match. Figure 7-20. Timing Chart When D01 < D11 FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register INTTAAnCC0 signal TAAnCCR1 register INTTAAnCC1 signal D01 D11 D01 D01 D01 D01 L Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 277 of 1817 Sep 19, 2011

7.5.3 External trigger pulse output m ode (TAAnMD2 to TAAnMD0 bits = 010)

In the external trigger pulse output mode, 16-bit timer/event counter AA waits for a trigger when the TAAnCTL0.TAAnCE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter AA starts counting, and outputs a PWM waveform from the TOAAn1 pin. Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the TOAAn0 pin. Figure 7-21. Configuration in External Trigger Pulse Output Mode CCR0 buffer registerTAAnCE bit TAAnCCR0 register 16-bit counter TAAnCCR1 register CCR1 buffer register Clear Match signal Match signal INTTAAnCC0 signal Output controller (RS-FF) Output controller TOAAn1 pin INTTAAnCC1 signal TOAAn0 pin Count clock selection Count start control Edge detector Software trigger generation TIAAn0 pin Transfer Transfer S R Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 278 of 1817 Sep 19, 2011 Figure 7-22. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register INTTAAnCC0 signal TAAnCCR1 register INTTAAnCC1 signal TOAAn1 pin output External trigger input (TIAAn0 pin input) TOAAn0 pin output (only when software trigger is used) D1 D1 D1 D1 D0 D0 D0 Wait for trigger Active level width (D1) Cycle (D0 + 1) Cycle (D0 + 1) Cycle (D0 + 1) Active level width (D1) Active level width (D1) 16-bit timer/event counter AA waits for a trigger when the TAAnCE bit is set to 1. When the trigger is generated, the 16- bit counter is cleared from FFFFH to 0000H, starts countin g at the same time, and outputs a PWM waveform from the TOAAn1 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The output of the TOAAn0 pin is inverted. The TOAAn1 pin outputs a high level regardless of the status (high/low) when a trigger occurs.) The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TAAnCCR1 register) × Count clock cycle Cycle = (Set value of TAAnCCR0 register + 1) × Count clock cycle Duty factor = (Set value of TAAnCCR1 register)/(Set value of TAAnCCR0 register + 1) The compare match request signal INTTAAnCC0 is generated t he next time the 16-bit counter counts after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H at the same time. The compare match interrupt request signal INTTAAnCC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TAAnCCRm register is transferred to t he CCRm buffer register when the count value of the 16-bit counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H. The valid edge of an external trigger input signal, or setting the software trigger (TAAnCTL1.TAAnEST bit) to 1 is used as the trigger. Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 279 of 1817 Sep 19, 2011 Figure 7-23. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) 0/1 0 0 0 0 TAAnCTL0 Select count clock 0: Stops counting 1: Enables counting 0/1 0/1 0/1 TAAnCKS2 TAAnCKS1 TAAnCKS0TAAnCE (b) TAAn control register 1 (TAAnCTL1) 0 0/1 0 0 0 TAAnCTL1 Generates software trigger when 1 is written 010 TAAnMD2 TAAnMD1 TAAnMD0TAAnEST TAAnEEE 0, 1, 0: External trigger pulse output mode (c) TAAn I/O control register 0 (TAAnIOC0) 0 0 0 0 0/1 TAAnIOC0 0: Disables TOAAn0 pin output 1: Enables TOAAn0 pin output Sets output level while operation of TOAAn0 pin is disabled 0: Low level 1: High level 0: Disables TOAAn1 pin output 1: Enables TOAAn1 pin output Specifies active level of TOAAn1 pin output 0: Active-high 1: Active-low 0/1 0/1 Note 0/1Note TAAnOE1 TAAnOL0 TAAnOE0TAAnOL1 TOAAn1 pin output 16-bit counter

• When TAAnOL1 bit = 0 TOAAn1 pin output 16-bit counter
• When TAAnOL1 bit = 1 Note Clear this bit to 0 when the TOAAn0 pin is not used in the external trigger pulse output mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 280 of 1817 Sep 19, 2011 Figure 7-23. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TAAn I/O control register 2 (TAAnIOC2) 0000 0 TAAnIOC2 Select valid edge of external trigger input 0 0/1 0/1 TAAnETS1 TAAnETS0TAAnEES1 TAAnEES0 (e) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register. (f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1) If D0 is set to the TAAnCCR0 register and D 1 to the TAAnCCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) × Count clock cycle Active level width = D1 × Count clock cycle Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are not used in the external trigger pulse output mode. 2. n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 281 of 1817 Sep 19, 2011 (1) Operation flow in extern al trigger pulse output mode Figure 7-24. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register CCR0 buffer register INTTAAnCC0 signal TAAnCCR1 register CCR1 buffer register INTTAAnCC1 signal TOAAn1 pin output External trigger input (TIAAn0 pin input) TOAAn0 pin output (only when software trigger is used) D10 D00 D00 D01 D00 D00 D10 D10 D11 D10 D10 D10 D11 D10 D01 D00 D10 D10 D00 D10 D00D11D11 D01 D01 D01 Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 282 of 1817 Sep 19, 2011 Figure 7-24. Software Processing Flow in External Trigger Pulse Output Mode (2/2) TAAnCE bit = 1 Setting of TAAnCCR0 register Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC0 register, TAAnIOC2 register, TAAnCCR0 register, TAAnCCR1 register Initial setting of these registers is performed before setting the TAAnCE bit to 1. The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting is enabled (TAAnCE bit = 1). Trigger wait status TAAnCCR1 register write processing is necessary only when the set cycle is changed. When the counter is cleared after setting, the values of the TAAnCCRm register are transferred to the CCRm buffer register in a batch. START Setting of TAAnCCR1 register <1> Count operation start flow <2> TAAnCCR0 and TAAnCCR1 register setting change flow Setting of TAAnCCR0 register When the counter is cleared after setting, the values of the TAAnCCRm register are transferred to the CCRm buffer register in a batch. Setting of TAAnCCR1 register <4> TAAnCCR0, TAAnCCR1 register setting change flow Only writing of the TAAnCCR1 register must be performed when the set duty factor is changed. When the counter is cleared after setting, the value of the TAAnCCRm register is transferred to the CCRm buffer register. Setting of TAAnCCR1 register <3> TAAnCCR0, TAAnCCR1 register setting change flow TAAnCE bit = 0 Counting is stopped. STOP <5> Count operation stop flow Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 283 of 1817 Sep 19, 2011 (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TAAnCCR1 register last. Rewrite the TAAnCCRm register after writing the TAAnCCR1 register after the INTTAAnCC0 signal is detected. Remark n = 0 to 5 m = 0, 1 FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register CCR0 buffer register INTTAAnCC0 signal TAAnCCR1 register CCR1 buffer register INTTAAnCC1 signal TOAAn1 pin output External trigger input (TIAAn0 pin input) TOAAn0 pin output (only when software trigger is used) D10 D00 D00 D01 D00 D10 D11 D10 D11 D01 D10 D10 D00 D00 D11D11 D01 D01

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 284 of 1817 Sep 19, 2011 In order to transfer data from the TAAnCCRm register to the CCRm buffer register, the TAAnCCR1 register must be written. To change both the cycle and active level width of the PW M waveform at this time, first set the cycle to the TAAnCCR0 register and then set the active level width to the TAAnCCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TAAnCCR0 register, and then write the same value to the TAAnCCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TAAnCCR1 register has to be set. After data is written to the TAAnCCR1 register, the value written to the TAAnCCRm register is transferred to the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TAAnCCR0 or TAAnCCR1 register again after writing the TAAnCCR1 register once, do so after the INTTAAnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined because the timing of transferring data from the TAAnCCRm register to the CCRm buffer register conflicts with writing the TAAnCCRm register. Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 285 of 1817 Sep 19, 2011 (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TAAnCCR1 register to 0000H. If the set value of the TAAnCCR0 register is FFFFH, the INTTAAnCC1 signal is generated periodically. Count clock 16-bit counter TAAnCE bit TAAnCCR0 register TAAnCCR1 register INTTAAnCC0 signal INTTAAnCC1 signal TOAAn1 pin output 0000H 0000H 0000H D0 − 1D 00000FFFF 0000 D 0 − 1D 0 00000001 Remark n = 0 to 5 To output a 100% waveform, set a value of (set value of TAAnCCR0 register + 1) to the TAAnCCR1 register. If the set value of the TAAnCCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter TAAnCE bit TAAnCCR0 register TAAnCCR1 register INTTAAnCC0 signal INTTAAnCC1 signal TOAAn1 pin output D0 + 1 D0 + 1 D0 + 1 D0 − 1D 00000FFFF 0000 D 0 − 1D 0 00000001 Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 286 of 1817 Sep 19, 2011 (c) Conflict between trigger detecti on and match with TAAnCCR1 register If the trigger is detected immediately after the INTTAAnCC1 signal is generated, the 16-bit counter is cleared to 0000H at the same time, the output signal of the TOAA n1 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter TAAnCCR1 register INTTAAnCC1 signal TOAAn1 pin output External trigger input (TIAAn0 pin input) D1 − 10000FFFF 0000 Shortened Remark n = 0 to 5 If the trigger is detected immediately before the INTT AAnCC1 signal is generated, the INTTAAnCC1 signal is not generated, and the 16-bit counter is cleared to 00 00H and continues counting. The output signal of the TOAAn1 pin remains active. Consequently, the active period of the PWM waveform is extended. 16-bit counter TAAnCCR1 register INTTAAnCC1 signal TOAAn1 pin output External trigger input (TIAAn0 pin input) D1 − 2D 1 − 1D 10000FFFF 0000 0001 Extended Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 287 of 1817 Sep 19, 2011 (d) Conflict between trigger detecti on and match with TAAnCCR0 register If the trigger is detected immediately after the INTTAAnCC0 signal is generated, the 16-bit counter is cleared to 0000H again and continues counting up. Therefore, t he active period of the TOAAn1 pin is extended by the time from generation of the INTTAAnCC0 signal to trigger detection. 16-bit counter TAAnCCR0 register INTTAAnCC0 signal TOAAn1 pin output External trigger input (TIAAn0 pin input) D0 − 1D 00000FFFF 0000 0000 Extended Remark n = 0 to 5 If the trigger is detected immediately before the INTT AAnCC0 signal is generated, the INTTAAnCC0 signal is not generated. The 16-bit counter is cleared to 0000H, the TOAAn1 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter TAAnCCR0 register INTTAAnCC0 signal TOAAn1 pin output External trigger input (TIAAn0 pin input) D0 − 1D 00000FFFF 0000 0001 Shortened Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 288 of 1817 Sep 19, 2011 (e) Generation timing of compare match interrupt request signal (INTTAAnCC1) The timing of generation of the INTTAAnCC1 signal in th e external trigger pulse output mode differs from the timing of other INTTAAnCC1 signals; the INTTAAnCC1 signal in the external trigger pulse output mode is generated when the count value of the 16-bit counter matches the value of the TAAnCCR1 register. Count clock 16-bit counter TAAnCCR1 register TOAAn1 pin output INTTAAnCC1 signal D1 − 2D 1 − 1D 1 D1 + 1 D 1 + 2 Remark n = 0 to 5 Usually, the INTTAAnCC1 signal is generated in synchronization with the next count-up, after the count value of the 16-bit counter matches the value of the TAAnCCR1 register. In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the timing of changing the output signal of the TOAAn1 pin.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 289 of 1817 Sep 19, 2011

7.5.4 One-shot pulse output mode (TAAnMD2 to TAAnMD0 bits = 011)

In the one-shot pulse output mode, 16-bit timer/event coun ter AA waits for a trigger when the TAAnCTL0.TAAnCE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter AA starts counting, and outputs a one-shot pulse from the TOAAn1 pin. Instead of the external trigger, a software trigger can al so be generated to output the pulse. When the software trigger is used, the TOAAn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). Figure 7-25. Configuration in One-Shot Pulse Output Mode CCR0 buffer registerTAAnCE bit TAAnCCR0 register TAAnCCR1 register CCR1 buffer register Clear Match signal Match signal INTTAAnCC0 signal Output controller (RS-FF) TOAAn1 pin INTTAAnCC1 signal TOAAn0 pinCount clock selection Count start control Edge detector Software trigger generation TIAAn0 pin Transfer Transfer S R Output controller (RS-FF) S R 16-bit counter Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 290 of 1817 Sep 19, 2011 Figure 7-26. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register INTTAAnCC0 signal TAAnCCR1 register INTTAAnCC1 signal TOAAn1 pin output External trigger input (TIAAn0 pin input) TOAAn0 pin output (only when software trigger is used) D1 D1 D1 D0 D0 Delay (D1) Delay Delay Active level width 0 − D1 + 1) Active level width 0 − D1 + 1) Active level width 0 − D1 + 1) When the TAAnCE bit is set to 1, 16-bit timer/event counter AA waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOAAn1 pin. After the one-shot pulse is output, t he 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is generated again while the one-shot pulse is being output, it is ignored. The output delay period and active level width of the one-shot pulse can be calculated as follows. Output delay period = (Set value of TAAnCCR1 register) × Count clock cycle Active level width = (Set value of TAAnCCR0 register − Set value of TAAnCCR1 register + 1) × Count clock cycle The compare match interrupt request signal INTTAAnCC0 is generated when the 16-bit counter counts after its count value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTAAnCC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The valid edge of an external trigger input or setting the so ftware trigger (TAAnCTL1.TAAnEST bit) to 1 is used as the trigger. Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 291 of 1817 Sep 19, 2011 Figure 7-27. Register Setting for Operation in One-Shot Pulse Output Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) 0/1 0 0 0 0 TAAnCTL0 Select count clock 0: Stops counting 1: Enables counting 0/1 0/1 0/1 TAAnCKS2 TAAnCKS1 TAAnCKS0TAAnCE (b) TAAn control register 1 (TAAnCTL1) 0 0/1 0 0 0TAAnCTL1 Generates software trigger when 1 is written 011 TAAnMD2 TAAnMD1 TAAnMD0TAAnEST TAAnEEE 0, 1, 1: One-shot pulse output mode (c) TAAn I/O control register 0 (TAAnIOC0) 0 0 0 0 0/1 TAAnIOC0 0: Disables TOAAn0 pin output 1: Enables TOAAn0 pin output Sets output level while operation of TOAAn0 pin is disabled 0: Low level 1: High level 0: Disables TOAAn1 pin output 1: Enables TOAAn1 pin output Specifies active level of TOAAn1 pin output 0: Active-high 1: Active-low 0/1 0/1 Note 0/1Note TAAnOE1 TAAnOL0 TAAnOE0TAAnOL1 TOAAn1 pin output 16-bit counter

• When TAAnOL1 bit = 0 TOAAn1 pin output 16-bit counter
• When TAAnOL1 bit = 1 Note Clear this bit to 0 when the TOAAn0 pin is not used in the one-shot pulse output mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 292 of 1817 Sep 19, 2011 Figure 7-27. Register Setting for Operation in One-Shot Pulse Output Mode (2/2) (d) TAAn I/O control register 2 (TAAnIOC2) 0000 0 TAAnIOC2 Select valid edge of external trigger input 0 0/1 0/1 TAAnETS1 TAAnETS0TAAnEES1 TAAnEES0 (e) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register. (f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1) If D0 is set to the TAAnCCR0 register and D1 to the TAAnCCR1 register, the active level width and output delay period of the one-shot pulse are as follows. Active level width = (D0 − D1 + 1) × Count clock cycle Output delay period = (D1) × Count clock cycle Caution One-shot pulses are not output even in the one-shot pulse out put mode, if the set value of the TAAnCCR1 register is greater than the set value of the TAAnCCR0 register. Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are not used in the one-shot pulse output mode. 2. n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 293 of 1817 Sep 19, 2011 (1) Operation flow in one-shot pulse output mode Figure 7-28. Software Processing Flow in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register INTTAAnCC0 signal TAAnCCR1 register INTTAAnCC1 signal TOAAn1 pin output External trigger input (TIAAn0 pin input) <1> <3> TAAnCE bit = 1 Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC0 register, TAAnIOC2 register, TAAnCCR0 register, TAAnCCR1 register Initial setting of these registers is performed before setting the TAAnCE bit to 1. The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting has been started (TAAnCE bit = 1). Trigger wait status START <1> Count operation start flow TAAnCE bit = 0 Count operation is stopped STOP <3> Count operation stop flow D10 D00 D11 D01 D00 D10 D11 <2> D01 Setting of TAAnCCR0, TAAnCCR1 registers As rewriting the TAAnCCRm register immediately forwards to the CCRm buffer register, rewriting immediately after the generation of the INTTAAnCCR0 signal is recommended. <2> TAAnCCR0, TAAnCCR1 register setting change flow Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 294 of 1817 Sep 19, 2011 (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TAAnCCRm register To change the set value of the TAAnCCRm register to a smaller value, stop counting once, and then change the set value. If the value of the TAAnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register INTTAAnCC0 signal TAAnCCR1 register INTTAAnCC1 signal TOAAn1 pin output External trigger input (TIAAn0 pin input) TOAAn0 pin output (only when software trigger is used) D10 D11 D00 D01 D00 D10 D10 D10 D01 D11 D00 D00 Delay (D10) Delay 10) Active level width (D00 − D10 + 1) Active level width (D00 − D10 + 1) Delay (10000H + D 11) Active level width (D01 − D11 + 1) When the TAAnCCR0 register is rewritten from D 00 to D 01 and the TAAnCCR1 register from D 10 to D 11 where D00 > D 01 and D 10 > D 11, if the TAAnCCR1 register is rewritten wh en the count value of the 16-bit counter is greater than D11 and less than D 10 and if the TAAnCCR0 register is rewr itten when the count value is greater than D 01 and less than D 00, each set value is reflected as soon as the register has been rewritten and compared with the count value. The counter c ounts up to FFFFH and then counts up again from 0000H. When the count value matches D 11, the counter generates the INTTAAnCC1 signal and asserts the TOAAn1 pin. When the count value matches D 01, the counter generates the INTTAAnCC0 signal, deasserts the TOAAn1 pin, and stops counting. Therefore, the counter may output a pu lse with a delay period or active per iod different from that of the one- shot pulse that is originally expected. Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 295 of 1817 Sep 19, 2011 (b) Generation timing of compare match interrupt request signal (INTTAAnCC1) The generation timing of the INTTAAnCC1 signal in the one-shot pulse output mode is different from other INTTAAnCC1 signals; the INTTAAnCC1 signal in the one-shot pulse output mode is generated when the count value of the 16-bit counter matches the value of the TAAnCCR1 register. Count clock 16-bit counter TAAnCCR1 register TOAAn1 pin output INTTAAnCC1 signal D1 − 2D 1 − 1D 1 D1 + 1 D 1 + 2 Remark n = 0 to 5 Usually, the INTTAAnCC1 signal is generated the next ti me the 16-bit counter counts after its count value matches the value of the TAAnCCR1 register. In the one-shot pulse output mode, however, it is gene rated one clock earlier. This is because the timing is changed to match the change timing of the TOAAn1 pin.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 296 of 1817 Sep 19, 2011

7.5.5 PWM output mode (TAAnMD 2 to TAAnMD0 bits = 100)

In the PWM output mode, a PWM waveform is output from the TOAAn1 pin when the TAAnCTL0.TAAnCE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOAAn0 pin. Figure 7-29. Configuration in PWM Output Mode CCR0 buffer register TAAnCCR0 register 16-bit counter TAAnCCR1 register CCR1 buffer register Clear Match signal Match signal INTTAAnCC0 signal Output controller (RS-FF) Output controller TOAAn1 pin INTTAAnCC1 signal TOAAn0 pin TAAnCE bit Count clock selection Transfer Transfer S R Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 297 of 1817 Sep 19, 2011 Figure 7-30. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register CCR0 buffer register INTTAAnCC0 signal TOAAn0 pin output TAAnCCR1 register CCR1 buffer register INTTAAnCC1 signal TOAAn1 pin output D10 D00 D00 D01 D00 D10 D11 D10 D11 D01 D10 D10 D00 D00 D11D11 D01 D01 Active period (D10) Cycle (D00 + 1) Inactive period (D00 − D10 + 1) When the TAAnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, st arts counting, and outputs a PWM waveform from the TOAAn1 pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TAAnCCR1 register) × Count clock cycle Cycle = (Set value of TAAnCCR0 register + 1) × Count clock cycle Duty factor = (Set value of TAAnCCR1 register)/(Set value of TAAnCCR0 register + 1) The PWM waveform can be changed by rewriting the TAAnCCRm register while the counter is operating. The newly written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTAAnCC0 is gene rated the next time the 16-bit counter counts after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is clear ed to 0000H. The compare match interrupt request signal INTTAAnCC1 is generated when the count value of the 16-bit c ounter matches the value of the CCR1 buffer register. The value set to the TAAnCCRm register is transferred to t he CCRm buffer register when the count value of the 16-bit counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H. Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 298 of 1817 Sep 19, 2011 Figure 7-31. Setting of Registers in PWM Output Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) 0/1 0 0 0 0 TAAnCTL0 Select count clockNote 1 0: Stops counting 1: Enables counting 0/1 0/1 0/1 TAAnCKS2 TAAnCKS1 TAAnCKS0TAAnCE (b) TAAn control register 1 (TAAnCTL1) 0 0 0/1 0 0 TAAnCTL1 100 TAAnMD2 TAAnMD1 TAAnMD0TAAnEEETAAnEST 1, 0, 0: PWM output mode 0: Operates on count clock selected by TAAnCKS0 to TAAnCKS2 bits 1: Counts external event input signal (c) TAAn I/O control register 0 (TAAnIOC0) 0 0 0 0 0/1 TAAnIOC0 0: Disables TOAAn0 pin output 1: Enables TOAAn0 pin output Sets output level while operation of TOAAn0 pin is disabled 0: Low level 1: High level 0: Disables TOAAn1 pin output 1: Enables TOAAn1 pin output Specifies active level of TOAAn1 pin output 0: Active-high 1: Active-low 0/1 0/1 Note 2 0/1Note 2 TAAnOE1 TAAnOL0 TAAnOE0TAAnOL1 TOAAn1 pin output 16-bit counter

• When TAAnOL1 bit = 0 TOAAn1 pin output 16-bit counter
• When TAAnOL1 bit = 1 Notes 1. The setting is invalid when the TAAnCTL1.TAAnEEE bit = 1. 2. Clear this bit to 0 when the TOAAn0 pin is not used in the PWM output mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 299 of 1817 Sep 19, 2011 Figure 7-31. Setting of Registers in PWM Output Mode (2/2) (d) TAAn I/O control register 2 (TAAnIOC2) 0 0 0 0 0/1 TAAnIOC2 Select valid edge of external event count input. 0/1 0 0 TAAnEES0 TAAnETS1 TAAnETS0TAAnEES1 (e) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register. (f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1) If D0 is set to the TAAnCCR0 register and D 1 to the TAAnCCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) × Count clock cycle Active level width = D1 × Count clock cycle Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are not used in the PWM output mode. 2. n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 300 of 1817 Sep 19, 2011 (1) Operation flow in PWM output mode Figure 7-32. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register CCR0 buffer register INTTAAnCC0 signal TOAAn0 pin output TAAnCCR1 register CCR1 buffer register INTTAAnCC1 signal TOAAn1 pin output D10 D00 D00 D01 D00 D00 D10 D10 D11 D10 D10 D10 D11 D10 D01 D00 D10 D10 D00 D10 D00D11D11 D01 D01 D01 Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 301 of 1817 Sep 19, 2011 Figure 7-32. Software Processing Flow in PWM Output Mode (2/2) TAAnCE bit = 1 Setting of TAAnCCR0 register Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC0 register, TAAnIOC2 register, TAAnCCR0 register, TAAnCCR1 register Initial setting of these registers is performed before setting the TAAnCE bit to 1. The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting is enabled (TAAnCE bit = 1). TAAnCCR1 write processing is necessary even if only the set cycle is changed. When the counter is cleared after setting, the values of the TAAnCCRm register are transferred to the CCRm buffer register in a batch. START Setting of TAAnCCR1 register <1> Count operation start flow <2> TAAnCCR0, TAAnCCR1 register setting change flow Setting of TAAnCCR0 register When the counter is cleared after setting, the values of compare register m are transferred to the CCRm buffer register in a batch. Setting of TAAnCCR1 register <4> TAAnCCR0, TAAnCCR1 register setting change flow Only writing of the TAAnCCR1 register must be performed when only the set duty factor is changed. When the counter is cleared after setting, the value of compare register m is transferred to the CCRm buffer register. Setting of TAAnCCR1 register <3> TAAnCCR0, TAAnCCR1 register setting change flow TAAnCE bit = 0 Counting is stopped. STOP <5> Count operation stop flow Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 302 of 1817 Sep 19, 2011 (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TAAnCCR1 register last. Rewrite the TAAnCCRm register after writing the TAAnCCR1 register after the INTTAAnCC1 signal is detected. FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register CCR0 buffer register TAAnCCR1 register CCR1 buffer register TOAAn1 pin output INTTAAnCC0 signal D10 D00 D00 D01 D00 D10 D11 D10 D11 D01 D10 D10 D00 D00 D11D11 D01 D01 To transfer data from the TAAnCCRm register to the CCRm buffer register, the TAAnCCR1 register must be written. To change both the cycle and active leve l of the PWM waveform at this time, first set the cycle to the TAAnCCR0 register and then set the active level to the TAAnCCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TAAnCCR0 register, and then write the same value to the TAAnCCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TAAnCCR1 register has to be set. After data is written to the TAAnCCR1 register, the value written to the TAAnCCRm register is transferred to the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TAAnCCR0 or TAAnCCR1 register again after writing the TAAnCCR1 register once, do so after the INTTAAnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined because the timing of transferring data from the TAAnCCRm register to the CCRm buffer register conflicts with writing the TAAnCCRm register. Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 303 of 1817 Sep 19, 2011 (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TAAnCCR1 register to 0000H. If the set value of the TAAnCCR0 register is FFFFH, the INTTAAnCC1 signal is generated periodically. Count clock 16-bit counter TAAnCE bit TAAnCCR0 register TAAnCCR1 register INTTAAnCC0 signal INTTAAnCC1 signal TOAAn1 pin output D00 0000H D00 0000H D00 0000H D00 − 1D 000000FFFF 0000 D 00 − 1D 00 00000001 Remark n = 0 to 5 To output a 100% waveform, set a value of (set value of TAAnCCR0 register + 1) to the TAAnCCR1 register. If the set value of the TAAnCCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter TAAnCE bit TAAnCCR0 register TAAnCCR1 register INTTAAnCC0 signal INTTAAnCC1 signal TOAAn1 pin output D00 D00 + 1 D00 D00 + 1 D00 D00 + 1 D00 − 1D 000000FFFF 0000 D 00 − 1D 00 00000001 Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 304 of 1817 Sep 19, 2011 (c) Generation timing of compare match interrupt request signal (INTTAAnCC1) The timing of generation of the INTTAAnCC1 signal in the PWM output mode differs from the timing of other INTTAAnCC1 signals; the INTTAAnCC1 signal in the PWM output mode is generated when the count value of the 16-bit counter matches the value of the TAAnCCR1 register. Count clock 16-bit counter TAAnCCR1 register TOAAn1 pin output INTTAAnCC1 signal D1 − 2D 1 − 1D 1 D1 + 1 D 1 + 2 Remark n = 0 to 5 Usually, the INTTAAnCC1 signal is generated in synchronization with the next count-up after the count value of the 16-bit counter matches the value of the TAAnCCR1 register. In the PWM output mode, however, it is generated one cl ock earlier. This is because the timing is changed to match the change timing of the output signal of the TOAAn1 pin.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 305 of 1817 Sep 19, 2011

7.5.6 Free-running timer mode (TAAnMD2 to TAAnMD0 bits = 101)

In the free-running timer mode, 16-bit timer/event counter AA starts counting when the TAAnCTL0.TAAnCE bit is set to 1. At this time, the TAAnCCRm register can be used as a compare register or a capture register, depending on the setting of the TAAnOPT0.TAAnCCS0 and TAAnOPT0.TAAnCCS1 bits. Figure 7-33. Configuration in Free-Running Timer Mode TAAnCCR0 register (capture) TAAnCE bit TAAnCCR1 register (capture) 16-bit counter TAAnCCR1 register (compare) TAAnCCR0 register (compare) Output controller TAAnCCS0, TAAnCCS1 bits (capture/compare selection) TOAAn0 pin output Output controller TOAAn1 pin output Edge detector Count clock selection Edge detector Edge detector TIAAn0 pin (external event count input/ capture trigger input) TIAAn1 pin (capture trigger input) Internal count clock INTTAAnOV signal INTTAAnCC1 signal INTTAAnCC0 signal Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 306 of 1817 Sep 19, 2011 When the TAAnCE bit is set to 1, 16-bit timer/event counter AA starts counting, and the output signals of the TOAAn0 and TOAAn1 pins are inverted. When the count value of the 16- bit counter later matches the set value of the TAAnCCRm register, a compare match interrupt request signal (INTTAAnCCm) is generated, and the output signal of the TOAAnm pin is inverted. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTAAnOV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. The TAAnCCRm register can be rewritten while the counter is operating. If it is re written, the new value is reflected at that time, and compared with the count value. Figure 7-34. Basic Timing in Free-Running Timer Mode (Compare Function) FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register INTTAAnCC0 signal TOAAn0 pin output TAAnCCR1 register INTTAAnCC1 signal TOAAn1 pin output INTTAAnOV signal TAAnOVF bit D00 D01 D10 D11 D00 D10 D10 D11 D11 D11 D00 D01 D01 Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 307 of 1817 Sep 19, 2011 When the TAAnCE bit is set to 1, the 16 -bit counter starts counting. When t he valid edge input to the TIAAnm pin is detected, the count value of the 16-bit counter is stor ed in the TAAnCCRm register, and a capture interrupt request signal (INTTAAnCCm) is generated. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTAAnOV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. Figure 7-35. Basic Timing in Free-Running Timer Mode (Capture Function) FFFFH 16-bit counter 0000H TAAnCE bit TIAAn0 pin input TAAnCCR0 register INTTAAnCC0 signal TIAAn1 pin input TAAnCCR1 register INTTAAnCC1 signal INTTAAnOV signal TAAnOVF bit D00 D01 D02 D03 D10 D00 D01 D02 D03 D11 D12 D13 D10 D11 D12 D13 Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 308 of 1817 Sep 19, 2011 Figure 7-36. Register Setting in Free-Running Timer Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) 0/1 0 0 0 0 TAAnCTL0 Select count clockNote 0: Stops counting 1: Enables counting 0/1 0/1 0/1 TAAnCKS2 TAAnCKS1 TAAnCKS0TAAnCE Note The setting is invalid when the TAAnCTL1.TAAnEEE bit = 1 (b) TAAn control register 1 (TAAnCTL1) 0 0 0/1 0 0 TAAnCTL1 101 TAAnMD2 TAAnMD1 TAAnMD0TAAnEEETAAnEST 1, 0, 1: Free-running mode 0: Operates with count clock selected by TAAnCKS0 to TAAnCKS2 bits 1: Counts on external event count input signal (c) TAAn I/O control register 0 (TAAnIOC0) 0 0 0 0 0/1 TAAnIOC0 0: Disables TOAAn0 pin output 1: Enables TOAAn0 pin output Sets output level with operation of TOAAn0 pin disabled 0: Low level 1: High level 0: Disables TOAAn1 pin output 1: Enables TOAAn1 pin output Sets output level with operation of TOAAn1 pin disabled 0: Low level 1: High level 0/1 0/1 0/1 TAAnOE1 TAAnOL0 TAAnOE0TAAnOL1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 309 of 1817 Sep 19, 2011 Figure 7-36. Register Setting in Free-Running Timer Mode (2/2) (d) TAAn I/O control register 1 (TAAnIOC1) 0 0 0 0 0/1 TAAnIOC1 Select valid edge of TIAAn0 pin input Select valid edge of TIAAn1 pin input 0/1 0/1 0/1 TAAnIS2 TAAnIS1 TAAnIS0TAAnIS3 (e) TAAn I/O control register 2 (TAAnIOC2) 0 0 0 0 0/1 TAAnIOC2 Select valid edge of external event count input 0/1 0 0 TAAnEES0 TAAnETS1 TAAnETS0TAAnEES1 (f) TAAn option register 0 (TAAnOPT0) 0 0 0/1 0/1 0 TAAnOPT0 Overflow flag Specifies if TAAnCCR0 register functions as capture or compare register Specifies if TAAnCCR1 register functions as capture or compare register 0 0 0/1 TAAnCCS0 TAAnOVFTAAnCCS1 (g) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register. (h) TAAn capture/compare regist ers 0 and 1 (TAAnCCR0 and TAAnCCR1) These registers function as capture registers or compare regi sters depending on the setting of the TAAnOPT0.TAAnCCSm bit. When the registers function as capture registers, they store the c ount value of the 16-bit counter when the valid edge input to the TIAAnm pin is detected. When the registers function as compare registers and when D m is set to the TAAnCCRm register, the INTTAAnCCm signal is generated when the counter reaches (D m + 1), and the output signal of the TOAAnm pin is inverted. Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 310 of 1817 Sep 19, 2011 (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register INTTAAnCC0 signal TOAAn0 pin output TAAnCCR1 register INTTAAnCC1 signal TOAAn1 pin output INTTAAnOV signal TAAnOVF bit D00 D01 D10 D11 D00 D10 D10 D11 D11 D11 D00 D01 D01 Cleared to 0 by CLR instruction Set value changed Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction <1> <3> Set value changed Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 311 of 1817 Sep 19, 2011 Figure 7-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) TAAnCE bit = 1 Read TAAnOPT0 register (check overflow flag). Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC0 register, TAAnIOC2 register, TAAnOPT0 register, TAAnCCR0 register, TAAnCCR1 register Initial setting of these registers is performed before setting the TAAnCE bit to 1. The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting has been started (TAAnCE bit = 1). START Execute instruction to clear TAAnOVF bit (CLR TAAnOVF). <1> Count operation start flow <2> Overflow flag clear flow TAAnCE bit = 0 Counter is initialized and counting is stopped by clearing TAAnCE bit to 0. STOP <3> Count operation stop flow TAAnOVF bit = 1 NO YES Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 312 of 1817 Sep 19, 2011 (b) When using capture/compare register as capture register Figure 7-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TAAnCE bit TIAAn0 pin input TAAnCCR0 register INTTAAnCC0 signal TIAAn1 pin input TAAnCCR1 register INTTAAnCC1 signal INTTAAnOV signal TAAnOVF bit D000000 0000 D01 D02 D03 D10 D00 D01 D02 D03 D11 D12 D100000 D 11 D12 0000 Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction <3><1> <2> <2> Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 313 of 1817 Sep 19, 2011 Figure 7-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) TAAnCE bit = 1 Read TAAnOPT0 register (check overflow flag). Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC1 register, TAAnOPT0 register Initial setting of these registers is performed before setting the TAAnCE bit to 1. The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting has been started (TAAnCE bit = 1). START Execute instruction to clear TAAnOVF bit (CLR TAAnOVF). <1> Count operation start flow <2> Overflow flag clear flow TAAnCE bit = 0 Counter is initialized and counting is stopped by clearing TAAnCE bit to 0. STOP <3> Count operation stop flow TAAnOVF bit = 1 NO YES Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 314 of 1817 Sep 19, 2011 (2) Operation timing in free-running timer mode (a) Interval operation with TAAnCCRm re gister used as compare register When 16-bit timer/event counter AA is used as an inte rval timer with the TAAnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTAAnCCm signal has been detected. FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register INTTAAnCC0 signal TOAAn0 pin output TAAnCCR1 register INTTAAnCC1 signal TOAAn1 pin output D00 D01 D02 D03 D04 D05 D10 D00 D11 D01 D12 D04 D13 D02 D03 D11D10 D12 D13 D14 Interval period (D10 + 1) Interval period (10000H + D11 − D10) Interval period (10000H + D12 − D11) Interval period (10000H + D13 − D12) Interval period (D00 + 1) Interval period (10000H + D01 − D00) Interval period (D02 − D01) Interval period (10000H + D03 − D02) Interval period (10000H + D04 − D03) When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TAAnCCRm register must be re-set in the interrupt servicing that is executed when the INTTAAnCCm signal is detected. The set value for re-setting the TAAnCCRm register can be calculated by the following expression, where “Dm” is the interval period. Compare register default value: Dm − 1 Value set to compare register second and subsequent times: Previous set value + Dm (If the calculation resu lt is greater than FFFFH, subtract 10000H fr om the result and set this value to the register.) Remark m = 0, 1 n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 315 of 1817 Sep 19, 2011 (b) Pulse width measurement with T AAnCCRm used as capture register When pulse width measurement is performed with the TAAnCCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTAAnCCm signal has been detected and for calculating the interval. FFFFH 16-bit counter 0000H TAAnCE bit TIAAn0 pin input TAAnCCR0 register INTTAAnCC0 signal TIAAn1 pin input TAAnCCR1 register INTTAAnCC1 signal INTTAAnOV signal TAAnOVF bit 0000H D 00 D01 D02 D03 D04 D10 D00 D11 D01 D12 D04 D13 D02 D03 D100000H D 11 D12 D13 Pulse interval (D00) Pulse interval (10000H + D01 − D00) Pulse interval (D02 − D01) Pulse interval (10000H + D03 − D02) Pulse interval (10000H + D04 − D03) Pulse interval (D10) Pulse interval (10000H + D11 − D10) Pulse interval (10000H + D12 − D11) Pulse interval (10000H + D13 − D12) Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction When executing pulse width measurement in the free-running timer mode, two pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TAAnCCRm register in synchronization with the INTTAAnCCm signal, and calc ulating the difference between the read value and the previously read value. Remark m = 0, 1 n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 316 of 1817 Sep 19, 2011 (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH 16-bit counter 0000H TAAnCE bit TIAAn0 pin input TAAnCCR0 register TIAAn1 pin input TAAnCCR1 register INTTAAnOV signal TAAnOVF bit D00 D01 D10 D11 D10 D00 D11 D01 The following problem may occur when two pulse widths are measured in the free-running timer mode. <1> Read the TAAnCCR0 register (setting of t he default value of the TIAAn0 pin input). <2> Read the TAAnCCR1 register (setting of t he default value of the TIAAn1 pin input). <3> Read the TAAnCCR0 register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 − D00). <4> Read the TAAnCCR1 register. Read the overflow flag. Because the flag is cleared in <3>, 0 is read. Because the overflow flag is 0, the pulse width can be calculated by (D 11 − D10) (incorrect). When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. Use software when using two capture registers. An example of how to use software is shown below.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 317 of 1817 Sep 19, 2011 (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TAAnCE bit INTTAAnOV signal TAAnOVF bit TAAnOVF0 flagNote TIAAn0 pin input TAAnCCR0 register TAAnOVF1 flagNote TIAAn1 pin input TAAnCCR1 register D10 D11 D00 D01 D10 D00 D11 D01 Note The TAAnOVF0 and TAAnOVF1 flags are set on the internal RAM by software. <1> Read the TAAnCCR0 register (setting of the default value of the TIAAn0 pin input). <2> Read the TAAnCCR1 register (setting of the default value of the TIAAn1 pin input). <3> An overflow occurs. Set the TAAnOVF0 and TAAnOVF1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> Read the TAAnCCR0 register. Read the TAAnOVF0 flag. If the TAAnOVF0 flag is 1, clear it to 0. Because the TAAnOVF0 flag is 1, the pulse width can be calculated by (10000H + D 01 − D00). <5> Read the TAAnCCR1 register. Read the TAAnOVF1 flag. If the TAAnOVF1 flag is 1, clear it to 0 (the TAAnOVF0 flag is cleared in <4>, and the TAAnOVF1 flag remains 1). Because the TAAnOVF1 flag is 1, the pul se width can be calculated by (10000H + D 11 − D 10) (correct). <6> Same as <3>

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 318 of 1817 Sep 19, 2011 (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TAAnCE bit INTTAAnOV signal TAAnOVF bit TAAnOVF0 flagNote TIAAn0 pin input TAAnCCR0 register TAAnOVF1 flagNote TIAAn1 pin input TAAnCCR1 register D10 D11 D00 D01 D10 D00 D11 D01 Note The TAAnOVF0 and TAAnOVF1 flags are set on the internal RAM by software. <1> Read the TAAnCCR0 register (setting of t he default value of the TIAAn0 pin input). <2> Read the TAAnCCR1 register (setting of t he default value of the TIAAn1 pin input). <3> An overflow occurs. Nothing is done by software. <4> Read the TAAnCCR0 register. Read the overflow flag. If the overflow flag is 1, set only the TAAnOVF1 flag to 1, and clear the overflow flag to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 − D00). <5> Read the TAAnCCR1 register. Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read. Read the TAAnOVF1 flag. If the TAAnOVF1 flag is 1, clear it to 0. Because the TAAnOVF1 flag is 1, the pul se width can be calculated by (10000H + D 11 − D 10) (correct). <6> Same as <3> Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 319 of 1817 Sep 19, 2011 (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below. Example of incorrect processing when capture trigger interval is long FFFFH 16-bit counter 0000H TAAnCE bit TIAAnm pin input TAAnCCRm register INTTAAnOV signal TAAnOVF bit Dm0 Dm1 Dm0 Dm1 1 cycle of 16-bit counter Pulse width The following problem may occur when a long pulse width is measured in the free-running timer mode. <1> Read the TAAnCCRm register (setting of t he default value of the TIAAnm pin input). <2> An overflow occurs. Nothing is done by software. <3> An overflow occurs a second time. Nothing is done by software. <4> Read the TAAnCCRm register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pul se width can be calculated by (10000H + D m1 − D m0) (incorrect). Actually, the pulse width must be (20000H + D m1 − Dm0) because an overflow occurs twice. If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. An example of how to use software is shown next. Remark m = 0, 1 n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 320 of 1817 Sep 19, 2011 Example when capture trigger interval is long FFFFH 16-bit counter 0000H TAAnCE bit TIAAnm pin input TAAnCCRm register INTTAAnOV signal TAAnOVF bit Overflow counterNote Dm0 Dm1 1H0H 2H 0H Dm0 Dm1 1 cycle of 16-bit counter Pulse width Note The overflow counter is set arbitrarily by software on the internal RAM. <1> Read the TAAnCCRm register (setting of t he default value of the TIAAnm pin input). <2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> Read the TAAnCCRm register. Read the overflow counter. → When the overflow counter is “N”, the pulse width can be calculated by (N × 10000H + D m1 – D m0). In this example, the pulse width is (20000H + D m1 – Dm0) because an overflow occurs twice. Clear the overflow counter (0H). Remark m = 0, 1 n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 321 of 1817 Sep 19, 2011 (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the T AAnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TAAnOPT0 register. To accurately detect an overflow, read the TAAnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) Operation to write 0 (without conflict with setting) (iii) Operation to clear to 0 (without conflict with setting) (ii) Operation to write 0 (conflict with setting) (iv) Operation to clear to 0 (conflict with setting) 0 write signal Overflow set signal Register access signal Overflow flag (TAAnOVF bit) Read Write 0 write signal Overflow set signal Register access signal Overflow flag (TAAnOVF bit) Read Write 0 write signal Overflow set signal 0 write signal Overflow set signal Overflow flag (TAAnOVF bit) Overflow flag (TAAnOVF bit) L H L Remark n = 0 to 5 To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of the overflow may be erased by writing 0 ((ii) in the above chart) . Therefore, software may judge that no overflow has occurred even when an overflow has actually occurred. If execution of the CLR instruction conf licts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set (1) even after execution of the clear instruction.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 322 of 1817 Sep 19, 2011

7.5.7 Pulse width measurement mode (TAAnMD2 to TAAnMD0 bits = 110)

In the pulse width measurement mode, 16-bit timer/event counter AA starts counting when the TAAnCTL0.TAAnCE bit is set to 1. Each time the valid edge input to the TIAAnm pin has been detected, the count value of the 16-bit counter is stored in the TAAnCCRm register, and the 16-bit counter is cleared to 0000H. The interval of the valid edge can be m easured by reading the TAAnCCRm regist er after a capture interrupt request signal (INTTAAnCCm) occurs. Select either the TIAAn0 or TIAAn1 pin as the capture trigger input pin. Specify “No edge detection” for the unused pins by using the TAAnIOC1 register. When an external clock is used as the count clock, measur e the pulse width of the TIAA n1 pin because the external clock is fixed to the TIAAn0 pin. At this time, clear t he TAAnIOC1.TAAnIS1 and TAAnIOC1.TAAnIS0 bits to 00 (capture trigger input (TIAAn0 pin): No edge detection). Figure 7-39. Configuration in Pulse Width Measurement Mode TAAnCCR0 register (capture) TAAnCE bit TAAnCCR1 register (capture) Count clock selection Edge detector Edge detector TIAAn1 pin (capture trigger input) TIAAn0 pin (capture trigger input) Clear INTTAAnOV signal INTTAAnCC0 signal INTTAAnCC1 signal 16-bit counter Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 323 of 1817 Sep 19, 2011 Figure 7-40. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TAAnCE bit TIAAnm pin input TAAnCCRm register INTTAAnCCm signal INTTAAnOV signal TAAnOVF bit D00000H D 1 D2 D3 Cleared to 0 by CLR instruction Remark n = 0 to 5 m = 0, 1 When the TAAnCE bit is set to 1, the 16 -bit counter starts counting. When t he valid edge input to the TIAAnm pin is later detected, the count value of the 16 -bit counter is stored in the TAAnCCRm re gister, the 16-bit counter is cleared to 0000H, and a capture interrupt request signal (INTTAAnCCm) is generated. The pulse width is calculated as follows. Pulse width = Captured value × Count clock cycle If the valid edge is not input to the TIAAnm pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt request signal (INTTAAnOV) is generated at the next count clock, and the counter is cleared to 0000H and continues counting. At this time, the overflow flag (TAAnOPT0.TAAnOVF bi t) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction via software. If the overflow flag is set to 1, the pulse width can be calculated as follows. Pulse width = (10000H × TAAnOVF bit set (1) count + Captured value) × Count clock cycle Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 324 of 1817 Sep 19, 2011 Figure 7-41. Register Setting in Pulse Width Measurement Mode (a) TAAn control register 0 (TAAnCTL0) 0/1 0 0 0 0 TAAnCTL0 Select count clock 0: Stops counting 1: Enables counting 0/1 0/1 0/1 TAAnCKS2 TAAnCKS1 TAAnCKS0TAAnCE (b) TAAn control register 1 (TAAnCTL1) 00 00 0 TAAnCTL1 110 TAAnMD2TAAnEST TAAnEEE TAAnMD1 TAAnMD0 1, 1, 0: Pulse width measurement mode (c) TAAn I/O control register 1 (TAAnIOC1) 0 0 0 0 0/1 TAAnIOC1 Select valid edge of TIAAn0 pin input Select valid edge of TIAAn1 pin input 0/1 0/1 0/1 TAAnIS2 TAAnIS1 TAAnIS0TAAnIS3 (d) TAAn option register 0 (TAAnOPT0) 0000 0 TAAnOPT0 Overflow flag 0 0 0/1 TAAnOVFTAAnCCS1 TAAnCCS0 (e) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register. (f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIAAnm pin is detected. Remarks 1. TAAn I/O control register 0 (TAAnIOC0), and TAAn I/O control register 2 (TAAnIOC2) are not used in the pulse width measurement mode. 2. m = 0, 1 n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 325 of 1817 Sep 19, 2011 (1) Operation flow in pul se width measurement mode Figure 7-42. Software Processing Flow in Pulse Width Measurement Mode <1> <2> Set TAAnCTL0 register (TAAnCE bit = 1) TAAnCE bit = 0 Register initial setting TAAnCTL0 register (TAAnCKS0 to TAAnCKS2 bits), TAAnCTL1 register, TAAnIOC1 register, TAAnOPT0 register Initial setting of these registers is performed before setting the TAAnCE bit to 1. The TAAnCKS0 to TAAnCKS2 bits can be set at the same time when counting has been started (TAAnCE bit = 1). The counter is initialized and counting is stopped by clearing the TAAnCE bit to 0. START STOP <1> Count operation start flow <2> Count operation stop flow FFFFH 16-bit counter 0000H TAAnCE bit TIAAn0 pin input TAAnCCR0 register INTTAAnCC0 signal D00000H 0000H D1 D2 Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 326 of 1817 Sep 19, 2011 (2) Operation timing in pul se width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the T AAnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TAAnOPT0 register. To accurately detect an overflow, read the TAAnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) Operation to write 0 (without conflict with setting) (iii) Operation to clear to 0 (without conflict with setting) (ii) Operation to write 0 (conflict with setting) (iv) Operation to clear to 0 (conflict with setting) 0 write signal Overflow set signal Register access signal Overflow flag (TAAnOVF bit) Read Write 0 write signal Overflow set signal Register access signal Overflow flag (TAAnOVF bit) Read Write 0 write signal Overflow set signal 0 write signal Overflow set signal Overflow flag (TAAnOVF bit) Overflow flag (TAAnOVF bit) L H L Remark n = 0 to 5 To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of the overflow may be erased by writing 0 ((ii) in the above chart) . Therefore, software may judge that no overflow has occurred even when an overflow has actually occurred. If execution of the CLR instruction conf licts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set (1) even after execution of the clear instruction.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 327 of 1817 Sep 19, 2011

7.5.8 Timer output operations

The following table shows the operations and output levels of the TOAAn0 and TOAAn1 pins. Table 7-5. Timer Output Control in Each Mode Operation Mode TOAAn1 Pin TOAAn0 Pin Interval timer mode Square wave output External event count mode Square wave output − External trigger pulse output mode External trigger pulse output One-shot pulse output mode One-shot pulse output PWM output mode PWM output Square wave output Free-running timer mode Square wave output (only when compare function is used) Pulse width measurement mode − Remark n = 0 to 5 Table 7-6. Truth Table of TOAAn0 and TOAAn1 Pins Under Control of Timer Output Control Bits TAAnIOC0.TAAnOLm Bit TAAnIOC0.TAAnOEm Bit TAAnCTL0.TAAnCE Bit Level of TOAAnm Pin 0 × Low-level output

0 Low-level output

1 Low level immediately before counting, high

level after counting is started 0 × High-level output

0 High-level output

1 High level immediately before counting, low level

Remark n = 0 to 5 m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 328 of 1817 Sep 19, 2011

7.6 Timer-Tuned Operation Function

Timer AA and timer AB have a timer-tuned operation function. The timer-tuned operation function is used to tune the internal timers of the V850ES/JH3-E and V850ES/JJ3-E, so that the number of capture or compare regist ers of the slave timer (the number of timer outputs and the number of compare match interrupts of the slave timer) can be added to the master timer. The timers that can be tuned are listed in Table 7-7. Table 7-7. Tuned-Operation Mode of Timers Master Timer Slave Timer TAA1 TAA0 TAA3 TAA2 TAB1 TAA4 The tuned-operation function has the following modes.

• PWM output mode
• Free-running timer mode Figure 7-43 shows an example where individual operation and tuned operation of TAA0 (as the master timer) and TAA1 (as the slave timer) are performed in PWM output mode. Figure 7-43. Differences Between Individual Operation and Tuned Operation Using TAA0 and TAA1 TAA1 TOAA11 (PWM output) 16-bit timer/counter Individual operation Two PWM outputs are available when PWM is operated separately with each timer. 16-bit capture/compare 16-bit capture/compare TOAA10 (square waveform output) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare TAA0 TOAA01 (PWM output) TOAA00 (square- waveform output) TAA1 (master) + TAA0 (slave) TOAA11 (PWM output) 16-bit timer/counter Tuned operation 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare TOAA10 (square waveform output) TOAA01 (PWM output) 16-bit capture/compare TOAA01 (PWM output) Three PWM outputs are available when PWM is operated in tuned-operation mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 329 of 1817 Sep 19, 2011 Table 7-8 show the timer modes that can be used in the t uned-operation mode and Table 7-9 shows the differences of the timer output functions between individual operation and tuned operation (√: Settable, ×: Not settable). Table 7-8. Timer Modes Usable in Tuned-Operation Mode Master Timer Slave Timer Fr ee-Running Timer Mode PWM Mode TAA1 TAA0 √ √ TAA3 TAA2 √ √ TAB0 TAA5 √ √ TAB1 TAA4 √ √ Table 7-9. Timer Output Functions Free-Running Timer Mode PWM Mode Tuned Channel Timer Pin Individual Operation Tuned Operation I ndividual Operation Tuned Operation TOAA10 PPG ← Toggle ← TAA1 (master) TOAA11 PPG ← PWM ← TOAA00 PGP ← Toggle PWM Ch0 TAA0 (slave) TOAA01 PPG ← PWM ← TOAA30 PPG ← Toggle ← TAA3 (master) TOAA31 PPG ← PWM ← TOAA20 PPG ← Toggle PWM Ch1 TAA2 (slave) TOAA21 PPG ← PWM ← TOAB00 PPG ← Toggle ← TAB0 (master) TOAB01 to TOAB03 PPG ← PWM ← TOAA50 PPG ← Toggle PWM Ch2 TAA5 (slave) TOAA51 PPG ← PWM ← TOAB10 PPG ← Toggle ← TAB1 (master) TOAB11 to TOAB13 PPG ← PWM ← TOAA40 PPG ← Toggle PWM Ch3 TAA4 (slave) TOAA41 PPG ← PWM ← Remark The timing of transmitting data from the compare register of the buffer register is as follows.

• PPG: CPU write timing
• Toggle, PWM, triangular wave PWM: Timing at which timer counter and compare register match TOAAn0 and TOABm0

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 330 of 1817 Sep 19, 2011

7.6.1 Free-running timer mode ( during timer-tuned operation)

This section explains the free-runnin g timer mode of the timer-tuned operation. For the combination of timer-tuned operations, see Table 7-7. In this section, an example of timer-tuned operation using TAA1 and TAA0 is shown. (i) Selecting capture/compare registers When the free-running timer mode of the timer-tuned operation is used with TAA1 and TAA0 connected to each other, the two capture/compare regist ers of TAA1 and two capture/compare registers of TAA0 can be used in combination. How the capture and compare registers are combined is not restricted and can be selected by using the TAAnCCSn bit of the master or slave timer. When the compare register is selected, the set value of the compare register can be rewritten during operation and the rewriting method is anytime write (n = 0, 1). (ii) Overflow If the counter overflows, an overflow interrupt (INTTAA1OV ) of the master timer is generated and the overflow flag (TAA1OVF) is set to “1”. The overflow interrupt (INTTAA0OV) and overflow fl ag (TAA0OVF) of the slave timer do not operate and are always at the low level.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 331 of 1817 Sep 19, 2011 (1) Settings in free-running ti mer mode (compare function) [Initial settings] Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled) Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled) [Initial settings of master timer (TAA1)]

• TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 101 (setting of free-running timer mode)
• TAA1OPT0.TAA1CCS1 and TAA1OPT0.TAA1CCS0 = 00 (setting of capture/compare select bit to “compare”.)
• TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any))
• TAA1CCR1 and TAA1CCR0 registers are set. [Initial settings of slave timer (TAA0)]
• TAA0CTL1.TAA0SYE = 1 (setting of timer-tuned operation)
• TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 101 (setting of free-running timer mode)
• TAA0OPT0.TAA0CCS1 and TAA0OPT0.TAA0CCS0 = 00 (setting of capture/compare select bit to “compare”.)
• TAA0CCR0 and TAA0CCR1 registers are set. Remark The initial settings of the master timer and slave timer may be performed in any order. [Starting counting] <1> Set TAA1CTL0.TAA1CE of the master timer to 1. <2> Start counting. <3> Changing the setting of the register during operation
• The compare register can be rewritten (anytime write). [End condition]
• Set TAA1CTL0.TAA1CE of the master timer to 0.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 332 of 1817 Sep 19, 2011 Figure 7-44. Example of Timing in Free-Running Mode (Compare Function) D10 D11 D00 D01 TOAA10 TOAA11 TOAA01 INTTAA0OV TAA0OVF TOAA00 TAA1CE INTTAA1CC0 INTTAA1CC1 INTTAA0CC0 INTTAA0CC1 INTTAA1OV TAA1OVF FFFFH 0000H TAA1 16-bit counter TAA1CCR0 TAA1CCR1 TAA0CCR0 TAA0CCR1 D10 D11 D00 D01 D10 D11 D00 D01 TAA1OVF write clear (0) L L

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 333 of 1817 Sep 19, 2011 (2) Settings in free-running ti mer mode (capture function) [Initial settings] Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled) Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled) [Initial settings of master timer (TAA1)]

• TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 101 (setting of free-running timer mode)
• TAA1OPT0.TAA1CCS1 and TAA1OPT0.TAA1CCS0 = 11 (setting of capture/compare select bit to “capture”.)
• TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any))
• TAA1IOC1.TAA1IS3 to TAA1IOC1.TAA1IS0 (specification of valid edge of capture trigger) [Initial settings of slave timer (TAA0)]
• TAA0CTL1.TAA0SYE = 1 (setting of timer-tuned operation)
• TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 101 (setting of free-running timer mode)
• TAA0OPT0.TAA0CCS1 and TAA0OPT0.TAA0CCS0 = 11 (setting of capture/compare select bit to “capture”.)
• TAA0IOC1.TAA0IS3 to TAA0IOC1.TAA0IS0 (specification of valid edge of capture trigger) Remark The initial settings of the master timer and slave timer may be performed in any order. [Starting counting] <1> Set TAA1CTL0.TAA1CE of the master timer to 1. <2> Start counting. [End condition]
• Set TAA1CTL0.TAA1CE of the master timer to 0.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 334 of 1817 Sep 19, 2011 Figure 7-45. Example of Timing in Free-Running Mode (Capture Function) D111 D101 D001 D011 INTTAA0OV TAA0OVF TAA1CE INTTAA1CC0 INTTAA1CC1 INTTAA0CC0 INTTAA0CC1 INTTAA1OV TAA1OVF FFFFH 0000H TAA1 16-bit counter TAA1CCR0 TAA1CCR1 TAA0CCR0 TAA0CCR1 TIAA10 TIAA11 TIAA00 TIAA01 D 100 D110 D000 D110 D101 D110 TAA1OVF write clear (0)L L

0000 D110 D111

0000 D000 D001

0000 D010 D011

0000 D100 D101

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 335 of 1817 Sep 19, 2011 (3) Settings in free-running timer mode (capture/compare used together) An example of using TAA0 as a capture register and TAA1 as a compare register is shown below. [Initial settings] Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled) Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled) [Initial settings of master timer (TAA1)]

• TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 101 (setting of free-running timer mode)
• TAA1OPT0.TAA1CCS1 and TAA1OPT0.TAA1CCS0 = 11 (setting of capture/compare select bit to “capture”.)
• TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any))
• TAA1.TAA0IS3 to TAA1.TAA1IS0 (specification of valid edge of capture trigger) [Initial settings of slave timer (TAA0)]
• TAA0CTL1.TAA0SYE = 1 (setting of timer-tuned operation)
• TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 101 (setting of free-running timer mode)
• TAA0OPT0.TAA0CCS1 and TAA0OPT0.TAA0CCS0 = 00 (setting of capture/compare select bit to “compare”.)
• TAA0CCR0 and TAA0CCR1 registers are set. Remark The initial settings of the master timer and slave timer may be performed in any order. [Starting counting] <1> Set TAA1CTL0.TAA1CE of the master timer to 1. <2> Start counting. [End condition]
• Set TAA1CTL0.TAA1CE of the master timer to 0.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 336 of 1817 Sep 19, 2011 Figure 7-46. Example of Timing in Free-Running Mode (Capture/Compare Used Together) D111 D000 D010 TAA1CE INTTAA1CC1 TOAA00 TOAA01 INTTAA0CC0 INTTAA0CC1 INTTAA1CC0 FFFFH 0000H TAA1 16-bit counter TAA0CCR0 TAA0CCR1 D110 D000 D010 D100 D000 D010 TAA1OVF INTTAA1OV TAA1OVF write clear (0) INTTAA0OV L TAA0OVF L TIAA10 TIAA11 TAA1CCR0 0000 D000 TAA1CCR1 0000 0000 0000 D110 D111

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 337 of 1817 Sep 19, 2011

7.6.2 PWM output mode (durin g timer-tuned operation)

This section explains the PWM output mode of timer-tuned operation. For combinations of timer-tuned operations, see Table 7-7. This section presents an example of a timer-tuned operation with TAB0 and TAA5. The TAB0CCR0 register of the master timer (TAB0) is used as a compare register for cycle, and the TAB0CCR1, TAB0CCR2, and TAB0CCR3 registers of the master timer (T AB0) and the TAA5CCR0 and TAA5CCR1 registers of the slave timer (TAA5) are used as compare registers for duty. The compare registers can be rewritten during operation and the rewriting method is batch writing. Batch writing is enabled when the TAB0CCR1 register of the master timer (TAB0) is written, and all the compare registers of the master and slave timers are rewritten or the same value is written to them when an interrupt, which is generated if the value of the TAB0CCR0 re gister of the master timer (TAB0) matc hes the value of the timer counter, is generated. (1) Settings in PWM output mode [Initials setting] Master timer: TAB0CTL0.TAB0CE = 0 (operation disabled) Slave timer: TAA5CTL0.TAA5CE = 0 (operation disabled) [Initial settings of master timer (TAB0)]

• TAB0CTL1.TAB0MD2 to TAB0CTL1.TAB0MD0 = 100 (setting of PWM output mode)
• TAB0OPT0.TAB0CCS3 to TAB0OPT0.TAB0CCS0 = 0000 (setting of capture/compare select bit to “compare”.)
• TAB0CCR0, TAB0CCR1, TAB0CCR2, and TAB0CCR3 registers are set. [Initial settings of slave timer (TAA5)]
• TAA5CTL1.TAA5SYE = 1 (setting of timer-tuned operation)
• TAA5CTL1.TAA5MD2 to TAA5CTL1.TAA5MD0 = 101 (setting of free-running timer mode)
• TAA5OPT0.TAA5CCS1 and TAA5OPT0.TAA5CCS0 = 00 (setting of capture/compare select bit to “compare”.)
• TAA5CCR0 and TAA5CCR1 registers are set. Remark The initial settings of the master timer and slave timer may be performed in any order. [Starting counting] <1> Set TAB0CTL0.TAB0CE of the master timer to 1. <2> Start counting. <3> Changing the setting of the register during operation
• The compare register can be rewritten (batch rewrite). [End condition]
• Set TAB0CTL0.TAB0CE of the master timer to 0.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 338 of 1817 Sep 19, 2011 [Batch write] In the PWM output mode, the next batch write is enabl ed by writing the TAB0CCR1 register of the master timer (TAB0). After all the compare registers that must be re written have been rewritten, therefore, the TAB0CCR1 register of the master timer (TAB0) must be written. Batch writing is executed when the value of the timer counter matches the value of the compare register for cycle (TAB0CCR0). If the TAB0CCR1 register of the master timer (TAB0) is not written, batch writing is no t enabled even if any other compare register is rewritten. Consequently, the valu e of the compare registers is not rewritten even when the value of the timer counter matches the value of the compare register for cycle (TAB0CCR0). Figure 7-47. Timing Example of Tuned PWM Function (TAB0, TAA5) TOAB00 pin output TOAB01 pin output TOAB02 pin output TOAA50 pin output TOAB03 pin output TAB0CCR0 register TAB0CE bit INTTAB0CC0 match interrupt TOAA51 pin output INTTAB0CC1 match interrupt INTTAB0CC2 match interrupt INTTAB0CC3 match interrupt INTTAA5CC0 match interrupt INTTAA5CC1 match interrupt FFFFH 0000H TAB0 16-bit counter D00 D50 D40 D30 D20 D10 D00 D50 D40 D30 D20 D10 TAB0CCR1 register TAB0CCR0 register TAB0CCR1 register TAA5CCR0 register TAA5CCR1 register D00 D10 D20 D30 D40 D50

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 339 of 1817 Sep 19, 2011

7.7 Simultaneous-Start Function

Timer AA and timer AB have a timer-tuned operation function. By using the simultaneous-start function, a timer operation in which the operation start timing and count up timing of the master timer and slave timer are synchronized can be performed. Only the PWM output mode can be used in the simultaneous-start function. The combinations of timers that can use the simultaneous-start function are listed in Table 7-10. Table 7-10. Timer Simultaneous-Start Function Master Timer Slave Timer TAA1 TAA0 TAA3 TAA2 TAB0 TAA5 TAB1 TAA4 Figure 7-48 shows an example where individual operation and simultaneous-start operation of TAA0 (as the master timer) and TAA1 (as the slave timer) are performed in PWM output mode. Figure 7-48. Differences Between Individual Operation and Simultaneous-Start Operation Using TAA1 and TAA0 TAA1 TOAA11 (PWM output) 16-bit timer/counter Individual operation If PWM operates separately with each timer, the 16-bit counter starts and the PWM output starts at a different timing for each timer. 16-bit capture/compare 16-bit capture/compare TOAA10 (square waveform output) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare TAA0 TOAA01 (PWM output) TOAA00 (square waveform output) TAA1 (master) TOAA11 (PWM output) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare TOAA10 (square waveform output) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare TAA0 (slave) TOAA01 (PWM output) Simultaneous-start signal TOAA00 (square waveform output) Simultaneous-start operation With the simultaneous-start function, PWM output operates with the count start timing and the count clock of both timers being synchronized.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 340 of 1817 Sep 19, 2011

7.7.1 PWM output mode (sim ultaneous-start operation)

In this section, the operation of the si multaneous-start function is shown, where TAA1 is used as the master timer and TAA0 is used as the slave timer. The master timer (TAA1) and slave timer (TAA0) start operati ng at the same time when the TAA1CTL0.TAA0CE bit of master timer is set to 1. The slave timer operates by the count clock supplied from the master timer (TAA1). After the slave timer starts operating, however, the 16-bit counter of the slave timer (TAA0) is not cleared even if the 16-bit counter of the master timer (TAA1) is cleared to 0000H upon a match between the 16-bit counter value of the master timer (TAA1) and the TAA1CCR0 register value, because each timer operates individually. In the same manner, if the compare register value of the master timer (TAA1) is rewritten by batch writing, the compare register of the slave timer is not affected. [Initial settings] Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled) Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled) [Initial settings of master timer (TAA1)]

• TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 100 (setting of PMW output mode)
• TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any))
• TAA1CCR1, TAA1CCR0 (specification of valid edge of capture trigger)
• TAA1IOC0 (specification of valid edge of capture trigger) [Initial settings of slave timer (TAA0)]
• TAA0CTL1.TAA0SYE = 1, TAA0SYM = 1 (simultaneous-start operation)
• TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 100 (setting of PMW output mode)
• TAA0CCR0, TAA1CCR1 (specification of valid edge of capture trigger)
• TAA0IOC0 (specification of valid edge of capture trigger) Remark The initial settings of the master timer and slave timer may be performed in any order. [Starting counting] <1> Set TAA1CTL0.TAA1CE of the master timer to 1. <2> Start counting. <3> Changing the setting of the register during operation
• The compare register can be rewritten (anytime write). [End condition]
• Set TAA1CTL0.TAA0CE of the master timer to 0.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 341 of 1817 Sep 19, 2011 Figure 7-49. Timing Example of Simultaneous-Start Function (TAA1: Master, TAA0: Slave) D10 D11 D00 D00 D01 D01 TOAA00 pin output TOAA01 pin output TOAA11 pin output TOAA10 pin output TAA1CE bit INTTAA0CC0 interrupt INTTAA0CC1 interrupt INTTAA1CC0 interrupt INTTAA1CC1 interrupt FFFFH 0000H TAA1 16-bit counter FFFFH 0000H TAA0 -bit counter TAA1CCR0 register TAA1CCR1 register TAA0CCR0 register TAA0CCR1 register D10 D11 D00 D01 D10 D11 D00 D01

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 342 of 1817 Sep 19, 2011

7.8 Cascade Connection

This section explains an operation of connecting two channels of TAA in cascade to form a 32-bit capture timer. For cascade connection, the free-running timer mode must be set and all the capture/compare registers must be set as capture registers (TAA0CCSn = 1). Combinations of TAA channels that can be connected in cascade are shown in the following table. Table 7-11. Cascade Connection of TAA Lower Timer (Master Timer) Higher Timer (Slave Timer) TAA1 TAA0 TAA3 TAA2 In the following example, TAA1 is used as the lower timer (master timer) and TAA0 is used as the higher timer (slave timer) to use them as a 32-bit capture timer by cascade connection. Figure 7-50. Cascade Connection Example Edge detection Count clock selection Operation enable bit (TAA1CE) FFFFH detection signal Capture signal 1 (TIAA11) Capture signal 0 (TIAA10) Lower capture interrupt 0 (INTTAA1CC0) Lower overflow interrupt (INTTAA1OV) Lower capture interrupt 1 (INTTAA1CC1) [Lower timer TAA1] [Higher timer TAA0] Lower timer counter Lower capture register 0 (TAA1CCR0) Lower capture register 1 (TAA1CCR1) Higher timer counter Higher capture register 0 (TAA0CCR0) Higher capture register 1 (TAA0CCR1) Higher overflow interrupt (INTTAA0OV) Edge detection

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 343 of 1817 Sep 19, 2011 The operation of each pin and signal when TAA1 and TAA0 are connected in cascade is shown below. Table 7-12. Status in Cascade Connection Name Higher/Lower Function Operation TIAA10 pin input Lower Capture input 0 The value of the lower timer counter is stored in the TAA1CCR0 register and the value of the higher timer counter is stored in the TAA0CCR0 register when the valid edge of this input is detected. TIAA11 pin input Lower Capture input 1 The value of the lower timer counter is stored in the TAA1CCR1 register and the value of the higher timer counter is stored in the TAA0CCR1 register when the valid edge of this input is detected. INTTAA1CCR0 interrupt signal Lower Capture interrupt 0 This interrupt is generated when the valid edge of the TIAA10 pin is detected. INTTAA1CCR1 interrupt signal Lower Capture interrupt 1 This interrupt is generated when the valid edge of the TIAA11 pin is detected. INTTAA1OV interrupt signal Lower Overflow interrupt This interrupt is generated when an overflow of the lower timer counter is detected. TIAA00 pin input Higher Capture input 0 Does not operate. TIAA01 pin input Higher Capture input 1 Does not operate. INTTAA0CCR0 interrupt signal Higher Capture interrupt 0 Does not operate. INTTAA0CCR1 interrupt signal Higher Capture interrupt 1 Does not operate. INTTAA0OV interrupt signal Higher Overflow interrupt This interrupt is generated when an overflow of the higher timer counter is detected.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 344 of 1817 Sep 19, 2011 Figure 7-51. Operation Flow in Cascade Connection of TAA1 and TAA0 (1/2) 32-bit counter FFFFFFFFH 00000000H Operation enable bit (TAA1CE) TIAA10 input D0a0b D0c0d D1c1d D0e0f D1e1f D0g0h Lower capture register 0 (TAA1CCR0) Lower capture interrupt 0 (INTTAA1CC0) TIAA11 input Lower c apture interrupt 1 (INTTAA1CC1) Overflow interrupt (INTTAA0OV) Overflow flag (TAA0OVF) Pulse interval D1c1d − D1a1b Pulse interval D1e1f − D1c1d D1a1b Pulse interval D0c0d − D0a0b Pulse interval D0e0f − D0c0d Pulse interval D0g0h − D0c0d Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction D0b D0d D0f D0h0000 Higher capture register 0 (TAA0CCR0) Lower capture register 1 (TAA1CCR1) Higher capture register 1 (TAA0CCR1) D0a D0c D0e D0g0000 D1d D1fD1b0000 D1c D1e 0000H 0000H 0000H 0000H D1a0000

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 345 of 1817 Sep 19, 2011 Figure 7-51. Operation Flow in Cascade Connection of TAA1 and TAA0 (2/2) TAA1CE bit = 1 Reading TAA0OPT0 register (checking overflow flag) [Lower timer: TAA1] TAA1CTL0 register (TAA1CKS0 to TAA1CKS2 bits), TAA1CTL1 register, TAA1IOC1 register, TAA1IOC2 register, TAA1OPT0 register [Higher timer: TAA0] TAA0CTL1 register, TAA0IOC1 register, TAA0OPT0 register, TAA0OPT1 register Perform initial setting of these registers before TAA1CE bit = 1. TAA1CKS0 to TAA1CKS2 bits can be set as soon as counting operation starts (TAA1CE bit = 1). START Executing instruction that clears TAA0OVF bit (CLR TAA0OVF) <1> Count operation start flow <4> Overflow flag clear flow TAA1CE bit = 0 Counter is initialized by stopping counting operation (TAA1CE bit = 0). STOP <5> Count operation stop flow TAA0OVF bit = 1 NO YES Reading TAA1CCR0 and TAA0CCR0 registers (reading capture register 0) Executing instruction that clears TAA0CCIC0.TAA0CCIF0 bit (CLR TAA0CCIF0) Calculating pulse interval (Captured value − Previously captured value) <2> Capture 0 read flow INTTAA0CCR0 generated? NO YES TAA1CCIF0 = 0? NO YES Reading TAA1CCR1 and TAA0CCR1 registers (reading capture register 0) Executing instruction that clears TAA0CCIC1.TAA0CCIF1 bit (CLR TAA0CCIF1) Calculating pulse interval (Captured value − Previously captured value) INTTAA0CCR1 generated? NO YES TAA0CCIF1 = 0? NO YES <2> Capture 1 read flow Register initial setting

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 346 of 1817 Sep 19, 2011 Figure 7-52. Example of Basic Timing When TAA1 and TAA0 Are Connected in Cascade 32-bit counter FFFFFFFFH 00000000H Operation enable bit (TAA1CE) TIAA10 input D0a0b D0c0d D1c1d D0e0f D1e1f D1g1h D0g0h D0i0j Lower capture register 0 (TAA1CCR0) Lower capture interrupt 0 (INTTAA1CC0) TIAA11 input Capture interrupt 1 (INTTAA1CC1) Overflow interrupt (INTTAA0OV) Overflow flag (TAA0OVF) Pulse interval D1c1d − D1a1b Pulse interval D1g1h − D1c1d Pulse interval D1e1f − D1c1d D1a1b Pulse interval D0c0d − D0a0b Pulse interval D0e0f − D0c0d Pulse interval D0g0h − D0c0d Pulse interval D0i0j − D0g0h Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction D0b D0d D0f D0h D0j0000 Higher capture register 0 (TAA0CCR0) Lower capture register 1 (TAA1CCR1) Higher capture register 1 (TAA0CCR1) D0a D0c D0e D0g D0i0000 D1d D1f D1hD1b0000 D1c D1e D1gD1a0000 The counting operation is star ted when the TAA1CTL.TAA1CE bit is set to 1 and the count clock is supplied. When the valid edge input to the TIAA10 pin is detected, the count value is stored in the capture register 0 (TAA1CCR0 and TAA0CCR0), and capture interrupt 0 signal (INTTAA1CC0) is issued. The timer counter continues the counting operation in syn chronization with the count clock. When it counts up to FFFFFFFFH, the overflow interrupt (INTTAA0OV) is generated at the next cl ock and the overflow flag (TAA0OVF) is set to 1. The timer counter is cleared to 00000000H and continues counting up. The overflow flag (TAA0OVF) is cleared by an instruction issued from the CPU that writes “0” to it. Because the free-running timer mode is set, the timer c ounter cannot be cleared by detection of the valid edge input to the TIAA10 pin. Using TOAA10 output is prohibited because it alternately functions as the TIAA10 input. Capture register 1 (TAA1CCR1 and TAA0CCR1) also operates in the same manner. If the lower timer counter (TAA1) overflows, an overflow interrupt (TAA1OVF) is generated. However, it is recommended to mask this interrupt because it cannot be used as an overflow interrupt of the 32-bit counter.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 347 of 1817 Sep 19, 2011

7.9 Selector Function

In the V850ES/JH3-E and V850ES/JJ3-E, t he alternate-function pins of ports or peripheral I/O (TAA1, TAB0, UARTC0, or UARTC1) signals can be selected as the capture trigger input of TAA1 and TAB0. If the signal input from the UARTCn pin is selected by the selector function when RXDCn is used, baud rate errors of the LIN reception transfer rate of UARTCn can be calculated (n = 0, 1). (1) Selector operation control register 0 (SELCNT0) The SELCNT0 register is an 8-bit register that selects the capture trigger for CAN0, TAA1, and TAB0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. 0SELCNT0 0 0 ISEL4 ISEL3 0 0 ISEL0 Note 65 43 21 ISEL4 Selection of TIAA11 capture trigger input signal TIAA11 (alternately functions as P33) pin RXDC1 (alternately functions as P24) pin ISEL3 Selection of TIAA10 capture trigger input signal TIAA10 (alternately functions as P32) pin RXDC0 (alternately functions as P31) pin ISEL0Note Selection of TIAB02 capture trigger input signal TIAB02 (alternately functions as P20) pin CAN0 TSOUT signal After reset: 00H R/W Address: FFFFF308H <7> 0 Note μPD70F3783 and 70F3786 only Cautions 1. To set the ISEL4, ISEL3, and ISEL0 bits to 1, set the corresponding function pin to the capture input mode. 2. Set the ISEL4, ISEL3, and ISEL0 bits when the operation of TAA1, TAB0, and UARTC0, UARTC1, and CAN0 are stopped. 3. Be sure to set bits 7 to 5, 2, and 1 to “0”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) R01UH0290EJ0300 Rev.3.00 Page 348 of 1817 Sep 19, 2011

7.10 Cautions

(1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH , not 0000H, may be captured in the TAAnCCR0 and TAAnCCR1 registers if the capture trigger is input immediately after the TAAnCE bit is set to 1. (a) Free-running timer mode Count clock 0000H FFFFH TAAnCE bit TAAnCCR0 register FFFFH 0001H0000H TIAAn0 pin input Capture trigger input 16-bit counter Sampling clock (fXX) Capture trigger input (b) Pulse width measurement mode 0000H FFFFH FFFFH 0002H0000H Count clock TAAnCE bit TAAnCCR0 register TIAAn0 pin input Capture trigger input 16-bit counter Sampling clock (fXX) Capture trigger input Remark n = 0 to 5

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 349 of 1817 Sep 19, 2011 CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) Timer AB (TAB) is a 16-bit timer/event counter. The V850ES/JH3-E and V850ES/JJ3-E have TAB0 and TAB1.

8.1 Overview

An outline of TABn is shown below.

• Clock selection: 8 ways
• Capture/trigger input pins: 4
• External event count input pins: 1
• External trigger input pins: 1
• Timer counters: 1
• Capture/compare registers: 4
• Capture/compare match interrupt request signals: 4
• Timer output pins: 4 Remark n = 0, 1

8.2 Functions

TABn has the following functions.

• Interval timer
• External event counter
• External trigger pulse output
• One-shot pulse output
• PWM output
• Free-running timer
• Pulse width measurement
• Triangular wave PWM output
• Timer-tuned operation function
• Simultaneous-start function Remark n = 0, 1

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8.3 Configuration

TABn includes the following hardware. Table 8-1. Configuration of TABn Item Configuration Registers 16-bit counter TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3) TABn counter read buffer register (TABnCNT) CCR0 to CCR3 buffer registers TABn control registers 0, 1 (TABnCTL0, TABnCTL1) TABn I/O control registers 0 to 2 (TABnIOC0 to TABnIOC2, TABnIOC4) TABn option register 0 (TABnOPT0) Timer inputs Note 1 4 (TIABn0 Note 2 to TIABn3 Note 3 pins), EVTAB1, TRGAB1 Timer outputs Note 1 4 (TOABn0 to TOABn3 Note 3 pins) Notes 1. When using the functions of the TIABn0 to TIABn3 and TOABn0 to TOABn3 pins, see Table 4-18 Using Port Pin as Alternate-Function Pin. 2. The TIAB00 pin functions alternat ely as a capture trigger input signal, external event count input signal, and external trigger input signal. 3. The TIAB03 and TOAB03 pins are not provided in the V850ES/JH3-E. Figure 8-1. Block Diagram of TABn TABnCNT TABnCCR0 TABnCCR1 TABnCCR2 TOABn0 INTTABnOV CCR2 buffer register TABnCCR3 CCR3 buffer register TOABn1 TOABn2 TOABn3Note 2 INTTABnCC0 INTTABnCC1 INTTABnCC2 INTTABnCC3 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 TIABn0Note 1 TIABn1 TIABn2 TIABn3Note 2 Selector Internal bus Internal bus Selector Edge detector CCR0 buffer register CCR1 buffer register 16-bit counter Output controller Clear Notes 1. TAB1: EVTAB1 pin and TRGAB1 pin 2. The TIAB03 and TOAB03 pins are not provided in the V850ES/JH3-E. Remarks 1. f XX: Main clock frequency 2. n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 351 of 1817 Sep 19, 2011 (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TABnCNT register. When the TABnCTL0.TABnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TABnCNT register is read at this time, 0000H is read. Reset sets the TABnCE bit to 0. Therefore, the 16-bit counter is set to FFFFH. (2) CCR0 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TABnCCR0 register is used as a compare regist er, the value written to the TABnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTABnCC0) is generated. The CCR0 buffer register cannot be read or written directly. The CCR0 buffer register is cleared to 0000H after reset, as the TABnCCR0 register is cleared to 0000H. (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TABnCCR1 register is used as a compare regist er, the value written to the TABnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTABnCC1) is generated. The CCR1 buffer register cannot be read or written directly. The CCR1 buffer register is cleared to 0000H after reset, as the TABnCCR1 register is cleared to 0000H. (4) CCR2 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TABnCCR2 register is used as a compare regist er, the value written to the TABnCCR2 register is transferred to the CCR2 buffer register. When the count value of the 16-bit counter ma tches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTABnCC2) is generated. The CCR2 buffer register cannot be read or written directly. The CCR2 buffer register is cleared to 0000H after reset, as the TABnCCR2 register is cleared to 0000H. (5) CCR3 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TABnCCR3 register is used as a compare regist er, the value written to the TABnCCR3 register is transferred to the CCR3 buffer register. When the count value of the 16-bit counter ma tches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTABnCC3) is generated. The CCR3 buffer register cannot be read or written directly. The CCR3 buffer register is cleared to 0000H after reset, as the TABnCCR3 register is cleared to 0000H. (6) Edge detector This circuit detects the valid edges input to the TIABn0 to TIABn3 pins. No edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the TABnIOC1 and TABnIOC2 registers. The TIAB03 pin is not provided in the V850ES/JH3-E.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 352 of 1817 Sep 19, 2011 (7) Output controller This circuit controls the output of the TOABn0 to TOABn3 pins. The output controller is controlled by the TABnIOC0 register. Note that the TOAB03 pin is not provided in the V850ES/JH3-E. (8) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 353 of 1817 Sep 19, 2011

8.4 Registers

The registers that control TABn are as follows.

• TABn control register 0 (TABnCTL0)
• TABn control register 1 (TABnCTL1)
• TABn I/O control register 0 (TABnIOC0)
• TABn I/O control register 1 (TABnIOC1)
• TABn I/O control register 2 (TABnIOC2)
• TABn I/O control register 4 (TABnIOC4)
• TABn option register 0 (TABnOPT0)
• TABn capture/compare register 0 (TABnCCR0)
• TABn capture/compare register 1 (TABnCCR1)
• TABn capture/compare register 2 (TABnCCR2)
• TABn capture/compare register 3 (TABnCCR3)
• TABn counter read buffer register (TABnCNT) Remarks 1. When using the functions of the TIABn0 to TIABn3 and TOABn0 to TOABn3 pins, see Table 4-18 Using Port Pin as Alternate-Function Pin. 2. n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 354 of 1817 Sep 19, 2011 (1) TABn control register 0 (TABnCTL0) The TABnCTL0 register is an 8-bit register that controls the operation of TABn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Software can be used to always write the same value to the TABnCTL0 register. TABnCE TABn operation disabled (TABn reset asynchronouslyNote). TABn operation enabled. TABn operation started. TABnCE TABn operation control TABnCTL0 (n = 0, 1) 00 00 TABnCKS2 TABnCKS1 TABnCKS0 65 43 21 After reset: 00H R/W Address: TAB0CTL0 FFFFF540H, TAB1CTL0 FFFFF560H <7> 0 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 TABnCKS2 Internal count clock selection TABnCKS1 TABnCKS0 Note TABnOPT0.TABnOVF bit, 16-bit counter, timer output (TOABn0 to TOABn3 pins) Cautions 1. Set the TABnCKS2 to TABnCKS 0 bits when the TABnCE bit = 0. When the value of the TABnCE bi t is changed from 0 to 1, the TABnCKS2 to TABnCKS0 bits can be set simultaneously. 2. Be sure to set bits 3 to 6 to “0”. Remark f XX: Main clock frequency

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 355 of 1817 Sep 19, 2011 (2) TABn control register 1 (TABnCTL1) The TABnCTL1 register is an 8-bit register that controls the operation of TABn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. TABnEST Software trigger control TABnCTL1 (n = 0, 1) TABnEST TABnEEE 00 TABnMD2 TABnMD1 TABnMD0 65 43 21 After reset: 00H R/W Address: TAB0CTL1 FFFFF541H, TAB1CTL1 FFFFF561H Generate a valid signal for external trigger input.

• In one-shot pulse output mode: A one-shot pulse is output with writing 1 to the TABnEST bit as the trigger.
• In external trigger pulse output mode: A PWM waveform is output with writing 1 to the TABnEST bit as the trigger. 7 0 Disable operation with external event count input. (Perform counting with the count clock selected by the TABnCTL0.TABnCK0 to TABnCTL0.TABnCK2 bits.) TABnEEE Count clock selection The TABnEEE bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. Interval timer mode External event count mode External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode Triangular wave PWM mode TABnMD2 Timer mode selection TABnMD1 TABnMD0 Enable operation with external event count input. (Perform counting at the valid edge of the external event count input signal.) Cautions 1. The TABnEST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored. 2. Be sure to set bits 3, 4, and 7 to “0”. 3. External event count input is select ed in the external event count mode regardless of the value of the TABnEEE bit. 4. Set the TABnEEE and TABnMD 2 to TABnMD0 bits when the TABnCTL0.TABnCE bit = 0. (The sam e value can be written when the TABnCE bit = 1.) The operation is not guaranteed when rewriting is performed with the TABnCE bit = 1. If rewriting was mistakenly performed, clear the TABnCE bit to 0 and then set the bits again.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 356 of 1817 Sep 19, 2011 (3) TABn I/O control register 0 (TABnIOC0) The TABnIOC0 register is an 8-bit register that controls the timer output (TOABn0 to TOABn3 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. TABnOL3Note 1 TABnOLm TOABnm pin output level setting (m = 0 to 3)Note 2 TOABnm pin high level start TOABnm pin low level start TABnIOC0 (n = 0, 1) TABnOE3Note 1 TABnOL2 TABnOE2 TABnOL1 TABnOE1 TABnOL0 TABnOE0 After reset: 00H R/W Address: TAB0IOC0 FFFFF542H, TAB1IOC0 FFFFF562H TABnOEm TOABnm pin output setting (m = 0 to 3) Timer output disabled

• When TABnOLm bit = 0: Low level is output from the TOABnm pin
• When TABnOLm bit = 1: High level is output from the TOABnm pin 7 <0> Timer output enabled (a square wave is output from the TOABnm pin). Notes 1. The TOAB03 pin is not provided in the V850ES/JH3-E. Set the TAB0OL3 and TAB0OE3 bits to 0. 2. The output level of the timer output pin (TOABnm) specified by the TABnOLm bit is shown below. TABnCE bit TOABnm output pin 16-bit counter
• When TABnOLm bit = 0 TABnCE bit TOABnm output pin 16-bit counter
• When TABnOLm bit = 1 Cautions 1. Rewrite the TABnOL m and TABnOEm bits when the TABnCTL0.TABnCE bit = 0. (The same value can be written when the TABnCE bit = 1.) If rewriting was mistakenly performed, clear the TABnCE bi t to 0 and then set the bits again. 2. Even if the TABnOLm bit is manipulated when the TABnCE and TABnOEm bits are 0, the TOABnm pin output level varies. Remark m = 0 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 357 of 1817 Sep 19, 2011 (4) TABn I/O control register 1 (TABnIOC1) The TABnIOC1 register is an 8-bit regist er that controls the valid edge of t he capture trigger input signals (TIABn0 to TIABn3 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. TABnIS7Note TABnIS7 TABnIS6 Capture trigger input signal (TIABn3 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges TABnIOC1 (n = 0, 1) TABnIS6Note TABnIS5 TABnIS4 TABnIS3 TABnIS2 TABnIS1 TABnIS0 65 43 21 After reset: 00H R/W Address: TAB0IOC1 FFFFF543H, TAB1IOC1 FFFFF563H TABnIS5 TABnIS4 Capture trigger input signal (TIABn2 pin) valid edge detection No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges 7 0 TABnIS3 TABnIS2 Capture trigger input signal (TIABn1 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges TABnIS1 TABnIS0 Capture trigger input signal (TIABn0 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges Note The TIAB03 pin is not provided in the V850ES/JH3-E. Set the TAB0IS7 and TAB0IS6 bits to 0 when using the V850ES/JH3-E. Cautions 1. Rewrite the TABnIS 7 to TABnIS0 bits when the TABnCTL0.TABnCE bit = 0. (The same value can be written when the TABnCE bit = 1.) If rewriting was mistakenly performed, clear the TABnCE bit to 0 and then set the bits again. 2. The TABnIS7 to TABnIS0 bi ts are valid only in the free- running timer mode and the pulse width measurement mode. In all other modes, a capture operation is not possible.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 358 of 1817 Sep 19, 2011 (5) TABn I/O control register 2 (TABnIOC2) The TABnIOC2 register is an 8-bit regi ster that controls the va lid edge of the external event count input signal (TIAB00/EVTAB1 pin) and external trigger input signal (TIAB00/TRGAB1 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. TABnEES1 TABnEES0 External event count input signal (TIAB00/EVTAB1 pin) valid edge setting No edge detection (external event count invalid) Detection of rising edge Detection of falling edge Detection of both edges TABnIOC2 (n = 0, 1) 00 0 TABnEES1TABnEES0 TABnETS1 TABnETS0 65 43 21 After reset: 00H R/W Address: TAB0IOC2 FFFFF544H, TAB1IOC2 FFFFF564H TABnETS1 TABnETS0 External trigger input signal (TIAB00/TRGAB1 pin) valid edge setting No edge detection (external trigger invalid) Detection of rising edge Detection of falling edge Detection of both edges 7 0 Cautions 1. Rewrite the T ABnEES1, TABnEES0, TABnETS1, and TABnETS0 bits when the TABnCTL0.TABnCE bit = 0. (The same value can be written when the TABnCE bit = 1.) If rewriting was mistakenly performed, clear the TABnCE bit to 0 and then set the bits again. 2. The TABnEES1 and TABnEES0 bits are valid only when the TABnCTL1.TABnEEE bit = 1 or when the external event count mode (TABnCTL1.TABnMD2 to TABnCTL1.TABnMD0 bits = 001) has been set. 3. The TABnETS1 and TABnETS0 bits are valid only when the external trigger pulse output mode (TABnCTL1.TABnMD2 to TABnCTL1.TABnMD0 bits = 010) or the one-shot pulse output mode (TABnCTL1.TABnMD2 to TABnCTL1.TABnMD0 = 011) is set.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 359 of 1817 Sep 19, 2011 (6) TABn I/O control register 4 (TABnIOC4) The TABnIOC4 register is an 8-bit register that controls the timer output. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. This register is not reset by stopping the timer operation (TABnCTL0.TABnCE = 0). Cautions 1. Accessing the TABnIOC4 register is prohib ited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock 2. The TABnIOC4 register can be set only in the interval timer mode and free-running timer mode. Be sure to set the TABnIOC4 register to 00H in all other modes (for details of the mode setting, see 8.4 (2) TABn control register 1 (TABnCTL1)). Even in free-running timer mode, if the TABnCCR0 to TABnCCR3 registers are set to the capture function, the setting of the TABnIOC4 register becomes invalid. TABnOS3NoteTABnIOC4 (n = 0, 1) TABnOR3Note TABnOS2 TABnOR2 TABnOS1 TABnOR1 TABnOS0 TABnOR0 6543217 0 After reset: 00H R/W Address: TAB0IOC4 FFFFF550H, TAB1IOC4 FFFFF570H TABnOSm TABnORm Toggle control of TOABnm pin (m = 0 to 3) No request. Normal toggle operation. Reset request Fix to inactive level upon next match between value of 16-bit counter and value of TAAnCCRm register. Set request Fix to active level upon next match between value of 16-bit counter and value of TAAnCCRm register. Keep request Keep the current output level. Note The TOAB03 pin is not provided in the V850ES/JH3-E. Set the TAB0OS3 and TAB0OR3 bits to 0.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 360 of 1817 Sep 19, 2011 (7) TABn option register 0 (TABnOPT0) The TABnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. TABnCCS3Note 1 TABnCCSm TABnCCRm register capture/compare selection The TABnCCSm bit setting is valid only in the free-running timer mode. Compare register selected Capture register selected TABnOPT0 (n = 0, 1) TABnCCS2 TABnCCS1 TABnCCS0 0 TAB1CMSNote 2 TABnCUF TABnOVF 65 43 21 After reset: 00H R/W Address: TAB0OPT0 FFFFF545H, TAB1OPT0 FFFFF565H TABnOVF Set (1) Reset (0) TABn overflow detection

• The TABnOVF bit is set to 1 when the 16-bit counter count value overflows from FFFFH to 0000H in the free-running timer mode or the pulse width measurement mode.  An interrupt request signal (INTTABnOV) is generated at the same time that the TABnOVF bit is set to 1. The INTTABnOV signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode.  The TABnOVF bit is not cleared even when the TABnOVF bit or the TABnOPT0 register are read when the TABnOVF bit = 1.  The TABnOVF bit can be both read and written, but the TABnOVF bit cannot be set to 1 by software. Writing 1 has no effect on the operation of TABn. Overflow occurred TABnOVF bit 0 written or TABnCTL0.TABnCE bit = 0 7 <0> Notes 1. The TIAB03 pin is not provided in the V850ES/JH3-E. Set the TAB0CCS3 bit to 0. 2. The TAB1CMS bit is used for the mo tor control function. For details, see CHAPTER 11 MOTOR CONTROL FUNCTION. Cautions 1. Rewrite the TABnCCS 3 to TABnCCS0 bits when the TABnCTL0.TABnCE bit = 0. (The same value can be written when the TABnCE bit = 1.) If rewriting was mistakenly performed, clear the TABnCE bit to 0 and then set the bits again. 2. Be sure to set bit 3 to “0”. When the motor control function is not used, be sure to also set bit 2 to “0”. Remark m = 0 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 361 of 1817 Sep 19, 2011 (8) TABn capture/compare register 0 (TABnCCR0) The TABnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capt ure register or a compare register only in the free-running timer mode, according to the setting of the TABnOPT0.TABnCCS0 bit. In the pulse width measurement mode, the TABnCCR0 register can be used only as a capture register. In an y other mode, this register can be used only as a compare register. The TABnCCR0 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TABnCCR0 register is prohibite d in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock TABnCCR0 (n = 0, 1) 12 10 8 6 4 2 After reset: 0000H R/W Address: TAB0CCR0 FFFFF546H, TAB1CCR0 FFFFF566H 14 013 11 9 7 5 315 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 362 of 1817 Sep 19, 2011 (a) Function as compare register The TABnCCR0 register can be rewritten even when the TABnCTL0.TABnCE bit = 1. The set value of the TABnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16- bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTABnCC0) is generated. If TOABn0 pin output is enab led at this time, the output of the TOABn0 pin is inverted. When the TABnCCR0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse out put mode, PWM output mode, or triangular wave PWM mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register. (b) Function as capture register When the TABnCCR0 register is used as a capture register in the free-runni ng timer mode, the count value of the 16-bit counter is stored in the TABnCCR0 register if the valid edge of the captur e trigger input pin (TIABn0 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TABnCCR0 register and the 16-bit counter is cleared (000 0H) if the valid edge of the capture trigger input pin (TIABn0 pin) is detected. Even if the capture operation and reading the TABnCCR0 register conflict, the correct value of the TABnCCR0 register can be read. Remark n = 0, 1 The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 8-2. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register − Triangular wave PWM mode Compare register Batch write

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 363 of 1817 Sep 19, 2011 (9) TABn capture/compare register 1 (TABnCCR1) The TABnCCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capt ure register or a compare register only in the free-running timer mode, according to the setting of the TABnOPT0.TABnCCS1 bit. In the pulse width measurement mode, the TABnCCR1 register can be used only as a capture register. In an y other mode, this register can be used only as a compare register. The TABnCCR1 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TABnCCR1 register is prohibite d in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock TABnCCR1 (n = 0, 1) 12 10 8 6 4 2 After reset: 0000H R/W Address: TAB0CCR1 FFFFF548H, TAB1CCR1 FFFFF568H 14 013 11 9 7 5 315 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 364 of 1817 Sep 19, 2011 (a) Function as compare register The TABnCCR1 register can be rewritten even when the TABnCTL0.TABnCE bit = 1. The set value of the TABnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16- bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTABnCC1) is generated. If TOABn1 pin output is enabled at this time , the output of the TOABn1 pin is inverted. (b) Function as capture register When the TABnCCR1 register is used as a capture register in the free-runni ng timer mode, the count value of the 16-bit counter is stored in the TABnCCR1 register if the valid edge of the captur e trigger input pin (TIABn1 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TABnCCR1 register and the 16-bit counter is cleared (000 0H) if the valid edge of the capture trigger input pin (TIABn1 pin) is detected. Even if the capture operation and reading the TABnCCR1 register conflict, the correct value of the TABnCCR1 register can be read. Remark n = 0, 1 The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 8-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register − Triangular wave PWM mode Compare register Batch write

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 365 of 1817 Sep 19, 2011 (10) TABn capture/compare register 2 (TABnCCR2) The TABnCCR2 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capt ure register or a compare register only in the free-running timer mode, according to the setting of the TABnOPT0.TABnCCS2 bit. In the pulse width measurement mode, the TABnCCR2 register can be used only as a capture register. In any ot her mode, this register can be used only as a compare register. The TABnCCR2 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TABnCCR2 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock TABnCCR2 (n = 0, 1) 12 10 8 6 4 2 After reset: 0000H R/W Address: TAB0CCR2 FFFFF54AH, TAB1CCR2 FFFFF56AH 14 013 11 9 7 5 315 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 366 of 1817 Sep 19, 2011 (a) Function as compare register The TABnCCR2 register can be rewritten even when the TABnCTL0.TABnCE bit = 1. The set value of the TABnCCR2 register is transferred to the CCR2 buffer register. When the value of the 16- bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTABnCC2) is generated. If TOABn2 pin output is enabled at this time , the output of the TOABn2 pin is inverted. (b) Function as capture register When the TABnCCR2 register is used as a capture register in the free-runni ng timer mode, the count value of the 16-bit counter is stored in the TABnCCR2 register if the valid edge of the captur e trigger input pin (TIABn2 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TABnCCR2 register and the 16-bit counter is cleared (000 0H) if the valid edge of the capture trigger input pin (TIABn2 pin) is detected. Even if the capture operation and reading the TABnCCR2 register conflict, the correct value of the TABnCCR2 register can be read. Remark n = 0, 1 The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 8-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register − Triangular wave PWM mode Compare register Batch write

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 367 of 1817 Sep 19, 2011 (11) TABn capture/compare register 3 (TABnCCR3) The TABnCCR3 register can be used as a capture register or a compare r egister depending on the mode. (Note that the TIAB03 pin is not provided in the V850ES/JH3-E. Theref ore, when using the V850ES/JH3-E, the TAB0CCR3 register can be used only as a compare register.) This register can be used as a capt ure register or a compare register only in the free-running timer mode, according to the setting of the TABnOPT0.TABnCCS3 bit. In the pulse width measurement mode, the TABnCCR3 register can be used only as a capture register. In any ot her mode, this register can be used only as a compare register. The TABnCCR3 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TABnCCR3 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock TABnCCR3 (n = 0, 1) 12 10 8 6 4 2 After reset: 0000H R/W Address: TAB0CCR3 FFFFF54CH, TAB1CCR3 FFFFF56CH 14 013 11 9 7 5 315 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 368 of 1817 Sep 19, 2011 (a) Function as compare register The TABnCCR3 register can be rewritten even when the TABnCTL0.TABnCE bit = 1. The set value of the TABnCCR3 register is transferred to the CCR3 buffer register. When the value of the 16- bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTABnCC3) is generated. If TOABn3 pin output is enabled at this time , the output of the TOABn3 pin is inverted. (b) Function as capture register When the TABnCCR3 register is used as a capture register in the free-runni ng timer mode, the count value of the 16-bit counter is stored in the TABnCCR3 register if the valid edge of the captur e trigger input pin (TIABn3 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TABnCCR3 register and the 16-bit counter is cleared (000 0H) if the valid edge of the capture trigger input pin (TIABn3 pin) is detected. Even if the capture operation and reading the TABnCCR3 register conflict, the correct value of the TABnCCR3 register can be read. Remark n = 0, 1 The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 8-5. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register − Triangular wave PWM mode Compare register Batch write

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 369 of 1817 Sep 19, 2011 (12) TABn counter read bu ffer register (TABnCNT) The TABnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TABnCTL0.TABnCE bit = 1, the count value of the 16-bit timer can be read. This register is read-only in 16-bit units. The value of the TABnCNT register is cleared to 0000H when the TABnCE bit = 0. If the TABnCNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. The value of the TABnCNT register is cleared to 0000H after reset, as the TABnCE bit is cleared to 0. Caution Accessing the TABnCNT register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock TABnCCR0 (n = 0, 1) 12 10 8 6 4 2 After reset: 0000H R/W Address: TAB0CCR0 FFFFF546H, TAB1CCR0 FFFFF566H 14 013 11 9 7 5 315 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 370 of 1817 Sep 19, 2011

8.5 Operation

TABn can perform the following operations. Operation TABnCTL1.TABnEST Bit (Software Trigger Bit) TIABn0 Pin (External Trigger Input) Capture/Compare Register Setting Compare Register Write Interval timer mode Invalid Invalid Compare only Anytime write External event count mode Note 1 Invalid Invalid Compare only Anytime write External trigger pulse output mode Note 2 Valid Valid Compare only Batch write One-shot pulse output mode Note 2 Valid Valid Compare only Anytime write PWM output mode Invalid Invalid Compare only Batch write Free-running timer mode Invalid Invalid Switching enabled Anytime write Pulse width measurement mode Note 2 Invalid Invalid Capture only Not applicable Triangular wave PWM mode Invalid Invalid Compare only Batch write Notes 1. To use the external event count mode, specify that t he valid edge of the TIABn0 pin capture trigger input is not detected (by clearing the TABnIOC1.TABnIS1 and TABnIOC1.TABnIS0 bits to “00”). 2. When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the TABnCTL1.TABnEEE bit to 0). Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 371 of 1817 Sep 19, 2011

8.5.1 Interval timer mode (T ABnMD2 to TABnMD0 bits = 000)

In the interval timer mode, an interrupt request signal (I NTTABnCC0) is generated at the specified interval if the TABnCTL0.TABnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOABn0 pin. Usually, the TABnCCR1 to TABnCCR3 registers are not used in the interval timer mode. Figure 8-2. Configuration of Interval Timer 16-bit counter Output controller CCR0 buffer registerTABnCE bit TABnCCR0 register Count clock selection Clear Match signal TOABn0 pin INTTABnCC0 signal Remark n = 0, 1 Figure 8-3. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register TOABn0 pin output INTTABnCC0 signal D0 D0 D0 D0 Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 372 of 1817 Sep 19, 2011 When the TABnCE bit is set to 1, the value of the 16-bi t counter is cleared from FFFFH to 0000H in synchronization with the count clock, and t he counter starts counting. At this time, the output of the TOABn0 pin is inverted. Additionally, the set value of the TABnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, the output of the TOABn0 pin is inverted, and a compare match interrupt request signal (INTTABnCC0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TABnCCR0 register + 1) × Count clock cycle Figure 8-4. Register Setting for Interval Timer Mode Operation (1/2) (a) TABn control register 0 (TABnCTL0) 0/1 0 0 0 0 TABnCTL0 Select count clock 0: Stop counting 1: Enable counting 0/1 0/1 0/1 TABnCKS2 TABnCKS1 TABnCKS0TABnCE (b) TABn control register 1 (TABnCTL1) 0 0 0/1 Note 00 TABnCTL1 0, 0, 0: Interval timer mode 000 TABnMD2 TABnMD1 TABnMD0TABnEEETABnESTTABnSYE 0: Operate on count clock selected by bits TABnCKS0 to TABnCKS2 1: Count with external event count input signal Note This bit can be set to 1 only when the interrupt request signals (INTTABnCC0 and INTTABnCCk) are masked by the interrupt mask flags (TABnCCMK0 to TABnCCMKk) and the timer output (TOABnk) is performed at the same time. However, the TABnCCR0 and TABnCCRk registers must be set to the same value (see 8.5.1 (2) (d) Operation of TABnCCR1 to TABnCCR3 registers) (k = 1 to 3). Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 373 of 1817 Sep 19, 2011 Figure 8-4. Register Setting for Interval Timer Mode Operation (2/2) (c) TABn I/O control register 0 (TABnIOC0) 0/1Note 0/1Note 0/1 0/1 0/1 TABnIOC0 0: Disable TOABn0 pin output 1: Enable TOABn0 pin output Setting of output level with operation of TOABn0 pin disabled 0: Low level 1: High level 0: Disable TOABn1 pin output 1: Enable TOABn1 pin output Setting of output level with operation of TOABn1 pin disabled 0: Low level 1: High level 0/1 0/1 0/1 TABnOE1 TABnOL0 TABnOE0TABnOL1 0: Disable TOABn2 pin output 1: Enable TOABn2 pin output Setting of output level with operation of TOABn2 pin disabled 0: Low level 1: High level 0: Disable TOABn3 pin output 1: Enable TOABn3 pin output Setting of output level with operation of TOABn3 pin disabled 0: Low level 1: High level TABnOE3 TABnOL2 TABnOE2TABnOL3 (d) TABn counter read buffer register (TABnCNT) By reading the TABnCNT register, the count value of the 16-bit counter can be read. (e) TABn capture/compare register 0 (TABnCCR0) If the TABnCCR0 register is set to D0, the interval is as follows. Interval = (D0 + 1) × Count clock cycle (f) TABn capture/compare register s 1 to 3 (TABnCCR1 to TABnCCR3) Usually, the TABnCCR1 to TABnCCR3 registers are not used in the interval timer mode. However, the set value of the TABnCCR1 to TABnCCR3 registers is transferred to the CCR1 to CCR3 buffer registers. The compare match interrupt request signals (INTTABnCCR1 to INTTABnCCR3) are generated when the count value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers. Therefore, mask the interrupt requests by using the corresponding interrupt mask flags (TABnCCMK1 to TABnCCMK3). Note The TIAB03 pin is not provided in the V850ES/JH3-E. Set the TAB0OL3 and TAB0OE3 bits to 0. Remarks 1. TABn I/O control register 1 (TABnIOC1), TABn I/O control register 2 (TABnIOC2), and TABn option register 0 (TABnOPT0) are not used in the interval timer mode. 2. n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 374 of 1817 Sep 19, 2011 (1) Interval timer mode operation flow Figure 8-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register TOABn0 pin output INTTABnCC0 signal D0 D0 D0 <1> <2> TABnCE bit = 1 TABnCE bit = 0 Register initial setting TABnCTL0 register (TABnCKS0 to TABnCKS2 bits) TABnCTL1 register, TABnIOC0 register, TABnCCR0 register The initial setting of these registers is performed before setting the TABnCE bit to 1. The TABnCKS0 to TABnCKS2 bits can be set at the same time when counting has been started (TABnCE bit = 1). The counter is initialized and counting is stopped by clearing the TABnCE bit to 0. START STOP <1> Count operation start flow <2> Count operation stop flow Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 375 of 1817 Sep 19, 2011 (2) Interval timer mode operation timing (a) Operation if TABnCCR0 register is set to 0000H If the TABnCCR0 register is set to 0000H, the IN TTABnCC0 signal is generated at each count clock subsequent to the first count clock, and the output of the TOABn0 pin is inverted. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter TABnCE bit TABnCCR0 register TOABn0 pin output INTTABnCC0 signal 0000H Interval time Count clock cycle Interval time Count clock cycle FFFFH 0000H 0000H 0000H 0000H Remark n = 0, 1 (b) Operation if TABnCCR0 register is set to FFFFH If the TABnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing . The INTTABnCC0 signal is generated and the output of the TOABn0 pin is inverted. At this time, an overflow interrupt request signal (INTTABnOV) is not generated, nor is the overflow flag (TABnOPT0.TABnOVF bit) set to 1. FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register TOABn0 pin output INTTABnCC0 signal FFFFH Interval time 10000H × count clock cycle Interval time 10000H × count clock cycle Interval time 10000H × count clock cycle Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 376 of 1817 Sep 19, 2011 (c) Notes on rewriting TABnCCR0 register To change the value of the TABnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register TABnOL0 bit TOABn0 pin output INTTABnCC0 signal D1 D2 D1 D1 D2D2 D2 L Interval time (1) Interval time (NG) Interval time (2) Remarks 1. Interval time (1): (D 1 + 1) × Count clock cycle Interval time (NG): (10000H + D 2 + 1) × Count clock cycle Interval time (2): (D 2 + 1) × Count clock cycle 2. n = 0, 1 If the value of the TABnCCR0 register is changed from D 1 to D 2 while the count value is greater than D 2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TABnCCR0 register has been rewritten. Consequently, the value of the 16-bit counter that is compared is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D 2, the INTTABnCC0 signal is generated and the output of the TOABn0 pin is inverted. Therefore, the INTTABnCC0 signal may not be generated at the interval time “(D 1 + 1) × Count clock cycle” or “(D2 + 1) × Count clock cycle” originally expected, but may be generated at an interval of “(10000H + D2 + 1) × Count clock period”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 377 of 1817 Sep 19, 2011 (d) Operation of TABnCCR 1 to TABnCCR3 registers Figure 8-6. Configuration of TABnCCR1 to TABnCCR3 Registers CCR0 buffer registerTABnCE bit TABnCCR0 register Clear Match signal INTTABnCC0 signal TOABn3 pinNote INTTABnCC3 signal TOABn0 pin TABnCCR1 register CCR1 buffer register Match signal TOABn1 pin INTTABnCC1 signal TABnCCR3 register CCR3 buffer register Match signal TOABn2 pin INTTABnCC2 signal TABnCCR2 register CCR2 buffer register Match signal Output controller Count clock selection Output controller Output controller Output controller 16-bit counter Note The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 378 of 1817 Sep 19, 2011 If the set value of the TABnCCRk register is less than the set value of the TABnCCR0 register, the INTTABnCCk signal is generated once per cycle. At the same time, the output of the TOABnk pin is inverted. The TOABnk pin outputs a square wave with the same cycle as that output by the TOABn0 pin. Remark k = 1 to 3, n = 0, 1 Figure 8-7. Timing Chart When D01 ≥ Dk1 D01 D11 D21 D31 D21 D11 D31 D01D01 D21 D11 D31 D01 D21 D11 D31 D01 D21 D11 D31 FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register TOABn0 pin output INTTABnCC0 signal TABnCCR1 register TOABn1 pin output INTTABnCC1 signal TABnCCR2 register TOABn2 pin output INTTABnCC2 signal TABnCCR3 register TOABn3 pin outputNote INTTABnCC3 signal Note The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 379 of 1817 Sep 19, 2011 If the set value of the TABnCCRk register is greater than the set value of the TABnCCR0 register, the count value of the 16-bit counter does not match the va lue of the TABnCCRk register. Consequently, the INTTABnCCk signal is not generated, nor is the output of the TOABnk pin changed. Remark k = 1 to 3, n = 0, 1 Figure 8-8. Timing Chart When D01 < Dk1 D01 D11 D21 L L L D31 D01D01 D01 D01 FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register TOABn0 pin output INTTABnCC0 signal TABnCCR1 register TOABn1 pin output INTTABnCC1 signal TABnCCR2 register TOABn2 pin output INTTABnCC2 signal TABnCCR3 register TOABn3 pin outputNote INTTABnCC3 signal Note The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 380 of 1817 Sep 19, 2011

8.5.2 External event count mode (TABnMD2 to TABnMD0 bits = 001)

In the external event count mode, the valid edge of the external event count input is counted when the TABnCTL0.TABnCE bit is set to 1, and an interrupt request signal (INTTABnCC0) is generated each time the specified number of edges have been counted. The TOABn0 pin cannot be used. Usually, the TABnCCR1 to TABnCCR3 registers are not used in the external event count mode. Figure 8-9. Configuration in External Event Count Mode 16-bit counter CCR0 buffer registerTABnCE bit TABnCCR0 register Edge detector Clear Match signal INTTABnCC0 signal TIAB00 pinNote (external event count input) Note TAB1: EVTAB1 pin Figure 8-10. Basic Timing in External Event Count Mode FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register INTTABnCC0 signal D0 D0 D0 16-bit counter TABnCCR0 register INTTABnCC0 signal External event count input (TIAB00 pin input)Note External event count interval 0 + 1) D0 − 1D 0 0000 0001 External event count interval 0 + 1) External event count interval 0 + 1) Note TAB1: EVTAB1 pin Remark This figure shows the basic timing when the rising edg e is specified as the va lid edge of the external event count input.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 381 of 1817 Sep 19, 2011 When the TABnCE bit is set to 1, the value of the 16-bit c ounter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of the external event count input is detected. Additionally, the set value of the TABnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTABnCC0) is generated. The INTTABnCC0 signal is generated each time the valid edge of the external event count input has been detected (set value of TABnCCR0 register + 1) times. Figure 8-11. Register Setting for Operation in External Event Count Mode (1/2) (a) TABn control register 0 (TABnCTL0) 0/1 0 0 0 0 TABnCTL0 0: Stop counting 1: Enable counting 000 TABnCKS2 TABnCKS1 TABnCKS0TABnCE (b) TABn control register 1 (TABnCTL1) 0000 0 TABnCTL1 0, 0, 1: External event count mode 001 TABnMD2 TABnMD1 TABnMD0TABnEEETABnESTTABnSYE (c) TABn I/O control register 0 (TABnIOC0) 0000 0 TABnIOC0 0: Disable TOABn0 pin output 0: Disable TOABn1 pin output 000 TABnOE1 TABnOL0 TABnOE0TABnOL1TABnOE3 TABnOL2 TABnOE2TABnOL3 0: Disable TOABn2 pin output 0: Disable TOABn3 pin output (d) TABn I/O control register 2 (TABnIOC2) 0 0 0 0 0/1 TABnIOC2 Select valid edge of external event count input 0/1 0 0 TABnEES0 TABnETS1 TABnETS0TABnEES1 Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 382 of 1817 Sep 19, 2011 Figure 8-11. Register Setting for Operation in External Event Count Mode (2/2) (e) TABn counter read buffer register (TABnCNT) The count value of the 16-bit counter can be read by reading the TABnCNT register. (f) TABn capture/compare register 0 (TABnCCR0) If D0 is set to the TABnCCR0 register, the counter is cleared and a compare match interrupt request signal (INTTABnCC0) is generated when the number of external event counts reaches (D0 + 1). (g) TABn capture/compare register s 1 to 3 (TABnCCR1 to TABnCCR3) Usually, the TABnCCR1 to TABnCCR3 registers are not used in the external event count mode. However, the set value of the TABnCCR1 to TABnCCR3 registers are transferred to the CCR1 to CCR3 buffer registers. When the count value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers, compare match interrupt request signals (INTTABnCC1 to INTTABnCC3) are generated. Therefore, mask the interrupt signals by using the interrupt mask flags (TABnCCMK1 to TABnCCMK3). Caution For TAB0, when an external clock is used as the count clock, the external clock can be input only from the TIAB00 pin. At th is time, set the TAB0IOC1.TAB0IS1 and TAB0IOC1.TAB0IS0 bits to 00 (capture trigger input (TIAB00 pin): no edge detection). Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are not used in the external event count mode. 2. n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 383 of 1817 Sep 19, 2011 (1) External event count mode operation flow Figure 8-12. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register INTTABnCC0 signal D0 D0 D0 <1> <2> TABnCE bit = 1 TABnCE bit = 0 Register initial setting TABnCTL0 register (TABnCKS0 to TABnCKS2 bits) TABnCTL1 register, TABnIOC0 register, TABnIOC2 register, TABnCCR0 register The initial setting of these registers is performed before setting the TABnCE bit to 1. The TABnCKS0 to TABnCKS2 bits can be set at the same time when counting has been started (TABnCE bit = 1). The counter is initialized and counting is stopped by clearing the TABnCE bit to 0. START STOP <1> Count operation start flow <2> Count operation stop flow Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 384 of 1817 Sep 19, 2011 (2) Operation timing in external event count mode Cautions 1. In the external event count mode , do not set the TABnCCR0 register to 0000H. 2. In the external event count mode, use of th e timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (TABnCTL1.TABnMD2 to TABnCTL1.TABnMD0 bits = 000, TABnCTL1.TABnEEE bit = 1). (a) Operation if TABnCCR0 register is set to FFFFH If the TABnCCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of the external event count signal has been detected. The 16-b it counter is cleared to 0000H in synchronization with the next count-up timing, and the INTTABnCC0 signal is generated. At this time, the TABnOPT0.TABnOVF bit is not set. FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register INTTABnCC0 signal FFFFH External event count signal interval External event count signal interval External event count signal interval Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 385 of 1817 Sep 19, 2011 (b) Notes on rewriting the TABnCCR0 register To change the value of the TABnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register INTTABnCC0 signal D1 D2 D1 D1 D2D2 D2 External event count signal interval (1) 1 + 1) External event count signal interval (NG) (10000H + D 2 + 1) External event count signal interval (2) 2 + 1) Remark n = 0, 1 If the value of the TABnCCR0 register is changed from D 1 to D 2 while the count value is greater than D 2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TABnCCR0 register has been rewritten. Consequently, the value that is compared with the 16-bit counter is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D 2, the INTTABnCC0 signal is generated. Therefore, the INTTABnCC0 signal may not be generated at the valid edge count of “(D1 + 1) times” or “(D2 + 1) times” originally expected, but may be generated at the valid edge count of “(10000H + D2 + 1) times”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 386 of 1817 Sep 19, 2011 (c) Operation of TABnCCR1 to TABnCCR3 registers Figure 8-13. Configuration of TABnCCR1 to TABnCCR3 Registers CCR0 buffer registerTABnCE bit TABnCCR0 register Clear Match signal INTTABnCC0 signal INTTABnCC3 signal TIAB00 pinNote TABnCCR1 register CCR1 buffer register Match signal INTTABnCC1 signal TABnCCR3 register CCR3 buffer register Match signal INTTABnCC2 signal TABnCCR2 register CCR2 buffer register Match signal 16-bit counter Edge detector Note TAB1: EVTAB1 pin Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 387 of 1817 Sep 19, 2011 If the set value of the TABnCCRk register is smalle r than the set value of the TABnCCR0 register, the INTTABnCCk signal is generated once per cycle. Remark k = 1 to 3, n = 0, 1 Figure 8-14. Timing Chart When D01 ≥ Dk1 D01 D11 D21 D31 D21 D11 D31 D01D01 D21 D11 D31 D01 D21 D11 D31 D01 D21 D11 D31 FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register INTTABnCC0 signal TABnCCR1 register INTTABnCC1 signal TABnCCR2 register INTTABnCC2 signal TABnCCR3 register INTTABnCC3 signal Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 388 of 1817 Sep 19, 2011 If the set value of the TABnCCRk register is greater than the set value of t he TABnCCR0 register, the INTTABnCCk signal is not generated because the coun t value of the 16-bit counter and the value of the TABnCCRk register do not match. Remark k = 1 to 3, n = 0, 1 Figure 8-15. Timing Chart When D01 < Dk1 D01 D11 D21 L L L D31 D01D01 D01 D01 FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register INTTABnCC0 signal TABnCCR1 register INTTABnCC1 signal TABnCCR2 register INTTABnCC2 signal TABnCCR3 register INTTABnCC3 signal Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 389 of 1817 Sep 19, 2011

8.5.3 External trigger pulse output m ode (TABnMD2 to TABnMD0 bits = 010)

In the external trigger pulse output mode, TABn waits for a trigger when the TABnCTL0.TABnCE bit is set to 1. When the valid edge of the external trigger input signal is detected, TABn starts counting, and outputs a PWM waveform from the TOABn1 to TOABn3 pins. Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the TOABn0 pin. Figure 8-16. Configuration in External Trigger Pulse Output Mode CCR0 buffer registerTABnCE bit TABnCCR0 register Clear Match signal INTTABnCC0 signal TOABn3 pinNote 2 INTTABnCC3 signal TOABn0 pin TIAB00 pinNote 1 Transfer S R TABnCCR1 register CCR1 buffer register Match signal TOABn1 pin INTTABnCC1 signal Transfer Transfer S R TABnCCR3 register CCR3 buffer register Match signal Transfer TOABn2 pin INTTABnCC2 signal S R TABnCCR2 register CCR2 buffer register Match signal 16-bit counter Count clock selection Count start control Edge detector Software trigger generation Output controller (RS-FF) Output controller Output controller (RS-FF) Output controller Notes 1. TAB1: TRGAB1 pin 2. The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 390 of 1817 Sep 19, 2011 Figure 8-17. Basic Timing in External Trigger Pulse Output Mode D1D1 Active level width (D2) Active level width (D Active level width (D Active level width (D Active level width (D Cycle (D0 + 1) Cycle (D 0 + 1)Wait for trigger Active level width (D Cycle (D0 + 1) FFFFH 16-bit counter 0000H TABnCE bit External trigger input (TIAB00 pin input)Note 1 TABnCCR0 register INTTABnCC0 signal TOABn0 pin output (only when software trigger is used) TABnCCR1 register INTTABnCC1 signal TOABn1 pin output TABnCCR2 register INTTABnCC2 signal TOABn2 pin output TABnCCR3 register INTTABnCC3 signal TOABn3 pin outputNote 2 Active level width Active level width Active level width Active level width Active level width D0 D0 D0 D0 Notes 1. TAB1: TRGAB1 pin 2. The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 391 of 1817 Sep 19, 2011 TABn waits for a trigger when the TABnCE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOABnk pin. If the trigger is generated again while the counter is op erating, the counter is cleared to 00 00H and restarted. (The output of the TOABn0 pin is inverted. The TOABnk pin outputs a high leve l regardless of the status (high/low) when a trigger is generated.) The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TABnCCRk register) × Count clock cycle Cycle = (Set value of TABnCCR0 register + 1) × Count clock cycle Duty factor = (Set value of TABnCCRk register)/(Set value of TABnCCR0 register + 1) The compare match request signal (INTTABnCC0) is generat ed when the 16-bit counter counts up next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is clear ed to 0000H. The compare match interrupt request signal (INTTABnCCk) is generated when the count value of the 16-bi t counter matches the value of the CCRk buffer register. The value set to the TABnCCRm register is transferred to t he CCRm buffer register when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The valid edge of the external trigger input signal or setti ng the software trigger (TABnCTL1.TABnEST bit) to 1 is used as the trigger. Remark k = 1 to 3, m = 0 to 3, n = 0, 1 Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (1/3) (a) TABn control register 0 (TABnCTL0) 0/1 0 0 0 0 TABnCTL0 Select count clockNote 0: Stop counting 1: Enable counting 0/1 0/1 0/1 TABnCKS2 TABnCKS1 TABnCKS0TABnCE Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 392 of 1817 Sep 19, 2011 Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (2/3) (b) TABn control register 1 (TABnCTL1) 0 0/1 0/1 0 0 TABnCTL1 Generate software trigger when 1 is written 010 TABnMD2 TABnMD1 TABnMD0TABnEST 0, 1, 0: External trigger pulse output mode TABnEEETABnSYE 0: Operate on count clock selected by TABnCKS0 to TABnCKS2 bits 1: Count by external event input signal (c) TABn I/O control register 0 (TABnIOC0) 0/1Note 1 0/1Note 1 0/1 0/1 0/1 TABnIOC0 0: Disable TOABn0 pin output 1: Enable TOABn0 pin output Setting of output level while operation of TOABn0 pin is disabled 0: Low level 1: High level 0: Disable TOABn1 pin output 1: Enable TOABn1 pin output Specification of active level of TOABn1 pin output 0: Active-high 1: Active-low 0/1 0/1 Note 2 0/1Note 2 TABnOE1 TABnOL0 TABnOE0TABnOL1 TOABnk pin output 16-bit counter

• When TABnOLk bit = 0 TOABnk pin output 16-bit counter
• When TABnOLk bit = 1 TABnOE3 TABnOL2 TABnOE2TABnOL3 Specification of active level of TOABn3 pin output 0: Active-high 1: Active-low 0: Disable TOABn2 pin output 1: Enable TOABn2 pin output Specification of active level of TOABn2 pin output 0: Active-high 1: Active-low 0: Disable TOABn3 pin output 1: Enable TOABn3 pin output Notes 1. The TOAB03 pin is not provided in the V850ES/ JH3-E. Set the TAB0OL3 and TAB0OE3 bits to 2. Clear this bit to 0 when the TOABn0 pin is not used in the external trigger pulse output mode. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 393 of 1817 Sep 19, 2011 Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (3/3) (d) TABn I/O control register 2 (TABnIOC2) 0 0 0 0 0/1 TABnIOC2 Select valid edge of external trigger input 0/1 0/1 0/1 TABnETS1 TABnETS0TABnEES0TABnEES1 Select valid edge of external event count input (e) TABn counter read buffer register (TABnCNT) The value of the 16-bit counter can be read by reading the TABnCNT register. (f) TABn capture/compare register s 0 to 3 (TABnCCR0 to TABnCCR3) If D0 is set to the TABnCCR0 register, D1 to the TABnCCR1 register, D2 to the TABnCCR2 register, and D3 to the TABnCCR3 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) × Count clock cycle TOABn1 pin PWM waveform active level width = D1 × Count clock cycle TOABn2 pin PWM waveform active level width = D2 × Count clock cycle TOABn3 pin PWM waveform active level width = D3 × Count clock cycle Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are not used in the external trigger pulse output mode. 2. Updating TABn capture/compare register 2 (TABnCCR2) and TABn capture/compare register 3 (TABnCCR3) is enabled by writing TABn capture/compare register 1 (TABnCCR1). 3. n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 394 of 1817 Sep 19, 2011 (1) Operation flow in extern al trigger pulse output mode Figure 8-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2) D10 D10 D10 D20 D30 D00 D11 D21 D01 D31 D11 D21 D00 D31 D20 D30 D00 D21 D00 D31 D11 D21 D00 D31 FFFFH 16-bit counter 0000H TABnCE bit External trigger input (TIAB00 pin input)Note 1 TABnCCR0 register CCR0 buffer register INTTABnCC0 signal TOABn0 pin output (only when software trigger is used) TABnCCR1 register CCR1 buffer register INTTABnCC1 signal TOABn1 pin output TABnCCR2 register CCR2 buffer register INTTABnCC2 signal TOABn2 pin output TABnCCR3 register CCR3 buffer register INTTABnCC3 signal TOABn3 pin outputNote 2 D00 D01 D00 D00 D01 D00 D10 D11 D10D10D11 D10 D11 D10 D11 D20 D21 D20 D21 D20 D21 D21 D30 D31 D30 D31 D30 D31 D30 D31 D11 D11 D20 D10 Notes 1. TAB1: TRGAB1 pin 2. The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 395 of 1817 Sep 19, 2011 Figure 8-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2) START <1> Count operation start flow TABnCE bit = 1 Register initial setting TABnCTL0 register (TABnCKS0 to TABnCKS2 bits), TABnCTL1 register, TABnIOC0 register, TABnIOC2 register, TABnCCR0 to TABnCCR3 registers The initial setting of these registers is performed before setting the TABnCE bit to 1. Writing the TABnCCR1 register must be performed only when the set duty factor is changed after writing the TABnCCR2 and TABnCCR3 registers. When the counter is cleared after setting, the value of the TABnCCRm register is transferred to the CCRm buffer register. Writing the same value to the TABnCCR1 register is necessary only when the set duty factor of the TOABn2 and TOABn3 pin outputs is changed. When the counter is cleared after setting, the value of the TABnCCRm register is transferred to the CCRm buffer register. The TABnCCR1 register only needs to be written, only when the set duty factor of the TOABn1 pin output is changed. When the counter is cleared after setting, the value of the TABnCCRm register is transferred to the CCRm buffer register. Counting is stopped. The TABnCKS0 to TABnCKS2 bits can be set at the same time when counting is enabled (TABnCE bit = 1). Trigger wait status Writing the TABnCCR1 register must be performed after writing the TABnCCR0, TABnCCR2, and TABnCCR3 registers. When the counter is cleared after setting, the value of the TABnCCRm register is transferred to the CCRm buffer registers. Writing the same value to the TABnCCR1 register is necessary only when the set cycle is changed. <2> TABnCCR0 to TABnCCR3 register setting change flow <3> TABnCCR0 register setting change flow <4> TABnCCR1 to TABnCCR3 register setting change flow <5> TABnCCR2, TABnCCR3 register setting change flow <6> TABnCCR1 register setting change flow <7> Count operation stop flow TABnCE bit = 0 Setting of TABnCCR2, TABnCCR3 registers Setting of TABnCCR1 register Setting of TABnCCR2, TABnCCR3 registers Setting of TABnCCR1 register STOP Setting of TABnCCR1 register Setting of TABnCCR0 register Setting of TABnCCR1 register Setting of TABnCCR0, TABnCCR2, and TABnCCR3 registers Setting of TABnCCR1 register When the counter is cleared after setting, the value of the TABnCCRm register is transferred to the CCRm buffer register. Remark m = 0 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 396 of 1817 Sep 19, 2011 (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TABnCCR1 register last. Rewrite the TABnCCRk register after writing the TABnCCR1 register after the INTTABnCC0 signal is detected. FFFFH 16-bit counter 0000H TABnCE bit External trigger input (TIAB00 pin input)Note 1 D30 D00 D01 D30 D30 D20 D20 D20 D21 D11 D00 D00 D31 D01 D01 D21 D11 D31 TABnCCR0 register CCR0 buffer register INTTABnCC0 signal TABnCCR1 register CCR1 buffer register INTTABnCC1 signal TOABn1 pin output TABnCCR2 register CCR2 buffer register INTTABnCC2 signal TOABn2 pin output TABnCCR3 register CCR3 buffer register INTTABnCC3 signal TOABn3 pin outputNote 2 TOABn0 pin output (only when software trigger is used) D10 D10 D10 D00 D11 D10 D11 D10 D21 D20 D21 D20 D31 D30 D31 D30 D00 D01 Notes 1. TAB1: TRGAB1 pin 2. The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 397 of 1817 Sep 19, 2011 To transfer data from the TABnCCRm register to the CCRm buffer register, the TABnCCR1 register must be written. To change both the cycle and active level width of the PW M waveform at this time, first set the cycle to the TABnCCR0 register, set the active level width to the TABnCCR2 and TABnCCR3 registers, and then set the active level to the TABnCCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TABnCCR0 register, and then write the same value to the TABnCCR1 register. To change only the active level width (duty factor) of the PWM waveform, first set the active level to the TABnCCR2 and TABnCCR3 registers and then set the active level to the TABnCCR1 register. To change only the active level width (duty factor) of the PWM waveform output by the TOABn1 pin, only the TABnCCR1 register has to be set. To change only the active level width (duty factor) of the PWM waveform output by the TOABn2 and TOABn3 pins, first set the active level width to the TABnCCR2 and TABnCCR3 registers, and then write the same value to the TABnCCR1 register. After data is written to the TABnCCR1 register, the value written to the TABnCCRm register is transferred to the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value to be compared with the 16-bit counter. To write the TABnCCR0 to TABnCCR3 registers again afte r writing the TABnCCR1 register once, do so after the INTTABnCC0 signal is generated. Otherwise, t he value of the CCRm buffer register may become undefined because the timing of transferring data from the TABnCCRm register to the CCRm buffer register conflicts with writing the TABnCCRm register. Remarks 1. The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. 2. m = 0 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 398 of 1817 Sep 19, 2011 (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TABnCCRk register to 0000H. If the set value of the TABnCCR0 register is FFFFH, the INTTABnCCk signal is generated periodically. Count clock 16-bit counter TABnCE bit TABnCCR0 register TABnCCRk register INTTABnCC0 signal INTTABnCCk signal TOABnk pin output 0000H 0000H 0000H D0 − 1D 00000FFFF 0000 D 0 − 1D 0 00000001 L Remark k = 1 to 3, n = 0, 1 To output a 100% waveform, set a value of “set value of TABnCCR0 register + 1” to the TABnCCRk register. If the set value of the TABnCCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter TABnCE bit TABnCCR0 register TABnCCRk register INTTABnCC0 signal INTTABnCCk signal TOABnk pin output D0 + 1 D0 + 1 D0 + 1 D0 − 1D 00000FFFF 0000 D 0 − 1D 0 00000001 Remark k = 1 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 399 of 1817 Sep 19, 2011 (c) Conflict between trigger detection and match with CCRk buffer register If the trigger is detected immediately after the INTT ABnCCk signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of t he TOABnk pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter CCRk buffer register INTTABnCCk signal TOABnk pin output External trigger input (TIAB00 pin input)Note Dk Dk − 10000FFFF 0000 Shortened Dk Note TAB1: TRGAB1 pin Remark k = 1 to 3, n = 0, 1 If the trigger is detected immediately before the INTT ABnCCk signal is generated, the INTTABnCCk signal is not generated, and the 16-bit counter is cleared to 00 00H and continues counting. The output signal of the TOABnk pin remains active. Consequently, the active period of the PWM waveform is extended. 16-bit counter CCRk buffer register INTTABnCCk signal TOABnk pin output External trigger input (TIAB00 pin input)Note Dk Dk − 2D k − 1D k0000FFFF 0000 0001 Extended Note TAB1: TRGAB1 pin Remark k = 1 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 400 of 1817 Sep 19, 2011 (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTABnCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOABnk pin is extended by time from generation of the INTTABnCC0 signal to trigger detection. 16-bit counter CCR0 buffer register INTTABnCC0 signal TOABnk pin output External trigger input (TIAB00 pin input)Note D0 − 1D 00000FFFF 0000 0000 Extended Note TAB1: TRGAB1 pin Remark k = 1 to 3, n = 0, 1 If the trigger is detected immediately before the INTT ABnCC0 signal is generated, the INTTABnCC0 signal is not generated. The 16-bit counter is cleared to 0000H, the TOABnk pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter CCR0 buffer register INTTABnCC0 signal TOABnk pin output External trigger input (TIAB00 pin input)Note D0 − 1D 00000FFFF 0000 0001 Shortened Note TAB1: TRGAB1 pin Remark k = 1 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 401 of 1817 Sep 19, 2011 (e) Generation timing of compare match interrupt request signal (INTTABnCCk) The timing of generation of the INTTABnCCk signal in th e external trigger pulse output mode differs from the timing of other INTTABnCCk signals; the INTTABnCCk signa l is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register. Count clock 16-bit counter CCRk buffer register TOABnk pin output INTTABnCCk signal Dk Dk − 2D k − 1D k Dk + 1 D k + 2 Remark k = 1 to 3, n = 0, 1 Usually, the INTTABnCCk signal is generated in synchronization with the next count-up after the count value of the 16-bit counter matches the value of the CCRk buffer register. In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the timing of changing the output signal of the TOABnk pin.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 402 of 1817 Sep 19, 2011

8.5.4 One-shot pulse output mode (TABnMD2 to TABnMD0 bits = 011)

In the one-shot pulse output mode, TABn waits for a trigger when the TABnCTL0.TABnCE bit is set to 1. When the valid edge of the external trigger input is detected, TABn starts counting, and outputs a one-s hot pulse from the TOABn1 to TOABn3 pins. Instead of the external trigger, a software trigger can al so be generated to output the pulse. When the software trigger is used, the TOABn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). Figure 8-20. Configuration in One-Shot Pulse Output Mode CCR0 buffer registerTABnCE bit TABnCCR0 register Clear Match signal INTTABnCC0 signal TOABn3 pinNote 2 INTTABnCC3 signal TOABn0 pin TIAB00 pinNote 1 Transfer S R S R TABnCCR1 register CCR1 buffer register Match signal TOABn1 pin INTTABnCC1 signal Transfer Transfer S R TABnCCR3 register CCR3 buffer register Match signal Transfer TOABn2 pin INTTABnCC2 signal S R TABnCCR2 register CCR2 buffer register Match signal 16-bit counterCount clock selection Count start control Edge detector Software trigger generation Output controller (RS-FF) Output controller (RS-FF) Output controller (RS-FF) Output controller (RS-FF) Notes 1. TAB1: TRGAB1 pin 2. The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 403 of 1817 Sep 19, 2011 Figure 8-21. Basic Timing in One-Shot Pulse Output Mode Delay (D1) Active level width (D0 − D1 + 1) Delay (D1) Active level width (D0 − D1 + 1) Delay (D1) Active level width (D0 − D1 + 1) Delay (D2) Active level width (D0 − D2 + 1) Delay (D2) Active level width (D0 − D2 + 1) Delay (D2) Active level width (D0 − D2 + 1) Delay (D3) Active level width (D0 − D3 + 1) Delay (D3) Active level width (D0 − D3 + 1) Delay (D3) Active level width (D0 − D3 + 1) FFFFH 16-bit counter 0000H TABnCE bit External trigger input (TIAB00 pin input)Note 1 TABnCCR0 register INTTABnCC0 signal TABnCCR2 register INTTABnCC2 signal TOABn2 pin output TABnCCR3 register INTTABnCC3 signal TOABn3 pin outputNote 2 TABnCCR1 register INTTABnCC1 signal TOABn1 pin output TOABn0 pin output (only when software trigger is used) Notes 1. TAB1: TRGAB1 pin 2. The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 404 of 1817 Sep 19, 2011 When the TABnCE bit is set to 1, TABn waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, a nd outputs a one-shot pulse from the TOABn k pin. After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and wa its for a trigger. If a trigger is generated again while the one-shot pulse is being output, it is ignored. The output delay period and active level width of the one-shot pulse can be calculated as follows. Output delay period = (Set value of TABnCCRk register) × Count clock cycle Active level width = (Set value of TABnCCR0 register − Set value of TABnCCRk register + 1) × Count clock cycle The compare match interrupt request signal INTTABnCC0 is generated when the 16-bit counter counts up after its count value matches the value of the CCR0 buffer register. The compare match interrupt request signal (INTTABnCCk) is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register. The valid edge of the external trigger input or setting the software trigger (TABnCTL1.TABnEST bit) to 1 is used as the trigger. Remark k = 1 to 3, n = 0, 1 Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (1/3) (a) TABn control register 0 (TABnCTL0) 0/1 0 0 0 0 TABnCTL0 Select count clockNote 0: Stop counting 1: Enable counting 0/1 0/1 0/1 TABnCKS2 TABnCKS1 TABnCKS0TABnCE (b) TABn control register 1 (TABnCTL1) 0 0/1 0/1 0 0TABnCTL1 Generate software trigger when 1 is written 011 TABnMD2 TABnMD1 TABnMD0TABnEST 0, 1, 1: One-shot pulse output mode TABnEEETABnSYE 0: Operate on count clock selected by TABnCKS0 to TABnCKS2 bits 1: Count by external event count input signal Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 405 of 1817 Sep 19, 2011 Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (2/3) (c) TABn I/O control register 0 (TABnIOC0) TOABnk pin output 16-bit counter

• When TABnOLk bit = 0 TOABnk pin output 16-bit counter
• When TABnOLk bit = 1 0/1Note 1 0/1Note 1 0/1 0/1 0/1 TABnIOC0 0: Disable TOABn0 pin output 1: Enable TOABn0 pin output Setting of output level while operation of TOABn0 pin is disabled 0: Low level 1: High level 0: Disable TOABn1 pin output 1: Enable TOABn1 pin output Specification of active level of TOABn1 pin output 0: Active-high 1: Active-low 0/1 0/1 Note 2 0/1Note 2 TABnOE1 TABnOL0 TABnOE0TABnOL1TABnOE3 TABnOL2 TABnOE2TABnOL3 Specification of active level of TOABn3 pin output 0: Active-high 1: Active-low 0: Disable TOABn2 pin output 1: Enable TOABn2 pin output Specification of active level of TOABn2 pin output 0: Active-high 1: Active-low 0: Disable TOABn3 pin output 1: Enable TOABn3 pin output (d) TABn I/O control register 2 (TABnIOC2) 0 0 0 0 0/1 TABnIOC2 Select valid edge of external trigger input 0/1 0/1 0/1 TABnETS1 TABnETS0TABnEES0TABnEES1 Select valid edge of external event count input (e) TABn counter read buffer register (TABnCNT) The value of the 16-bit counter can be read by reading the TABnCNT register. Notes 1. The TIAB03 pin is not provided in the V850ES/JH 3-E. Set the TAB0OL3 and TAB0OE3 bits to 2. Clear this bit to 0 when the TOABn0 pin is not used in the one-shot pulse output mode. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 406 of 1817 Sep 19, 2011 Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (3/3) (f) TABn capture/compare register s 0 to 3 (TABnCCR0 to TABnCCR3) If D0 is set to the TABnCCR0 register and Dk to the TABnCCRk register, the active level width and output delay period of the one-shot pulse are as follows. Active level width = (D0 − Dk + 1) × Count clock cycle Output delay period = (Dk) × Count clock cycle Caution One-shot pulses are not output even in the one-shot pulse out put mode, if the set value of the TABnCCRk register is greater than that value of the TABnCCR0 register. Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are not used in the one-shot pulse output mode. 2. k = 1 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 407 of 1817 Sep 19, 2011 (1) Operation flow in one-shot pulse output mode Figure 8-23. Software Processing Flow in One-Shot Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TABnCE bit External trigger input (TIAB00 pin input)Note 1 TABnCCR0 register INTTABnCC0 signal TOABn0 pin output (only when software trigger is used) TABnCCR1 register INTTABnCC1 signal TOABn1 pin output TABnCCR2 register INTTABnCC2 signal TOABn2 pin output TABnCCR3 register INTTABnCC3 signal TOABn3 pin outputNote 2 D00 D01 D11D10 D21D20 D31D30 D10 D20 D30 D11 D21 D31 D00 D01 Notes 1. TAB1: TRGAB1 pin 2. The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 408 of 1817 Sep 19, 2011 Figure 8-23. Software Processing Flow in One-Shot Pulse Output Mode (2/2) TABnCE bit = 1 Register initial setting TABnCTL0 register (TABnCKS0 to TABnCKS2 bits), TABnCTL1 register, TABnIOC0 register, TABnIOC2 register, TABnCCR0 to TABnCCR3 registers The initial setting of these registers is performed before setting the TABnCE bit to 1. The TABnCKS0 to TABnCKS2 bits can be set at the same time when counting has been started (TABnCE bit = 1). Trigger wait status START <1> Count operation start flow TABnCE bit = 0 Count operation is stopped STOP <3> Count operation stop flow Setting of TABnCCR0 to TABnCCR3 registers As rewriting the TABnCCRm register immediately sends the data to the CCRm buffer register, rewriting immediately after the generation of the INTTABnCCR0 signal is recommended. <2> TABnCCR0 to TABnCCR3 register setting change flow Remark m = 0 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 409 of 1817 Sep 19, 2011 (2) Operation timing in one-shot pulse output mode (a) Notes on rewriting TABnCCRm register To change the set value of the TABnCCRm register to a smaller value, stop counting once, and then change the set value. If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. Dk0 Dk1 D01 D01D00 Dk1 D01 Dk0 Dk0 Dk1 D00 D00 FFFFH 16-bit counter 0000H TABnCE bit External trigger input (TIAB00 pin input)Note TABnCCR0 register INTTABnCC0 signal TOABn0 pin output (only when software trigger is used) TABnCCRk register INTTABnCCk signal TOABnk pin output Delay (Dk0) Active level width (D00 − Dk0 + 1) Active level width (D01 − Dk1 + 1) Active level width (D01 − Dk1 + 1) Delay (Dk1) Delay (10000H + Dk1) Note TAB1: TRGAB1 pin When the TABnCCR0 register is rewritten from D 00 to D 01 and the TABnCCRk register from D k0 to D k1 where D00 > D 01 and D k0 > D k1, if the TABnCCRk register is rewritten when the count value of the 16-bit counter is greater than D k1 and less than D k0 and if the TABnCCR0 register is rewri tten when the count value is greater than D 01 and less than D 00, each set value is reflected as soon as the register has been rewritten and compared with the count value. The counter c ounts up to FFFFH and then counts up again from 0000H. When the count value matches D k1, the counter generates the INTTABn CCk signal and asserts the TOABnk pin. When the count value matches D 01, the counter generates the INTTABnCC0 signal, deasserts the TOABnk pin, and stops counting. Therefore, the counter may output a pu lse with a delay period or active per iod different from that of the one- shot pulse that is originally expected. Remark k = 1 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 410 of 1817 Sep 19, 2011 (b) Generation timing of compare match interrupt request signal (INTTABnCCk) The generation timing of the INTTABnCCk signal in the o ne-shot pulse output mode is different from other INTTABnCCk signals; the INTTABnCCk signal is generated when the count value of the 16-bit counter matches the value of the TABnCCRk register. Count clock 16-bit counter TABnCCRk register TOABnk pin output INTTABnCCk signal Dk Dk − 2D k − 1D k Dk + 1 D k + 2 Usually, the INTTABnCCk signal is generated when the 16-bit counter counts up next time after its count value matches the value of the TABnCCRk register. In the one-shot pulse output mode, however, it is gene rated one clock earlier. This is because the timing is changed to match the change timing of the TOABnk pin. Remark k = 1 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 411 of 1817 Sep 19, 2011

8.5.5 PWM output mode (TABnMD 2 to TABnMD0 bits = 100)

In the PWM output mode, a PWM waveform is output from the TOABn1 to TOABn3 pins when the TABnCTL0.TABnCE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOABn0 pin. Figure 8-24. Configuration in PWM Output Mode CCR0 buffer registerTABnCE bit TABnCCR0 register Clear Match signal INTTABnCC0 signal TOABn3 pinNote INTTABnCC3 signal TOABn0 pin Transfer S R TABnCCR1 register CCR1 buffer register Match signal TOABn1 pin INTTABnCC1 signal Transfer Transfer S R TABnCCR3 register CCR3 buffer register Match signal Transfer TOABn2 pin INTTABnCC2 signal S R TABnCCR2 register CCR2 buffer register Match signal 16-bit counter Count clock selection Output controller (RS-FF) Output controller Output controller (RS-FF) Output controller (RS-FF) Note The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 412 of 1817 Sep 19, 2011 Figure 8-25. Basic Timing in PWM Output Mode D0D0 FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register INTTABnCC0 signal TOABn0 pin output TABnCCR1 register INTTABnCC1 signal TOABn1 pin output TABnCCR2 register INTTABnCC2 signal TOABn2 pin output TABnCCR3 register INTTABnCC3 signal TOABn3 pin outputNote Active level width (D3) Cycle (D0 + 1) Cycle (D 0 + 1) Cycle (D 0 + 1) Cycle (D 0 + 1) Active level width (D Active level width (D Active level width (D Active level width (D1) Active level width (D1) Active level width (D1) Active level width (D1) Active level width (D2) Active level width (D2) Active level width (D2) Active level width (D2) Note The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 413 of 1817 Sep 19, 2011 When the TABnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, st arts counting, and outputs a PWM waveform from the TOABnk pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TABnCCRk register) × Count clock cycle Cycle = (Set value of TABnCCR0 register + 1) × Count clock cycle Duty factor = (Set value of TABnCCRk register)/(Set value of TABnCCR0 register + 1) The PWM waveform can be changed by rewriting the TABnCCRm register while the counter is operating. The newly written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal (INTTABnCC0) is generated when the 16-bit c ounter counts up next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal (INTTABnCCk) is gener ated when the count value of the 16-bit counter matches the value of the CCRk buffer register. Remark k = 1 to 3, m = 0 to 3, n = 0, 1 Figure 8-26. Setting of Registers in PWM Output Mode (1/3) (a) TABn control register 0 (TABnCTL0) 0/1 0 0 0 0 TABnCTL0 Select count clockNote 0: Stop counting 1: Enable counting 0/1 0/1 0/1 TABnCKS2 TABnCKS1 TABnCKS0TABnCE (b) TABn control register 1 (TABnCTL1) 0 0 0/1 0 0 TABnCTL1 100 TABnMD2 TABnMD1 TABnMD0TABnEEETABnESTTABnSYE 1, 0, 0: PWM output mode 0: Operate on count clock selected by TABnCKS0 to TABnCKS2 bits 1: Count by external event count input signal Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 414 of 1817 Sep 19, 2011 Figure 8-26. Setting of Registers in PWM Output Mode (2/3) (c) TABn I/O control register 0 (TABnIOC0) TOABnk pin output 16-bit counter

• When TABnOLk bit = 0 TOABnk pin output 16-bit counter
• When TABnOLk bit = 1 0/1Note 1 0/1Note 1 0/1 0/1 0/1 TABnIOC0 0: Disable TOABn0 pin output 1: Enable TOABn0 pin output Setting of output level while operation of TOABn0 pin is disabled 0: Low level 1: High level 0: Disable TOABn1 pin output 1: Enable TOABn1 pin output Specification of active level of TOABn1 pin output 0: Active-high 1: Active-low 0/1 0/1 Note 2 0/1Note 2 TABnOE1 TABnOL0 TABnOE0TABnOL1TABnOE3 TABnOL2 TABnOE2TABnOL3 Specification of active level of TOABn3 pin output 0: Active-high 1: Active-low 0: Disable TOABn2 pin output 1: Enable TOABn2 pin output Specification of active level of TOABn2 pin output 0: Active-high 1: Active-low 0: Disable TOABn3 pin output 1: Enable TOABn3 pin output (d) TABn I/O control register 2 (TABnIOC2) 0 0 0 0 0/1 TABnIOC2 Select valid edge of external event count input. 0/1 0 0 TABnEES0 TABnETS1 TABnETS0TABnEES1 (e) TABn counter read buffer register (TABnCNT) The value of the 16-bit counter can be read by reading the TABnCNT register. Notes 1. The TIAB03 pin is not provided in the V850ES/ JH3-E. Set the TAB0OL3 and TAB0OE3 bits to 2. Clear this bit to 0 when the TOABn0 pin is not used in the PWM output mode. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 415 of 1817 Sep 19, 2011 Figure 8-26. Register Setting in PWM Output Mode (3/3) (f) TABn capture/compare register s 0 to 3 (TABnCCR0 to TABnCCR3) If D0 is set to the TABnCCR0 register and D k to the TABnCCRk register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) × Count clock cycle Active level width = Dk × Count clock cycle Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are not used in the PWM output mode. 2. Updating TABn capture/compare register 2 (TABnCCR2) and TABn capture/compare register 3 (TABnCCR3) is enabled by writing TABn capture/compare register 1 (TABnCCR1). 3. n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 416 of 1817 Sep 19, 2011 (1) Operation flow in PWM output mode Figure 8-27. Software Processing Flow in PWM Output Mode (1/2) D10 D10 D10 D20 D30 D00 D11 D21 D01 D31 D11 D21 D00 D31 D20 D30 D00 D21 D00 D31 D11 D21 D00 D31 FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register CCR0 buffer register INTTABnCC0 signal TOABn0 pin output TABnCCR1 register CCR1 buffer register INTTABnCC1 signal TOABn1 pin output TABnCCR2 register CCR2 buffer register INTTABnCC2 signal TOABn2 pin output TABnCCR3 register CCR3 buffer register INTTABnCC3 signal TOABn3 pin outputNote D00 D01 D00 D00 D01 D00 D10 D11 D10D10D11 D10 D11 D10D11 D11 D20 D21 D20 D21 D20 D21 D21 D30 D31 D30 D31 D30 D31 D30 D31 D11 D10 D20 Note The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 417 of 1817 Sep 19, 2011 Figure 8-27. Software Processing Flow in PWM Output Mode (2/2) START <1> Count operation start flow TABnCE bit = 1 Register initial setting TABnCTL0 register (TABnCKS0 to TABnCKS2 bits), TABnCTL1 register, TABnIOC0 register, TABnIOC2 register, TABnCCR0 to TABnCCR3 registers The initial setting of these registers is performed before setting the TABnCE bit to 1. Writing the TABnCCR1 register must be performed only when the set duty factor is changed after writing the TABnCCR2 and TABnCCR3 registers. When the counter is cleared after setting, the value of the TABnCCRm register is transferred to the CCRm buffer register. Writing the same value to the TABnCCR1 register is necessary only when the set duty factor of TOABn2 and TOABn3 pin outputs is changed. When the counter is cleared after setting, the value of the TABnCCRm register is transferred to the CCRm buffer register. The TABnCCR1 register only needs to be written, only when the set duty factor is changed. When the counter is cleared after setting, the value of the TABnCCRm register is transferred to the CCRm buffer register. Counting is stopped. The TABnCKS0 to TABnCKS2 bits can be set at the same time when counting is enabled (TABnCE bit = 1). Writing the TABnCCR1 register must be performed after writing the TABnCCR0, TABnCCR2, and TABnCCR3 registers. When the counter is cleared after setting, the value of the TABnCCRm register is transferred to the CCRm buffer registers. Writing the same value to TABnCCR1 is necessary only when the set cycle is changed. <2> TABnCCR0 to TABnCCR3 register setting change flow <3> TABnCCR0 register setting change flow <4> TABnCCR1 to TABnCCR3 register setting change flow <5> TABnCCR2, TABnCCR3 register setting change flow <6> TABnCCR1 register setting change flow <7> Count operation stop flow TABnCE bit = 0 Setting of TABnCCR2, TABnCCR3 registers Setting of TABnCCR1 register Setting of TABnCCR2, TABnCCR3 registers Setting of TABnCCR1 register STOP Setting of TABnCCR1 register Setting of TABnCCR0 register Setting of TABnCCR1 register Setting of TABnCCR0, TABnCCR2, and TABnCCR3 registers Setting of TABnCCR1 register When the counter is cleared after setting, the value of the TABnCCRm register is transferred to the CCRm buffer register. Remark k = 1 to 3, m = 0 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 418 of 1817 Sep 19, 2011 (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TABnCCR1 register last. Rewrite the TABnCCRk register after writing the TABnCCR1 register after the INTTABnCC1 signal is detected. FFFFH 16-bit counter 0000H TABnCE bit D30 D00 D01 D30 D30 D20 D20 D20 D21 D11 D00 D00 D31 D01 D01 D21 D11 D31 TABnCCR0 register CCR0 buffer register INTTABnCC0 signal TABnCCR1 register CCR1 buffer register INTTABnCC1 signal TOABn1 pin output TABnCCR2 register CCR2 buffer register INTTABnCC2 signal TOABn2 pin output TABnCCR3 register CCR3 buffer register INTTABnCC3 signal TOABn3 pin outputNote TOABn0 pin output D10 D10 D10 D00 D11 D10 D11 D10 D21 D20 D21 D20 D31 D30 D31 D30 D00 D01 Note The V850ES/JH3-E has the TOAB13 pin only and doesn’t have the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 419 of 1817 Sep 19, 2011 To transfer data from the TABnCCRm register to the CCRm buffer register, the TABnCCR1 register must be written. To change both the cycle and active leve l of the PWM waveform at this time, first set the cycle to the TABnCCR0 register, set the active level width to the TABnCCR2 and TABnCCR3 registers, and then set the active level width to the TABnCCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TABnCCR0 register, and then write the same value to the TABnCCR1 register. To change only the active level width (duty factor) of the PWM wave, first set the active level to the TABnCCR2 and TABnCCR3 registers, and then set the active level to the TABnCCR1 register. To change only the active level width (duty factor) of the PWM waveform output by the TOABn1 pin, only the TABnCCR1 register has to be set. To change only the active level width (duty factor) of the PWM waveform output by the TOABn2 and TOABn3 pins, first set the active level width to the TABnCCR2 and TABnCCR3 registers, and then write the same value to the TABnCCR1 register. After the TABnCCR1 register is written, the value written to the TABnCCRm register is transferred to the CCRm buffer register in synchronization with the timing of clea ring the 16-bit counter, and is used as the value to be compared with the value of the 16-bit counter. To write the TABnCCR0 to TABnCCR3 registers again afte r writing the TABnCCR1 register once, do so after the INTTABnCC0 signal is generated. Otherwise, t he value of the CCRm buffer register may become undefined because the timing of transferring data from the TABnCCRm register to the CCRm buffer register conflicts with writing the TABnCCRm register. Remark m = 0 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 420 of 1817 Sep 19, 2011 (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TABnCCRk register to 0000H. If the set value of the TABnCCR0 register is FFFFH, the INTTABnCCk signal is generated periodically. Count clock 16-bit counter TABnCE bit TABnCCR0 register TABnCCRk register INTTABnCC0 signal INTTABnCCk signal TOABnk pin output 0000H 0000H 0000H D0 − 1D 00000FFFF 0000 D 0 − 1D 0 00000001 L Remark k = 1 to 3, n = 0, 1 To output a 100% waveform, set a value of “set value of TABnCCR0 register + 1” to the TABnCCRk register. If the set value of the TABnCCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter TABnCE bit TABnCCR0 register TABnCCRk register INTTABnCC0 signal INTTABnCCk signal TOABnk pin output D0 + 1 D0 + 1 D0 + 1 D0 − 1D 00000FFFF 0000 D 0 − 1D 0 00000001 Remark k = 1 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 421 of 1817 Sep 19, 2011 (c) Generation timing of compare match interrupt request signal (INTTABnCCk) The timing of generation of the INTTABnCCk signal in the PWM output mode differs from the timing of other INTTABnCCk signals; the INTTABnCCk signal is generated when the count value of the 16-bit counter matches the value of the TABnCCRk register. Count clock 16-bit counter CCRk buffer register TOABnk pin output INTTABnCCk signal Dk Dk − 2D k − 1D k Dk + 1 D k + 2 Remark k = 1 to 3, n = 0, 1 Usually, the INTTABnCCk signal is generated in synchronization with the next counting up after the count value of the 16-bit counter matches the value of the TABnCCRk register. In the PWM output mode, however, it is generated one cl ock earlier. This is because the timing is changed to match the change timing of the output signal of the TOABnk pin.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 422 of 1817 Sep 19, 2011

8.5.6 Free-running timer mode (TABnMD2 to TABnMD0 bits = 101)

In the free-running timer mode, TABn starts counting when t he TABnCTL0.TABnCE bit is set to 1. At this time, the TABnCCRm register can be used as a co mpare register or a capture regist er, according to the setting of the TABnOPT0.TABnCCS0 and TABnOPT0.TABnCCS1 bits. Remark m = 0 to 3, n = 0, 1 Figure 8-28. Configuration in Free-Running Timer Mode TOABn3 pin outputNote 2 TOABn2 pin output TOABn1 pin output TOABn0 pin output INTTABnOV signal TABnCCS0, TABnCCS1 bits (capture/compare selection) INTTABnCC3 signal INTTABnCC2 signal INTTABnCC1 signal INTTABnCC0 signal TIABn3 pinNote 2 (capture trigger input) TABnCCR3Note 2 register (capture) TIAB00 pin (external event count inputNote 1/ capture trigger input) Internal count clock TABnCE bit TIABn1 pin (capture trigger input) TIABn2 pin (capture trigger input) TABnCCR0 register (capture) TABnCCR1 register (capture) TABnCCR2 register (capture) TABnCCR3 register (compare) TABnCCR2 register (compare) TABnCCR1 register (compare) 16-bit counter TABnCCR0 register (compare) Output controller Output controller Output controller Output controller Count clock selectionEdge detector Edge detector Edge detector Edge detector Edge detector Notes 1. TAB1: EVTAB1 pin 2. The TIAB03 and TOAB03 pins are not prov ided in the V850ES/JH3-E, and the TAB0CCR3 register cannot be used as a capture register when using the V850ES/JH3-E.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 423 of 1817 Sep 19, 2011 When the TABnCE bit is set to 1, TABn starts counting, and the output signals of t he TOABn0 to TOABn3 pins are inverted. When the count value of the 16-bit counter subs equently matches the set value of the TABnCCRm register, a compare match interrupt request signal (INTTABnCCm) is generated, and the output signal of the TOABnm pin is inverted. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTABnOV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TABnOPT0.TABnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. The TABnCCRm register can be rewritten while the counter is operating. If it is re written, the new value is reflected at that time, and compared with the count value. Remark m = 0 to 3, n = 0, 1 Figure 8-29. Basic Timing in Free-Running Timer Mode (Compare Function) D10 D20 D30 D00 D20 D31 D31 D30 D00 D11D11 D21 D01 D11 D21 D01 Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction FFFFH 16-bit counter 0000H TOABn1 pin output TABnCCR2 register INTTABnCC2 signal TOABn2 pin output TABnCCR3 register INTTABnCC3 signal TOABn3 pin outputNote INTTABnOV signal TABnOVF bit TOABn0 pin output TABnCCR1 register INTTABnCC1 signal TABnCE bit TABnCCR0 register INTTABnCC0 signal D00 D01 D11D10 D21D20 D31D30 Note The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 424 of 1817 Sep 19, 2011 When the TABnCE bit is set to 1, the 16 -bit counter starts counting. When t he valid edge input to the TIABnm pin is detected, the count value of the 16-bit counter is stor ed in the TABnCCRm register, and a capture interrupt request signal (INTTABnCCm) is generated. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTABnOV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TABnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. Remark m = 0 to 3, n = 0, 1 Figure 8-30. Basic Timing in Free-Running Timer Mode (Capture Function) D20 D00 D30 D10 D11 D21 D31 D12D01 D02 D22 D32 D03 D13 D33 D23

0000 D 00 D01 D02 D03

0000 D 10 D11 D12 D13

0000 D 20 D21 D23D22

0000 D 30 D31 D32 D33

Note The V850ES/JH3-E only includes the TIAB13 pin; it is not provided with the TIAB03 pin. When using the V850ES/JH3-E, the TAB0CCR3 register and the INTTAB0CCR3 signal cannot be used.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 425 of 1817 Sep 19, 2011 Figure 8-31. Register Setting in Free-Running Timer Mode (1/3) (a) TABn control register 0 (TABnCTL0) 0/1 0 0 0 0 TABnCTL0 Select count clockNote 0: Stop counting 1: Enable counting 0/1 0/1 0/1 TABnCKS2 TABnCKS1 TABnCKS0TABnCE Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1 (b) TABn control register 1 (TABnCTL1) 0 0 0/1 0 0 TABnCTL1 101 TABnMD2 TABnMD1 TABnMD0TABnEEETABnESTTABnSYE 1, 0, 1: Free-running mode 0: Operate with count clock selected by TABnCKS0 to TABnCKS2 bits 1: Count by external event count input signal (c) TABn I/O control register 0 (TABnIOC0) 0/1Note 0/1Note 0/1 0/1 0/1 TABnIOC0 0: Disable TOABn0 pin output 1: Enable TOABn0 pin output 0: Disable TOABn1 pin output 1: Enable TOABn1 pin output Setting of output level with operation of TOABn1 pin disabled 0: Low level 1: High level 0/1 0/1 0/1 TABnOE1 TABnOL0 TABnOE0TABnOL1TABnOE3 TABnOL2 TABnOE2TABnOL3 Setting of output level with operation of TOABn3 pin disabled 0: Low level 1: High level 0: Disable TOABn2 pin output 1: Enable TOABn2 pin output Setting of output level with operation of TOABn2 pin disabled 0: Low level 1: High level 0: Disable TOABn3 pin output 1: Enable TOABn3 pin output Setting of output level with operation of TOABn0 pin disabled 0: Low level 1: High level Note The TOAB03 pin is not provided in the V850ES/JH 3-E. Set the TAB0OL3 and TAB0OE3 bits to 0. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 426 of 1817 Sep 19, 2011 Figure 8-31. Register Setting in Free-Running Timer Mode (2/3) (d) TABn I/O control register 1 (TABnIOC1) 0/1 0/1 0/1 0/1 0/1 TABnIOC1 Select valid edge of TIABn0 pin input Select valid edge of TIABn1 pin input 0/1 0/1 0/1 TABnIS2 TABnIS1 TABnIS0TABnIS3TABnIS6Note TABnIS5 TABnIS4TABnIS7Note Select valid edge of TIABn2 pin input Select valid edge of TIABn3 pin input Note The TIAB03 pin is not provided in the V850ES/JH 3-E. Set the TAB0IS7 and TAB0IS6 bits to 0. (e) TABn I/O control register 2 (TABnIOC2) 0 0 0 0 0/1 TABnIOC2 Select valid edge of external event count input 0/1 0 0 TABnEES0 TABnETS1 TABnETS0TABnEES1 (f) TABn option register 0 (TABnOPT0) 0/1Note 0/1Note 0/1 0/1 0 TABnOPT0 Overflow flag Specifies if TABnCCR0 register functions as capture or compare register Specifies if TABnCCR1 register functions as capture or compare register 0 0 0/1 TABnCCS0 TABnOVFTABnCCS1TABnCCS2TABnCCS3 Specifies if TABnCCR2 register functions as capture or compare register Specifies if TABnCCR3 register functions as capture or compare register Note The TAB0CCR3 register cannot be used as a capture register in the V850ES/JH3-E, so set bits TAB0CCS3 and TAB0CCS2 to 0. (g) TABn counter read buffer register (TABnCNT) The value of the 16-bit counter can be read by reading the TABnCNT register. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 427 of 1817 Sep 19, 2011 Figure 8-31. Register Setting in Free-Running Timer Mode (3/3) (h) TABn capture/compare register s 0 to 3 (TABnCCR0 to TABnCCR3) These registers function as captur e registers or compare registers according to the setting of the TABnOPT0.TABnCCSm bit. When the registers function as capture registers, they store the c ount value of the 16-bit counter when the valid edge input to the TIABnm pin is detected. When the registers function as compare registers and when D m is set to the TABnCCRm register, the INTTABnCCm signal is generated when the counter reaches (D m + 1), and the output signal of the TOABnm pin is inverted. Remark m = 0 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 428 of 1817 Sep 19, 2011 (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 8-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) D10 D20 D30 D00 D10 D20 D30 D00 D11 D31 D01 D21 D21 D11 D11 D31 D01 FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register INTTABnCC0 signal TOABn0 pin output TABnCCR1 register INTTABnCC1 signal TOABn1 pin output TABnCCR2 register INTTABnCC2 signal TOABn2 pin output TABnCCR3 register INTTABnCC3 signal TOABn3 pin outputNote INTTABnOV signal TABnOVF bit D00 D10 D20 D30 D01 D11 D21 D31 Cleared to 0 by CLR instruction Set value changed Set value changed Set value changed Set value changed Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction <3><1> Note The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 429 of 1817 Sep 19, 2011 Figure 8-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) TABnCE bit = 1 Read TABnOPT0 register (check overflow flag). Register initial setting TABnCTL0 register (TABnCKS0 to TABnCKS2 bits), TABnCTL1 register, TABnIOC0 register, TABnIOC2 register, TABnOPT0 register, TABnCCR0 to TABnCCR3 registers The initial setting of these registers is performed before setting the TABnCE bit to 1. The TABnCKS0 to TABnCKS2 bits can be set at the same time when counting has been started (TABnCE bit = 1). START Execute instruction to clear TABnOVF bit (CLR TABnOVF). <1> Count operation start flow <2> Overflow flag clear flow TABnCE bit = 0 The counter is initialized and counting is stopped by clearing the TABnCE bit to 0. STOP <3> Count operation stop flow TABnOVF bit = 1 NO YES Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 430 of 1817 Sep 19, 2011 (b) When using capture/compare register as capture register Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) D20 D00 D30 D10 D11 D21 D31 D12D01 D02 D22 D32 D03 D13 D33 D23

0000 D 00 D01 D02 D03 0000

<3><1> FFFFH 16-bit counter 0000H TABnCE bit TIABn2 pin input TABnCCR2 register INTTABnCC2 signal TIABn3 pin inputNote TABnCCR3 registerNote INTTABnCC3 signalNote INTTABnOV signal TABnOVF bit TIABn1 pin input TABnCCR1 register INTTABnCC1 signal TIABn0 pin input TABnCCR0 register INTTABnCC0 signal Note The V850ES/JH3-E only includes the TIAB13 pin; it is not provided with the TIAB03 pin. When using the V850ES/JH3-E, the TAB0CCR3 register and the INTTAB0CCR3 signal cannot be used. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 431 of 1817 Sep 19, 2011 Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) TABnCE bit = 1 Read TABnOPT0 register (check overflow flag). Register initial setting TABnCTL0 register (TABnCKS0 to TABnCKS2 bits), TABnCTL1 register, TABnIOC1 register, TABnOPT0 register The initial setting of these registers is performed before setting the TABnCE bit to 1. The TABnCKS0 to TABnCKS2 bits can be set at the same time when counting has been started (TABnCE bit = 1). START Execute instruction to clear TABnOVF bit (CLR TABnOVF). <1> Count operation start flow <2> Overflow flag clear flow TABnCE bit = 0 The counter is initialized and counting is stopped by clearing the TABnCE bit to 0. STOP <3> Count operation stop flow TABnOVF bit = 1 NO YES Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 432 of 1817 Sep 19, 2011 (2) Operation timing in free-running timer mode (a) Interval operation with compare register When TABn is used as an interval timer with the T ABnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTABnCCm signal has been detected. D00 D10 D20 D01 D30 D12 D03 D22 D31 D21 D23D02 D13FFFFH 16-bit counter 0000H TABnCE bit TABnCCR0 register INTTABnCC0 signal TOABn0 pin output TABnCCR1 register INTTABnCC1 signal TOABn1 pin output TABnCCR2 register INTTABnCC2 signal TOABn2 pin output TABnCCR3 register INTTABnCC3 signal TOABn3 pin outputNote Interval period (D00 + 1) Interval period (10000H + D02 − D01) Interval period (D01 − D00) Interval period (D03 − D02) Interval period (D04 − D03) D00 D01 D02 D03 D04 D05 Interval period (D10 + 1) Interval period (10000H + D12 − D11) Interval period (D11 − D10) Interval period (D13 − D12) D10 D11 D12 D13 D14 Interval period (D20 + 1) Interval period (10000H + D21 − D20) Interval period (10000H + D23 − D22) Interval period (D22 − D21) Interval period (D30 + 1) Interval period (10000H + D31 − D30) D20 D21 D22 D23 D31D30 D32 D04D11 Note The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 433 of 1817 Sep 19, 2011 When performing an interval operation in the free-running timer mode, four intervals can be set with one channel. To perform the interval operation, the value of the corresponding TABnCCRm register must be re-set in the interrupt servicing that is executed when the INTTABnCCm signal is detected. The set value for re-setting the TABnCCRm register can be calculated by the following expression, where “Dm” is the interval period. Compare register default value: Dm − 1 Value set to compare register second and subsequent times: Previous set value + Dm (If the calculation resu lt is greater than FFFFH, subtract 10000H fr om the result and set this value to the register.) Remark m = 0 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 434 of 1817 Sep 19, 2011 (b) Pulse width measurement with capture register When pulse width measurement is performed with the TABnCCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTABnCCm signal has been detected and for calculating an interval. D20 D00 D30 D10 D11 D21 D31 D12D01 D02 D32 D13 D03 D22 D33 D23 0000 Pulse interval (10000H + D01 − D00) Pulse interval (10000H + D02 − D01) Pulse interval (10000H + D03 − D02) D00 D01 D02 D03 Pulse interval (D00 + 1) 0000 Pulse interval (10000H + D11 − D10) Pulse interval (10000H + D12 − D11) Pulse interval (D13 − D12) D10 D11 D12 D13 Pulse interval (D10 + 1) 0000 Pulse interval (10000H + D21 − D20) Pulse interval (20000H + D22 − D21) Pulse interval (D23 − D22) D20 D21 D23D22 Pulse interval (D20 + 1) 0000 Pulse interval (10000H + D31 − D30) Pulse interval (10000H + D32 − D31) Pulse interval (10000H + D33 − D32) D30 D31 D32 D33 Pulse interval (D30 + 1) Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction FFFFH 16-bit counter 0000H TABnCE bit TIABn0 pin input TABnCCR0 register INTTABnCC0 signal TIABn2 pin input TABnCCR2 register INTTABnCC2 signal TIABn3 pin inputNote TABnCCR3 registerNote INTTABnCC3 signalNote INTTABnOV signal TABnOVF bit TIABn1 pin input TABnCCR1 register INTTABnCC1 signal Note The V850ES/JH3-E only includes the TIAB13 pin; it is not provided with the TIAB03 pin. When using the V850ES/JH3-E, the TAB0CCR3 regist er and the INTTAB0CCR3 signal cannot be used. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 435 of 1817 Sep 19, 2011 When executing pulse width measurement in the free-running timer mode, four pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TABnCCRm register in synchronization with the INTTABnCCm signal, and calculat ing the difference between the value read this time and the previously read value. Remark m = 0 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 436 of 1817 Sep 19, 2011 (c) Processing of overflow when two or more capture registers are used Care must be exercised in processing the overflow flag when two or more capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two or more capture registers are used FFFFH 16-bit counter 0000H TABnCE bit TIABn0 pin input TABnCCR0 register TIABn1 pin input TABnCCR1 register INTTABnOV signal TABnOVF bit D00 D01 D10 D11 D10 D00 D11 D01 The following problem may occur when two pulse widths are measured in the free-running timer mode. <1> Read the TABnCCR0 register (setting of t he default value of the TIABn0 pin input). <2> Read the TABnCCR1 register (setting of t he default value of the TIABn1 pin input). <3> Read the TABnCCR0 register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 − D00). <4> Read the TABnCCR1 register. Read the overflow flag. Because the flag is cleared in <3>, 0 is read. Because the overflow flag is 0, the pulse width can be calculated by (D 11 − D10) (incorrect). Remark n = 0, 1 When two or more capture registers ar e used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. Use software when using two or more capture registers. An example of how to use software is shown below.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 437 of 1817 Sep 19, 2011 (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TABnCE bit INTTABnOV signal TABnOVF bit TABnOVF0 flagNote TIABn0 pin input TABnCCR0 register TABnOVF1 flagNote TIABn1 pin input TABnCCR1 register D10 D11 D00 D01 D10 D00 D11 D01 Note The TABnOVF0 and TABnOVF1 flags are set in the internal RAM by software. <1> Read the TABnCCR0 register (setting of the default value of the TIABn0 pin input). <2> Read the TABnCCR1 register (setting of the default value of the TIABn1 pin input). <3> An overflow occurs. Set the TABnOVF0 and TABnOVF1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> Read the TABnCCR0 register. Read the TABnOVF0 flag. If the TABnOVF0 flag is 1, clear it to 0. Because the TABnOVF0 flag is 1, the pulse width can be calculated by (10000H + D 01 − D00). <5> Read the TABnCCR1 register. Read the TABnOVF1 flag. If the TABnOVF1 flag is 1, clear it to 0 (the TABnOVF0 flag is cleared in <4>, and the TABnOVF1 flag remains 1). Because the TABnOVF1 flag is 1, the pul se width can be calculated by (10000H + D 11 − D 10) (correct). <6> Same as <3>

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 438 of 1817 Sep 19, 2011 (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TABnCE bit INTTABnOV signal TABnOVF bit TABnOVF0 flagNote TIABn0 pin input TABnCCR0 register TABnOVF1 flagNote TIABn1 pin input TABnCCR1 register D10 D11 D00 D01 D10 D00 D11 D01 Note The TABnOVF0 and TABnOVF1 flags are set in the internal RAM by software. <1> Read the TABnCCR0 register (setting of t he default value of the TIABn0 pin input). <2> Read the TABnCCR1 register (setting of t he default value of the TIABn1 pin input). <3> An overflow occurs. Nothing is done by software. <4> Read the TABnCCR0 register. Read the overflow flag. If the overflow flag is 1, set only the TABnOVF1 flag to 1, and clear the overflow flag to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 − D00). <5> Read the TABnCCR1 register. Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read. Read the TABnOVF1 flag. If the TABnOVF1 flag is 1, clear it to 0. Because the TABnOVF1 flag is 1, the pul se width can be calculated by (10000H + D 11 − D 10) (correct). <6> Same as <3>

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 439 of 1817 Sep 19, 2011 (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below. Example of incorrect processing when capture trigger interval is long FFFFH 16-bit counter 0000H TABnCE bit TIABnm pin input TABnCCRm register INTTABnOV signal TABnOVF bit Dm0 Dm1 Dm0 Dm1 1 cycle of 16-bit counter Pulse width The following problem may occur when a long pulse width is measured in the free-running timer mode. <1> Read the TABnCCRm register (setting of t he default value of the TIABnm pin input). <2> An overflow occurs. Nothing is done by software. <3> An overflow occurs a second time. Nothing is done by software. <4> Read the TABnCCRm register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pul se width can be calculated by (10000H + D m1 − D m0) (incorrect). Actually, the pulse width must be (20000H + D m1 − Dm0) because an overflow occurs twice. Remark m = 0 to 3, n = 0, 1 If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. An example of how to use software is shown next.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 440 of 1817 Sep 19, 2011 Example when capture trigger interval is long FFFFH 16-bit counter 0000H TABnCE bit TIABnm pin input TABnCCRm register INTTABnOV signal TABnOVF bit Overflow counterNote Dm0 Dm1 1H0H 2H 0H Dm0 Dm1 1 cycle of 16-bit counter Pulse width Note The overflow counter is set arbitrarily by software in the internal RAM. <1> Read the TABnCCRm register (setting of t he default value of the TIABnm pin input). <2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> Read the TABnCCRm register. Read the overflow counter. When the overflow counter is “N”, the pulse width can be calculated by (N × 10000H + Dm1 – Dm0). In this example, the pulse width is (20000H + D m1 – Dm0) because an overflow occurs twice. Clear the overflow counter (0H). Remark m = 0 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 441 of 1817 Sep 19, 2011 (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the T ABnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TABnOPT0 register. To accurately detect an overflow, read the TABnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) Operation to write 0 (without conflict with setting) (iii) Operation to clear to 0 (without conflict with setting) (ii) Operation to write 0 (conflict with setting) (iv) Operation to clear to 0 (conflict with setting) 0 write signal Overflow set signal Register access signal Overflow flag (TABnOVF bit) Read Write 0 write signal Overflow set signal Register access signal Overflow flag (TABnOVF bit) Read Write 0 write signal Overflow set signal 0 write signal Overflow set signal Overflow flag (TABnOVF bit) Overflow flag (TABnOVF bit) L H L Remark n = 0, 1 To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set overflow information may be erased by writing 0 ((ii) in the above chart). Ther efore, software may judge that no overflow has occurred even when an overflow actually has occurred. If execution of the CLR instruction conf licts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the CLR instruction.

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8.5.7 Pulse width measurement mode (TABnMD2 to TABnMD0 bits = 110)

In the pulse width measurement mode, TA Bn starts counting when the TABnCTL0.TABnCE bit is set to 1. Each time the valid edge input to the TIABnm pi n has been detected, the count value of the 16-bit counter is stored in the TABnCCRm register, and the 16-bit counter is cleared to 0000H. The interval of the valid edge can be m easured by reading the TABnCCRm regist er after a capture interrupt request signal (INTTABnCCm) occurs. Select one of the TIABn0 to TIABn3 pins as the capture trigger input pin. S pecify “No edge detected” for the unused pins by using the TABnIOC1 register. When an external clock is used as the count clock, measur e the pulse width of the TIAB0k pin because the external clock is fixed to the TIAB00 pin. At this time, clear t he TAB0IOC1.TAB0IS1 and TAB0IOC1.TAB0IS0 bits to 00 (capture trigger input (TIAB00 pin): No edge detected). For TAB1, the external clock is input from the EVTAB1 pi n, and the pulse width can be measured by using the TIAB10 to TIAB13 pins. Remark m = 0 to 3, n = 0, 1 k = 1 to 3 Figure 8-34. Configuration in Pulse Width Measurement Mode INTTABnOV signal INTTABnCC0 signal INTTABnCC1 signal INTTABnCC2 signal INTTABnCC3 signalNote 2 TIABn3 pinNote 2 (capture trigger input) TABnCCR3Note 2 register (capture) TIAB00 pin (external event count inputNote 1/ capture trigger input) Internal count clock TABnCE bit TIABn1 pin (capture trigger input) TIABn2 pin (capture trigger input) TABnCCR0 register (capture) TABnCCR1 register (capture) TABnCCR2 register (capture) 16-bit counter ClearEdge detector Edge detector Edge detector Edge detector Edge detector Count clock selection Notes 1. TAB1: EVTAB1 pin 2. The V850ES/JH3-E only includes the TIAB13 pin; it is not provided with the TIAB03 pin. When using the V850ES/JH3-E, the TAB0CCR3 regi ster and the INTTAB0CCR3 signal cannot be used. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 443 of 1817 Sep 19, 2011 Figure 8-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TABnCE bit TIABnm pin input TABnCCRm register INTTABnCCm signal INTTABnOV signal TABnOVF bit D00000H D 1 D2 D3 Cleared to 0 by CLR instruction Remark m = 0 to 3, n = 0, 1 When the TABnCE bit is set to 1, the 16 -bit counter starts counting. When t he valid edge input to the TIABnm pin is later detected, the count value of the 16 -bit counter is stored in the TABnCCRm re gister, the 16-bit counter is cleared to 0000H, and a capture interrupt request signal (INTTABnCCm) is generated. The pulse width is calculated as follows. Pulse width = Captured value × Count clock cycle If the valid edge is not input to the TIABnm pin even when the 16-bit counte r has counted up to FFFFH, an overflow interrupt request signal (INTTABnOV) is generated at the ne xt count clock, and the counter is cleared to 0000H and continues counting. At this time, the overflow flag (TABnOPT0.TABnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction via software. If the overflow flag is set to 1, the pulse width can be calculated as follows. Pulse width = (10000H × TABnOVF bit setting (1) count + Captured value) × Count clock cycle Remark m = 0 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 444 of 1817 Sep 19, 2011 Figure 8-36. Register Setting in Pulse Width Measurement Mode (1/2) (a) TABn control register 0 (TABnCTL0) 0/1 0 0 0 0 TABnCTL0 Select count clockNote 0: Stop counting 1: Enable counting 0/1 0/1 0/1 TABnCKS2 TABnCKS1 TABnCKS0TABnCE Note The setting is invalid when the TABnEEE bit = 1. (b) TABn control register 1 (TABnCTL1) 0 0 0/1 0 0 TABnCTL1 110 TABnMD2 TABnMD1 TABnMD0 1, 1, 0: Pulse width measurement mode TABnEEETABnEST 0: Operate on count clock selected by TABnCKS0 to TABnCKS2 bits 1: Count by external event count input signal (c) TABn I/O control register 1 (TABnIOC1) 0/1Note 0/1Note 0/1 0/1 0/1 TABnIOC1 Select valid edge of TIABn0 pin input Select valid edge of TIABn1 pin input 0/1 0/1 0/1 TABnIS2 TABnIS1 TABnIS0TABnIS3TABnIS6 TABnIS5 TABnIS4TABnIS7 Select valid edge of TIABn2 pin input Select valid edge of TIABn3 pin input Note The TIAB03 pin is not provided in the V850ES/JH3-E. Set the TAB0IS7 and TAB0IS6 bits to 0. (d) TABn I/O control register 2 (TABnIOC2) 0 0 0 0 0/1 TABnIOC2 0/1 0 0 TABnETS1 TABnETS0TABnEES0TABnEES1 Select valid edge of external event count input Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 445 of 1817 Sep 19, 2011 Figure 8-36. Register Setting in Pulse Width Measurement Mode (2/2) (e) TABn option register 0 (TABnOPT0) 0000 0 TABnOPT0 Overflow flag 0 0 0/1 TABnOVFTABnCCS0TABnCCS1TABnCCS2TABnCCS3 (f) TABn counter read buffer register (TABnCNT) The value of the 16-bit counter can be read by reading the TABnCNT register. (g) TABn capture/compare register s 0 to 3 (TABnCCR0 to TABnCCR3) These registers store the count value of the 16-bit counter when the valid edge input to the TIABnm pin is detected. Remarks 1. TABn I/O control register 0 (TABnIOC0) is not used in the pulse width measurement mode. 2. m = 0 to 3, n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 446 of 1817 Sep 19, 2011 (1) Operation flow in pul se width measurement mode Figure 8-37. Software Processing Flow in Pulse Width Measurement Mode <1> <2> Set TABnCTL0 register (TABnCE bit = 1) TABnCE bit = 0 Register initial setting TABnCTL0 register (TABnCKS0 to TABnCKS2 bits), TABnCTL1 register, TABnIOC1 register, TABnIOC2 register, TABnOPT0 register The initial setting of these registers is performed before setting the TABnCE bit to 1. The TABnCKS0 to TABnCKS2 bits can be set at the same time when counting has been started (TABnCE bit = 1). The counter is initialized and counting is stopped by clearing the TABnCE bit to 0. START STOP <1> Count operation start flow <2> Count operation stop flow FFFFH 16-bit counter 0000H TABnCE bit TIABn0 pin input TABnCCR0 register INTTABnCC0 signal D00000H 0000H D1 D2

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 447 of 1817 Sep 19, 2011 (2) Operation timing in pul se width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the T ABnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TABnOPT0 register. To accurately detect an overflow, read the TABnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) Operation to write 0 (without conflict with setting) (iii) Operation to clear to 0 (without conflict with setting) (ii) Operation to write 0 (conflict with setting) (iv) Operation to clear to 0 (conflict with setting) 0 write signal Overflow set signal Register access signal Overflow flag (TABnOVF bit) Read Write 0 write signal Overflow set signal Register access signal Overflow flag (TABnOVF bit) Read Write 0 write signal Overflow set signal 0 write signal Overflow set signal Overflow flag (TABnOVF bit) Overflow flag (TABnOVF bit) L H L Remark n = 0, 1 To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set overflow information may be erased by writing 0 ((ii) in the above chart). Ther efore, software may judge that no overflow has occurred even when an overflow actually has occurred. If execution of the CLR instruction conf licts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the CLR instruction.

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8.5.8 Triangular wave PWM mode (TABnMD2 to TABnMD0 bits = 111)

In the triangular wave PWM mode, TABn capture/compare register k (TABnCCRk) is used to set the duty factor, and TABn capture/compare register 0 (TABnCCR0) is used to set the cycle. By using these four registers and operating the timer, triangular wave PWM with a variable cycle is output. The value of the TABnCCRm register can be rewritten when TABnCE = 1. To stop timer AB, clear TABnCE to 0. The PWM waveform is output from the TOABnk pin. The TOABn0 pin produces a toggle output when the value of the 16- bit counter matches the value of the T ABnCCR0 register and when the counter underflows. Caution In the PWM mode, the capture function of the TABnCCRm register cannot be used because this register can be used only as a compare register. Remark n = 0, 1, m = 0 to 3, k = 1 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) R01UH0290EJ0300 Rev.3.00 Page 449 of 1817 Sep 19, 2011 Figure 8-38. Timing of Basic Operation in Triangular Wave PWM Mode (TABnOE0 = 1, TABnOE1 = 1, TABnOE2 = 1, TABnOE3 = 1, TABnOL0 = 0, TABnOL1 = 0, TABnOL2 = 0, TABnOL3 = 0) TABnCE = 1 FFFFH 16-bit counter TOABn0 TOABn1 INTTABnOV INTTABnCC0 match interrupt INTTABnCC1 match interrupt TABnCCR0 TOABn2 TOABn3Note INTTABnCC2 match interrupt INTTABnCC3 match interrupt 0000H D00 D00 D30 D30 D20 D20 D10 D10 TABnCCR1 0000H D10 TABnCCR2 0000H D20 TABnCCR3 0000H D 30 D00 D30 D30 D20 D20 D10 D00 D30 D30 D20 D20 Note The V850ES/JH3-E only includes the TOAB13 pin; it is not provided with the TOAB03 pin. Remark n = 0, 1

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8.5.9 Timer output operations

The following table shows the operations and output levels of the TOABn0 to TOABn3 pins. Table 8-6. Timer Output Control in Each Mode Operation Mode TOABn0 Pin TOABn1 Pin TOABn2 Pin TOABn3 Pin Interval timer mode Square wave output External event count mode Square wave output − External trigger pulse output mode External trigger pulse output External trigger pulse output External trigger pulse output One-shot pulse output mode One-shot pulse output One-shot pulse output One-shot pulse output PWM output mode Square wave output PWM output PWM output PWM output Free-running timer mode Square wave output (only when compare function is used) Pulse width measurement mode − Triangular wave PWM output mode Square wave output Triangular PWM output Triangular PWM output Triangular PWM output Table 8-7. Truth Table of TOABn0 to TOABn3 Pins Under Control of Timer Output Control Bits TABnIOC0.TABnOLm Bit TABnIOC0.TABnOEm Bit TABnCTL0.TABnCE Bit Level of TOABnm Pin 0 × Low-level output

1 Low level immediately before counting,

high level after counting is started 0 × High-level output

1 High level immediately before counting, low

level after counting is started Remark m = 0 to 3, n = 0, 1

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8.6 Timer-Tuned Operation Functi on/Simultaneous-Start Function

Timer AA and timer AB have a timer-tuned operation function/simultaneous-start function. The timers that can be synchronized are listed in Table 8-8. Table 8-8. Timer-Tuned Operation Mode Master Timer Slave Timer TAA1 TAA0 TAA3 TAA2 TAB0 TAA5 TAB1 TAB4 For details of the timer-tun ed operation function, see 7.6 Timer-Tuned Operation Function , and for details of the simultaneous-start function, see 7.7 Simultaneous-Start Function.

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8.7 Cautions

(1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH , not 0000H, may be captured in the TABnCCR0, TABnCCR1, TABnCCR2, and T ABnCCR3 registers if the capture trigger is input immediately after the TABnCE bit is set to 1. (a) Free-running timer mode Count clock 0000H FFFFH TABnCE bit TABnCCR0 register FFFFH 0001H0000H TIABn0 pin input Capture trigger input 16-bit counter Sampling clock (fXX) Capture trigger input (b) Pulse width measurement mode 0000H FFFFH FFFFH 0002H0000H Count clock TABnCE bit TABnCCR0 register TIABn0 pin input Capture trigger input 16-bit counter Sampling clock (fXX) Capture trigger input Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 453 of 1817 Sep 19, 2011 CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) Timer T (TMT) is a 16-bit timer/event counter. An encoder count function and other functions are added to timer AA (TAA). However, TMT does not have a function to operate with an external event count input when it operates in the interval timer mode. The V850ES/JH3-E and V850ES/JJ3-E have one TMT channel.

9.1 Overview

An overview of TMT0 is given below.

• Clock selection: 8 types
• Capture trigger input pins (TIT00, TIT01): 2
• Encoder input pins (TENC00 Note , TENC01): 2
• Encoder clear input pin (TECR0): 1
• External trigger input pin: 1
• External event count input pin: 1
• Timer counter: 1
• Capture/compare registers: 2
• Capture/compare match interrupt request signals: 2
• Timer output pins: 2 Note The TENC00 pin is also used for the capture trigger inpu t, external event count input, and external encoder input signals.

9.2 Functions

The functions of TMT0 are shown below.

• Interval timer
• External event counter
• External trigger pulse output
• One-shot pulse output
• PWM output
• Free-running timer
• Pulse width measurement
• Triangular-wave PWM output
• Encoder count

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9.3 Configuration

TMT0 includes the following hardware. Table 9-1. Configuration of TMT0 Item Configuration Registers 16-bit counter × 1 TMT0 capture/compare registers 0, 1 (TT0CCR0, TT0CCR1) TMT0 counter read buffer register (TT0CNT) TMT0 counter write register (TT0TCW) CCR0, CCR1 buffer registers TMT0 control registers 0, 1 (TT0CTL0, TT0CTL1) TMT0 control registers 2 (TT0CTL2) TMT0 I/O control registers 0 to 3 (TT0IOC0 to TT0IOC3) TMT0 option register 0 (TT0OPT0) TMT0 option register 1 (TT0OPT1) TMT noise elimination control register (TTNFC) Timer input • TIT00, TIT01 (capture trigger input pins)

• TENC00 Note (encoder 0 input pin)
• TENC01 (encoder 1 input pin)
• TENCR0 (encoder clear input pin) Timer output TOT00, TOT01 Note The TENC00 pin is also used for the capture trigger input, external event count input, and external encoder input signals.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 455 of 1817 Sep 19, 2011 Figure 9-1. Block Diagram of TMT0 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 TT0CNT TT0TCW TT0CCR0 TT0CCR1 INTTT0OV INTTT0CC0 TOT00 TOT01 INTTT0CC1 INTTT0EC TIT01 TIT00 TECR0 TENC00Note TENC01 fXX fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 Selector Internal bus Internal bus CCR1 buffer register 16-bit counter CCR0 buffer register Counter control Clear Selector Output controller Sampling clock Edge detection/ Noise eliminator Edge detection/ Noise eliminator Edge detection/ Noise eliminator Edge detection/ Noise eliminator Edge detection/ Noise eliminator Note The TENC00 pin is also used for the capture trigger input, external event count input, and external encoder input signals. Remark f XX: Peripheral clock

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 456 of 1817 Sep 19, 2011 (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TT0CNT register. When the TT0CTL0.TT0CE bit = 0, the valu e of the 16-bit counter is FFFFH. If t he TT0CNT register is read at this time, 0000H is read. Reset sets the TT0CE bit to 0. (2) CCR0 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TT0CCR0 register is used as a compare regi ster, the value written to the TT0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTTCC00) is generated. The CCR0 buffer register cannot be read or written directly. The CCR0 buffer register is set to 0000H after reset, and the TT0CCR0 register is set to 0000H. (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TT0CCR1 register is used as a compare regi ster, the value written to the TT0CCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTTCC01) is generated. The CCR1 buffer register cannot be read or written directly. The CCR1 buffer register is set to 0000H after reset, and the TT0CCR1 register is set to 0000H. (4) Edge detector This circuit detects the valid edges input to the TIT00, TIT01, TENC00, TENC01, and TECR0 pins. No edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the TT0IOC1, TT0IOC2, and TT0IOC3 registers. (5) Output controller This circuit controls the output of the TOT00 and TOT01 pins via the TT0IOC0 register. (6) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock. (7) Counter control The count operation is controlled by the timer mode selected by the TT0CTL1 register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 457 of 1817 Sep 19, 2011

9.3.1 Pin configuration

The timer inputs and outputs that configure TMT0 are shared with the followi ng ports. The port functions must be set when using each pin (see Table 4-18 Using Port Pin as Alternate-Function Pin). Table 9-2. Pin Configuration Port Timer Input Pin Timer Ou tput Other Alternate Function P96 TIT00 (capture trigger input 0) TE CR0 (encoder clear input) TOT00 KR6/A6 P97 TIT01 (capture trigger input 1) TENC00 Note (encoder input) TOT01 KR7/A7 P98 − TENC01 (encoder input) − INTP17/A8 Note The TENC00 pin is also used for the capture trigger i nput, external event count input, and external encoder input signals. Set each signal for use by using the TT0IOC2 and TT0IOC3 registers after setting the corresponding port.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 458 of 1817 Sep 19, 2011

9.4 Registers

(1) TMT0 control register 0 (TT0CTL0) The TT0CTL0 register is an 8-bit register that controls the operation of TMT0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TT0CTL0 register by software. TT0CE TMT0 operation disabled (TMT0 reset asynchronouslyNote) TMT0 operation enabled. TMT0 operation start TT0CE TMT0 operation control TT0CTL0 0 0 0 0 TT0CKS2 TT0CKS1 TT0CKS0 65 43 21 After reset: 00H R/W Address: FFFF600H <7> 0 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 TT0CKS2 Internal count clock selection TT0CKS1 TT0CKS0 Note The TT0OPT0.TT0OVF bit and 16-bit counter are reset simultaneously. Moreover, timer outputs (TOT00 and TOT01) are reset at the same time as the 16-bit counter. Cautions 1. Set the TT0CKS2 to TT0CKS0 bits when the TT0CE bit = 0. When the value of the TT0CE bit is changed from 0 to 1, the TT0CKS2 to TT0CKS0 bits can be set simultaneously. 2. Be sure to set bits 3 to 6 to “0”. Remark f XX: Peripheral clock

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 459 of 1817 Sep 19, 2011 (2) TMT0 control register 1 (TT0CTL1) The TT0CTL1 register is an 8-bit register that controls the TMT0 operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) 0TT0CTL1 TT0EST TT0EEE 0 TT0MD3 TT0MD2 TT0MD1 TT0MD0 65 43 21 After reset: 00H R/W Address: FFFFF601H 7 0 TT0EST Software trigger control Generates a valid signal for external trigger input.

• In one-shot pulse output mode: A one-shot pulse is output with writing 1 to the TT0EST bit as the trigger.
• In external trigger pulse output mode: A PWM waveform is output with writing 1 to the TT0EST bit as the trigger.Disables operation with external event count input (TENC00 pin). (Performs counting with the count clock selected by the TT0CTL0.TT0CKS0 to TT0CTL0.TT0CKS2 bits.) TT0EEE Count clock selection The TT0EEE bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. Enables operation with external event count input (TENC00 pin). (Performs counting at every valid edge of the external event count input signal (TENC00 pin).) −The read value of the TT0EST bit is always 0. Interval timer mode External event count mode External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode Triangular-wave PWM output mode Encoder compare mode Setting prohibited Timer mode selection TT0MD3 Other than above TT0MD2 TT0MD1 TT0MD0

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 460 of 1817 Sep 19, 2011 (2/2) Cautions 1. The TT0EST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored. 2. The TT0EEE bit is valid only in the interval timer mode, external trigger pulse output mode, one-shot pulse output mode, PWM output mode , free-running timer mode, pulse width measurement mode, or triangular-wave PWM output mode. In any other mode, writing 1 to this bit is ignored. 3. External event count input (TENC00) or encoder inputs (TENC00, TENC01) is selected in the external event count mode or encoder co mpare mode regardless of the value of the TT0EEE bit. 4. Set the TT0EEE and TT0MD3 to TT0MD0 bits wh en the TT0CTL0.TT0CE bit = 0. (The same value can be written when the TT0CE bit = 1.) The operation is not guaranteed when rewriting is performed with the TT0CE bit = 1. If rewriting was mistakenly performed, clear the TT0CE bit to 0 and then set the bits again. 5. Be sure to set bits 4 and 7 to “0”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 461 of 1817 Sep 19, 2011 (3) TMT0 control register 2 (TT0CTL2) The TT0CTL2 register is an 8-bit register that controls the encoder count function operation. The TT0CTL2 register is valid only in the encoder compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution For details of each bit of th e TT0CTL2 register, see 9.6.9 (5) Controlling bits of TT0CTL2 register. (1/2) TT0ECCTT0CTL2 0 0 TT0LDE TT0ECM1 TT0ECM0 TT0UDS1 TT0UDS0 65 43 21 Disables transfer of set value of TT0CCR0 to 16-bit counter in case of underflow. Enables transfer of set value of TT0CCR0 to 16-bit counter in case of underflow. TT0LDE Transfer setting to 16-bit counter After reset: 00H R/W Address: FFFFF602H The 16-bit counter is not cleared to 0000H when its count value matches value of CCR1 register. The 16-bit counter is cleared to 0000H when the count after a match between the 16-bit counter count value and CCR1 register value is a down-count TT0ECM1 Control of encoder clear operation 1 The 16-bit counter is not cleared to 0000H when its count value matches value of CCR0 register. The 16-bit counter is cleared to 0000H when the count after a match between the 16-bit counter count value and CCR0 register value is an up-count TT0ECM0 Control of encoder clear operation 0 Normal operation Holds count value of 16-bit counter when TT0CTL0.TT0CE bit = 0. TT0ECC Encoder counter control

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 462 of 1817 Sep 19, 2011 (2/2) When valid edge of TENC00 input is detected Counts down when TENC01 = high level. Counts up when TENC01 = low level. Counts up when valid edge of TENC00 input is detected. Counts down when valid edge of TENC01 input is detected. Counts down when rising edge of TENC00 input is detected. Counts up when falling edge of TENC00 input is detected. However, count operation is performed only when TENC01 = low level. Both rising and falling edges of TENC00 and TENC01 are detected. Count operation is automatically identified by combination of edge detection and level detection. TT0UDS1 Up/down count selectionTT0UDS0 Cautions 1. The TT0ECC bit is valid only in the encoder compare mode. In any other mode, writing “1” to this bit is ignored. If the TT0CTL0.TT0CE bit is cleared to 0 while the TT0ECC bit = 1, the values of the timer/counter and capture registers (TT0CCR0 and TT0CCR1), and the TT0OPT1, TT0EUF, TT0EOF, and TT0ESF flags are retained. If the TT0CE bit is set from 0 to 1 when the TT0ECC bit = 1, the value of the TT0TCW register is not transferred to the 16-bit counter. 2. The TT0LDE bit is valid only when the TT0ECM1 and TT0ECM0 bits = 00, 01. Writing “1” to this bit is ignored when the TT0ECM1 and TT0ECM0 bits = 10, 11. 3. The edge detection of the TENC 00 and TENC01 inputs specified by the TT0IOC3.TT0EIS1 and TT0IOC3. TT0EIS0 bits is invalid and fixed to both the rising and falling edges when the TT0UDS1 and TT0UDS0 bits = 10, 11. 4. Set the TT0LDE, TT0ECM1, TT0ECM0 , TT0UDS1, and TT0UDS0 bits when the TT0CTL0.TT0CE bit = 0 (the same va lue can be written to these bits when the TT0CE bit = 1). If the valu e of these bits is changed when the TT0CE bit = 1, the operation cannot be guaranteed. If it is changed by mistake, clear the TT0CE bit and then set the correct value. 5. Be sure to set bits 5 and 6 to “0”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 463 of 1817 Sep 19, 2011 (4) TMT0 I/O control register 0 (TT0IOC0) The TT0IOC0 register is an 8-bit register that controls the timer output (TOT00, TOT01 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 464 of 1817 Sep 19, 2011 TT0OL1 TOT01 pin output level settingNote TOT01 pin starts output at high level. TOT01 pin starts output at low level. TT0IOC0 0 0 0 TT0OL1 TT0OE1 TT0OL0 TT0OE0 65 43 < 2 > 1TT0OE1 TOT01 pin output setting Timer output prohibited

• Low level is output from the TOT01 pin when the TT0OL1 bit = 0.
• High level is output from the TOT01 pin when the TT0OL1 bit = 1. Timer output enabled (A pulse is output from the TOT01 pin.) TT0OL0 TOT00 pin output level settingNote TOT00 pin starts output at high level. TOT00 pin starts output at low level. TT0OE0 TOT00 pin output setting Timer output prohibited
• Low level is output from the TOT00 pin when the TT0OL0 bit = 0.
• High level is output from the TOT00 pin when the TT0OL0 bit = 1. Timer output enabled (A pulse is output from the TOT00 pin.) 7 <0> After reset: 00H R/W Address: FFFFF603H Note The output level of the timer output pi ns (TOT00 and TOT01) specified by the TT0OLn bit is shown below (n = 0, 1). TT0CE bit TOT0n pin output 16-bit counter TT0CE bit TOT0n pin output 16-bit counter
• When TT0OLn bit = 0 • When TT0OLn bit = 1 Cautions 1. If the setting of the TT0IOC0 register is changed when TOT00 and TOT01 outputs are set for the port mode, the output of the pins change. Set the port in the input mode and make the port go into a high-impedance state, noting changes in the pin status. 2. Rewrite the TT0OL1, TT0OE1, TT0OL0, and TT0OE0 bits when the TT0CTL0.TT0CE bit = 0. (The same value can be written when the TT0CE bit = 1.) If rewriting was mistakenly performed, clear the TT0CE bit to 0 and then set the bits again. 3. Even if the TT0OL0 or TT0OL1 bit is manipulated when the TT0CE, TT0OE0, and TT0OE1 bits are 0, the output level of the TOT00 and TOT01 pins changes.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 465 of 1817 Sep 19, 2011 (5) TMT0 I/O control register 1 (TT0IOC1) The TT0IOC1 register is an 8-bit register that controls the valid edge for the capture trigger input signals (TIT00, TIT01 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. TT0IS3 TT0IS2 Capture trigger input signal (TIT01 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges 0 0 0 TT0IS3 TT0IS2 TT0IS1 TT0IS0 65 43 21 TT0IS1 TT0IS0 Capture trigger input signal (TIT00 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges 7 0 TT0IOC1 After reset: 00H R/W Address: FFFFF604H Cautions 1. Rewrite the TT0IS3 to TT0IS0 bits when the TT0CTL0.TT0CE bit = 0. (The same value can be written when the TT0CE bit = 1.) If rewriting was mistakenly performed, clear th e TT0CE bit to 0 and then set the bits again. 2. The TT0IS3 and TT0IS2 bits are valid only in the free-running timer mode (only when the TT0OPT0.TT0CCS1 bit = 1) and the pulse width measurement mode. In all other modes, a capture operation is not performed. The TT0IS1 and TT0IS0 bits are va lid only in the free-running timer mode (only when the TT0OPT0. TT0CCS0 bit = 1) and the pulse width measurement mode. In all other modes, a capture operation is not performed.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 466 of 1817 Sep 19, 2011 (6) TMT0 I/O control register 2 (TT0IOC2) The TT0IOC2 register is an 8-bit regist er that controls the valid edge for t he external event count input signal (TENC00 pin) and external trigger input signal. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. TT0EES1 TT0EES0 External event count input signal (TENC00 pin) valid edge setting No edge detection (external event count invalid) Detection of rising edge Detection of falling edge Detection of both edges 0 0 0 TT0EES1 TT0EES0 TT0ETS1 TT0ETS0 65 43 21 TT0ETS1 TT0ETS0 External trigger input signal (TENC00 pin) valid edge setting No edge detection (external trigger invalid) Detection of rising edge Detection of falling edge Detection of both edges 7 0 TT0IOC2 After reset: 00H R/W Address: FFFFF605H Cautions 1. Rewrite the TT0EES1, TT0EES0, TT0ETS1, and TT0ETS0 bits when the TT0CTL0.TT0CE bit = 0. (The same value can be written when the TT0CE bit = 1.) If rewriting was mistakenly performed, clear the TT0CE bit to 0 and then set the bits again. 2. The TT0EES1 and TT0EES0 bi ts are valid only when the TT0CTL1.TT0EEE bit = 1 or when the external event count mode (the TT0CTL1.TT0MD3 to TT0CTL1.TT0MD0 bits = 0001) has been set. 3. The TT0ETS1 and TT0ETS0 bits are valid only in the external trigger pulse mode or one-shot pulse output mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 467 of 1817 Sep 19, 2011 (7) TMT0 I/O control register 3 (TT0IOC3) The TT0IOC3 register is an 8-bit register that controls the encoder clear function operation. The TT0IOC3 register is valid only in the encoder compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) TT0SCETT0IOC3 TT0ZCL TT0BCL TT0ACL TT0ECS1 TT0ECS0 TT0EIS1 TT0EIS0 65 43 21 After reset: 00H R/W Address: FFFFF606H 7 0 TT0SCE Encoder clear selection

• Clears the 16-bit counter to 0000H when the valid edge of TECR0 pin specified by the TT0ECS1 and TT0ECS0 bits is detected when the TT0SCE bit = 0.
• Clears the 16-bit counter to 0000H when the clear level conditions of the TT0ZCL, TT0BCL, and TT0ACL bits match the input levels of the TECR0, TENC01, and TENC00 pins when TT0SCE bit = 1.
• Setting of the TT0ZCL, TT0BCL, and TT0ACL bits is valid and that of the TT0ECS1 and TT0ECS0 bits is invalid when the TT0SCE bit = 1. An encoder clear interrupt request signal (INTTTI0EC) is not generated.
• Setting of the TT0ZCL, TT0BCL, and TT0ACL bits is invalid and setting of the TT0ECS1 and TT0ECS0 bits is valid when the TT0SCE bit = 0. The INTTTI0EC signal is generated when the valid edge specified by the TT0ECS1 and TT0ECS0 bits is detected.
• Be sure to set the TT0CTL2.TT0UDS1 and TT0CTL2.TT0UDS0 bits to 10 or 11 when the TT0SCE bit = 1. Operation is not guaranteed if the TT0UDS1 and TT0UDS0 bits = 00 or 01 and the TT0SCE bit = 1. Clears 16-bit counter on detection of edge of encoder clear signal (TECR0 pin). Clears 16-bit counter on detection of clear level condition of the TENC00, TENC01, and TECR0 pins. TT0ZCL Clear level selection of encoder clear signal (TECR0 pin) Setting of the TT0ZCL bit is valid only when the TT0SCE bit = 1. Clears low level of the TECR0 pin. Clears high level of the TECR0 pin. TT0BCL Clear level selection of encoder input signal (TENC01 pin) Setting of the TT0BCL bit is valid only when the TT0SCE bit = 1. Clears low level of the TENC01 pin. Clears high level of the TENC01 pin. TT0ACL Clear level selection of encoder input signal (TENC00 pin) Setting of the TT0ACL bit is valid only when the TT0SCE bit = 1. Clears low level of the TENC00 pin. Clears high level of the TENC00 pin.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 468 of 1817 Sep 19, 2011 (2/2) TT0ECS1 TT0ECS0 Valid edge setting of encoder clear signal (TECR0 pin) Detects no edge (clearing encoder is invalid). Detects rising edge. Detects falling edge. Detects both edges. TT0EIS1 TT0EIS0 Valid edge setting of encoder input signals (TENC00, TENC01 pins) Detects no edge (inputting encoder is invalid). Detects rising edge. Detects falling edge. Detects both edges. Cautions 1. Rewrite the TT0SCE, TT0Z CL, TT0BCL, TT0ACL, TT0ECS1, TT0ECS0, TT0EIS1, and TT0EIS0 bits when the TT0CTL0.TT0CE bit = 0. (The same value can be written to these bits when the TT0CE bit = 1.) If rewriting was mistakenly performed, clear the TT0CE bit to 0 and then set these bits again. 2. The TT0ECS1 and TT0ECS0 bits ar e valid only when the TT0SCE bit = 0 and the encoder compare mode is set. 3. The TT0EIS1 and TT0EIS0 bits ar e valid only when the TT0CTL2.TT0UDS1 and TT0CTL2.TT0UDS0 bits = 00 or 01.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 469 of 1817 Sep 19, 2011 (8) TMT0 option register 0 (TT0OPT0) The TT0OPT0 register is an 8-bit register that sets the capture/compare operation and detects overflows. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. TT0CCS1 TT0CCR1 register capture/compare selection The TT0CCS1 bit setting is valid only in the free-running timer mode. Selected as compare register Selected as capture register (cleared by the TT0CTL0.TT0CE bit = 0)

0 TT0CCS1 TT0CCS0 0 0 0 TT0OVF

TT0CCR0 register capture/compare selection The TT0CCS0 bit setting is valid only in the free-running timer mode. Selected as compare register Selected as capture register (cleared by the TT0CTL0.TT0CE bit = 0) TT0OVF Set (1) Reset (0) TMT0 overflow detection flag

• The TT0OVF bit is set to 1 when the 16-bit counter value overflows from FFFFH to 0000H in the free-running timer mode or the pulse width measurement mode.
• An overflow interrupt request signal (INTTT0OV) is generated when the TT0OVF bit is set to 1. The INTTT0OV signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode.
• The TT0OVF bit is not cleared to 0 even when the TT0OVF bit or the TT0OPT0 register are read when the TT0OVF bit = 1.
• Before clearing the TT0OVF bit to 0 after generation of the INTTT0OV signal, be sure to confirm (by reading) that the TT0OVF bit is set to 1.
• The TT0OVF bit can be both read and written, but the TT0OVF bit cannot be set to 1 by software. Writing 1 has no effect on the operation of TMT0. Overflow occurred 0 written to TT0OVF bit or TT0CTL0.TT0CE bit = 0 7 <0> TT0OPT0 After reset: 00H R/W Address: FFFFF607H Cautions 1. Rewrite the TT0CCS1 and TT0CCS0 bits when the TT0CE bit = 0. (The same value can be written when the TT0CE bit = 1.) If rewriting was mistakenly performed, clear the TT0CE bit to 0 and then set these bits again. 2. Be sure to set bits 1 to 3, 6, and 7 to “0”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 470 of 1817 Sep 19, 2011 (9) TMT0 option register 1 (TT0OPT1) The TT0OPT1 register is an 8-bit register that detects overflows, underflows, and count-up/down operations of the encoder count function. The TT0OPT1 register is valid only in the encoder compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. This register can be rewritten even when the TT0CTL0.TT0CE bit = 1. (1/2) 0TT0OPT1 0 0 0 0 TT0EUF TT0EOF TT0ESF 6 5 4 3 <2> <1> After reset: 00H R/W Address: FFFFF608H TT0EUF Set (1) Reset (0) TMT0 underflow detection flag

• The TT0EUF bit is set to 1 when the 16-bit counter underflows from 0000H to FFFFH in the encoder compare mode.
• When the TT0CTL2.TT0LDE bit = 1, the TT0EUF bit is set to 1 when the value of the 16-bit counter is changed from 0000H to the set value of the TT0CCR0 register.
• An overflow interrupt request signal (INTTTOV0) is generated as soon as the TT0EUF bit is set to 1.
• The TT0EUF bit is not cleared to 0 even if the TT0EUF bit or TT0OPT1 register is read when the TT0EUF bit = 1.
• The status of the TT0EUF bit is retained even if the TT0CTL0.TT0CE bit is cleared to 0 when the TT0CTL2.TT0ECC bit = 1.
• Before clearing the TT0EUF bit to 0 after the INTTTOV0 signal is generated, be sure to confirm (read) that the TT0EUF bit is set to 1.
• The TT0EUF bit can be read or written, but it cannot be set to 1 by software. Setting this bit to 1 does not affect the operation of TMT0. Underflow occurs. Cleared by writing to TT0EUF bit or when TT0CTL0.TT0CE bit = 0 7 <0>

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 471 of 1817 Sep 19, 2011 (2/2) TT0ESF TMT0 count-up/-down operation status detection flag

• This bit is cleared to 0 if the TT0CTL0.TT0CE bit = 0 when the TT0CTL2.TT0ECC bit = 0.
• The status of the TT0ESF bit is retained even if the TT0CE bit = 0 when the TT0ECC bit = 1. TMT0 is counting up. TMT0 is counting down. TT0EOF Set (1) Reset (0) Overflow detection flag for TMT0 encoder function
• The TT0EOF bit is set to 1 when the 16-bit counter overflows from FFFFH to 0000H in the encoder compare mode.
• As soon as the TT0EOF bit has been set to 1, an overflow interrupt request signal (INTTTOV0) is generated. At this time, the TT0OPT0.TT0OVF bit is not set to 1.
• The TT0EOF bit is not cleared to 0 even if the TT0EOF bit or TT0OPT1 register is read when the TT0EOF bit = 1.
• The status of the TT0EOF bit is retained even if the TT0CTL0.TT0CE bit is cleared to 0 when the TT0CTL2.TT0ECC bit = 1.
• Before clearing the TT0EOF bit to 0 after the INTTTOV0 signal is generated, be sure to confirm (read) that the TT0EOF bit is set to 1.
• The TT0EOF bit can be read or written, but it cannot be set to 1 by software. Writing 1 to this bit does not affect the operation of TMT0. Overflow occurs. Cleared by writing 0 to the TT0EOF bit or when the TT0CTL0.TT0CE bit = 0 Caution Be sure to set bits 3 to 7 to “0”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 472 of 1817 Sep 19, 2011 (10) TMT0 capture/compare register 0 (TT0CCR0) The TT0CCR0 register is a 16-bit regist er that can be used as a capture regi ster or compare register depending on the mode. This register can be used as a capt ure register or a compare register only in the free-running timer mode, depending on the setting of the TT0OPT0.TT0CCS0 bit. In the pulse width measurement mode, the TT0CCR0 register can be used only as a capture register. In any ot her mode, this register can be used only as a compare register. The TT0CCR0 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. TT0CCR0 12 10 8 6 4 2 After reset: 0000H R/W Address: FFFFF60AH 14 013 11 9 7 5 315 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 473 of 1817 Sep 19, 2011 (a) Function as compare register The TT0CCR0 register can be rewritten even when the TT0CTL0.TT0CE bit = 1. The set value of the TT0CCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTT0CC0) is generated. If TOT00 pin output is enabled at this time, the output of the TOT00 pin is inverted. When the TT0CCR0 register is used as a cycle register in the interval timer mode, or when the TT0CCR0 register is used as a cycle register in the external event count mode, external trigger pulse output mode, one- shot pulse output mode, PWM output mode, triangula r-wave PWM output mode, or encoder compare mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register. The compare register is not cleared by setting the TT0CTL0.TT0CE bit to 0. (b) Function as capture register In the free-running timer mode (when the TT0CCR0 register is used as a capture regi ster), the count value of the 16-bit counter is stored in the TT0CCR0 register if the valid edge of the capture trigger input pin (TIT00 pin) is detected. In the pulse width m easurement mode, the count value of t he 16-bit counter is stored in the TT0CCR0 register and the 16-bit counter is cleared (0000H ) if the valid edge of the capture trigger input pin (TIT00 pin) is detected. Even if the capture operation and reading the TT0CCR0 register conflic t, the correct value of the TT0CCR0 register can be read. The capture register is cleared by setting the TT0CTL0.TT0CE bit to 0. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 9-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode TT0CCR0 Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write Note One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Note Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register None Triangular-wave WPM output Compare register Batch write Note Encoder compare Compare register Anytime write Note Writing to the TT0CCR1 register is the trigger. Remark For anytime write and batch write, see 9.6 (2) Anytime write and batch write.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 474 of 1817 Sep 19, 2011 (11) TMT0 capture/compare register 1 (TT0CCR1) The TT0CCR1 register is a 16-bit regist er that can be used as a capture regi ster or compare register depending on the mode. This register can be used as a capt ure register or a compare register only in the free-running timer mode, depending on the setting of the TT0OPT0.TT0CCS1 bit. In the pulse width measurement mode, the TT0CCR1 register can be used only as a capture register. In any ot her mode, this register can be used only as a compare register. The TT0CCR1 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. TT0CCR1 12 10 8 6 4 2 After reset: 0000H R/W Address: FFFFFF60CH 14 013 11 9 7 5 315 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 475 of 1817 Sep 19, 2011 (a) Function as compare register The TT0CCR1 register can be rewritten even when the TT0CTL0.TT0CE bit = 1. The set value of the TT0CCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer r egister, a compare match interrupt request signal (INTTT0CC01) is generated. If TOT01 pin output is enabled at this time, the output of the TOT01 pin is inverted. The compare register is not cleared by setting the TT0CTL0.TT0CE bit to 0. (b) Function as capture register In the free-running timer mode (when the TT0CCR1 register is used as a capture regi ster), the count value of the 16-bit counter is stored in the TT0CCR1 register if the valid edge of the capture trigger input pin (TIT01 pin) is detected. In the pulse width m easurement mode, the count value of t he 16-bit counter is stored in the TT0CCR1 register and the 16-bit counter is cleared (0000H ) if the valid edge of the capture trigger input pin (TIT01 pin) is detected. Even if the capture operation and reading the TT0CCR1 register conflic t, the correct value of the TT0CCR1 register can be read. The capture register is cleared by setting the TT0CTL0.TT0CE bit to 0. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 9-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode TT0CCR1 Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write Note One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Note Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register None Triangular-wave PWM output Compare register Batch write Note Encoder compare Compare register Anytime write Note Writing to the TT0CCR1 register is the trigger. Remark For anytime write and batch write, see 9.6 (2) Anytime write and batch write.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 476 of 1817 Sep 19, 2011 (12) TMT0 counter write register (TT0TCW) The TT0TCW register is used to set the initial value of the 16-bit counter. The TT0TCW register is valid only in the encoder compare mode. This register can be read or written in 16-bit units. Rewrite the TT0TCW register when the TT0CTL0.TT0CE bit = 0. The value of the TT0TCW register is transferred to the 16-bit counter when the TT0CE bit is set (1). Reset sets this register to 0000H. TT0TCW 12 10 8 6 4 2 After reset: 0000H R/W Address: FFFFF610H 14 013 11 9 7 5 315 1 (13) TMT0 counter read buffer register (TT0CNT) The TT0CNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TT0CTL0.TT0CE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units. The value of the TT0CNT register is set to 0000H when the TT0CTL2.TT0ECC and TT0CE bits = 0. If the TT0CNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. The TT0CNT register is not set to 0000H but the previous value is read when the TT0ECC bit = 1 and TT0CE bit = 0. The TT0ECC and TT0CE bits are set to 0 after reset, and the value of the TT0CNT register is set to 0000H. TT0CNT 12 10 8 6 4 2 After reset: 0000H R Address: FFFFFF60EH 14 013 11 9 7 5 315 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 477 of 1817 Sep 19, 2011 (14) Noise elimination control register (TTNFC) Digital noise elimination can be select ed for the TIT00, TIT01, TENC00, TENC01, and TECR0 pins. The noise elimination settings are performed using the TTNFC register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among fXX, fXX/4, fXX/8, fXX/16, fXX/32, and fXX/64. Sampling is performed 3 times. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution Time equal to the sampling clock × 3 clocks is required until th e digital noise eliminator is initialized after the sampling cloc k has been changed. If the va lid edge of the TIT00, TIT01, TENC00, TENC01, and TECR0 pins is input a fter the sampling clock has been changed and before the time of the sampling clock × 3 clocks passes, therefore, an interrupt request signal may be generated. Therefore, when using the external trigger function, the external event function, the capture trigger f unction, and the encoder function of TMT, enable TMT operation after the sampling clock × 3 clocks have elapsed. TTNFENTTNFC 0 0 0 0 TTNFC2 TTNFC1 TTNFC0 fXX fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 TTNFC2 Digital sampling clock Setting prohibited TTNFC1 TTNFC0 After reset: 00H R/W Address: FFFFF726H Digital noise elimination not executed Digital noise elimination executed TTNFEN Settings of digital noise elimination Other than above < > Remarks 1. Since sampling is performed three times, the noise width for reliably eliminating noise is 2 sampling clocks. 2. In the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is generated if noise synchronized with the sampling clock is input.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 478 of 1817 Sep 19, 2011 A timing example of noise elimination performed by the timer T input pin digital filter is shown Figure 9-2. Figure 9-2. Example of Digital Noise Elimination Timing Noise elimination clock Input signal Internal signal 3 clocks Sampling 3 times 3 clocks1 clock 1 clock 2 clocks 2 clocks Sampling 3 times Remark If there are two or fewer noise elimination cloc ks while the TIT00, TIT01, TENC00, TENC01, and TECR0 input signals are high level (or low level), t he input signal is eliminated as noise. If it is sampled three times or more, the edge is detected as a valid input.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 479 of 1817 Sep 19, 2011

9.5 Timer Output Operations

The following table shows the operations and output levels of the TOT00 and TOT01 pins. Table 9-5. Timer Output Control in Each Mode Operation Mode TOT01 Pin TOT00 Pin Interval timer mode Square wave output External event count mode None External trigger pulse output mode External trigger pulse output One-shot pulse output mode One-shot pulse output PWM output mode PWM output Square wave output Free-running timer mode Square wave output (only when compare function is used) Pulse width measurement mode None Triangular-wave PWM output mode Triangular-wave PWM output Encoder compare mode None Table 9-6. Truth Table of TOT00 and TOT01 Pins Under Control of Timer Output Control Bits TT0IOC0.TT0OLn Bit TT0IOC0.TT0OEn Bit TT0CTL0.TT0CE Bit Level of TOT0n Pin 0 × Low-level output level after counting is started 0 × High-level output Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 480 of 1817 Sep 19, 2011

9.6 Operation

The functions of TMT0 that can be impl emented differ from one channel to anothe r. The functions of each channel are shown below. Table 9-7. TMT0 Specifications in Each Mode Operation TT0CTL1.TT0EST Bit (Software Trigger Bit) TENC00 Pin (External Trigger Input) Capture/Compare Register Setting Compare Register Write Method Interval timer mode Invalid Invalid Compare only Anytime write External event count mode Invalid Invalid Compare only Anytime write External trigger pulse output mode Va lid Valid Compare only Batch write One-shot pulse output mode Valid Valid Compare only Anytime write PWM output mode Invalid Invalid Compare only Batch write Free-running timer mode Invalid Invalid Switchable Anytime write Pulse width measurement mode Invalid Invalid Capture only Not applicable Triangular-wave PWM output mode Invalid Invalid Compare only Batch write Encoder compare mode Invalid Invalid Compare only Anytime write

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 481 of 1817 Sep 19, 2011 (1) Basic counter operation This section explains the basic operation of the 16-bit counte r. For details, refer to the description of the operation in each mode. (a) Count start operation

• Encoder compare mode A count operation is controlled by TENC00 and TENC01 phases. The 16-bit counter initial setting is performed by transfer ring the set value of the TT0TCW register to the 16- bit counter and the count operation is started. (When the TT0CTL2.TT0ECC bit = 0, the TT0TCW register set value is transferred to the 16-bit counter at the timing when the TT0CTL0.TT0CE bit changes from 0 to 1.)
• Triangular-wave PWM mode The 16-bit counter starts counting from the initial value FFFFH. It counts up FFFFH, 0000H, 0001H, 0002H, 0003H, and so on. Following the count-up operation, the counter counts down upon a match between the 16-bit count value and the CCR0 buffer register.
• Mode other than above The 16-bit counter starts counting from the initial value FFFFH. It counts up FFFFH, 0000H, 0001H, 0002H, 0003H, and so on. (b) Clear operation The 16-bit counter is cleared to 0000H when its value ma tches the value of the compare register, when its value is captured, when the edge of the encoder clear signal is detected, and when the clear level condition of the TENC00, TENC01, and TECR0 pins is detected. The c ount operation from FFFFH to 0000H that takes place immediately after the counter has started counting or when the counter overflows is not a clear operation. Therefore, the INTTT0CC0 and INTTT0CC1 interrupt signals are not generated. (c) Overflow operation The 16-bit counter overflows when it counts up from FFFFH to 0000H in the free-running mode, pulse width measurement mode, and encoder compare mode. If the counter overflows in the free-running mode and pulse width measurement mode, the TT0OPT0.TT0OVF bit is se t to 1 and an interrupt request signal (INTTT0OV) is generated. If the counter overflows in the encoder compare mode, the TT0OPT1.TT0EOF bit is set to 1 and an interrupt request signal (INTTT0OV) is generated. Note that the INTTT0OV signal is not generated under the following conditions.
• Immediately after a count operation has been started
• If the counter value matches the compare value FFFFH and is cleared
• When FFFFH is captured and cleared to 0000H in the pulse width measurement mode Caution After the overflow interrupt request signal (INTTT0OV) has been generated, be sure to check that the overflow flag (TT0OVF, TT0EOF bits) is set to 1.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 482 of 1817 Sep 19, 2011 (d) Count value hold operation The value of the 16-bit counter is held by the TT0CTL2.TT0ECC bit in the encoder compare mode. The value of the 16-bit counter is reset to FFFFH when the TT0ECC bit = 0 and TT0CTL0.TT0CE bit = 0. When the TT0CE bit is next set to 1, the set value of the TT0TCW register is transferred to the 16-bit counter and a count operation is performed. If the TT0ECC bit = 1 and TT0CE bit = 0, the value of the 16-bit counter is held. When the TT0CE bit is next set to 1, the counter resumes the count operation from the held value. (e) Counter read operation during count operation The value of the 16-bit counter of TMT0 can be read by using the TT0CNT register during the count operation. When the TT0CTL0.TT0CE bit = 1, the value of the 16-bit counter can be read by reading the TT0CNT register. If the TT0CNT register is read when the TT0CTL2.TT0ECC bi t = 0 and TT0CE bit = 0, however, it is 0000H. The held value of the TT0CNT register is read if the register is read when the TT0ECC bit = 1 and TT0CE bit = (f) Underflow operation A 16-bit counter underflow occurs at the timing when th e 16-bit counter value changes from 0000H to FFFFH in the encoder compare mode. When an underflow occurs, the TT0OPT1.TT0EUF bit is set to 1 and an interrupt request signal (INTTT0OV) is generated. (g) Interrupt operation TMT0 generates the following four types of interrupt request signals.

• INTTT0CC0 interrupt: This signal func tions as a match interrupt request signal of the CCR0 buffer register and as a capture interrupt request signal to the TT0CCR0 register.
• INTTT0CC1 interrupt: This signal func tions as a match interrupt request signal of the CCR1 buffer register and as a capture interrupt request signal to the TT0CCR1 register.
• INTTT0OV interrupt: This signal functions as an overflow interrupt request signal.
• INTTT0EC interrupt: This signal functions as a valid edge detection interr upt request signal of the encoder clear input (TECR0 pin).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 483 of 1817 Sep 19, 2011 (2) Anytime write and batch write The TT0CCR0 and TT0CCR1 registers in TMT0 can be rewri tten during timer operation (TT0CTL0.TT0CE bit = 1), but the write method (anytime write, bat ch write) of the CCR0 and CCR1 buffer registers differs depending on the mode. (a) Anytime write In this mode, data is transferred at any time from the TT0CCR0 and TT0CCR1 registers to the CCR0 and CCR1 buffer registers during timer operation (n = 0, 1). Figure 9-3. Flowchart of Basic Operation for Anytime Write START Initial settings

• Set values to TT0CCRn register
• Timer operation enable (TT0CE bit = 1) → Transfer values of TT0CCRn register to CCRn buffer register Timer operation
• Match between 16-bit counter and CCR1 buffer register Note
• Match between 16-bit counter and CCR0 buffer register
• 16-bit counter clear & start IINTTT0CC1 signal output TTnCCRn register rewrite → Transfer to CCRn buffer register IINTTT0CC0 signal output Note The 16-bit counter is not cleared upon a match between the 16-bit counter value and the CCR1 buffer register value. It is cleared upon a match between the 16-bit counter value and the CCR0 buffer register value. Remarks 1. The above flowchart illustrates an exam ple of the operation in the interval timer mode. 2. n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 484 of 1817 Sep 19, 2011 Figure 9-4. Timing of Anytime Write D01 D01 D01 D010000H TT0CE bit = 1 D02 D02 D11 D11 D11 D12 D12 D12 D02 D110000H D12 16-bit counter TT0CCR0 register TT0CCR1 register INTTT0CC0 signal INTTT0CC1 signal CCR0 buffer register CCR1 buffer register 0000H FFFFH Remarks 1. D 01, D02: Set values of TT0CCR0 register D 11, D12: Set values of TT0CCR1 register 2. The above timing chart illustrates an example of the operation in the interval timer mode. 3. n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 485 of 1817 Sep 19, 2011 (b) Batch write In this mode, data is transferred all at once from the TT0CCR0 and TT0CCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter. Transfer is enabled by writing to the TT0CCR1 register. Whether to enable or disable the next transfer timing is controlled by writing or not writing to the TT0CCR1 register. In order for the set value when the TT0CCR0 and TT0CCR1 registers are rewritten to become the 16-bit counter comparison value (in other words, in order fo r this value to be transferred to the CCR0 and CCR1 buffer registers), it is necessary to rewrite the TT0CCR0 register and then write to the TT0CCR1 register before the 16-bit counter value and the CCR0 buffer register value match. Therefore, the values of the TT0CCR0 and TT0CCR1 registers are transferred to the CCR0 and CCR1 buffer registers upon a match between the count value of the 16-bit counter and the value of the CCR0 buffer register. Thus even when wishing only to rewrite the value of the TT0CCR0 register, also write the same value (same as preset value of the TT0CCR1 register) to the TT0CCR1 register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 486 of 1817 Sep 19, 2011 Figure 9-5. Flowchart of Basic Operation for Batch Write START Initial settings

• Set values to TT0CCRn register
• Timer operation enable (TT0CE bit = 1) → Transfer values of TT0CCRn register to CCRn buffer register Timer operation
• Match between 16-bit counter and CCR1 buffer register Note
• Match between 16-bit counter and CCR0 buffer register
• 16-bit counter clear & start
• Transfer of values of TT0CCRn register to CCRn buffer register INTTT0CC1 signal output TT0CCR0 register rewrite TT0CCR1 register rewrite INTTT0CC0 signal output Batch write enable Note The 16-bit counter is not cleared upon a matc h between the 16-bit counter value and the CCR1 buffer register value. It is cleared upon a match between the 16-bit counter value and the CCR0 buffer register value. Caution Writing to the TT0CCR1 register include s enabling of batch write. Thus, rewrite the TT0CCR1 register after rewriting the TT0CCR0 register. Remark The above flowchart illustrates an example of the operation in the PWM output mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 487 of 1817 Sep 19, 2011 Figure 9-6. Timing of Batch Write D01 D01 D02 D03 0000H D 01 D11 D12 D12 0000H D 11 TT0CE bit = 1 Note 1 D02 D02 D03 D11 D12D12D12D1216-bit counter TT0CCR0 register TT0CCR1 register INTTT0CC0 signal INTTT0CC1 signal TOT01 pin output TOT00 pin output CCR0 buffer register CCR1 buffer register Note 1 Note 1 Note 1Same value write D02 D12 0000H D03 D12 Note 2 Note 3 FFFFH Notes 1. Because the TT0CCR1 register was not rewritten, D 03 is not transferred. 2. Because the TT0CCR1 register has been written (D 12), data is transferred to the CCR1 buffer register upon a match between the value of the 16-bit counter and the value of the TT0CCR0 register (D01). 3. Because the TT0CCR1 register has been written (D 12), data is transferred to the CCR1 buffer register upon a match between the value of the 16-bit counter and the value of the TT0CCR0 register (D02). Remarks 1. D 01, D02, D03: Set values of TT0CCR0 register D 11, D12: Set values of TT0CCR1 register 2. The above timing chart illustrates the opera tion in the PWM output mode as an example.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 488 of 1817 Sep 19, 2011

9.6.1 Interval timer mode (TT0MD3 to TT0MD0 bits = 0000)

In the interval timer mode, an interr upt request signal (INTTT0CC0 ) is generated at the in terval set by the TT0CCR0 register if the TT0CTL0.TT0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOT00 pin. The TT0CCR1 register is not used in the interval timer m ode. However, the set value of the TT0CCR1 register is transferred to the CCR1 buffer register, and when the count va lue of the 16-bit counter matc hes the value of the CCR1 buffer register, a compare match interrupt request signal (INTTT0CC1) is generated. In addition, a square wave, which is inverted when the INTTT0CC1 signal is generated, can be output from the TOT01 pin. The value of the TT0CCR0 and TT0CCR1 registers can be rewritten even while the timer is operating. Figure 9-7. Configuration of Interval Timer 16-bit counter Output controller CCR0 buffer registerTT0CE bit TT0CCR0 register Count clock selection Clear Match signal TOT00 pin INTTT0CC0 signal Figure 9-8. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register TOT00 pin output INTTT0CC0 signal D0 D0 D0 D0 Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 489 of 1817 Sep 19, 2011 When the TT0CE bit is set to 1, the value of the 16-bit c ounter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts count ing. At this time, the output of the TOT00 pin is inverted. Additionally, the set value of the TT0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, the output of the TOT00 pin is inverted, and a compare match interrupt request signal (INTTT0CC0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TT0CCR0 register + 1) × Count clock cycle Figure 9-9. Register Setting for Interval Timer Mode Operation (1/2) (a) TMT0 control register 0 (TT0CTL0) 0/1 0 0 0 0 TT0CTL0 Select count clock 0: Stops counting 1: Enables counting 0/1 0/1 0/1 TT0CKS2 TT0CKS1 TT0CKS0TT0CE (b) TMT0 control register 1 (TT0CTL1) 0000 0 TT0CTL1 0, 0, 0, 0: Interval timer mode 000 TT0MD2TT0MD3 TT0MD1 TT0MD0TT0EEETT0EST (c) TMT0 I/O control register 0 (TT0IOC0) 0 0 0 0 0/1 TT0IOC0 0: Disables TOT00 pin output 1: Enables TOT00 pin output Setting of TOT00 pin output level before count operation 0: Low level 1: High level 0: Disables TOT01 pin output 1: Enables TOT01 pin output Setting of TOT01 pin output level before count operation 0: Low level 1: High level 0/1 0/1 0/1 TT0OE1 TT0OL0 TT0OE0TT0OL1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 490 of 1817 Sep 19, 2011 Figure 9-9. Register Setting for Interval Timer Mode Operation (2/2) (d) TMT0 counter read buffer register (TT0CNT) By reading the TT0CNT register, the count value of the 16-bit counter can be read. (e) TMT0 capture/compare register 0 (TT0CCR0) If the TT0CCR0 register is set to D0, the interval is as follows. Interval = (D0 + 1) × Count clock cycle (f) TMT0 capture/compare register 1 (TT0CCR1) The TT0CCR1 register is not used in the interval ti mer mode. However, the set value of the TT0CCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, the TOT01 pi n output is inverted and a compare match interrupt request signal (INTTT0CC1) is generated. By setting this register to the same value as the value set in the TT0CCR0 register, a square wave can be output from the TOT01 pin. When the TT0CCR1 register is not used, it is reco mmended to set its value to FFFFH. Also mask the register by the interrupt mask flag (TT0CCIC1.TT0CCMK1). Remark TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control register 2 (TT0IOC2), TMT0 I/O control regi ster 3 (TT0IOC3), TMT0 option register 0 (TT0OPT0), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW) are not used in the interval timer mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 491 of 1817 Sep 19, 2011 (1) Interval timer mode operation flow Figure 9-10. Software Processing Flow in Interval Timer Mode TT0CE bit = 1 TT0CE bit = 0 Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits) TT0CTL1 register, TT0IOC0 register, TT0CCR0 register Initial setting of these registers is performed before setting the TT0CE bit to 1. The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting starts (TT0CE bit = 1). The counter is initialized and counting is stopped by clearing the TT0CE bit to 0. The output level of the TOT00 pin is as specified by the TT0IOC0 register. START STOP <1> Count operation start flow <2> Count operation stop flow <1> <2> D0 D0 D0 FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register TOT00 pin output INTTT0CC0 signal

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 492 of 1817 Sep 19, 2011 (2) Interval timer mode operation timing (a) Operation if TT0CCR0 re gister is set to 0000H If the TT0CCR0 register is set to 0000H, the INTTT0CC0 signal is generated at each count clock, and the output of the TOT00 pin is inverted. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter TT0CE bit TT0CCR0 register TOT00 pin output INTTT0CC0 signal 0000H Interval time Count clock cycle Interval time Count clock cycle Interval time Count clock cycle FFFFH 0000H 0000H 0000H 0000H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 493 of 1817 Sep 19, 2011 (b) Operation if TT0CCR0 register is set to FFFFH If the TT0CCR0 register is set to FFFFH, the 16-bit c ounter counts up to FFFFH. T he counter is cleared to 0000H in synchronization with the next count-up timing. The INTTT0CC0 signal is generated and the output of the TOT00 pin is inverted. At this time, an overflow interrupt request signal (INTTT0OV) is not generated, nor is the overflow flag (TT0OPT0.TT0OVF bit) set to 1. FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register TOT00 pin output INTTT0CC0 signal FFFFH Interval time 10000H × count clock cycle Interval time 10000H × count clock cycle Interval time 10000H × count clock cycle

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 494 of 1817 Sep 19, 2011 (c) Notes on rewriting TT0CCR0 register If the value of the TT0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When an overflow may occur, stop counting and then change the set value. FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register TT0OL0 bit TOT00 pin output INTTT0CC0 signal D1 D2 D1 D1 D2D2 D2 L Interval time (1) Interval time (NG) Interval time (2) Remark Interval time (1): (D 1 + 1) × Count clock cycle Interval time (NG): (10000H + D 2 + 1) × Count clock cycle Interval time (2): (D 2 + 1) × Count clock cycle If the value of the TT0CCR0 register is changed from D 1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TT0CCR0 register has been rewritten. Consequently, the value of the 16-bit counter that is compared is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTT0CC0 signal is generated and the output of the TOT00 pin is inverted. Therefore, the INTTT0CC0 signal may not be generated at the interval time “(D 1 + 1) × Count clock cycle” or “(D2 + 1) × Count clock cycle” as originally expected, but may be generated at an interval of “(10000H + D2 + 1) × Count clock cycle”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 495 of 1817 Sep 19, 2011 (d) Operation of TT0CCR1 register Figure 9-11. Configuration of TT0CCR1 Register CCR0 buffer register TT0CCR0 register TT0CCR1 register CCR1 buffer register TOT00 pin INTTT0CC0 signal TOT01 pin INTTT0CC1 signal 16-bit counter Output controller TT0CE bit Count clock selection Clear Match signal Output controller Match signal

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 496 of 1817 Sep 19, 2011 When the TT0CCR1 register is set to the same val ue as the TT0CCR0 register, the INTTT0CC0 signal is generated at the same timing as the INTTT0CC1 signal and the TOT01 pin output is inverted. In other words, a square wave can be output from the TOT01 pin. The following shows the operation when the TT0CCR1 r egister is set to other than the value set in the TT0CCR0 register. If the set value of the TT0CCR1 register is less than the set value of the TT0CCR0 register, the INTTT0CC1 signal is generated once per cycle. At the same time, the output of the TOT01 pin is inverted. The TOT01 pin outputs a square wave after outputting a short-width pulse. Figure 9-12. Timing Chart When D 01 ≥ D11 FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register TOT00 pin output INTTT0CC0 signal TT0CCR1 register TOT01 pin output INTTT0CC1 signal D01 D11 D01 D11 D11 D11 D11 D01 D01 D01

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 497 of 1817 Sep 19, 2011 If the set value of the TT0CCR1 register is greater than the set value of the TT0CCR0 register, the count value of the 16-bit counter does not match the value of the TT0CCR1 register. Consequently, the INTTT0CC1 signal is not generated, nor is the output of the TOT01 pin changed. When the TT0CCR1 register is not used, it is recommended to set its value to FFFFH. Figure 9-13. Timing Chart When D01 < D11 FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register TOT00 pin output INTTT0CC0 signal TT0CCR1 register TOT01 pin output INTTT0CC1 signal D01 D11 D01 D01 D01 D01 L

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 498 of 1817 Sep 19, 2011

9.6.2 External event count mode (TT0MD3 to TT0MD0 bits = 0001)

In the external event count mode, the valid edge of the external event count input (TENC00) is counted when the TT0CTL0.TT0CE bit is set to 1, and an inte rrupt request signal (INTTT0CC0) is generated each time the number of edges set by the TT0CCR0 register have been counted. The TOT00 and TOT01 pins cannot be used. The TT0CCR1 register is not used in the external event count mode. Figure 9-14. Configuration in External Event Count Mode 16-bit counter CCR0 buffer registerTT0CE bit TT0CCR0 register Edge detectorNote Clear Match signal INTTT0CC0 signal TENC00 pin (external event count input) Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 499 of 1817 Sep 19, 2011 Figure 9-15. Basic Timing in External Event Count Mode FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal D0 D0 D0 16-bit counter TT0CCR0 register INTTT0CC0 signal External event count input (TENC00 pin input) External event count 0 + 1) External event count 0 + 1) External event count 0 + 1) D0 − 1D 0 0000 0001 Remark This figure shows the basic timing when the risi ng edge is specified as the valid edge of the external event count input.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 500 of 1817 Sep 19, 2011 When the TT0CE bit is set to 1, the value of the 16-bit c ounter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TT0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTT0CC0) is generated. The INTTT0CC0 signal is gene rated each time the valid edge of the exte rnal event count input has been detected “value set to TT0CCR0 register + 1” times. Figure 9-16. Register Setting for Operation in External Event Count Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) 0/1 0 0 0 0 TT0CTL0 0: Stops counting 1: Enables counting 000 TT0CKS2 TT0CKS1 TT0CKS0TT0CE (b) TMT0 control register 1 (TT0CTL1) 0000 0 TT0CTL1 0, 0, 0, 1: External event count mode 001 TT0MD2TT0MD3 TT0MD1 TT0MD0TT0EEETT0EST (c) TMT0 I/O control register 2 (TT0IOC2) 0 0 0 0 0/1 TT0IOC2 Select valid edge of external event count input (TENC00 pin) 0/1 0 0 TT0EES0 TT0ETS1 TT0ETS0TT0EES1 (d) TMT0 counter read buffer register (TT0CNT) The count value of the 16-bit counter can be read by reading the TT0CNT register. (e) TMT0 capture/compare register 0 (TT0CCR0) If the TT0CCR0 register is set to D0, the count is cleared when the number of external events has reached (D0 + 1) and the compare match interrupt request signal (INTTT0CC0) is generated.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 501 of 1817 Sep 19, 2011 Figure 9-16. Register Setting for Operation in External Event Count Mode (2/2) (f) TMT0 capture/compare register 1 (TT0CCR1) The TT0CCR1 register is not used in the external ev ent count mode. However, the set value of the TT0CCR1 register is transferred to the CCR1 buffer re gister. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a co mpare match interrupt requ est signal (INTTT0CC1) is generated. When the TT0CCR1 register is not used, it is recommended to set its value to FFFFH. Also mask the register by the interrupt mask flag (TT0CCIC1.TT0CCMK1). Remark TMT0 control register 2 (TT0CTL2), TMT0 I/O c ontrol register 0 (TT0IOC0), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control regi ster 3 (TT0IOC3), TMT0 option register 0 (TT0OPT0), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW) are not used in the external event count mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 502 of 1817 Sep 19, 2011 (1) External event count mode operation flow Figure 9-17. Software Processing Flow in External Event Count Mode TT0CE bit = 1 TT0CE bit = 0 Register initial setting TT0CTL1 register, TT0IOC2 register, TT0CCR0, TT0CCR1 registers Initial setting of these registers is performed before setting the TT0CE bit to 1. The counter is initialized and counting is stopped by clearing the TT0CE bit to 0. START STOP <1> Count operation start flow <2> Count operation stop flow D0 D0 D0 <1> <2> FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 503 of 1817 Sep 19, 2011 (2) Operation timing in external event count mode (a) Operation if TT0CCR0 re gister is set to 0000H When the TT0CCR0 register is set to 0000H, the 16-bit counter is repeatedly cleared to 0000H and generates the INTTT0CC0 signal each time it has detected the valid edge of the external event count signal and its value has matched that of the CCR0 buffer register. The value of the 16-bit counter is always 0000H. FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal 0000H INTTT0CC0 signal is generated each time the 16-bit counter counts the valid edge of the external event count input. (b) Operation if TT0CCR0 register is set to FFFFH If the TT0CCR0 register is set to FFFFH, the 16-bit co unter counts up to FFFFH each time the valid edge of the external event count signal has be en detected. The 16-bit counter is cleared to 0000H in synchronization with the next count-up timing, and the INTTT0CC0 signal is generated. At this time, the TT0OPT0.TT0OVF bit is not set. FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal FFFFH External event count: 10000H External event count: 10000H External event count: 10000H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 504 of 1817 Sep 19, 2011 (c) Operation with TT0CCR0 set to FFFFH and TT0CCR1 register to 0000H When the TT0CCR0 register is set to FFFFH, the 16-bit c ounter counts up to FFFFH each time it has detected the valid edge of the external event count signal. The counter is then cleared to 0000H in synchronization with the next count-up timing and the INTTT0CC0 signal is generated. At this time, the TT0OPT0.TT0OVF bit is not set. If the TT0CCR1 register is set to 0000H, the INTTT0CC1 signal is generated when the 16-bit counter is cleared to 0000H. FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal TT0CCR1 register INTTT0CC1 signal FFFFH 0000H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 505 of 1817 Sep 19, 2011 (d) Notes on rewriting TT0CCR0 register If the value of the TT0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When an overflow may occur, stop counting once and then change the set value. FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal D1 D2 D1 D1 D2D2 D2 External event count (1): 1 + 1) External event count (NG): (10000H + D 2 + 1) External event count (2): 2 + 1) If the value of the TT0CCR0 register is changed from D 1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TT0CCR0 register has been rewritten. Consequently, the value that is compared with the 16-bit counter is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTT0CC0 signal is generated. Therefore, the INTTT0CC0 signal may not be generated at the valid edge count of “(D1 + 1) times” or “(D2 + 1) times” as originally expected, but may be generated at the valid edge count of “(10000H + D2 + 1) times”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 507 of 1817 Sep 19, 2011 If the set value of the TT0CCR1 register is greater than the set value of the TT0CCR0 register, the INTTT0CC1 signal is not generated because the count value of the 16-bit counter and the val ue of the TT0CCR1 register do not match. When the TT0CCR1 register is not used, it is recommended to set its value to FFFFH. Figure 9-20. Timing Chart When D01 < D11 FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal TT0CCR1 register INTTT0CC1 signal D01 D11 D01 D01 D01 D01 L

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 508 of 1817 Sep 19, 2011

9.6.3 External trigger pulse output m ode (TT0MD3 to TT0MD0 bits = 0010)

In the external trigger pulse output mode, 16-bit timer/ev ent counter T waits for a trigger when the TT0CTL0.TT0CE bit is set to 1. When the valid edge of an external trigger input (TENC00) is detected, 16-bit timer/event counter T starts counting, and outputs a PWM waveform from the TOT01 pin. Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software trigger, a square wave that has the set value of the TT0CCR0 register + 1 as half its cycle can also be output from the TOT00 pin. Figure 9-21. Configuration in External Trigger Pulse Output Mode CCR0 buffer registerTT0CE bit TT0CCR0 register 16-bit counter TT0CCR1 register CCR1 buffer register Clear Match signal Match signal INTTT0CC0 signal Output controller (RS-FF) Output controller TOT01 pin INTTT0CC1 signal TOT00 pin Count clock selectionInternal count clock Count start control Edge detector Note 2 Software trigger generation TENC00 pin Note 1 (external trigger input/ external event count input) Edge detector Note 3 Transfer Transfer S R Notes 1. The external trigger input (TENC00) pin is also used for the external event count input function. In the external trigger pulse output mode, theref ore, the external event count input function cannot be used. 2. Edge detector for external trigger input. Set by the TT0IOC2.TT0ETS1 and TT0IOC2.TT0ETS0 bits. 3. Edge detector for external event count input. Set by the TT0IOC2.TT0 EES1 and TT0IOC2.TT0EES0 bits.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 509 of 1817 Sep 19, 2011 Figure 9-22. Basic Timing in External Trigger Pulse Output Mode D1 D1 D1 D1 D0 D0 D0 FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal TOT00 pin output TT0CCR1 register INTTT0CC1 signal TOT01 pin output External trigger input (TENC00 pin input) Wait for trigger Active level width (D1) Cycle (D0 + 1) Cycle (D 0 + 1) Cycle (D 0 + 1) Active level width (D1) Active level width (D1) 16-bit timer/event counter T waits for a trigger when the TT0CE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOT01 pin. If the trigger is generated again while the counter is o perating, the counter is cleared to 0000H and restarted. (The output of the TOT00 pin is inverted. The TOT01 pin outputs a high level regardless of the status (high/low) when a trigger occurs.) The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TT0CCR1 register) × Count clock cycle Cycle = (Set value of TT0CCR0 register + 1) × Count clock cycle Duty factor = (Set value of TT0CCR1 register)/(Set value of TT0CCR0 register + 1) The compare match request signal (INTTT0CC0) is generated the next time the 16-bit counter counts after its count value matches the value of the CCR0 buffer register, and t he 16-bit counter is cleared to 0000H. The compare match interrupt request signal (INTTT0CC1) is generated when the c ount value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TT0CCRn register is transferred to the CCRn buffer register when t he count value of the 16-bit counter matches the value of the CCRn buffer register and the 16-bit counter is cleared to 0000H. The valid edge of an external trigger input (TENC00), or setting the software trigger (TT0CTL1.TT0EST bit) to 1 is used as the trigger (n = 0, 1).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 510 of 1817 Sep 19, 2011 Figure 9-23. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) 0/1 0 0 0 0 TT0CTL0 Select count clock 0: Stops counting 1: Enables counting 0/1 0/1 0/1 TT0CKS2 TT0CKS1 TT0CKS0TT0CE (b) TMT0 control register 1 (TT0CTL1) 0 0/1 0 0 0 TT0CTL1 Generates software trigger when 1 is written 010 TT0MD2 TT0MD1 TT0MD0TT0EEETT0EST 0, 0, 1, 0: External trigger pulse output mode TT0MD3 (c) TMT0 I/O control register 0 (TT0IOC0) 0 0 0 0 0/1 TT0IOC0 0: Disables TOT00 pin output 1: Enables TOT00 pin output Setting of TOT00 pin output level while waiting for external trigger 0: Low level 1: High level 0: Disables TOT01 pin output 1: Enables TOT01 pin output Setting of TOT01 pin output level while waiting for external trigger 0: Low level 1: High level 0/1 0/1 0/1 TT0OE1 TT0OL0 TT0OE0TT0OL1 TOT01 pin output 16-bit counter

• When TT0OL1 bit = 0 TOT01 pin output 16-bit counter
• When TT0OL1 bit = 1 (d) TMT0 I/O control register 2 (TT0IOC2) 0000 0TT0IOC2 Select valid edge of external trigger input (TENC00 pin)Note 0 0/1 0/1 TT0EES0 TT0ETS1 TT0ETS0TT0EES1 Note Set the valid edge selection of the unused alter nate external input signals to “No edge detection”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 511 of 1817 Sep 19, 2011 Figure 9-23. Setting of Registers in External Trigger Pulse Output Mode (2/2) (e) TMT0 counter read buffer register (TT0CNT) The value of the 16-bit counter can be read by reading the TT0CNT register. (f) TMT0 capture/compare regist ers 0 and 1 (TT0CCR0 and TT0CCR1) If D0 is set to the TT0CCR0 register and D1 to the TT0CCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) × Count clock cycle Active level width = D1 × Count clock cycle Remark TMT0 control register 2 (TT0CTL2), TMT0 I/O c ontrol register 1 (TT0IOC1), TMT0 I/O control register 3 (TT0IOC3), TMT0 option register 0 ( TT0OPT0), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW) are not used in the external trigger pulse output mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 512 of 1817 Sep 19, 2011 (1) Operation flow in extern al trigger pulse output mode Figure 9-24. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register CCR0 buffer register INTTT0CC0 signal TOT00 pin output TT0CCR1 register CCR1 buffer register INTTT0CC1 signal TOT01 pin output External trigger input (TENC00 pin input) D10 D00 D00 D01 D00 D00 D10 D10 D11 D10 D10 D10 D11 D10 D01 D00 D10 D10 D00 D10 D00D11D11 D01 D01 D01

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 513 of 1817 Sep 19, 2011 Figure 9-24. Software Processing Flow in External Trigger Pulse Output Mode (2/2) TT0CE bit = 1 Setting of TT0CCR0 register Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits) TT0CTL1 register, TT0IOC0 register, TT0IOC2 register, TT0CCR0 register, TT0CCR1 register Initial setting of these registers is performed before setting the TT0CE bit to 1. The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting is enabled (TT0CE bit = 1). Trigger wait status. Writing the same value (same as preset value of the TT0CCR1 register) to the TT0CCR1 register is necessary only when the set cycle is changed. When the counter is cleared after setting, the values of the TT0CCRn register are transferred to the CCRn buffer register in a batch. START Setting of TT0CCR1 register <1> Count operation start flow <2> TT0CCR0 and TT0CCR1 register setting change flow Setting of TT0CCR0 register When the counter is cleared after setting, the value of the TT0CCRn register is transferred to the CCRn buffer register. Setting of TT0CCR1 register <4> TT0CCR0, TT0CCR1 register setting change flow Writing of the TT0CCR1 register must be performed when only the set duty factor is changed. When the counter is cleared after setting, the value of the TT0CCRn register is transferred to the CCRn buffer register. Setting of TT0CCR1 register <3> TT0CCR0, TT0CCR1 register setting change flow TT0CE bit = 0 Counting is stopped. STOP <5> Count operation stop flow Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 514 of 1817 Sep 19, 2011 (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TT0CCR1 register last. Rewrite the TT0CCRn register after writing the TT0CCR1 register after the INTTT0CC0 signal is detected. FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register CCR0 buffer register INTTT0CC0 signal TOT00 pin output TT0CCR1 register CCR1 buffer register INTTT0CC1 signal TOT01 pin output External trigger input (TENC00 pin input) D10 D00 D00 D01 D00 D10 D11 D10 D11 D01 D10 D10 D00 D00 D11D11 D01 D01

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 515 of 1817 Sep 19, 2011 In order to transfer data from the TT0CCRn register to the CCRn buffer register, the TT0CCR1 register must be written. To change both the cycle and active level width of the PW M waveform at this time, first set the cycle to the TT0CCR0 register and then set the active level width to the TT0CCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TT0CCR0 register, and then write the same value (same as preset value of the TT0CCR1 register) to the TT0CCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TT0CCR1 register has to be set. After data is written to the TT0CCR1 register, the value written to the TT0CCRn register is transferred to the CCRn buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TT0CCR0 or TT0CCR1 register again after writing the TT0CCR1 register once, do so after the INTTT0CC0 signal is generated. Otherwise, the value of the CCRn buffer regist er may become undefined because the timing of transferring data from the TT0CCRn register to the CCRn buffer register conflicts with writing the TT0CCRn register. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 516 of 1817 Sep 19, 2011 (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TT0CCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTT0CC0 and INTTT0CC1 signals are generated after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register. Count clock 16-bit counter TT0CE bit TT0CCR0 register TT0CCR1 register INTTT0CC0 signal INTTT0CC1 signal TOT01 pin output External trigger input (TENC00 pin input) L 0000H 0000H 0000H D0 − 1D 00000FFFF 0000 D 0 − 1D 0 00000001 Note Note Note Note Note The timing is actually delayed by one operating clock (fXX).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 517 of 1817 Sep 19, 2011 To output a 100% waveform, set a value of (set value of TT0CCR0 register + 1) to the TT0CCR1 register. If the set value of the TT0CCR0 register is FFFFH, 100% output cannot be produced. D0 + 1 D0 + 1 D0 + 1 D00000FFFF 0000 D 0 00000001 Count clock 16-bit counter TT0CE bit TT0CCR0 register TT0CCR1 register INTTT0CC0 signal INTTT0CC1 signal TOT01 pin output D0 − 1D 0 − 1 External trigger input (TENC00 pin input) Note Note Note The timing is actually delayed by one operating clock (fXX).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 518 of 1817 Sep 19, 2011 (c) Conflict between trigger detection and match with CCR1 buffer register If the trigger is detected immediately after the IN TTT0CC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the TOT01 pin is assert ed, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter CCR1 buffer register INTTT0CC1 signal TOT01 pin output External trigger input (TENC00 pin input) D1 − 10000FFFF 0000 Shortened If the trigger is detected immediatel y before the INTTT0CC1 signal is gene rated, the INTTT0CC1 signal is not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the TOT01 pin remains active. Consequently, the active period of the PWM waveform is extended. 16-bit counter CCR1 buffer register INTTT0CC1 signal TOT01 pin output External trigger input (TENC00 pin input) D1 − 2D 1 − 1D 10000FFFF 0000 0001 Extended

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 519 of 1817 Sep 19, 2011 (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTT0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up again from that point. Therefore, the active period of the TOT01 pin is extended by the time from generation of the INTTT0CC0 signal to trigger detection. 16-bit counter CCR0 buffer register INTTT0CC0 signal TOT01 pin output External trigger input (TENC00 pin input) D0 − 1D 00000FFFF 0000 0000 Extended If the trigger is detected immediatel y before the INTTT0CC0 signal is gene rated, the INTTT0CC0 signal is not generated. The 16-bit counter is cleared to 0000H, t he TOT01 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter CCR0 buffer register INTTT0CC0 signal TOT01 pin output External trigger input (TENC00 pin input) D0 − 1D 00000FFFF 0000 0001 Shortened

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 520 of 1817 Sep 19, 2011 (e) Generation timing of compare match interrupt request signal (INTTT0CC1) The timing of generating the INTTT0CC1 signal in the external trigger pulse output mode differs from the timing of generating INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TT0CCR1 register. Count clock 16-bit counter TT0CCR1 register TOT01 pin output INTTT0CC1 signal D1 − 2D 1 − 1D 1 D1 + 1 D 1 + 2 Note Note Note The timing is actually delayed by one operating clock (fXX). Usually, the INTTT0CC1 signal is generated in synchronization with the next count-up, after the count value of the 16-bit counter matches the value of the TT0CCR1 register. In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the timing when the output signal of the TOT01 pin changes.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 521 of 1817 Sep 19, 2011

9.6.4 One-shot pulse output mode (TT0MD3 to TT0MD0 bits = 0011)

In the one-shot pulse output mode, 16-bit timer/event counte r T waits for a trigger when the TT0CTL0.TT0CE bit is set to 1. When the valid edge of an external trigger input (EVTT0 ) is detected, 16-bit timer/even t counter T starts counting, and outputs a one-shot pulse from the TOT01 pin. Instead of the external trigger input (EVTT0), a software tr igger can also be generated to output the pulse. When the software trigger is used, the TOT00 pin outputs the active leve l while the 16-bit counter is c ounting, and the inactive level when the counter is stopped (waiting for a trigger). Figure 9-25. Configuration in One-Shot Pulse Output Mode CCR0 buffer registerTT0CE bit TT0CCR0 register 16-bit counter TT0CCR1 register CCR1 buffer register Clear Match signal Match signal INTTT0CC0 signal Output controller (RS-FF) Output controller (RS-FF) TOT01 pin INTTT0CC1 signal TOT00 pin Count clock selectionInternal count clock Count start control Edge detector Note 2 Software trigger generation Edge detector Note 3 Transfer Transfer S R S R TENC00 pin Note 1 (external trigger input/ external event count input) Notes 1. Because the TENC00 pin functions as both an exte rnal trigger input and a external event count input, the external event count input function (EVTT0) cannot be used when using an external trigger input. 2. Edge detector for external trigger input. Set by the TT0IOC2.TT0ETS1 and TT0IOC2.TT0ETS0 bits. 3. Edge detector for external event count input. Set by the TT0IOC2.TT0 EES1 and TT0IOC2.TT0EES0 bits.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 522 of 1817 Sep 19, 2011 Figure 9-26. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal TOT00 pin output TT0CCR1 register INTTT0CC1 signal TOT01 pin output External trigger input (TENC00 pin input) D1 D1 D1 D0 D0 Delay (D1) Active level width 0 − D1 + 1) Delay Active level width 0 − D1 + 1) Delay Active level width 0 − D1 + 1) When the TT0CE bit is set to 1, 16-bit timer/event counter T waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOT01 pin. After the one- shot pulse is output, the 16-bit counter is cleared to 0000H, stops counting, and waits for a trigger. When the trigger is generated again, the 16-bit counter starts counting from 0000H. If a trigger is generated again while the one-shot pulse is being output, it is ignored. The output delay period and active level width of the one-shot pulse can be calculated as follows. Output delay period = (Set value of TT0CCR1 register) × Count clock cycle Active level width = (Set value of TT0CCR0 register − Set value of TT0CCR1 register + 1) × Count clock cycle The compare match interrupt request signa l (INTTT0CC0) is generated the next time the 16-bit counter counts after its count value matches the va lue of the CCR0 buffer register. The compar e match interrupt reques t signal (INTTT0CC1) is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The valid edge of an external trigger input (TENC00 pin) or setting the software trigger (TT0CTL1.TT0EST bit) to 1 is used as the trigger.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 523 of 1817 Sep 19, 2011 Figure 9-27. Setting of Registers in One-Shot Pulse Output Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) 0/1 0 0 0 0 TT0CTL0 Select count clockNote 0: Stops counting 1: Enables counting 0/1 0/1 0/1 TT0CKS2 TT0CKS1 TT0CKS0TT0CE Note The setting is invalid when the TT0CTL1.TT0EEE bit = 1. (b) TMT0 control register 1 (TT0CTL1) 0 0/1 0 0 0TT0CTL1 Generates software trigger when 1 is written 011 TT0MD2 TT0MD1 TT0MD0TT0EEETT0EST 0, 0, 1, 1: One-shot pulse output mode TT0MD3 (c) TMT0 I/O control register 0 (TT0IOC0) 0 0 0 0 0/1 TT0IOC0 0: Disables TOT00 pin output 1: Enables TOT00 pin output Setting of TOT00 pin output level while waiting for external trigger 0: Low level 1: High level 0: Disables TOT01 pin output 1: Enables TOT01 pin output Setting of TOT01 pin output level while waiting for external trigger 0: Low level 1: High level 0/1 0/1 0/1 TT0OE1 TT0OL0 TT0OE0TT0OL1 TOT01 pin output 16-bit counter

• When TT0OL1 bit = 0 TOT01 pin output 16-bit counter
• When TT0OL1 bit = 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 524 of 1817 Sep 19, 2011 Figure 9-27. Setting of Registers in One-Shot Pulse Output Mode (2/2) (d) TMT0 I/O control register 2 (TT0IOC2) 0000 0 TT0IOC2 Select valid edge of external trigger input (TENC00 pin)Note 0 0/1 0/1 TT0EES0 TT0ETS1 TT0ETS0TT0EES1 Note Set the valid edge selection of the unused alternate external input signals to “No edge detection”. (e) TMT0 counter read buffer register (TT0CNT) The value of the 16-bit counter can be read by reading the TT0CNT register. (f) TMT0 capture/compare regist ers 0 and 1 (TT0CCR0 and TT0CCR1) If D0 is set to the TT0CCR0 register and D 1 to the TT0CCR1 register, the active level width and output delay period of the one-shot pulse are as follows. Active level width = (D0 − D1 + 1) × Count clock cycle Output delay period = D1 × Count clock cycle Remark TMT0 control register 2 (TT0 CTL2), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control register 3 (TT0IOC3), TMT0 option register 0 (TT0OPT0), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW) are not used in the one-shot pulse output mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 525 of 1817 Sep 19, 2011 (1) Operation flow in one-shot pulse output mode Figure 9-28. Software Processing Flow in One-Shot Pulse Output Mode START STOP D10 D11 D00 D01 D00 D10 D11 D01 Setting of TT0CCR0, TT0CCR1 registers <2> TT0CCR0, TT0CCR1 register setting change flow TT0CE bit = 1 TT0CE bit = 0 Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits) TT0CTL1 register, TT0IOC0 register, TT0IOC2 register, TT0CCR0 register, TT0CCR1 register Initial setting of these registers is performed before setting the TT0CE bit to 1. The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting starts (TT0CE bit = 1). Trigger wait status Count operation is stopped <1> Count operation start flow <3> Count operation stop flow FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal TT0CCR1 register INTTT0CC1 signal TOT01 pin output External trigger input (TENC00 pin input) As rewriting the TT0CCRn register immediately forwards to the CCRn buffer register, rewriting immediately after the generation of the INTTT0CC0 signal is recommended. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 526 of 1817 Sep 19, 2011 (2) Operation timing in one-shot pulse output mode (a) Note on rewriti ng TT0CCRn register If the value of the TT0CCRn register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When an overflow may occur, stop counting and then change the set value. Remark n = 0, 1 D10 D11 D00 D01 D00 D10 D10 D10 D01 D11 D00 D00 FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal TOT00 pin output TT0CCR1 register INTTT0CC1 signal TOT01 pin output External trigger input (TENC00 pin input) Delay (D10) Active level width (D00 − D10 + 1) Delay 10) Active level width 00 − D10 + 1) Delay (10000H + D 11) Active level width 01 − D11 + 1) When the TT0CCR0 register is rewritten from D00 to D01 and the TT0CCR1 register from D10 to D11 where D00 > D01 and D 10 > D 11, if the TT0CCR1 register is rewritten when the count value of the 16-bit counter is greater than D11 and less than D 10 and if the TT0CCR0 register is rewritt en when the count value is greater than D 01 and less than D00, each set value is reflected as soon as the register has been rewritten and compared with the count value. The counter counts up to FFFFH and t hen counts up again from 0000H. When the count value matches D11, the counter generates the INTTT0CC1 signal and asserts the TOT01 pin. When the count value matches D01, the counter generates the INTTT0CC0 signal, deasserts the TOT01 pin, and stops counting. Therefore, the counter may output a pu lse with a delay period or active per iod different from that of the one- shot pulse that is originally expected.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 527 of 1817 Sep 19, 2011 (b) Generation timing of compare match interrupt request signal (INTTT0CC1) The generation timing of the IN TTT0CC1 signal in the on e-shot pulse output mode is different from INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the co unt value of the 16-bit counter matches the value of the TT0CCR1 register. Count clock 16-bit counter TT0CCR1 register TOT01 pin output INTTT0CC1 signal D1 − 2D 1 − 1D 1 D1 + 1 D 1 + 2 Note Note Note The timing is actually delayed by one operating clock (fXX). Usually, the INTTT0CC1 signal is generated the next time the 16-bit counter counts up after its count value matches the value of the TT0CCR1 register. In the one-shot pulse output mode, however, it is gene rated one clock earlier. This is because the timing is changed to match the timing the output signal of the TOT01 pin changes.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 528 of 1817 Sep 19, 2011

9.6.5 PWM output mode (TT0 MD3 to TT0MD0 bits = 0100)

In the PWM output mode, a PWM waveform is output from the TOT01 pin when the TT0CTL0.TT0CE bit is set to 1. In addition, a square wave with the set value of the TT0CCR0 register + 1 as half its cycle is output from the TOT00 pin. Figure 9-29. Configuration in PWM Output Mode CCR0 buffer registerTT0CE bit TT0CCR0 register 16-bit counter TT0CCR1 register CCR1 buffer register Clear Match signal Match signal INTTT0CC0 signal Output controller (RS-FF) Output controller TOT01 pin INTTT0CC1 signal TOT00 pin Transfer Transfer S R Count clock selection Internal count clock TENC00 pin (external event count input) Edge detectorNote Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 529 of 1817 Sep 19, 2011 Figure 9-30. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register CCR0 buffer register INTTT0CC0 signal TOT00 pin output TT0CCR1 register CCR1 buffer register INTTT0CC1 signal TOT01 pin output D10 D00 D00 D01 D00 D10 D11 D10 D11 D01 D10 D10 D00 D00 D11D11 D01 D01 Active period (D10) Cycle (D00 + 1) Inactive period (D00 - D10 + 1) When the TT0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a PWM waveform from the TOT01 pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TT0CCR1 register) × Count clock cycle Cycle = (Set value of TT0CCR0 register + 1) × Count clock cycle Duty factor = (Set value of TT0CCR1 register)/(Set value of TT0CCR0 register + 1) The PWM waveform can be changed by rewriting the TT0CCRn register while the counter is operating. The newly written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The compare match interrupt request signa l (INTTT0CC0) is generated the next time the 16-bit counter counts after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is clear ed to 0000H. The compare match interrupt request signal (INTTT0CC1) is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TT0CCRn register is transferred to the CCRn buffer register when t he count value of the 16-bit counter matches the value of the CCRn buffer register and the 16-bit counter is cleared to 0000H. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 530 of 1817 Sep 19, 2011 Figure 9-31. Setting of Registers in PWM Output Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) 0/1 0 0 0 0 TT0CTL0 Select count clockNote 0: Stops counting 1: Enables counting 0/1 0/1 0/1 TT0CKS2 TT0CKS1 TT0CKS0TT0CE Note The setting is invalid when the TT0CTL1.TT0EEE bit = 1. (b) TMT0 control register 1 (TT0CTL1) 0 0 0/1 0 0 TT0CTL1 100 TT0MD2 TT0MD1 TT0MD0TT0EEETT0EST 0, 1, 0, 0: PWM output mode 0: Operates on count clock selected by TT0CKS0 to TT0CKS2 bits 1: Counts with external event count input signal TT0MD3 (c) TMT0 I/O control register 0 (TT0IOC0) 0 0 0 0 0/1 TT0IOC0 0: Disables TOT00 pin output 1: Enables TOT00 pin output Setting of TOT00 pin output level before count operation 0: Low level 1: High level 0: Disables TOT01 pin output 1: Enables TOT01 pin output Setting of TOT01 pin output level before count operation 0: Low level 1: High level 0/1 0/1 0/1 TT0OE1 TT0OL0 TT0OE0TT0OL1 TOT01 pin output 16-bit counter

• When TT0OL1 bit = 0 TOT01 pin output 16-bit counter
• When TT0OL1 bit = 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 531 of 1817 Sep 19, 2011 Figure 9-31. Register Setting in PWM Output Mode (2/2) (d) TMT0 I/O control register 2 (TT0IOC2) 0 0 0 0 0/1 TT0IOC2 Select valid edge of external event count input (TENC00 pin). 0/1 0 0 TT0EES0 TT0ETS1 TT0ETS0TT0EES1 (e) TMT0 counter read buffer register (TT0CNT) The value of the 16-bit counter can be read by reading the TT0CNT register. (f) TMT0 capture/compare regist ers 0 and 1 (TT0CCR0 and TT0CCR1) If D0 is set to the TT0CCR0 register and D 1 to the TT0CCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) × Count clock cycle Active level width = D1 × Count clock cycle Remark TMT0 control register 2 (TT0 CTL2), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control register 3 (TT0CTL3), TMT0 option register 0 (TT0OPT0), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW) are not used in the PWM output mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 532 of 1817 Sep 19, 2011 (1) Operation flow in PWM output mode Figure 9-32. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register CCR0 buffer register INTTT0CC0 signal TOT00 pin output TT0CCR1 register CCR1 buffer register INTTT0CC1 signal TOT01 pin output D10 D00 D00 D01 D00 D00 D10 D10 D11 D10 D10 D10 D11 D10 D01 D00 D10 D10 D00 D10 D00D11D11 D01 D01 D01

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 533 of 1817 Sep 19, 2011 Figure 9-32. Software Processing Flow in PWM Output Mode (2/2) TT0CE bit = 1 Setting of TT0CCR0 register Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits) TT0CTL1 register, TT0IOC0 register, TT0IOC2 register, TT0CCR0 register, TT0CCR1 register Initial setting of these registers is performed before setting the TT0CE bit to 1. The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting is enabled (TT0CE bit = 1). Writing the same value (same as preset value of the TT0CCR1 register) to the TT0CCR1 register is necessary only when the set cycle is changed. When the counter is cleared after setting, the value of the TT0CCRn register is transferred to the CCRn buffer register. START Setting of TT0CCR1 register <1> Count operation start flow <2> TT0CCR0, TT0CCR1 register setting change flow (cycle only) Setting of TT0CCR0 register When the counter is cleared after setting, the values of compare register n are transferred to the CCRn buffer register in a batch. Setting of TT0CCR1 register <4> TT0CCR0, TT0CCR1 register setting change flow (cycle and duty) Only writing of the TT0CCR1 register must be performed when the set duty factor is changed. When the counter is cleared after setting, the value of compare register n is transferred to the CCRn buffer register. Setting of TT0CCR1 register <3> TT0CCR0, TT0CCR1 register setting change flow (duty only) TT0CE bit = 0 Counting is stopped. STOP <5> Count operation stop flow Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 534 of 1817 Sep 19, 2011 (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TT0CCR1 register last. Rewrite the TT0CCRn register after writing the TT0CCR1 register after the INTTT0CC1 signal is detected. FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register CCR0 buffer register TT0CCR1 register CCR1 buffer register TOT01 pin output INTTT0CC0 signal D10 D00 D00 D01 D00 D10 D11 D10 D11 D01 D10 D10 D00 D00 D11D11 D01 D01 To transfer data from the TT0CCRn register to the CCRn buffer register, the TT0CCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TT0CCR0 register and then set the active level width to the TT0CCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TT0CCR0 register, and then write the same value (same as preset value of the TT0CCR1 register) to the TT0CCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TT0CCR1 register has to be set. After data is written to the TT0CCR1 register, the value written to the TT0CCRn register is transferred to the CCRn buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TT0CCR0 or TT0CCR1 register again after writing the TT0CCR1 register once, do so after the INTTT0CC0 signal is generated. Otherwise, the value of the CCRn buffer regist er may become undefined because the timing of transferring data from the TT0CCRn register to the CCRn buffer register conflicts with writing the TT0CCRn register. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 535 of 1817 Sep 19, 2011 (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TT0CCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTT0CC0 and INTTT0CC1 signals are generated after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register. Count clock 16-bit counter TT0CE bit TT0CCR0 register TT0CCR1 register INTTT0CC0 signal INTTT0CC1 signal TOT01 pin output D00 0000H D00 0000H D00 0000H D00 − 1D 000000FFFF 0000 D 00 − 1D 00 00000001 L Note Note Note Note Note The timing is actually delayed by one operating clock (fXX). To output a 100% waveform, set a value of (set value of TT0CCR0 register + 1) to the TT0CCR1 register. If the set value of the TT0CCR0 register is FFFFH, 100% output cannot be produced. D00 D00 + 1 D00 D00 + 1 D00 D00 + 1 D000000FFFF 0000 D 00 00000001 Count clock 16-bit counter TT0CE bit TT0CCR0 register TT0CCR1 register INTTT0CC0 signal INTTT0CC1 signal TOT01 pin output D00 − 1D 00 − 1 Note Note Note The timing is actually delayed by one operating clock (fXX).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 536 of 1817 Sep 19, 2011 (c) Generation timing of compare match interrupt request signal (INTTT0CC1) The timing of generation of the INTTT0CC1 signal in the PWM output mode differs from the timing of INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the co unt value of the 16-bit counter matches the value of the TT0CCR1 register. Count clock 16-bit counter TT0CCR1 register TOT01 pin output INTTT0CC1 signal D1 − 2D 1 − 1D 1 D1 + 1 D 1 + 2 Note Note Note The timing is actually delayed by one operating clock (fXX). Usually, the INTTT0CC1 signal is gene rated in synchronization with the next count-up after the count value of the 16-bit counter matches the value of the TT0CCR1 register. In the PWM output mode, however, it is generated one cl ock earlier. This is because the timing is changed to match the timing at which the output signal of the TOT01 pin changes.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 537 of 1817 Sep 19, 2011

9.6.6 Free-running timer mode ( TT0MD3 to TT0MD0 bits = 0101)

In the free-running timer mode, 16-bit timer/event counter T starts counting when the TT0CTL0.TT0CE bit is set to 1. At this time, the TT0CCR0 and TT0CCR1 registers can be used as compare registers or capture registers, depending on the setting of the TT0OPT0.TT0CCS0 and TT0OPT0.TT0CCS1 bits. Figure 9-33. Configuration in Free-Running Timer Mode TT0CCR0 register (capture) TT0CE bit TT0CCR1 register (compare) 16-bit counter TT0CCR1 register (compare) TT0CCR0 register (capture) Output controller TT0CCS0, TT0CCS1 bits (capture/compare selection) TOT00 pinNote 1 output Output controller TOT01 pinNote 1 output Edge detectorNote 2 Count clock selection Edge detectorNote 3 Edge detectorNote 4 TENC00 pin (external event count input) TIT00 pinNote 1 (capture trigger input) TIT01 pinNote 1 (capture trigger input) Internal count clock INTTT0OV signal INTTT0CC1 signal INTTT0CC0 signal Notes 1. Because the capture trigger input pins (TIT00, TIT01) also f unction as the timer output pins (TOT00, TOT01), the timer output functions cannot be used when using an capture trigger input. 2. Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits. 3. Set by the TT0IOC1.TT0IS1 and TT0IOC1.TT0IS0 bits. 4. Set by the TT0IOC1.TT0IS3 and TT0IOC1.TT0IS2 bits.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 538 of 1817 Sep 19, 2011

• Compare operation When the TT0CE bit is set to 1, 16-bit timer/event counter T starts counting, and the output signal of the TOT0n pin is inverted. When the count value of the 16-bit counter later matches the set value of the TT0CCRn register, a compare match interrupt request signal (INTTT0CCn) is generated, and the output signal of the TOT0n pin is inverted. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTT0OV) at the next clock, is cl eared to 0000H, and continues counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Confirm that the overflow flag is set to 1 and then clear it to 0 by executing the CLR instruction via software. The TT0CCRn register can be rewritten whil e the counter is operating. If it is re written, the new value is reflected at that time by anytime write, and compared with the count value. Figure 9-34. Basic Timing in Free-Running Timer Mode (Compare Function) FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal TOT00 pin output TT0CCR1 register INTTT0CC1 signal TOT01 pin output INTTT0OV signal TT0OVF bit D00 D01 D10 D11 D00 D10 D10 D11 D11 D11 D00 D01 D01 Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 539 of 1817 Sep 19, 2011

• Capture operation When the TT0CE bit is set to 1, the 16- bit counter starts counting. When the valid edge input to the TIT0n pin is detected, the count value of the 16-bit counter is stored in the TT0CCRn register, and a capture interrupt request signal (INTTT0CCn) is generated. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTT0OV) at the next clock, is cl eared to 0000H, and continues counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Confirm that the overflow flag is set to 1 and then clear it to 0 by executing the CLR instruction via software. Figure 9-35. Basic Timing in Free-Running Timer Mode (Capture Function) FFFFH 16-bit counter 0000H TT0CE bit TIT00 pin input TT0CCR0 register INTTT0CC0 signal TIT01 pin input TT0CCR1 register INTTT0CC1 signal INTTT0OV signal TT0OVF bit D00 D01 D02 D03 D10 D00 D01 D02 D03 D11 D12 D13 D10 D11 D12 D13 Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 540 of 1817 Sep 19, 2011 Figure 9-36. Register Setting in Free-Running Timer Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) 0/1 0 0 0 0 TT0CTL0 Select count clockNote 0: Stops counting 1: Enables counting 0/1 0/1 0/1 TT0CKS2 TT0CKS1 TT0CKS0TT0CE Note The setting is invalid wh en the TT0CTL1.TT0EEE bit = 1 (b) TMT0 control register 1 (TT0CTL1) 0 0 0/1 0 0 TT0CTL1 101 TT0MD2 TT0MD1 TT0MD0TT0EEETT0EST TT0MD3 0, 1, 0, 1: Free-running timer mode 0: Operates with count clock selected by TT0CKS0 to TT0CKS2 bits 1: Counts on external event count input signal (c) TMT0 I/O control register 0 (TT0IOC0) 0 0 0 0 0/1 TT0IOC0 0: Disables TOT00 pin output 1: Enables TOT00 pin output Setting of TOT00 pin output level before count operation 0: Low level 1: High level 0: Disables TOT01 pin output 1: Enables TOT01 pin output Setting of TOT01 pin output level before count operation 0: Low level 1: High level 0/1 0/1 0/1 TT0OE1 TT0OL0 TT0OE0TT0OL1 (d) TMT0 I/O control register 1 (TT0IOC1) 0 0 0 0 0/1 TT0IOC1 Select valid edge of TIT00 pin input Select valid edge of TIT01 pin input 0/1 0/1 0/1 TT0IS2 TT0IS1 TT0IS0TT0IS3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 541 of 1817 Sep 19, 2011 Figure 9-36. Register Setting in Free-Running Timer Mode (2/2) (e) TMT0 I/O control register 2 (TT0IOC2) 0 0 0 0 0/1 TT0IOC2 Select valid edge of external event count input (TENC00 pin) 0/1 0 0 TT0EES0 TT0ETS1 TT0ETS0TT0EES1 (f) TMT0 option register 0 (TT0OPT0) 0 0 0/1 0/1 0 TT0OPT0 Overflow flag Specifies if TT0CCR0 register functions as capture or compare register 0: Compare register 1: Capture register Specifies if TT0CCR1 register functions as capture or compare register 0: Compare register 1: Capture register 0 0 0/1 TT0CCS0 TT0OVFTT0CCS1 (g) TMT0 counter read buffer register (TT0CNT) The value of the 16-bit counter can be read by reading the TT0CNT register. (h) TMT0 capture/compare regist ers 0 and 1 (TT0CCR0 and TT0CCR1) These registers function as capt ure registers or compare regist ers depending on the setting of the TT0OPT0.TT0CCSn bit. When the registers function as capture registers, they store the count value of the 16-bit counter when the valid edge input to the TIT0n pin is detected. When the registers function as compare registers and when D a is set to the TT0CCRn register, the INTTT0CCn signal is generated when the counter reaches (D a + 1), and the output signals of the TOT00 and TOT01 pins are inverted. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 542 of 1817 Sep 19, 2011 (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 9-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) D00 D01 D10 D11 D00 D10 D10 D11 D11 D11 D00 D01 D01 Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction <1> <3> FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal TOT00 pin output TT0CCR1 register INTTT0CC1 signal TOT01 pin output INTTT0OV signal TT0OVF bit

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 543 of 1817 Sep 19, 2011 Figure 9-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) TT0CE bit = 1 Read TT0OPT0 register (check overflow flag). Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits) TT0CTL1 register, TT0IOC0 register, TT0IOC2 register, TT0OPT0 register, TT0CCR0 register, TT0CCR1 register Initial setting of these registers is performed before setting the TT0CE bit to 1. The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting starts (TT0CE bit = 1). START Execute instruction to clear TT0OVF bit (CLR TT0OVF). <1> Count operation start flow <2> Overflow flag clear flow TT0CE bit = 0 Counter is initialized and counting is stopped by clearing TT0CE bit to 0. STOP <3> Count operation stop flow TT0OVF bit = 1 No Yes

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 544 of 1817 Sep 19, 2011 (b) When using capture/compare register as capture register Figure 9-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TT0CE bit TIT00 pin input TT0CCR0 register INTTT0CC0 signal TIT01 pin input TT0CCR1 register INTTT0CC1 signal INTTT0OV signal TT0OVF bit D000000 0000 D01 D02 D03 D10 D00 D01 D02 D03 D11 D12 D100000 D 11 D12 0000 Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction <3><1> <2> <2>

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 545 of 1817 Sep 19, 2011 Figure 9-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) TT0CE bit = 1 Read TT0OPT0 register (check overflow flag). Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits) TT0CTL1 register, TT0IOC1 register, TT0OPT0 register Initial setting of these registers is performed before setting the TT0CE bit to 1. The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting starts (TT0CE bit = 1). START Execute instruction to clear TT0OVF bit (CLR TT0OVF). <1> Count operation start flow <2> Overflow flag clear flow TT0CE bit = 0 Counter is initialized and counting is stopped by clearing TT0CE bit to 0. STOP <3> Count operation stop flow TT0OVF bit = 1 No Yes

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 546 of 1817 Sep 19, 2011 (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter T is used as an interval timer with the TT0CCRn register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTT0CCn signal has been detected. FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal TOT00 pin output TT0CCR1 register INTTT0CC1 signal TOT01 pin output D00 D01 D02 D03 D04 D05 D10 D00 D11 D01 D12 D04 D13 D02 D03 D11D10 D12 D13 D14 Interval period (D10 + 1) Interval period (10000H + D11 − D10) Interval period (10000H + D12 − D11) Interval period (10000H + D13 − D12) Interval period (D00 + 1) Interval period (10000H + D01 − D00) Interval period (D02 − D01) Interval period (10000H + D03 − D02) Interval period (10000H + D04 − D03) When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, t he value of the corresponding TT0CCRn register must be re-set in the interrupt servicing that is executed when the INTTT0CCn signal is detected. The set value for re-setting the TT0CCRn register can be calculated by the following expression, where “D a” is the interval period. Compare register default value: Da − 1 Value set to compare register second and subsequent time: Previous set value + Da (If the calculation resu lt is greater than FFFFH, subtract 10000H fr om the result and set this value to the register.)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 547 of 1817 Sep 19, 2011 (b) Pulse width measurement with capture register When pulse width measurement is performed with the TT0 CCRn register used as a capture register, software processing is necessary for reading the capture register each time t he INTTT0CCn signal has been detected and for calculating an interval. 0000H D 00 D01 D02 D03 D04 D10 D00 D11 D01 D12 D04 D13 D02 D03 D100000H D 11 D12 D13 FFFFH 16-bit counter 0000H TT0CE bit TIT00 pin input TT0CCR0 register INTTT0CC0 signal TIT01 pin input TT0CCR1 register INTTT0CC1 signal INTTT0OV signal TT0OVF bit Pulse interval (D00) Pulse interval (10000H + D01 - D00) Pulse interval (D02 − D01) Pulse interval (10000H + D03 − D02) Pulse interval (10000H + D04 − D03) Pulse interval (D10) Pulse interval (10000H + D11 − D10) Pulse interval (10000H + D12 − D11) Pulse interval (10000H + D13 − D12) Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction When executing pulse width measurement in the free-running timer mode, two pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calcul ated by reading the value of the TT0CCRn register in synchronization with the INTTT0CCn signal, and calcul ating the difference between the read value and the previously read value.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 548 of 1817 Sep 19, 2011 (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH 16-bit counter 0000H TT0CE bit TIT00 pin input TT0CCR0 register TIT01 pin input TT0CCR1 register INTTT0OV signal TT0OVF bit D00 D01 D10 D11 D10 D00 D11 D01 The following problem may occur when two pulse widths are measured in the free-running timer mode. <1> Read the TT0CCR0 register (setting of t he default value of the TIT00 pin input). <2> Read the TT0CCR1 register (setting of t he default value of the TIT01 pin input). <3> Read the TT0CCR0 register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D 01 − D00). <4> Read the TT0CCR1 register. Read the overflow flag. Because the flag is cleared in <3>, 0 is read. Because the overflow flag is 0, the pulse width can be calculated by (D 11 − D10) (incorrect). When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. Use software when using two capture registers. An example of how to use software is shown below.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 549 of 1817 Sep 19, 2011 (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TT0CE bit INTTT0OV signal TT0OVF bit TT0OVF0 flagNote TIT00 pin input TT0CCR0 register TT0OVF1 flagNote TIT01 pin input TT0CCR1 register D10 D11 D00 D01 D10 D00 D11 D01 Note The TT0OVF0 and TT0OVF1 flags are set on the internal RAM by software. <1> Read the TT0CCR0 register (setting of t he default value of the TIT00 pin input). <2> Read the TT0CCR1 register (setting of t he default value of the TIT01 pin input). <3> An overflow occurs. Set the TT0OVF0 and TT0OVF1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> Read the TT0CCR0 register. Read the TT0OVF0 flag. If the TT0OVF0 flag is 1, clear it to 0. Because the TT0OVF0 flag is 1, the pulse width can be calculated by (10000H + D01 − D00). <5> Read the TT0CCR1 register. Read the TT0OVF1 flag. If the TT0OVF1 flag is 1, clear it to 0 (the TT0OVF0 flag is cleared in <4>, and the TT0OVF1 flag remains 1). Because the TT0OVF1 flag is 1, the pulse width can be calculated by (10000H + D 11 − D 10) (correct). <6> Same as <3>

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 550 of 1817 Sep 19, 2011 (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TT0CE bit INTTT0OV signal TT0OVF bit TT0OVF0 flagNote TIT00 pin input TT0CCR0 register TT0OVF1 flagNote TIT01 pin input TT0CCR1 register D10 D11 D00 D01 D10 D00 D11 D01 Note The TT0OVF0 and TT0OVF1 flags are set on the internal RAM by software. <1> Read the TT0CCR0 register (setting of t he default value of the TIT00 pin input). <2> Read the TT0CCR1 register (setting of t he default value of the TIT01 pin input). <3> An overflow occurs. Nothing is done by software. <4> Read the TT0CCR0 register. Read the overflow flag. If the overflow flag is 1, set only the TT0OVF1 flag to 1, and clear the overflow flag to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 − D00). <5> Read the TT0CCR1 register. Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read. Read the TT0OVF1 flag. If the TT0OVF1 flag is 1, clear it to 0. Because the TT0OVF1 flag is 1, the pulse width can be calculated by (10000H + D 11 − D 10) (correct). <6> Same as <3>

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 551 of 1817 Sep 19, 2011 (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below. Example of incorrect processing when capture trigger interval is long FFFFH 16-bit counter 0000H TT0CE bit TIT0n pin input TT0CCRn register INTTT0OV signal TT0OVF bit Da0 Da1 Da0 Da1 1 cycle of 16-bit counter Pulse width The following problem may occur when long pulse width is measured in the free-running timer mode. <1> Read the TT0CCRn register (setting of t he default value of the TIT0n pin input). <2> An overflow occurs. Nothing is done by software. <3> An overflow occurs a second time. Nothing is done by software. <4> Read the TT0CCRn register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pu lse width can be calculated by (10000H + D a1 − D a0) (incorrect). Actually, the pulse width must be (20000H + D a1 − Da0) because an overflow occurs twice. Remark n = 0, 1 If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. An example of how to use software is shown next.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 552 of 1817 Sep 19, 2011 Example when capture trigger interval is long FFFFH 16-bit counter 0000H TT0CE bit TIT0n pin input TT0CCRn register INTTT0OV signal TT0OVF bit Overflow counterNote Da0 Da1 1H0H 2H 0H Da0 Da1 1 cycle of 16-bit counter Pulse width Note The overflow counter is set arbitrarily by software on the internal RAM. <1> Read the TT0CCRn register (setting of t he default value of the TIT0n pin input). <2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> An overflow occurs a second time. Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> Read the TT0CCRn register. Read the overflow counter. → When the overflow counter is “N”, t he pulse width can be calculated by (N × 10000H + D a1 – D a0). In this example, the pulse width is (20000H + D a1 – Da0) because an overflow occurs twice. Clear the overflow counter (0H). Remark n = 0, 1 (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TT0OVF bit to 0 with the CLR instruction after reading the TT0OVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TT0OPT0 register after reading the TT0OVF bit when it is 1.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 553 of 1817 Sep 19, 2011

9.6.7 Pulse width measurement mode (TT0MD3 to TT0MD0 bits = 0110)

In the pulse width measurement mode, 16-bit timer/event counter T starts counting when the TT0CTL0.TT0CE bit is set to 1. Each time the valid edge input to the TIT0n pin has been detected, the count value of the 16-bit counter is stored in the TT0CCRn register, and the 16-bit counter is cleared to 0000H. The interval of the valid edge can be measured by reading the TT0CCRn register after a capture interrupt request signal (INTTT0CCn) occurs. As shown in Figure 9-39, select either the TIT00 or TIT01 pin as the capture trigger input pin and set the unused pins to “No edge detection” by using the TT0IOC1 register. Figure 9-39. Configuration in Pulse Width Measurement Mode TT0CCR0 register (capture) TT0CE bit TT0CCR1 register (capture) Edge detectorNote 1 Count clock selection Edge detectorNote 2 Edge detectorNote 3 TENC00 pin (external event count input) TIT00 pin (capture trigger input) TIT01 pin (capture trigger input) Internal count clock Clear INTTT0OV signal INTTT0CC0 signal INTTT0CC1 signal 16-bit counter Notes 1. Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits. 2. Set by the TT0IOC1.TT0IS1 and TT0IOC1.TT0IS0 bits. 3. Set by the TT0IOC1.TT0IS3 and TT0IOC1.TT0IS2 bits.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 554 of 1817 Sep 19, 2011 Figure 9-40. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TT0CE bit TIT0n pin input TT0CCRn register INTTT0CCn signal INTTT0OV signal TT0OVF bit D00000H D 1 D2 D3 Cleared to 0 by CLR instruction Remark n = 0, 1 When the TT0CE bit is set to 1, the 16-bit counter starts count ing. When the valid edge input to the TIT0n pin is later detected, the count value of the 16-bit counter is stored in the TT0CCRn r egister, the 16-bit counter is cleared to 0000H, and a capture interrupt request signal (INTTT0CCn) is generated. The pulse width is calculated as follows. Pulse width = Captured value × Count clock cycle If the valid edge is not input to the TI T0n pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt request signal (INTTT0OV) is generated at the next count clock, and the counter is cl eared to 0000H and continues counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction via software. If the overflow flag is set to 1, the pulse width can be calculated as follows. Pulse width = (10000H × TT0OVF bit set (1) count + Captured value) × Count clock cycle Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 555 of 1817 Sep 19, 2011 Figure 9-41. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) 0/1 0 0 0 0 TT0CTL0 Select count clockNote 0: Stops counting 1: Enables counting 0/1 0/1 0/1 TT0CKS2 TT0CKS1 TT0CKS0TT0CE Note Setting is invalid when the TT0CTL1.TT0EEE bit = 1. (b) TMT0 control register 1 (TT0CTL1) 0 0 0/1 0 0 TT0CTL1 110 TT0MD2 TT0MD1 TT0MD0TT0EEETT0EST TT0MD3 0, 1, 1, 0: Pulse width measurement mode 0: Operates with count clock selected by TT0CKS0 to TT0CKS2 bits 1: Counts on external event count input signal (c) TMT0 I/O control register 1 (TT0IOC1) 0 0 0 0 0/1 TT0IOC1 Select valid edge of TIT00 pin input Select valid edge of TIT01 pin input 0/1 0/1 0/1 TT0IS2 TT0IS1 TT0IS0TT0IS3 (d) TMT0 I/O control register 2 (TT0IOC2) 0 0 0 0 0/1 TT0IOC2 Select valid edge of external event count input (TENC00 pin) 0/1 0 0 TT0EES0 TT0ETS1 TT0ETS0TT0EES1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 556 of 1817 Sep 19, 2011 Figure 9-41. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMT0 option register 0 (TT0OPT0) 0000 0 TT0OPT0 Overflow flag 0 0 0/1 TT0CCS0 TT0OVFTT0CCS1 (f) TMT0 counter read buffer register (TT0CNT) The value of the 16-bit counter can be read by reading the TT0CNT register. (g) TMT0 capture/compare regist ers 0 and 1 (TT0CCR0 and TT0CCR1) These registers store the count va lue of the 16-bit counter when the valid edge input to the TIT00 and TIT01 pins is detected. Remark TMT0 control register 2 (TT0 CTL2), TMT0 I/O control register 0 (TT0IOC0), TMT0 I/O control register 3 (TT0IOC3), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW) are not used in the pulse width measurement mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 557 of 1817 Sep 19, 2011 (1) Operation flow in pul se width measurement mode Figure 9-42. Software Processing Flow in Pulse Width Measurement Mode <1> <2> TT0CE bit = 1 TT0CE bit = 0 Register initial setting TT0CTL0 register (TT0CKS0 to TT0CKS2 bits), TT0CTL1 register, TT0IOC1 register, TT0IOC2 register, TT0OPT0 register Initial setting of these registers is performed before setting the TT0CE bit to 1. The TT0CKS0 to TT0CKS2 bits can be set at the same time as when counting starts (TT0CE bit = 1). The counter is initialized and counting is stopped by clearing the TT0CE bit to 0. START STOP <1> Count operation start flow <2> Count operation stop flow FFFFH 16-bit counter 0000H TT0CE bit TIT00 pin input TT0CCR0 register INTTT0CC0 signal D00000H 0000H D1 D2

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 558 of 1817 Sep 19, 2011 (2) Operation timing in pul se width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TT0OVF bit to 0 with the CLR instruction after reading the TT0OVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TT0OPT0 register after reading the TT0OVF bit when it is 1.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 559 of 1817 Sep 19, 2011

9.6.8 Triangular-wave PWM output mode (TT0MD3 to TT0MD0 bits = 0111)

In the triangular-wave PWM output mode, a triangular-wav e PWM waveform is output fr om the TOT01 pin when the TT0CTL0.TT0CE bit is set to 1. A PWM waveform that is inverted when the count value of the 16-bit counter matches t he value of the CCR0 buffer register and when the 16-bit counter is set to 0000H is output from the TOT00 pin. Figure 9-43. Configuration in Triangular-Wave PWM Output Mode CCR0 buffer registerTT0CE bit TT0CCR0 register 16-bit counter TT0CCR1 register CCR1 buffer register Clear Match signal Match signal INTTT0CC0 signal Output controller (RS-FF) Output controller TOT01 pin INTTT0CC1 signal TOT00 pin Transfer Transfer S R Count clock selectionTENC00 pin (external event count input) Internal count clock Edge detectorNote Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 560 of 1817 Sep 19, 2011 Figure 9-44. Basic Timing in Triangular-Wave PWM Output Mode FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register CCR0 buffer register INTTT0CC0 signal TOT00 pin output TT0CCR1 register CCR1 buffer register INTTT0CC1 signal TOT01 pin output INTTT0OV signal D10 D00 D01 D02 D00 D01 D10 D11 D12 D10 D11 D12 D02 D10 D00 D12 D12 D11 D11 D01 D02 The 16-bit counter is cleared from FFFFH and 0000H and starts counting when the TT0CE bit is set to 1. The triangular PWM waveform is output from the TOT01 pin. In the triangular-wave PWM output mode, the counter count s up or down. When the 16-bit counter reaches 0000H while it is counting down, an overflow interrupt request signal (IN TTT0OV) is generated. At this time, the TT0OPT0.TT0OVF bit is not set to 1. If the count value of the 16-bit counter matches the value of the CCR0 buffer register while the counter is counting up, a compare match interrupt request signal (INTTT0CC0) is generated. The counting direction is changed from up to down when the value of the 16-bit counter matches that of the CCR0 buffer register, and from down to up when the counter is cleared to 0000H. The PWM waveform can be changed by rewriting the TT0CCRn register during operation. To change the PWM waveform during operation, write the TT0CCR1 register last. The cycle of the triangular PWM waveform is set by the TT0CCR0 register and its duty factor is set by the TT0CCR1 register. Set a value to the TT0CCR0 register in a range of “0 ≤ TT0CCR0 ≤ FFFEH”. The rewritten value is reflected when the 16-bit counter reaches 0000H while it is counting down. Even when changing only the cycle of the PWM waveform, fi rst set a period to the TT0CCR0 register, and then write the same value (value same as that set to the TT0CCR1 register) to the TT0CCR1 register. To transfer data from the TT0CCRn register to the CCRn buffer register, the data must be written to the TT0CCR1 register (n = 0, 1).

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9.6.9 Encoder count function

The encoder count function includ es an encoder compare mode (see 9.6.10 Encoder compare mode (TT0MD3 to TT0MD0 bits = 1000)). Mode TT0CCR0 Register TT0CCR1 Register Encoder compare mode Compare only Compare only (1) Count-up/-down control Counting up or down by the 16-bit counter is controlled by the phase of input encoder signals (TENC00 and TENC01) and settings of the TT0CTL2.TT0UDS1 and TT0CTL2.TT0UDS0 bits. When the encoder count function is used, the internal count clock and external event count input (TENC00) cannot (2) Setting initial value of 16-bit counter The initial count value set to the TT0TCW register when the TT0CTL2.TT0ECC bit = 0 is transferred to the 16-bit counter immediately after the counter starts its operation (TT0CTL0.TT0CE bit = 0 → 1), and the counter starts the operation after it detects the valid edge of the encoder input signal (TENC00 or TENC01). (3) Basic operation The TT0CCRn register generates a compare match interrup t request signal (INTTT0CCn) when the count value of the 16-bit counter matches the value of the CCRn buffer register. (4) Clear operation The 16-bit counter is cleared when the following conditions are satisfied in the encoder compare mode.

• When the value of the 16-bit counter matches the value of the compare register (the TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits are set)
• When the edge of the encoder clear input signal (TECR0 ) is detected (the TT0ECS1 and TT0ECS0 bits are set when the TT0IOC3.TT0SCE bit = 0)
• When the clear level condition of the TENC00, TENC01, and TECR0 pins is detected (the TT0ZCL, TT0BCL, and TT0ACL bits are set when the TT0SCE bit = 1) Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 562 of 1817 Sep 19, 2011 (5) Controlling bits of TT0CTL2 register The setting of the TT0CTL2 register in the encoder compare mode is shown below. Table 9-8. Setting of TT0CTL2 Register Mode TT0UDS1, TT0UDS0 Bits (<1>) TT0ECM1 Bit (<2>) TT0ECM0 Bit (<2>) TT0LDE Bit (<3>) Counter Clear (Target Compare Register) Transfer to Counter 0 − 0 Possible 0 − TT0CCR0 Possible Note

0 Invalid TT0CCR1 −

Can be set to 00, 01, 10, or 11.

1 Invalid TT0CCR0,

Note The counter can operate in a range from 0000H to the set value of the TT0CCR0 register. (a) Outline of each bit <1> The TT0UDS1 and TT0UDS0 bits identify the counting di rection (up or down) of the 16-bit counter by the phase input from the encoder input pin (TENC00 or TENC01). <2> The TT0ECM1 and TT0ECM0 bits control clearing of the 16-bit counter when its count value matches the value of the CCR0 or CCR1 buffer register. <3> The TT0LDE bit controls a function to transfer the set value of the TT0CCR0 register to the 16-bit counter when the counter underflows. The TT0LDE bit is valid only when the TT0ECM1 and TT0ECM0 bits are 00 and 01, respectively. It is invalid when these bits are set to any other values.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 563 of 1817 Sep 19, 2011 (b) Detailed explanation of each bit <1> TT0UDS1 and TT0UDS0 bits: Count-up/-down selection Whether the 16-bit counter is count ing up or down is identified by t he phase input from the TENC00 or TENC01 pin and depending on the settings of the TT0UDS1 and TT0UDS0 bits. These bits are valid only in the encoder compare mode.

• When TT0UDS1 and TT0UDS0 bits = 00 TENC00 Pin TENC01 Pin Count Operation Rising edge Falling edge Both edges High level Count down Rising edge Falling edge Both edges Low level Count up Remark Detecting the edge of the TENC00 pin is s pecified by the TT0IOC3.TT0EIS1 and TT0EIS0 bits. Figure 9-45. Operation Example (When Valid Edge of TENC00 Pin Is Specified to Be Rising Edge and No Edge Is Specified as Valid Edge of TENC01 Pin) 0007H TENC00 TENC01 16-bit counter 0006H Count down Count up 0005H 0004H 0005H 0006H 0007H

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• When TT0UDS1 and TT0UDS0 bits = 01 TENC00 Pin TENC01 Pin Count Operation Rising edge Falling edge Low level Both edges Rising edge Falling edge High level Both edges Count down Rising edge Falling edge Both edges High level Rising edge Falling edge Both edges Low level Count up Simultaneous input to TENC00 and TENC01 pins Counter does not perform count operation but holds value immediately before. Remark Detecting the edges of the TENC00 and TENC01 pins is specified by the TT0IOC3.TT0EIS1 and TT0IOC3.TT0EIS0 bits. Figure 9-46. Operation Example (When Rising Edge Is Specified as Valid Edges of TENC00 and TENC01 Pins) 0006H TENC00 TENC01 16-bit counter 0007H 0008H Count up Value held Count down 0007H 0006H 0005H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 567 of 1817 Sep 19, 2011 <2> TT0ECM1 and TT0ECM0 bits: Timer/counter clear function upon match of the compare register The 16-bit counter performs its count operation in ac cordance with the set value of the TT0ECM1 and TT0ECM0 bits when the count value of the counter matches the value of the CCRn buffer register.

• When TT0ECM1 and TT0ECM0 bits = 00 The 16-bit counter is not cleared when its count value matches the value of the CCRn buffer register.
• When TT0ECM1 and TT0ECM0 bits = 01 The 16-bit counter performs a count operation under the following condition when its count value matches the value of the CCR0 buffer register. Next Count Operation Description Count up 16-bit counter is cleared to 0000H. Count down Count value of 16-bit counter is counted down.
• When TT0ECM1 and TT0ECM0 bits = 10 The 16-bit counter performs a count operation under the following condition when its count value matches the value of the CCR1 buffer register. Next Count Operation Description Count up Count value of 16-bit counter is counted up. Count down 16-bit counter is cleared to 0000H.
• When TT0ECM1 and TT0ECM0 bits = 11 The 16-bit counter performs a count operation under the following condition when its count value matches the value of the CCR0 buffer register. Next Count Operation Description Count up 16-bit counter is cleared to 0000H. Count down Count value of 16-bit counter is counted down. The 16-bit counter performs a count operation under the following condition when its count value matches the value of the CCR1 buffer register. Next Count Operation Description Count up Count value of 16-bit counter is counted up. Count down 16-bit counter is cleared to 0000H.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 568 of 1817 Sep 19, 2011 <3> TT0LDE bit: Transfer function of the set value of the TT0CCR0 register to the 16-bit counter when the counter underflows When the TT0LDE bit = 1, the set value of the TT0CCR0 register can be transferred to the 16-bit counter when the counter underflows. The TT0LDE bit is valid only in the encoder compare mode.

• Count operation in range from 0000H to set value of the TT0CCR0 register If the 16-bit counter performs a count operation when the TT0LDE bit = 1 and TT0ECM1 and TT0ECM0 bits = 01, and when the count value of the counter matches the set value of the CCR0 buffer register when the TT0ECM0 bit = 1, the 16-bit counter is cleared to 0000H if the next count operation is counting up. If the 16-bit counter underflows when the TT0LDE bit = 1, the set value of the TT0CCR0 register is transferred to the counter. Therefore, the counter can operate in a range from 0000H to the set value of the TT0CCR0 register in which the upper-limit count value is the set value of the TT0CCR0 register and the lower-limit value is 0000H. Figure 9-51. Operation Example (Count Operation in Range from 0000H to Set Value of TT0CCR0 Register) 16-bit counter is cleared to 0000H. Set value of TT0CCR0 register is transferred to 16-bit counter. 16-bit counter underflows. Count up Count down Count value of 16-bit counter matches value of CCR0 buffer register. 16-bit counter Set value of TT0CCR0 register (N) 0000H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 569 of 1817 Sep 19, 2011 Figure 9-52. Operation Timing (Count Operation in Range from 0000H to Set Value of TT0CCR0 Register) Peripheral clock TT0ESF bit TT0CNT register TT0CCR0 register INTTT0CC0 signal TT0EOF bit TT0EUF bit INTTT0OV signal Count timing signal N 0002H H = down counting L 0001H 0000H N N − 1 Remark TT0ESF bit: Bit 0 of TMT0 option register 1 (TT0OPT1) TT0EOF bit: Bit 1 of TMT0 option register 1 (TT0OPT1) TT0EUF bit: Bit 2 of TMT0 option register 1 (TT0OPT1)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 570 of 1817 Sep 19, 2011 (6) Function to clear counter to 0000H by encoder clear signal (TECR0 pin) The 16-bit counter can be cleared to 0000H by the input signal of the TECR0 pin in two ways which are selected by the TT0IOC3.TT0SCE bit. The TT0SCE bit also cont rols, depending on its setting, the TT0IOC3.TT0ZCL, The counter can be cleared by the methods described below only in the encoder compare mode. Table 9-9. Relationship Between TT0SCE Bit and TT0ZCL, TT0BCL, TT0ACL, TT0ECS1, and TT0ECS0 Bits Clearing Method TT0SCE Bit TT0ZCL Bit TT0BC L Bit TT0ACL Bit TT0ECS1, TT0ECS0 Bits <1> 0 Invalid Invalid Invalid Valid <2> 1 Valid Valid Valid Invalid (a) Clearing method <1>: By detecting edge of en coder clear signal (TECR0 pin) (TT0SCE bit = 0) When the TT0SCE bit = 0, the 16-bit counter is cleared to 0000H in synchronization with the peripheral clock if the valid edge of the TECR0 pin specif ied by the TT0ECS1 and TT0ECS0 bits is detected. At this time, an encoder clear interrupt request signal (INTTT0EC) is generated. When the TT0SCE bit = 0, the settings of the TT0ZCL, TT0BCL, and TT0ACL bits is invalid. Figure 9-53. Operation Example (When TT0SCE Bit = 0, TT0ECS1 and TT0ECS0 Bits = 01, and TT0UDS1 and TT0UDS0 Bits = 11) Peripheral clock TT0CNT register Encoder input (TENC00 pin input) Encoder input (TENC01 pin input) Encoder clear input (TECR0 pin input) Count timing signal N + 1N Counter clear 0000H 0001H 0002H INTTT0EC interrupt

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 571 of 1817 Sep 19, 2011 (b) Clearing method <2>: By detecting clear level condition of the TENC00, TENC01, and TECR0 pins (TT0SCE bit = 1) When the TT0SCE bit = 1, the 16-bit counter is cleared to 0000H if the clear level condition of the TECR0, TENC00, or TENC01 pin specified by the TT0ZCL, TT0BCL, and TT0ACL bits is detected. At this time, the encoder clear interrupt request si gnal (INTTT0EC) is not generated. The settings of the TT0ECS1 and TT0ECS0 bits is invalid when the TT0SCE bit = 1. Table 9-10. 16-bit Counter Clearing Condition When TT0SCE Bit = 1 Clear Level Condition Setting Input Level of Encoder Pin TT0ZCL Bit TT0BCL Bit TT0ACL Bit TECR0 Pin TENC01 Pin TENC00 Pin 0 0 0 L L L 0 0 1 L L H 0 1 0 L H L 0 1 1 L H H 1 0 0 H L L 1 0 1 H L H 1 1 0 H H L 1 1 1 H H H Caution The 16-bit counter is cleare d to 0000H when the clear level c ondition of the TT0ZCL, TT0BCL, and TT0ACL bits match the input level of the TECR0, TENC01, or TENC00 pin.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 572 of 1817 Sep 19, 2011 Figure 9-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (1/3) (i) If inputting the high level to the TECR0 pin lags behind inputting the low level to the TENC01 pin while the counter is counting up, the counter is cleared after it counts up. Peripheral clock Clear signal TT0CNT register TT0CCR0 register INTTT0CC0 signal TT0CCR1 register INTTT0CC1 signal TT0CCR0 register INTTT0CC0 signal Encoder input (TENC00 pin input) Encoder input (TENC01 pin input) Encoder clear input (TECR0 pin input) Count timing signal N + 1N Compare match interrupt request signal is not generated. H L H 0000H N + 1 (when TT0CCR0 register is set to N + 1) N (when TT0CCR0 register is set to N) 0000H (when TT0CCR1 register is set to 0000H)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 573 of 1817 Sep 19, 2011 Figure 9-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (2/3) (ii) If the high level is input to the TECR0 pin at the same time as the low level is input to the TECN01 pin while the counter is counting up, the counter is cleared without counting up. Peripheral clock Clear signal TT0CNT register Encoder input (TENC00 pin input) Encoder input (TENC01 pin input) Encoder clear input (TECR0 pin input) Count timing signal 0000HN H L H (iii) If the high level is input to the TECR0 pin earlier than the low level is input to the TENC01 pin while the counter is counting up, the counter is cleared without counting up. Peripheral clock Clear signal TT0CNT register Encoder input (TENC00 pin input) Encoder input (TENC01 pin input) Encoder clear input (TECR0 pin input) Count timing signal 0000HN H L H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 574 of 1817 Sep 19, 2011 Figure 9-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (3/3) (iv) If the high level is input to the TECR0 pin later than the low level is input to the TENC01 pin while the counter is counting up, the counter is cleared after it counts up. Peripheral clock Clear signal TT0CNT register TT0CCR0 register INTTT0CC0 signal TT0CCR1 register INTTT0CC1 signal TT0CCR0 register INTTT0CC0 signal Encoder input (TENC00 pin input) Encoder input (TENC01 pin input) Encoder clear input (TECR0 pin input) Count timing signal N − 1N Compare match interrupt request signal is not generated. H L H 0000H N − 1 (when TT0CCR0 register is set to N − 1) N (when TT0CCR0 register is set to N) 0000H (when TT0CCR1 register is set to 0000H) If the counter is cleared in this way, a miscount does not occur even if inputting the signal to the TECR0 pin is late, because the clear level condition of the TECR0, TENC01, and TENC00 pins is set and the 16-bit counter is cleared to 0000H when the clear level condition is detected.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 575 of 1817 Sep 19, 2011 (7) Notes on using encoder count function (a) If compare match interrupt is not gene rated immediately after operation is started If a value which is the same as that of the TT0TCW r egister is set to the TT0CCR0 or TT0CCR1 register and the counter operation is st arted when the TT0CTL2.TT0ECC bit = 0, an d if the count value (TT0TCW) of the 16-bit counter matches the value of the CCRn buffer regi ster immediately after the start of the operation, the match is masked and the compare match interrupt request signal (INTTT0CCn) is not generated (n = 0, 1). In addition, the 16-bit counter is not cleared to 0000H by setting the TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits. TT0CNT register TT0CCR1 register INTTT0CC1 signal Count clock TT0CE bit Peripheral clock Count timing signal Count up/down signal TT0TCW − 1FFFFH H = Count down TT0TCW TT0TCW Match does not occur. 16-bit counter is not cleared.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 576 of 1817 Sep 19, 2011 (b) If overflow does not occur i mmediately after start of operation If the count operation is resumed when the TT0CTL2.TT0ECC bit = 1, the 16-bit counter does not overflow if its count value that has been held is FFFFH and if the next count operation is counting up. After the counter starts operating an d counts up from a count value (value of TT0TCW register = FFFFH), the counter overflows from FFFFH to 0000H. However, det ection of the overflow is masked, the overflow flag (TT0EOF) is not set, and the overflow interrupt request signal (INTTT0OV) is not generated. TT0ECC bit TT0CNT register TT0TCW register INTTT0OV signal TT0EOF bit Count clock TT0CE bit Peripheral clock Count timing signal Count up/down signal 0000HFFFFH L = Count up Hold H TT0TCW = FFFFH FFFFH Overflow does not occur.

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9.6.10 Encoder compare mode (TT0MD3 to TT0MD0 bits = 1000)

In the encoder compare mode, the enc oder is controlled by using both the TT0CCR0 and TT0CCR1 registers as compare registers and the input pins for encoder count function (TENC00, TENC01, and TECR0). In this mode, the 16-bit counter can be cleared to 0000H in three ways: when the count va lue of the counter matches the value of the CCRn buffer register (compare match interrupt request si gnal (INTTT0CCn) is generated), when the edge of the encoder clear input (TECR0 pin) is detected, and when the clear level co ndition of TENC00, TENC01, and TECR0 pins is detected. When the 16-bit counter underflows, the set value of the TT0CCR0 register can be transferred to the counter. (1) Encoder compare mode operation flow Figure 9-55. Encoder Compare Mode Operation Flow TT0CE bit = 1 TT0CE bit = 0 Encoder compare mode operation processing Register initial setting TT0CTL1 register (TT0MD3 to TT0MD0 bits), TT0CTL2 register (TT0LDE, TT0ECM1, TT0ECM0, TT0UDS1, TT0UDS0 bits), TT0IOC3 register (TT0SCE, TT0ZCL, TT0ACL, TT0BCL, TT0ECS1, TT0ECS0, TT0EIS1, TT0EIS0 bits), TT0CCR0, TT0CCR1 registers, TT0TCW register START END Operation end? Yes No : See Figure 9-56 Encoder Compare Mode Operation Processing.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 578 of 1817 Sep 19, 2011 Figure 9-56. Encoder Compare Mode Operation Processing Count up 16-bit counter cleared and started. INTTT0CC0 signal generated. 16-bit counter cleared and started. 16-bit counter cleared and started. INTTIEC0 signal generated. TT0ECM0 = 1? (TT0CTL2) Yes No TECR0 edge detected? Yes NoClear level condition of TENC00, TENC01, and TECR0 pins detected? Yes A A No TT0SCE = 1? (TT0IOC3) Yes No Count value matches CCR0 register value? Yes No No 16-bit counter cleared and started. INTTT0CC1 signal generated. TT0CCR0 set value transferred to 16-bit counter. INTTT0CC0 signal generated. Valid edge of TENC00, TENC01 detected? Yes No Which count operation? Count down TT0ECM1 = 1? (TT0CTL2) Yes No Yes TT0LDE = 1? (TT0CTL2) Yes No Underflow? Yes No Count value matches CCR1 register value?

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 579 of 1817 Sep 19, 2011 (2) Encoder compare mode operation timing (a) Basic timing 1 [Register setting conditions]

• TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 01 The 16-bit counter is cleared to 0000H when its count value matches the value of the CCR0 buffer register.
• TT0CTL2.TT0LDE bit = 1 The set value of the TT0CCR0 register is transferred to the 16-bit counter when it overflows.
• TT0IOC3.TT0SCE bit = 0, and TT0IOC3.TT 0ECS1 and TT0IOC3.TT0ECS0 bits = 00 Specification of clearing the 16-bit counter when the ed ge of the encoder clear input signal (TECR0 pin) is detected (no edge specified) CM00CM00 TT0CCR0 register CCR0 buffer register INTTT0CC0 signal TT0CCR1 register CCR1 buffer register INTTT0CC1 signal TT0ESF bit INTTT0OV signal TT0EOF bit TT0EUF bit 0000H FFFFH TT0CNT register Clear Clear Clear Transfer CM00 CM01 CM00 CM10 CM11 CM10 L CM11 CM12 CM12 CM01 CM02 CM02 CM03 CM03 CM03 CM03 CM11 CM02 CM12 CM01

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 580 of 1817 Sep 19, 2011 When the 16-bit counter starts operating (TT0CE bit = 0 → 1), the set value of the TT0TCW register is transferred to the counter and the 16-bit counter starts operating. When the count value of the counter matches the valu e of the CCR0 buffer register, the compare match interrupt request signal (INTTT0CC0) is generated. Be cause the TT0ECM0 bit = 1, the 16-bit counter is cleared to 0000H if the next count operation is counting up. When the count value of the 16-bit co unter matches the value of the CCR1 buffer register, the compare match interrupt request signal (INTTT0CC1) is generated. Because the TT0ECM1 bit = 0, the 16-bit counter is not cleared to 0000H when its value matches that of the CCR1 buffer register. When the TT0LDE bit = 1 and TT0ECM0 bit = 1, the counter can operate in a range from 0000H to the set value of the TT0CCR0 register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 581 of 1817 Sep 19, 2011 (b) Basic timing 2 [Register setting condition]

• TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 00 The 16-bit counter is not cleared even when its count value matches the value of the CCRn buffer register (a = 0, 1).
• TT0CTL2.TT0LDE bit = 0 The set value of the TT0CCR0 register is not transferred to the 16-bit counter after the counter underflows.
• TT0IOC3.TT0SCE bit = 0, and TT0IOC3.TT 0ECS1 and TT0IOC3.TT0ECS0 bits = 00 Specification of clearing the 16-bit counter when the ed ge of the encoder clear input signal (TECR0 pin) is detected (no edge specified) CM10 CM00 CM00 TT0CCR0 register CCR0 buffer register INTTT0CC0 signal TT0CCR1 register CCR1 buffer register INTTT0CC1 signal TT0ESF bit INTTT0OV signal TT0EOF bit TT0EUF bit 0000H FFFFH TT0CNT register Underflow Overflow CM00 CM01 CM00 CM10 CM11 CM10 CM11 CM12 CM12 CM01 CM02 CM02 CM11 CM02 CM12 CM01 CM01

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 582 of 1817 Sep 19, 2011 When the 16-bit counter starts operating (TT0CE bit = 0 → 1), the set value of the TT0TCW register is transferred to the 16-bit counter and the counter starts operating. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTT0CC0) is generated. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTT0CC1) is generated. The 16-bit counter is not cleared to 0000H even when it s count value matches the value of the CCRn buffer register because the TT0ECM1 and TT0ECM0 bits = 00 (n = 0, 1).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 583 of 1817 Sep 19, 2011 (c) Basic timing 3 [Register setting condition]

• TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 11 The count value of the 16- bit counter is cleared to 0000H when it s value matches the value of the CCR0 buffer register. The count value of the 16- bit counter is cleared to 0000H when it s value matches the value of the CCR1 buffer register.
• Setting of the TT0CTL2.TT0LDE bit is invalid.
• TT0IOC3.TT0SCE bit = 0, and TT0IOC3.TT 0ECS1 and TT0IOC3.TT0ECS0 bits = 00 Specification of clearing the 16-bit counter when the ed ge of the encoder clear input signal (TECR0 pin) is detected (no edge specified) CM00 CM01 CM01 CM11 CM10 TT0CCR0 register CCR0 buffer register INTTT0CC0 signal TT0CCR1 register CCR1 buffer register INTTT0CC1 signal TT0ESF bit INTTT0OV signal TT0EOF bit TT0EUF bit 0000H FFFFH TT0CNT register Clear ClearClear Clear Underflow Underflow Underflow Overflow CM00 CM01 CM00 CM10 CM11 CM10 CM11 CM12 CM12 CM01 CM02 CM02 CM12 CM12 CM02

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) R01UH0290EJ0300 Rev.3.00 Page 584 of 1817 Sep 19, 2011 When the 16-bit counter starts operating (TT0CE bit = 0 → 1), the set value of the TT0TCW register is transferred to the 16-bit counter and the counter starts operating. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTT0CC0) is generated. At this time, the 16-bit counter is cleared to 0000H if the next count operation is counting up. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTT0CC1) is generated. At this time, the 16-bit counter is cleared to 0000H if the next count operation is counting down.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) R01UH0290EJ0300 Rev.3.00 Page 585 of 1817 Sep 19, 2011 CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) The V850ES/JH3-E and V850ES/JJ3-E have four TMM channels (TMMn).

10.1 Overview

TMMn has the following features.

• Interval function
• 8 clocks selectable
• 16-bit counter × 1 (The 16-bit counter cannot be read during timer count operation.)
• Compare register × 1 (The compare register cannot be written during timer counter operation.)
• Compare match interrupt × 1 TMMn supports only the clear & start mode. The free-running timer mode is not supported. Remark n = 0 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) R01UH0290EJ0300 Rev.3.00 Page 586 of 1817 Sep 19, 2011

10.2 Configuration

TMMn includes the following hardware. Table 10-1. Configuration of TMMn Item Configuration Timer register 16-bit counter Register TMMn compare register 0 (TMnCMP0) Control register TMMn control register 0 (TMnCTL0) Figure 10-1. Block Diagram of TMMn TMnCTL0 Internal bus fXX/2 fXX/4 fXX/8 fXX/16 fXX/64 fXX/256 fXX/512 fXX/1024 Controller 16-bit counter Match Clear INTTMnEQ0 TMnCMP0TMnCE TMnCKS2 TMnCKS1TMnCKS0 Selector Note Note In TMM0, fXX, fXX/2, fXX/4, fXX/64, fXX/512, fXX/1024, fR, fXT Remark f XX: Main clock frequency f R: Internal oscillation clock frequency f XT: Subclock frequency n = 0 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) R01UH0290EJ0300 Rev.3.00 Page 587 of 1817 Sep 19, 2011 (1) 16-bit counter This is a 16-bit counter that counts the internal clock. The 16-bit counter cannot be read or written. (2) TMMn compare register 0 (TMnCMP0) The TMnCMP0 register is a 16-bit compare register. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Software can be used to always write the same value to the TMnCMP0 register. Rewriting the TMnCMP0 register is prohibited when the TMnCTL0.TMnCE bit = 1. TMnCMP0 (n = 0 to 3) 12 10 8 6 4 2 After reset: 0000H R/W Address: TM0CMP0 FFFFFA84H, TM1CMP0 FFFFFA94H, TM2CMP0 FFFFFAA4H, TM3CMP0 FFFFFAB4H 14 013 11 9 7 5 315 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) R01UH0290EJ0300 Rev.3.00 Page 588 of 1817 Sep 19, 2011

10.3 Registers

(1) TMMn control register (TMnCTL0) The TMnCTL0 register is an 8-bit register that controls the TMMn operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Software can be used to always write the same value to the TMnCTL0 register. Remark n = 0 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) R01UH0290EJ0300 Rev.3.00 Page 589 of 1817 Sep 19, 2011 TMMn operation disabled (16-bit counter reset asynchronously). Operation clock application stopped. TMMn operation enabled. Operation clock application started. TMMn operation started. Internal clock control and internal circuit reset for TMMn are performed asynchronously using the TMnCE bit. When the TMnCE bit is cleared to 0, the internal clock of TMMn is disabled (fixed to low level) and 16-bit counter is reset asynchronously. TMnCETMnCTL0 (n = 0 to 3) 0 0 0 0 TMnCKS2 TMnCKS1 TMnCKS0 65 43 21 After reset: 00H R/W Address: TM0CTL0 FFFFFA80H, TM1CTL0 FFFFFA90H, TM2CTL0 FFFFFAA0H, TM3CTL0 FFFFFAB0H TMnCE Internal clock operation enable/disable specification 0<7> Count clock selection (m = 1 to 3) Count clock selection (m = 0) TMmCKS2 TMmCKS1 f XX/2 fXX/4 fXX/8 fXX/16 fXX/64 fXX/256 fXX/512 fXX/1024 fXX = 50 MHz 40.0 ns 80.0 ns 160 ns 320 ns 1.28 s 5.12 s 10.24 s 20.48 s fXX = 48 MHz 41.7 ns 83.3 ns 167 ns 333 ns 1.33 s 5.33 s 10.67 s 21.33 s fXX = 32 MHz 62.5 ns 125 ns 250 ns 500 ns 2.00 s 8.00 s 16.0 s 32.0 s f XX fXX/2 fXX/4 fXX/64 fXX/512 fXX/1024 fR/8 fXT TMmCKS2 TMmCKS1 TMmCKS0 fXX = 50 MHz 20.0 ns 40.0 ns 80.0 ns 1.28 s 10.24 s 20.48 s 36.36 s 30.52 s fXX = 48 MHz 20.8 ns 41.7 ns 83.3 ns 1.33 s 10.7 s 21.33 s 36.36 s 30.52 s fXX = 32 MHz 31.3 ns 62.5 ns 125 ns 2.00 s 16.0 s 32.0 s 36.36 s 30.52 s TMmCKS0 μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ μ Cautions 1. Set the TMnCKS2 to TMnCKS0 bits when the TMnCE bit = 0. When changing the value of TMnCE from 0 to 1, it is not possible to set the value of the TMnCKS2 to TMnCKS0 bits simultaneously. 2. Be sure to clear bits 3 to 6 to “0”. Remark f XX: Main clock frequency f R: Internal oscillation clock frequency f XT: Subclock frequency

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) R01UH0290EJ0300 Rev.3.00 Page 590 of 1817 Sep 19, 2011

10.4 Operation

Caution Do not set the TMnCMP0 register to FFFFH.

10.4.1 Interval timer mode

In the interval timer mode, an interrupt request signal (I NTTMnEQ0) is generated at the specified interval if the TMnCTL0.TMnCE bit is set to 1. Figure 10-2. Configuration of Interval Timer 16-bit counter TMnCMP0 registerTMnCE bit Count clock selection Clear Match signal INTTMnEQ0 signal Remark n = 0 to 3 Figure 10-3. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter 0000H TMnCE bit TMnCMP0 register INTTMnEQ0 signal D D D D D Interval (D + 1) Interval (D + 1) Interval (D + 1) Interval (D + 1) Remark n = 0 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) R01UH0290EJ0300 Rev.3.00 Page 591 of 1817 Sep 19, 2011 When the TMnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. When the count value of the 16-bit counter matches the value of the TMnCMP0 register, the 16-bit counter is cleared to 0000H and a compare match interrupt request signal (INTTMnEQ0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TMnCMP0 register + 1) × Count clock cycle Figure 10-4. Register Setting for Interval Timer Mode Operation (a) TMMn control register 0 (TMnCTL0) 0/1 0 0 0 0 TMnCTL0 0/1 0/1 0/1 TMnCKS2 TMnCKS1 TMnCKS0TMnCE 0: Stop counting 1: Enable counting Select count clock (b) TMMn compare register 0 (TMnCMP0) If the TMnCMP0 register is set to D, the interval is as follows. Interval = (D + 1) × Count clock cycle Remark n = 0 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) R01UH0290EJ0300 Rev.3.00 Page 592 of 1817 Sep 19, 2011 (1) Interval timer mode operation flow Figure 10-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TMnCE bit TMnCMP0 register INTTMnEQ0 signal D D D D <1> <2> TMnCE bit = 1 TMnCE bit = 0 Register initial setting TMnCTL0 register (TMnCKS0 to TMnCKS2 bits) TMnCMP0 register The initial setting of these registers is performed before setting the TMnCE bit to 1. The TMnCKS0 to TMnCKS2 bits cannot be set at the same time when counting has been started (TMnCE bit = 1). The counter is initialized and counting is stopped by clearing the TMnCE bit to 0. START STOP <1> Count operation start flow <2> Count operation stop flow Remark n = 0 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) R01UH0290EJ0300 Rev.3.00 Page 593 of 1817 Sep 19, 2011 (2) Interval timer mode operation timing Caution Do not set the TMnCMP0 register to FFFFH. (a) Operation if TMnCMP0 register is set to 0000H If the TMnCMP0 register is set to 0000H, the INTTMnEQ0 signal is generated at each count clock. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter TMnCE bit TMnCMP0 register INTTMnEQ0 signal 0000H Interval time Count clock cycle FFFFH 0000H 0000H 0000H 0000H Interval time Count clock cycle Remark n = 0 to 3 (b) Operation if TMnCMP0 register is set to N If the TMnCMP0 register is set to N, the 16-bit counte r counts up to N. The counter is cleared to 0000H in synchronization with the next count-up timing and the INTTMnEQ0 signal is generated. FFFFH 16-bit counter 0000H TMnCE bit TMnCMP0 register INTTMnEQ0 signal N Interval time (N + 1) × count clock cycle Interval time (N + 1) × count clock cycle Interval time (N + 1) × count clock cycle N Remark n = 0 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) R01UH0290EJ0300 Rev.3.00 Page 594 of 1817 Sep 19, 2011

10.4.2 Cautions

(1) It takes the 16-bit counter up to the following time to start counting after the TMnCTL0.TMnCE bit is set to 1, depending on the count clock selected. (n = 0) Selected Count Clock Maximum Time Before Counting Start fXX 2/f XX fXX/2 3/f XX fXX/4 6/f XX fXX/64 128/f XX fXX/512 1024/f XX fXX/1024 2048/f XX fR/8 16/f R fXT 2/f XT (n = 1 to 3) Selected Count Clock Maximum Time Before Counting Start fXX/2 4/f XX fXX/4 6/f XX fXX/8 12/f XX fXX16 32/f XX fXX/64 128/f XX fXX/256 512/f XX fXX/512 1024/f XX fXX/1024 2048/f XX (2) Rewriting the TMnCMP0 and TMnCTL0 regist ers is prohibited while TMMn is operating. If these registers are rewritten while the TMnC E bit is 1, the operation cannot be guaranteed. If they are rewritten by mistake, clear the TM nCTL0.TMnCE bit to 0, and re-set the registers. Remark n = 0 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 595 of 1817 Sep 19, 2011 CHAPTER 11 MOTOR CONTROL FUNCTION

11.1 Functional Overview

Timer AB1 (TAB1) and the TAB1 option (TAB1OP0) can be used as an inverter function that controls a motor. It performs a tuning operation with timer AA4 (TAA4) and A/D conversion of the A/D converter can be started when the value of TAB1 matches the value of TAA4. The following operations can be performed as motor control functions.

• 6-phase PWM output function with 16-bit accuracy
• Timer tuning operation function (tunable with TAA4)
• Cycle setting function (cycle can be changed dur ing operation of crest or valley interrupt)
• Compare register rewriting: Anytime rewrite, batch rewrite, or intermittent rewrite (selectable during TAB1 operation)
• Interrupt and transfer culling functions
• Dead-time setting function
• A/D trigger timing function of the A/D converter
• 0% output and 100% output available
• 0% output and 100% output selectable by crest interrupt and valley interrupt
• Forcible output stop function
• When valid edge detected by external pin input (TOAB1OFF , TOAA1OFF)
• When main clock oscillation stop detected by clock monitor function

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 596 of 1817 Sep 19, 2011

11.2 Configuration

The motor control function consists of the following hardware. Item Configuration Timer register Dead-time counters Compare register TAB1 dead-time compare register (TAB1DTC register) Control registers TAB1 option register 1 (TAB1OPT1) TAB1 option register 2 (TAB1OPT2) TAB1 I/O control register 3 (TAB1IOC3) High-impedance output control register 0 (HZA0CTL0) High-impedance output control register 1 (HZA0CTL1)

• 6-phase PWM output can be produced with dead time by using the output of TAB1 (TOAB11, TOAB12, TOAB13).
• The output level of the 6-phase PWM output can be set individually.
• The 16-bit timer/counter of TAB1 c ounts up/down triangular waves. W hen the timer/counter underflows and when a cycle match occurs, an interrupt is generated. Interrupt generation, however, can be suppressed up to 31 times.
• TAA4 can execute counting at the same time as TAB1 (tim er tuning operation function). TAA4 can be set in three ways as it can generate an A/D trigger source (TABTADT0 ) and two types of interrupts: a TAB1 underflow interrupt (INTTAB1OV) and a cycle match interrupt (INTTAB1CC0).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 597 of 1817 Sep 19, 2011 Figure 11-1. Block Diagram of Motor Control

• Carrier
• 3-phase PWM generation TAB1
• 6-phase PWM generation with dead time from 3-phase PWM
• Culling control
• A/D trigger selection TAB1 option
• A/D trigger generation in synchronization with TAB1 TAA4
• PWM generation TAA1
• Interrupt control INTC High-impedance output controller TOAB1T1 TOAB1B1 TOAB1T2 TOAB1B2 TOAB1T3 TOAB1B3 TOAA11 TOAB10 INTP18/TOAB1OFF Valley interrupt (INTTAB1OV) Crest interrupt (INTTAB1CC0) Edge detection Edge detection Noise elimination INTP06/TOAA1OFFNoise elimination A/D trigger of A/D converter

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 598 of 1817 Sep 19, 2011 Figure 11-2. TAB1 Option TOAB1T1 High-impedance output controller TOAB1B1 TABnDTC (10-bit dead-time value) TOAB11Note (internal signal) TOAB12Note (internal signal) TOAB13Note (internal signal) TAB1 Channel 2 Dead-time counter 1 (10 bits) Edge detection Channel 1 Positive phase F/F Active setting Clear Negative phase F/F Active setting Level control Output control Level control Output control Counter Mask count buffer Interrupt culling circuit A/D trigger generator 1 Number of masks Crest/valley interrupt selection Culling enable Mask control Internal bus TOAB1T2 TOAB1B2 Channel 3 INTTAA4CC0 INTTAA4CC1 TAA4 INTTAB1OV INTTAB1CC0 INTC TOAB1T3 TOAB1B3 TABTADT0 A/D trigger selection (TAB1OPT2 register) Up/down selection TOAB10 TOAB10 A/D converterTABTICCn0 TABTIOVn INTTAB1OV_BASE Note TOAB11, TOAB12, and TOAB13 functi on alternately as output pins.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 599 of 1817 Sep 19, 2011 (1) TAB1 dead-time compare register (TAB1DTC) The TAB1DTC register is a 10-bit compare register that specifies the dead-time value. Rewriting this register is prohibited when the TAB1CTL0.TAB1CE bit = 1. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution When generating a dead-time period, set the TAB1DTC register to 1 or higher. Note, when the operation is stopped (TAB1CTL0 .TAB1CE bit = 0), a dead-time period is not generated, so the output levels of the TOAB1T1 to TOAB1T3 and TOAB1B1 to TOAB1B3 pins are in their default states. Therefore, for the protection of the system, take measures such as making the TOAB1T1 to TOAB1T3 and TOAB1B1 to TOAB1B3 pins go into a high-impedance state before stopping operation, or setting the output levels of the pins before switching port modes. When a dead-time period is not need ed, set the TAB1DTC register to 0. TAB1DTC 000000 TAB1DTC9 to TAB1DTC0 10 9 After reset: 0000H R/W Address: FFFFF584H 15 0 (2) Dead-time counters 1 to 3 The dead-time counters are 10-bit counters that count dead time. These counters are cleared or count up at the rising or falling edge of the TOAB1m output signal of TAB1, and are cleared or stopped when their count va lue matches the value of the TAB1DTC register. The count clock of these counters is the same as that set by the TAB1CTL0.TAB1CKS2 to TAB1CTL0.TAB1CKS0 bits of TAB1. dead-time width narrowing function (TAB1OPT2.TAB1DTM bit = 1). 2. m = 1 to 3

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11.3 Control Registers

(1) TAB1 option register 1 (TAB1OPT1) The TAB1OPT1 register is an 8-bit register that contro ls the interrupt request signal generated by the timer AB1 option function. This register can be rewritten when the TAB1CTL0.TAB1CE bit is 1. Two rewrite modes (batch write m ode and anytime write mode) can be sele cted, depending on the setting of the TAB1OPT0.TAB1CMS bit. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. TAB1ICE TAB1ICE Crest interrupt (INTTAB1CC0 signal) enable Do not use INTTAB1CC0 signal (do not use it as count signal for interrupt culling). Use INTTAB1CC0 signal (use it as count signal for interrupt culling). TAB1OPT1 TAB1IOE 0 TAB1ID4 TAB1ID3 TAB1ID2 TAB1ID1 TAB1ID0 < 6 > 54 321 TAB1IOE Valley interrupt (INTTAB1OV signal) enable Do not use INTTAB1OV signal (do not use it as count signal for interrupt culling). Use INTTAB1OV signal (use it as count signal for interrupt culling). After reset: 00H R/W Address: FFFFF580H <7> 0 Not culled (all interrupts are output) 1 masked (one of two interrupts is output) 2 masked (one of three interrupts is output) 3 masked (one of four interrupts is output) 28 masked (one of 29 interrupts is output) 29 masked (one of 30 interrupts is output) 30 masked (one of 31 interrupts is output) 31 masked (one of 32 interrupts is output) TAB1ID4 Number of times of interrupt TAB1ID3 TAB1ID2 TAB1ID1 TAB1ID0

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 601 of 1817 Sep 19, 2011 (2) TAB1 option register 2 (TAB1OPT2) The TAB1OPT2 register is an 8-bit register that controls the timer AB1 option function. This register can be rewritten when the TAB1CTL0.TAB1CE bit is 1. However, rewriting the TAB1DTM bit is prohibited when the TAB1CE bit is 1. The same value can be rewritten. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) TAB1RDETAB1OPT2 TAB1DTM TAB1ATM3 TAB1ATM2 TAB1AT3 TAB1AT2 TAB1AT1 TAB1AT0 Rewriting the TAB1DTM bit is disabled during timer operation. If it is rewritten by mistake, stop the timer operation by clearing the TAB1CE bit to 0, and re-set the TAB1DTM bit. TAB1DTM Dead-time counter operation mode selection (m = 1 to 3) The dead-time counter counts up normally and, if TOAB1m output of TAB1 is at a narrow interval (TOAB1m output width < dead-time width), the dead-time counter is cleared and counts up again. The dead-time counter counts up normally and, if TOAB1m output of TAB1 is at a narrow interval (TOAB1m output width < dead-time width), the dead-time counter counts down and the dead-time control width is automatically narrowed. After reset: 00H R/W Address: FFFFF581H <7> <0> TAB1RDE Transfer culling enable Do not cull transfer (transfer timing is generated every time at crest and valley). Cull transfer at the same interval as interrupt culling set by the TAB1OPT1 register. Cautions 1. When using interrupt culling (the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits are set to other than 00000), be sure to set the TAB1RDE bit to 1. This means that interrupts and transfers ar e generated at the same timing. Interrupts and transfers, cannot be set separately. If interrupts and transf ers are set separately (TAB1RDE bit = 0), transfers are not performed normally. 2. When generating a dead-time period, set the TAB1DTC register to 1 or higher. Note, when the operation is stopped (TAB 1CTL0.TAB1CE bit = 0), a dead-time period is not generated, so the output levels of the TOAB1T1 to TOAB1T3 and TOAB1B1 to TOAB1B3 pins are in their default states. Therefore, for the protection of the system, take measures such as making the TOAB1T1 to TOAB1T3 and TOAB1B1 to TOAB1B3 pins go into a high-impedance state before stopping operation, or setting the output levels of the pins before switching port modes. When a dead-time period is not need ed, set the TAB1DTC register to 0.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 602 of 1817 Sep 19, 2011 (2/2) TAB1AT3Note A/D trigger output control 3 Disable output of A/D trigger signal (TABTADT0) for INTTAA4CC1 interrupt. Enable output of A/D trigger signal (TABTADT0) for INTRAA4CC1 interrupt. TAB1AT2Note A/D trigger output control 2 Disable output of A/D trigger signal (TABTADT0) for INTTAA4CC0 interrupt. Enable output of A/D trigger signal (TABTADT0) for INTTAA4CC0 interrupt. TAB1AT1Note A/D trigger output control 1 Disable output of A/D trigger signal (TABTADT0) for INTTAB1CC0 (crest interrupt). Enable output of A/D trigger signal (TABTADT0) for INTTAB1CC0 (crest interrupt). TAB1AT0Note A/D trigger output control 0 Disable output of A/D trigger signal (TABTADT0) for INTTAB1OV (valley interrupt). Enable output of A/D trigger signal (TABTADT0) for INTTAB1OV (valley interrupt). TAB1ATM3 TAB1ATM3 mode selection Output A/D trigger signal (TABTADT0) for INTTAA4CC1 interrupt while dead-time counter is counting up. Output A/D trigger signal (TABTADT0) for INTTAA4CC1 interrupt while dead-time counter is counting down. TAB1ATM2 TAB1ATM2 mode selection Output A/D trigger signal (TABTADT0) for INTTAA4CC0 interrupt while dead-time counter is counting up. Output A/D trigger signal (TABTADT0) for INTTAA4CC0 interrupt while dead-time counter is counting down. Note For the setting of the TAB1AT3 to TAB1AT0 bits, see CHAPTER 15 A/D CONVERTER.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 603 of 1817 Sep 19, 2011 (3) TAB1 I/O control register 3 (TAB1IOC3) The TAB1IOC3 register is an 8-bit register that controls the output of the timer AB1 option function. To output from the TOAB1Tm pin, set the TAB1IOC0.TAB1OEm bit to 1 and then set the TAB1IOC3 register. The TAB1IOC3 register can be rewritten only when the TAB1CTL0.TAB1CE bit is 0. Rewriting each bit of the TAB1IOC3 register is prohibit ed when the TAB1CTL0.TAB1CE bit is 1; however the same value can be rewritten to each bit of the TAB1IOC3 register when the TAB1CTL0.TAB1CE bit is 1. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to A8H. Caution Set the TAB1IOC3 register to the reset value (A8H) when the time r is used in a mode other than the 6-phase PWM output mode. Remarks 1. Set the output level of the TOAB1Tm pin by using the TAB1IOC0 register. 2. m = 1 to 3 TAB1OLB3TAB1IOC3 TAB1OEB3 TAB1OLB2 TAB1OEB2 TAB1OLB1TAB1OEB1 00 Setting of TOAB1Bm pin output level (m = 1 to 3) Disable inversion of output of TOAB1Bm pin Enable inversion of output of TOAB1Bm pin TAB1OEBm TAB1OLBm TOAB1Bm pin output (m = 1 to 3) Disable TOAB1Bm pin output.

• When TAB1OLBm bit = 0, low level is output from TOAB1Bm pin.
• When TAB1OLBm bit = 1, high level is output from TOAB1Bm pin. Enable TOAB1Bm pin output. After reset: A8H R/W Address: FFFFF582H <7> 0

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 604 of 1817 Sep 19, 2011 (a) Output from TOAB1 Tm and TOAB1Bm pins The TOAB1Tm pin output is controlled by the TAB1IOC0.TAB1OLm and TAB1IOC0.TAB1OEm bits. The TOAB1Bm pin output is controlled by the TAB1IOC3.TAB1OLBm and TAB1IOC3.TAB1OEBm bits. The timer output with each setting in the 6-phase PWM output mode is shown below. Figure 11-3. Output Control of TOAB1Tm and TOAB1Bm Pins (Without Dead Time) 16-bit counter Fixed to low-level output Fixed to high-level output TOAB1Tm pin output TAB1OEm bit = 0, TAB1OLm bit = 0 (status after reset) TAB1OEBm bit = 0, TAB1OLBm bit = 1 (status after reset) TAB1OEm bit = 1, TAB1OLm bit = 0 (positive-phase output) TAB1OEBm bit = 1, TAB1OLBm bit = 1 (negative-phase output) TAB1OEm bit = 1, TAB1OLm bit = 0 (positive-phase output) TAB1OEBm bit = 1, TAB1OLBm bit = 0 (positive-phase output) TAB1OEm bit = 1, TAB1OLm bit = 1 (negative-phase output) TAB1OEBm bit = 1, TAB1OLBm bit = 1 (negative-phase output) TOAB1Bm pin output TOAB1Tm pin output TOAB1Bm pin output TOAB1Tm pin output TOAB1Bm pin output TOAB1Tm pin output TOAB1Bm pin output Remark m = 1 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 605 of 1817 Sep 19, 2011 Table 11-1. TOAB1Tm Pin Output TAB1OLm Bit TAB1OEm Bit TAB1CE Bit TOAB1Tm Pin Output 0 x Low-level output

1 TOAB1Tm positive-phase output

1 TOAB1Tm negative-phase output

Remark m = 1 to 3 Table 11-2. TOAB1Bm Pin Output TAB1OLBm Bit TAB1OEBm Bit TAB1CE Bit TOAB1Bm Pin Output 0 x Low-level output

1 TOAB1Bm positive-phase output

1 TOAB1Bm negative-phase output

Remark m = 1 to 3 (6) High-impedance output control re gisters 0, 1 (HZA0CTL0, HZA0CTL1) The HZA0CTL0 and HZA0CTL1 regi sters are 8-bit registers that control the high-impedance st ate of the output buffer. These registers can be read or written in 8-bit or 1-bit units. However, the HZA0DCFn bit is a read-only bit and cannot be written. 16-bit access is not possible. Reset sets these registers to 00H. Software can be used to always write the same value to the HZA0CTLn register. The relationship between detection factor and the control registers is shown below. High-Impedance Control Factor Pins Subject to High-Impedance Control External Pin Control Register When TOAB1T1 to TOAB1T3 are output When TOAB1B1 to TOAB1B3 are output TOAB1OFF/INTP18 HZA0CTL0 When TOAA11 is output TOAA1OFF/INTP06 HZA0CTL1 Caution High impedance control is pe rformed only when the target port is specified as a target pin in the above table. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 606 of 1817 Sep 19, 2011 (1/2) HZA0DCEn HZA0DCEn High-impedance output control Disable high-impedance output control operation. Pins can function as output pins. Enable high-impedance output control operation. HZA0CTLn HZA0DCMn HZA0DCNn HZA0DCPn HZA0DCTn HZA0DCCn 0 HZA0DCFn HZA0DCNn HZA0DCPn External pin input edge specification No valid edge (setting the HZA0DCFn bit by external pin input is prohibited). Rising edge of the external pin is valid (abnormality is detected by rising edge input). Falling edge of the external pin is valid (abnormality is detected by falling edge input). Setting prohibited HZA0DCMn Condition of clearing high-impedance state by HZA0DCCn bit Setting of the HZA0DCCn bit is valid regardless of the external pin input. Setting of the HZA0DCCn bit is invalid while the external pin input holds a level detected as abnormal (active level). After reset: 00H R/W Address: HZA0CTL0 FFFFF590H, HZA0CTL1 FFFFF591H <7> <0> Rewrite the HZA0DCMn bit when the HZA0DCEn bit = 0.

• Rewrite the HZA0DCNn and HZA0DCPn bits when the HZA0DCEn bit is 0.
• For the valid edge specification of the interrupts of the INTP06 and INTP18 pins, see 25.6.2 (2) External interrupt falling, rising edge specification register 2 (INTR2, INTF2) and (6) External interrupt falling, rising edge specification register 9H (INTR9, INTF9).
• For the edge specification of the external pins, begin with the TOAB1OFF and TOAA1OFF pins. Then, perform edge specification for the external pins other than the TOAB1OFF and TOAA1OFF pins. Otherwise, an undefined edge may be detected when the edge for the TOAB1OFF and TOAA1OFF pins is specified.
• High-impedance output control is performed when the valid edge is input after the operation is enabled (by setting HZA0DCEn bit to 1). If the external pin is at the active level when the operation is enabled, therefore, high-impedance output control is not performed. (n = 0, 1)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 607 of 1817 Sep 19, 2011 (2/2) HZA0DCCn High-impedance output control clear bit No operation Pins that have gone into a high-impedance state are output-enabled by software and the HZA0DCFn bit is cleared to 0.

• Pins can function as output pins when the HZA0DCM bit = 0, regardless of the status of the external pin.
• If an edge indicating abnormality is input to the external pin (which is set by the HZA0DCNn and HZA0DCPn bits) when the HZA0DCM bit = 1, the HZA0DCCn bit is invalid even if it is set to 1.
• The HZA0DCCn bit is always 0 when it is read.
• The HZA0DCCn bit is invalid even if it is set to 1 when the HZA0DCEn bit = 0.
• Simultaneously setting the HZA0DCTn and HZA0DCCn bits to 1 is prohibited. HZA0DCFn High-impedance output status flag Indicates that output of the pin is enabled.
• This bit is cleared to 0 when the HZA0DCEn bit = 0.
• This bit is cleared to 0 when the HZA0DCCn bit = 1. Indicates that the pin goes into a high-impedance state.
• This bit is set to 1 when the HZA0DCTn bit = 1.
• This bit is set to 1 when an edge indicating abnormality is input to the external pin (which is detected according to the setting of the HZA0DCNn and HZA0DCPn bits). HZA0DCTn High-impedance output trigger bit No operation Pins are made to go into a high-impedance state by software and the HZA0DCFn bit is set to 1.
• If an edge indicating abnormality is input to the external pin (which is detected according to the setting of the HZA0DCNn and HZA0DCPn bits), the HZA0DCTn bit is invalid even if it is set to 1.
• The HZA0DCTn bit is always 0 when it is read because it is a software-triggered bit.
• The HZA0DCTn bit is invalid even if it is set to 1 when the HZA0DCEn bit = 0.
• Simultaneously setting the HZA0DCTn and HZA0DCCn bits to 1 is prohibited.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 608 of 1817 Sep 19, 2011 Figure 11-4. High-Impedance Output Controller Configuration TOAB1B1 TOAB1T1 TOAB1B2 TOAB1T2 TOAB1B3 TOAB1T3 TOAA1OFF/ INTP06 TOAB1OFF/ INTP18 TAA1 TAB1OP TOAA11 PLL HZA0CTL1 HZA0CTL0 INTP18 INTP06 Analog filter Edge detection Edge detection Analog filter Main oscillator Clock monitor circuit Remark Also see Figures 11-1 and 11-2.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 609 of 1817 Sep 19, 2011 (a) Setting procedure (i) Setting of high-impedance control operation <1> Set the HZA0DCMn, HZA0DCNn, and HZA0DCPn bits. <2> Set the HZA0DCEn bit to 1 (enable high-impedance control). (ii) Changing setting after enablin g high-impedance control operation <1> Clear the HZA0DCEn bit to 0 (to stop the high-impedance control operation). <2> Change the setting of the HZA0 DCMn, HZA0DCNn, and HZA0DCPn bits. <3> Set the HZA0DCEn bit to 1 (to enable t he high-impedance control operation again). (iii) Resuming output when pins are in high-impedance state If the HZA0DCMn bit is 1, set the HZA0DCCn bit to 1 to clear the high-impedance state after the valid edge of the external pin is detected. However, t he high-impedance state cannot be cleared unless this bit is set while the input level of the external pin is inactive. <1> Set the HZA0DCCn bit to 1 (command si gnal to clear the high-impedance state). <2> Read the HZA0DCFn bit and check the flag status. <3> Return to <1> if the HZA0DCFn bit is 1. T he input level of the external pin must be checked. The pin can function as an output pin if the HZA0DCFn bit is 0. (iv) Making pin go into high-impedance state by software The HZA0DCTn bit must be set to 1 by software to ma ke the pin go into a high-impedance state while the input level of the external pin is inactive. The following procedure is an example in which the setting is not dependent upon the setting of the HZA0DCMn bit. <1> Set the HZA0DCTn bit to 1 (high-impedance output command). <2> Read the HZA0DCFn bit to check the flag status. <3> Return to <1> if the HZA0DCFn bit is 0. T he input level of the external pin must be checked. The pin is in a high-impedance state if the HZA0DCFn bit is 1. However, if the external pin is not used with the HZA0DCPn bit and HZA0DCNn bit cleared to 0, the pin goes into a high-impedance state when the HZA0DCTn bit is set to 1. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 610 of 1817 Sep 19, 2011

11.4 Operation

11.4.1 System outline

(1) Outline of 6-phase PWM output The 6-phase PWM output mode is used to generate a 6- phase PWM output wave, by using the timer AB1 (TAB1) and the TAB1 option (TAB1OP0) in combination. The 6-phase PWM output mode is enabled by setting the TAB1CTL1.TAB1MD2 to TAB1CTL1.TAB1MD0 bits of TAB1 to “111”. One 16-bit counter and four 16-bit compare registers of TAB1 are used to generate a basic 3-phase wave. The functions of the compare registers are as follows. TAA4 can perform a tuning operation with TAB1 to generate a conversion trigger source for the A/D converter. Compare Register Function Settable Range TAB1CCR0 register Setting of cycle 0002H ≤ m ≤ FFFEH TAB1CCR1 register Specifying output width of phase U 0000H ≤ i ≤ m + 1 TAB1CCR2 register Specifying output width of phase V 0000H ≤ j ≤ m + 1 TAB1CCR3 register Specifying output width of phase W 0000H ≤ k ≤ m + 1 Remark m = Set value of TAB1CCR0 register i = Set value of TAB1CCR1 register j = Set value of TAB1CCR2 register k = Set value of TAB1CCR3 register A dead-time interval is generated from the basic 3-phase wave generated by using three 10-bit dead-time counters and one compare register to create a wave with a revers e phase to that of the bas ic 3-phase wave. Then a 6- phase PWM output wave (U, U, V, V, W, and W) is generated. The 16-bit counter for generating the basic 3-phase wave counts up or down. After the operation has been started, this counter counts up. When its count value matches the cycle set to the TAB1CCR0 register, the counter starts counting down. When the count value ma tches 0001H, the counter counts up agai n. This means that a value two times higher than the value set to the TAB1CCR0 register + 1 is the carrier cycle. 10-bit dead-time counters 1 to 3, which generate the dead-time interval, count up. Therefore, the value set to the TAB1 dead-time compare register (TAB1DTC) is used as a dead-time value as is. Because three counters are used, dead time can be generated independently in phases U, V, and W. However, because there is only one register that specifies a dead-time value (TAB1DTC), the same dead-time value is used in all three phases.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 611 of 1817 Sep 19, 2011 Figure 11-5. Outline of 6-Phase PWM Output Mode TOT1 TOAB1T1 pin output (U) TOB1 TOAB1B1 pin output (U) TOAB1T2 pin output (V) TOAB1B2 pin output (V) TOAB1T3 pin output (W) TOAB1B3 pin output (W) TOT2 TOB2 TOT3 TOB3 16-bit counter Up/down selection TAB1CCR0 register (carrier cycle) TOAB11 (internal signal)Note 0001H TOAB12 (internal signal)Note TOAB13 (internal signal)Note TAB1CCR1 register (phase U output data) TAB1CCR2 register (phase V output data) TAB1CCR3 register (phase W output data) Dead-time counter 1 Dead-time counter 2 Dead-time counter 3 TAB1DTC register (dead-time value) INTTAB1OV signal (valley interrupt) INTTAB1CC0 signal (crest interrupt) TOAB10 pin output INTTAB1OV_BASE Interrupt culling circuit A/D trigger generator Note TOAB11, TOAB12, and TOAB13 functi on alternately as output pins.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 612 of 1817 Sep 19, 2011 Figure 11-6. Timing Chart of 6-Phase PWM Output Mode 16-bit counter M (carrier data)TAB1CCR0 register 0000H TOAB11 signal (internal signal) TOAB12 signal (internal signal) TOAB13 signal (internal signal) TAB1DTC register TOAB1T1 pin output (U) TOAB1B1 pin output (U) Dead-time counter 1 Dead-time counter 2 Dead-time counter 3 TAB1CCR1 register TAB1CCR2 register TAB1CCR3 register N (dead-time value) i (phase U data) j (phase V data) k (phase W data) i ii i j j j j kkkk M + 1 M + 1 TOAB10 pin output Basic phase U output width = (M + 1 - i) ´ 2 Basic phase V output width = (M + 1 − j) × 2 Basic phase W output width = (M + 1 − k) × 2 Phase U output width = (M + 1 − i) × 2 − N Phase V output width = (M + 1 − j) × 2 − N Phase W output width = (M + 1 − k) × 2 − N Dead-time width = N Phase U output width = (M + 1 − i) × 2 + N Carrier cycle = (M + 1) × 2 TOAB1T2 pin output (V) TOAB1B2 pin output (V) TOAB1T3 pin output (W) TOAB1B3 pin output (W) Phase V output width = (M + 1 − j) × 2 + N Phase W output width = (M + 1 − k) × 2 + N Cautions 1. Set the value “M” of the TAB1CCR0 register in a range of 0002H ≤ M ≤ FFFEH in the 6-phase PWM output mode. 2. Only a value of up to “M + 1” can be set to the TAB1CCR1, TAB1CCR2, and TAB1CCR3 registers. 3. The output is 100% if “0000H” is set to the TAB1CCR1, TAB1CCR2, and TAB1CCR3 registers. The output is 0% if “M + 1” is set to the TAB1CCR1, TAB1CCR2, and TAB1CCR3 registers. The output (duty 50%) rises at the crest (M + 1) of the 16-bit counter and falls at the valley (0000H) if “M + 2” or higher is set to the TAB1CCR1, TAB1CCR2, and TAB1CCR3 registers. 4. If the operation value of an equation (suc h as (M + 1 – i) × 2 – N) of the output width of phases U, V, and W is 0 or lower, it is converged to 0 (100% output). If the operation value is higher than “(M + 1) × 2”, it is converged to (M + 1) × 2 (0% output).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 613 of 1817 Sep 19, 2011 (2) Interrupt requests Two types of interrupt requests are available: the IN TTAB1CC0 (crest interrupt) signal and INTTAB1OV (valley interrupt) signal. The INTTAB1CC0 and INTTAB1OV signals can be culled by using the TAB1OPT1 register. For details of culling interrupts, see 11.4.3 Interrupt culling function.

• INTTAB1CC0 (crest interrupt) signal: An interrupt signal indicating a match between the value of the 16-bit counter that counts up and the value of the TAB1CCR0 register
• INTTAB1OV (valley interrupt) signal: An interrupt si gnal indicating a match between the value of the 16-bit counter that counts down and the value 0001H (3) Rewriting registers during timer operation The following registers have a buffer register and can be rewritten in the anytime rewrite mode, batch rewrite mode, or intermittent batch rewrite mode. Related Unit Register Timer AA1 TAA1 capture/compare register 0 (TAA1CCR0) TAA1 capture/compare register 1 (TAA1CCR1) Timer AB1 TAB1 capture/compare register 0 (TAB1CCR0) TAB1 capture/compare register 1 (TAB1CCR1) TAB1 capture/compare register 2 (TAB1CCR2) TAB1 capture/compare register 3 (TAB1CCR3) Timer AB1 option TAB1 option register 1 (TAB1OPT1) For details of the transfer function of the compare register, see 11.4.4 Operation to rewrite register with transfer function. (4) Counting-up/down operation of 16-bit counter The operation status of the 16-bit counter can be checked by using the TAB1CUF bit of TAB1 option register 0 (TAB1OPT0). Status of TAB1CUF Bit Status of 16-Bit Counter Range of 16-Bit Counter Value TAB1CUF bit = 0 Counting up 0000H − m TAB1CUF bit = 1 Counting down (m + 1) − 0001H Remark m = Set value of TAB1CCR0 register

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 614 of 1817 Sep 19, 2011 Figure 11-7. Interrupt and Up/Down Flag 16-bit counter M (carrier data)TAB1CCR0 register 0000H TOAB1T1 pin output (U) TOAB1B1 pin output (U) TAB1CCR1 register TAB1CCR2 register TAB1CCR3 register i (phase U data) j (phase V data) k (phase W data) i i i i j j j j kkkk M + 1 M + 1 TOAB1T2 pin output (V) TOAB1B2 pin output (V) TOAB10 pin output INTTAB1CC0 (crest interrupt) INTTAB1OV (valley interrupt) TAB1CUF (up/down flag) TOAB1T3 pin output (W) TOAB1B3 pin output (W)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 615 of 1817 Sep 19, 2011

11.4.2 Dead-time control (generat ion of negative-phase wave signal)

(1) Dead-time control mechanism In the 6-phase PWM output mode, compare registers 1 to 3 (TAB1CCR1, TAB1CCR2, and TAB1CCR3) are used to set the duty factor, and compare register 0 (TAB1CCR0) is us ed to set the cycle. By setting these four registers and by starting the operation of TAB1, three types of PWM output waves (basic 3-phase waves) with a variable duty factor are generated. These three PWM output waves are input to the timer AB option unit (TABOP) and their inverted signal with dead-time is created to generate three sets of (six) PWM waves. The TABOP unit consists of three 10-bit counters (dead-time counters 1 to 3) that operate in synchronization with the count clock of TAB1, and a TAB1 dead-time compare register (TAB1DTC) that specifies dead time. If “a” is set to the TAB1DTC register, the dead-time value is “a”, and interval “a” is created between a positive-phase wave and a negative-phase wave. Figure 11-8. PWM Output Wave with Dead Time (1) (a) When dead time is inserted (TAB1DTC register = a) a a 16-bit counter TOAB1m signal (internal signal) Dead-time counter m TOAB1Tm pin output TOAB1Bm pin output (b) No dead time (TAB1DTC register = 000H) 0 0 0000H 16-bit counter TOAB1m signal (internal signal) Dead-time counter m TOAB1Tm pin output TOAB1Bm pin output Remark m = 1 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 616 of 1817 Sep 19, 2011 (2) PWM output of 0%/100% The V850ES/JH3-E and V850ES/JJ3-E are capable of 0% wave output and 100% wave output for PWM output. A low level is continuously output from the TOAB1Tm pin as the 0% wave output. A high level is continuously output from the TOAB1Tm pin as the 100% wave output. A 0% wave is output by setting the TAB1CCRm register to “M + 1” when the TAB1CCR0 register = M. A 100% wave is output by setting the TAB1CCRm register to “0000H”. Rewriting the TAB1CCRm register is enabled while the timer is operating, and 0% wave output or 100% wave output can be selected at the point of the crest interrupt (INTTAB1CC0) and valley interrupt (INTTAB1OV). Remark m = 1 to 3 Figure 11-9. 0% PWM Output Waveform (With Dead Time) ii 0% output i i i i i M i i i M + 1 M + 1 M + 1 M + 1 i i 0000H 0% output 16-bit counter TAB1CCR0 register TAB1CCR1 register TOAB1T1 pin output TOAB1B1 pin output CCR1 buffer register Forced timing of timer output <1> 0% output is selected by the valley in terrupt (without a match with the 16-bit counter). The valley interrupt forcibly lowers t he timer output. This produces the 0% output. <2> 0% output is canceled by the crest inte rrupt (without a match with the 16-bit counter). The crest interrupt forcibly raises the ti mer output. This cancels the 0% output. <3> 0% output is selected by the crest inte rrupt (with a match with the 16-bit counter). The crest interrupt forcibly raises the timer outpu t, but lowering the timer output takes precedence when the value of the TAB1CCRm register matches the value of the 16-bit counter. As a result, the 0% wave is output. <4> 0% output is canceled by the valley inte rrupt (without a match with the 16-bit counter). The valley interrupt forcibly lowers the timer output. This cancels the 0% output. Remarks 1. means forcible raising and means forcible lowering. 2. m = 1 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 617 of 1817 Sep 19, 2011 Figure 11-10. 100% PWM Output Waveform (With Dead Time) ii i ii i M i ii i0000H 0000H0000H 0000H 0000H i i 100% output 100% output 16-bit counter TAB1CCR0 register TAB1CCR1 register TOAB1T1 pin output TOAB1B1 pin output CCR1 buffer register Forced timing of timer output <1> 100% output is selected by the valley in terrupt (with a match with the 16-bit counter). The valley interrupt forcibly lowers the timer output, but raising the timer output takes precedence when the value of the TAB1CCRm register matches the value of the 16-bit counter. As a result, the 100% output is produced. <2> 100% output is canceled by the valley inte rrupt (without a match with the 16-bit counter). The valley interrupt forcibly lowers the timer output. This cancels the 100% output. <3> 100% output is selected by the crest inte rrupt (without a match with the 16-bit counter). The crest interrupt forcibly raises the ti mer output. This produces the 100% output. <4> 100% output is canceled by the crest inte rrupt (without a match with the 16-bit counter). The crest interrupt forcibly raises the ti mer output. This cancels the 100% output. Remarks 1. means forcible raising and means forcible lowering. 2. m = 1 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 618 of 1817 Sep 19, 2011 Figure 11-11. PWM Output Waveform from 0% to 100% and from 100% to 0% (With Dead Time) 0% output M 0000H 0000H 0000H0000H 0000H 0000H M + 1M + 1 M + 1 M + 1 0000H 100% output 100% output 100% output 16-bit counter TAB1CCR0 register TAB1CCR1 register TOAB1T1 pin output TOAB1B1 pin output CCR1 buffer register Forced timing of timer output 0% output <1> The valley interrupt selects 100% ←→ 0% or 0% ←→ 100% output. Output can be selected from 100% ←→ 0% or 0% ←→ 100% immediately after the timer has been started. <2> The crest interrupt selects 100% ←→ 0% output. The crest interrupt selects 100% → 0% output by using the timer output forcible raising function and by a match between the 16-bit counter value and the TAB1CCR0 register value. (3) Output waveform in vicinity of 0% and 100% output If an interrupt is generated because the value of the 16-bit counter matches the value of the compare register while dead time is being counted, the dead-time counter is cleared and starts its count operation again. The output waveform of dead-time control in the vicinity of 0% and 100% output is shown below.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 619 of 1817 Sep 19, 2011 Figure 11-12. PWM Output Waveform with Dead Time (2) (a) 0% output (TAB1CCRm register = M + 1, TAB1CCR0 register = M, TAB1DTC register = a) 16-bit counter 000H (dead-time counter m does not count) H L L 0000H TOAB1m signal (internal signal) Dead-time counter m TOAB1Tm pin output TOAB1Bm pin output (b) In vicinity of 0% output (TAB1CCRm register = i ≥ M + 1 − a/2, TAB1CCR0 register = M, TAB1DTC register = Dead-time counter is cleared and counts again Negative-phase output width: (M + 1 − i) × 2 + a (e.g., output width is 2 + a where TAB1CCRm register = M) L 16-bit counter 0000H TOAB1m signal (internal signal) Dead-time counter m TOAB1Tm pin output TOAB1Bm pin output 000H (c) In vicinity of 100% output (TAB1CCRm register = i ≤ a/2, TAB1CCR0 register = M, TAB1DTC register = a) Counter is cleared and counts again Positive-phase output width: (M + 1 − i) × 2 − a) (e.g., output width is 2 − a where TAB1CCRm register = 0001H.) 16-bit counter 0000H TOAB1m signal (internal signal) Dead-time counter m TOAB1Tm pin output TOAB1Bm pin output 000H (d) 100% output (TAB1CCRm register = 0000H, TAB1CCR0 register = M, TAB1DTC register = a) 000H (dead-time counter m does not count) 16-bit counter 0000H TOAB1m signal (internal signal) Dead-time counter m TOAB1Tm pin output TOAB1Bm pin output Remark m = 1 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 620 of 1817 Sep 19, 2011 (4) Automatic dead-time width narrowing function (TAB1OPT2.TAB1DTM bit = 1) The dead-time width can be automatically narrowed in the vicinity of 0% output or 100% output by setting the TAB1OPT2.TAB1DTM bit to 1. By setting the TAB1DTM bit to 1, the dead-time counter is not cleared, but starts down counting if the TOAB1m (internal signal) output of timer AB changes during dead-time counting. The following timing chart shows the operation of the dead-time counter when the TAB1DTM bit is set to 1. Figure 11-13. Operation of Dead-Time Counter m (1) (a) In vicinity of 0% output (TAB1CCRm register = i ≥ M + 1 − a/2, TAB1CCR0 register = M, TAB1DTC register = a) Dead-time counter m starts counting down Negative-phase wave output width: (M + 1 − i) × 4 (e.g., output width is 4 where TAB1CCRm = M) 16-bit counter 0000H TOAB1m signal (internal signal) Dead-time counter m TOAB1Tm pin output TOAB1Bm pin output 000H (b) In vicinity of 100% output (TAB1CCRm register = i ≤ a/2, TAB1CCR0 register = M, TAB1DTC register = a) Dead-time counter m starts counting down Positive-phase wave output width: (M + 1 − i) × 2 − (i × 2) (e.g., output width is M × 2 − 2 where TAB1CCRm = 0001H) Note 16-bit counter 0000H TOAB1m signal (internal signal) Dead-time counter m TOAB1Tm pin output TOAB1Bm pin output 000H Note The output width of the first wave differs from t hat of the second and subsequent waves immediately after the TAB1CTL0.TAB1CE bit has been set. The first wave is shorter than the second wave because the dead time is fully counted. Remark m = 1 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 621 of 1817 Sep 19, 2011 (5) Dead-time control in case of incorrect setting Usually, the TOAB1m (internal signal) output of TAB1 chang es only once during dead-time counting, only in the vicinity of 0% and 100% output. Th is section shows an example where the TAB1CCR0 register (carrier cycle) and TAB1DTC register (dead-time value) are incorrectly set. If these registers are incorrectly set, the TOAB1m (internal signal) output of TAB1 changes twice or three times durin g dead-time counting. The following flowchart shows the 6-phase PWM output wave in this case. Figure 11-14. Operation of Dead-Time Counter m (2) (a) When TAB1OPT2.TAB1DTM bit = 0, TAB1CCR0 register = 0006H, TAB1DTC register = 000FH, TAB1CCRm register = 0004H Counter cleared Counter is not cleared but continues counting 000H 001H 002H 003H 004H 005H 006H 001H 002H 003H 004H 005H 006H 007H 008H 009H 00AH 00BH 00CH 00DH 00EH 00FH 000H 001H 16-bit counter TOAB1m signal (internal signal) Dead-time counter m TOAB1Tm pin output TOAB1Bm pin output (b) When TAB1OPT2.TAB1DTM bit = 1, TAB1CCR0 register = 0006H, TAB1DTC register = 000FH, TAB1CCRm register = 0002H Starts counting down. Output does not change and dead-time counter m continues counting down 001H 002H 003H 004H 005H 006H 007H 008H 009H 00AH 009H 008H 007H 006H 005H 004H 003H 002H 001H 001H 002H 003H 004H 003H 002H 001H000H 000H 16-bit counter TOAB1m signal (internal signal) Dead-time counter m TOAB1Tm pin output TOAB1Bm pin output Remark m = 1 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 622 of 1817 Sep 19, 2011

11.4.3 Interrupt culling function

• The interrupts to be culled are INTTAB1CC0 (crest interrupt) and INTTAB1OV (valley interrupt).
• The TAB1OPT1.TAB1ICE bit is used to enable output of the INTTAB1CC0 interrupt and the number of times the interrupt is to be culled.
• The TAB1OPT1.TAB1IOE bit is used to enable output of the INTTAB1OV interrupt and the number of times the interrupt is to be culled.
• The TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits are used to specify the number of counts by which a specified interrupt is to be culled. The interrupt is masked for t he duration of the specified nu mber of counts and is generated at the next interrupt timing.
• The TAB1OPT2.TAB1RDE bit is used to specify whether transfer is to be culled or not. If it is specified that transfer is to be culled, transfer is executed at the same timing as the interrupt output after culling. If it is specified that transfer is not to be culled, transfer is executed at the transfer timing after the TAB1CCR1 register has been written.
• The TAB1OPT0.TAB1CMS bit is used to specify whether the registers with a transfer function are batch rewritten or anytime rewritten. The values of the registers are updated in synchronizati on with transfer when the TAB1CMS bit is 0. When the TAB1CMS bit is 1, the values of the registers are immediately updated when a new value is written to the registers. Transfer is performed from the TAB1CCRm register to the CCRm buffer register in synchronization with the interrupt culling timing. Cautions 1. When using the interrupt culling function in the batch rewrite mode (transfer mode), execute the function in the intermittent batch rewrite mode (transfer culling mode). 2. The interrupt is generate d at the timing after culling. Remark m = 1 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 623 of 1817 Sep 19, 2011 (1) Interrupt culling operation Figure 11-15. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT2.TAB1RDE Bit = 1 (Crest/Valley Interrupt Output) 16-bit counter TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled) TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001 (1 mask) TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00010 (2 masks) TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00011 (3 masks) TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00100 (4 masks) TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00101 (5 masks) TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00110 (6 masks) INTTAB1CC0 signal INTTAB1CC0 signal INTTAB1CC0 signal INTTAB1CC0 signal INTTAB1CC0 signal INTTAB1CC0 signal INTTAB1CC0 signal INTTAB1OV signal INTTAB1OV signal INTTAB1OV signal INTTAB1OV signal INTTAB1OV signal INTTAB1OV signal INTTAB1OV signal Remark : Culled interrupt

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 624 of 1817 Sep 19, 2011 Figure 11-16. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 0, TAB1OPT2.TAB1RDE Bit = 1 (Crest Interrupt Output) 16-bit counter TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled) TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001 (1 mask) TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00010 (2 masks) TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00011 (3 masks) TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00100 (4 masks) INTTAB1CC0 signal INTTAB1CC0 signal INTTAB1CC0 signal INTTAB1CC0 signal INTTAB1CC0 signal INTTAB1OV signal INTTAB1OV signal INTTAB1OV signal INTTAB1OV signal INTTAB1OV signal Remark : Culled interrupt

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 625 of 1817 Sep 19, 2011 Figure 11-17. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 0, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT2.TAB1RDE Bit = 1 (Valley Interrupt Output) 16-bit counter TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled) TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001 (1 mask) TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00010 (2 masks) TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00011 (3 masks) TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00100 (4 masks) INTTAB1CC0 signal INTTAB1CC0 signal INTTAB1CC0 signal INTTAB1CC0 signal INTTAB1CC0 signal INTTAB1OV signal INTTAB1OV signal INTTAB1OV signal INTTAB1OV signal INTTAB1OV signal Remark : Culled interrupt

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 626 of 1817 Sep 19, 2011 (2) To alternately output crest interrupt (INTTAB1CC0) and valley interrupt (INTTAB1OV) To alternately output the crest and valley interrupt s, set both the TAB1OPT1.TAB1ICE and TAB1OPT1.TAB1IOE bits to 1. Figure 11-18. Crest/Valley Interrupt Output (a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.TAB1RDE bit = 1 (with transfer culling control) 16-bit counter TAB1ID4 to TAB1ID0 bits TAB1ID4 to TAB1ID0 bits (slave bit) INTTAB1OV signal 00010 00010 00100 Transfer Timing of rewriting transfer culling count from 2 to 4 00100 INTTAB1CC0 signal Remarks 1. Transfer is performed at the culled interrupt output timing. The other transfer timing is ignored. 2. : Culled interrupt (b) TAB1CMS bit = 1, TAB1RDE bit = 0 or 1 (without transfer control) 00010 00010 00100 Reflected immediately 00100 Timing of rewriting transfer culling count from 2 to 4 16-bit counter TAB1ID4 to TAB1ID0 bits TAB1ID4 to TAB1ID0 bits (slave bit) INTTAB1OV signal INTTAB1CC0 signal Remarks 1. Rewriting is reflected immediately. The transfer timing is ignored. 2. : Culled interrupt

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 627 of 1817 Sep 19, 2011 (3) To output only crest interrupt (INTTAB1CC0) Set the TAB1OPT1.TAB1ICE bit to 1 and clear the TAB1OPT1.TAB1IOE bit to 0. Figure 11-19. Crest Interrupt Output (a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.TAB1RDE bit = 1 (with transfer culling control) 00010 L 00010 00011 Transfer 00011 Timing of rewriting transfer culling count from 2 to 3 16-bit counter TAB1ID4 to TAB1ID0 bits TAB1ID4 to TAB1ID0 bits (slave bit) INTTAB1OV signal INTTAB1CC0 signal Remarks 1. Transfer is performed at the culled interrupt output timing. The other transfer timing is ignored. 2. : Culled interrupt (b) TAB1CMS bit = 1, TAB1RDE bit = 0 or 1 (without transfer control) 00010 L Reflected immediately 00011 00010 00011 Timing of rewriting transfer culling count from 2 to 3 16-bit counter TAB1ID4 to TAB1ID0 bits TAB1ID4 to TAB1ID0 bits (slave bit) INTTAB1OV signal INTTAB1CC0 signal Remarks 1. Rewriting is reflected immediately. The transfer timing is ignored. 2. : Culled interrupt

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 628 of 1817 Sep 19, 2011 (4) To output only valley interrupt (INTTAB1OV) Clear the TAB1OPT1.TAB1ICE bit to 0 and set the TAB1IOE bit to 1. Figure 11-20. Valley Interrupt Output (a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.TAB1RDE bit = 1 (with transfer culling control) 00010 L 00010 00011 Transfer 00011 Timing of rewriting transfer culling count from 2 to 3 16-bit counter TAB1ID4 to TAB1ID0 bits TAB1ID4 to TAB1ID0 bits (slave bit) INTTAB1OV signal INTTAB1CC0 signal Remarks 1. Transfer is performed at the culled interrupt output timing. The other transfer timing is ignored. 2. : Culled interrupt (b) TAB1CMS bit = 1, TAB1RDE bit = 0 or 1 (without transfer control) 00010 L Reflected immediately 00011 00010 00011 Timing of rewriting transfer culling count from 2 to 3 16-bit counter TAB1ID4 to TAB1ID0 bits TAB1ID4 to TAB1ID0 bits (slave bit) INTTAB1OV signal INTTAB1CC0 signal Remarks 1. Rewriting is reflected immediately. The transfer timing is ignored. 2. : Culled interrupt

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 629 of 1817 Sep 19, 2011

11.4.4 Operation to rewrite re gister with transfer function

The following seven registers are provided with a transfer f unction and are used to control a motor. Each of the registers has a buffer register.

• TAB1CCR0: Register that specifies the cycle of the 16-bit counter (TAB)
• TAB1CCR1: Register that specifies the duty factor of TOAB1T1 (U) and TOAB1B1 (U)
• TAB1CCR2: Register that specifies the duty factor of TOAB1T2 (V) and TOAB1B2 (V)
• TAB1CCR3: Register that specifies the duty factor of TOAB1T3 (W) and TOAB1B3 (W)
• TAB1OPT1: Register that specifies the culling of interrupts
• TAA4CCR0: Register that specifies the A/D conversion start trigger generation timing (TAA4 during tuning operation)
• TAA4CCR1: Register that specifies the A/D conversion start trigger generation timing (TAA4 during tuning operation) The following three rewrite modes are provided in the registers with a transfer function.
• Anytime rewrite mode This mode is set by setting the TAB1OPT0.TAB1CMS bit to 1. The specification of the TAB1OPT2.TAB1RDE bit is ignored. In this mode, each compare register is updated independe ntly, and the value of the com pare register is updated as soon as a new value is written to it.
• Batch rewrite mode (transfer mode) This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0, the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits to 00000, and the TAB1OPT2.TAB1RDE bit to 0. When data is written to the TAB1CCR1 register, data in the seven registers are transferred to the buffer register all at once at the next transfer timing. Unless the TAB1CCR1 regi ster is rewritten, the trans fer operation is not performed even if the other six registers are rewritten. The transfer timing is the timing of each crest (match between the 16-bit counter value and TAB1CCR0 register value) and valley (match between the 16-bit counter value and 0001H) regardless of the interrupt.
• Intermittent batch rewrite mode (transfer culling mode) This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0 and setting the TAB1OPT2.TAB1RDE bit to 1. When data is written to the TAB1CCR1 register, data from the seven registers is transferred to the buffer register all at once at the next transfer timing. Unless the TAB1CCR1 regi ster is rewritten, the trans fer operation is not performed even if the other six registers are rewritten. If interrupt culling is specified by the TAB1OPT1 register, the transfer timing is also culled as the interrupts are culled, and data from the seven registers is transferred all at once at the culled timing of the crest interrupt (match between the 16-bit counter value and TAB1CCR0 register value) or valley interrupt (match between the 16-bit counter value and 0001H). For details of the interrupt culling function, see 11.4.3 Interrupt culling function.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 632 of 1817 Sep 19, 2011 Figure 11-24. Example of Rewriting TAB1CCR1 to TAB1CCR3 Registers (Rewriting Before Match Occurs) (a) If the TAB1CCRm register is rewritten before its value matches the value of the 16-bit counter, the register value will match the value of the 16-b it counter after the register has been rewritten. Consequently, the new register value is immediately reflected. 16-bit counter CCRm buffer register TAB1CCRm register TOAB1Tm pin output i k ki k k ik (b) If a value less than the value of the 16- bit counter (greater if the counter is counting down) is written to the TAB1CCRm register, the output waveform is as follows because the register value do es not match the counter value. i i r r r r ir 16-bit counter CCRm buffer register TAB1CCRm register TOAB1Tm pin output If the register value does not match the counter value, the TOAB1Tm pin output does not change. Even if the value of the 16-bit counter does not match the value of the TAB1CCR m register, the TOAB1Tm pin output always changes to the high level if the crest interrupt occurs and to the low level if the valley interrupt occurs. This is a function provided for 0% output and 100% output. For details, see 11.4.2 (2) PWM output of 0%/100%. Remarks 1. i, r, k = Set values of TAB1CCRm register 2. m = 1 to 3

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 633 of 1817 Sep 19, 2011 Figure 11-25. Example of Rewriting TAB1CCR1 to TAB1CCR3 Registers (Rewriting After Match Occurs) CCRm buffer register 16-bit counter TAB1CCRm register INTTAB1CCm signal TOAB1Tm pin output i k k i i k k ik <1> <3> <2> <1> Matching of the count value of the 16-bit counter and the value of t he TAB1CCRm register as a result of rewriting the register is ignored after a matc h signal has been generated, and the PWM output does not change. <2> Even if the PWM output does not change, the interrupt generat ed upon a match between the 16-bit counter value and the TAB1CCRm register value (INTTAB1CCm) is output. <3> The next match between the 16-bit counter and TAB1CCRm register is valid after the counter has changed its counting direction to up or down, and the PWM output changes. If the TAB1CCRm register is rewritten after its value matc hes the value of the 16-bit counter, the next match is ignored after the first match occurs and the rewritten value is not reflected in the TO AB1Tm pin output. If the register is rewritten while the counter is counting down, the match that occu rs after the counter starts counting down is valid (the match that occurs after the counter has started counting up is valid if the register is rewritten while the counter is counting up). Remarks 1. i, r, k = Set value of TAB1CCRm register 2. m = 1 to 3 (c) Rewriting TAB1OPT1 register The interrupt culling counter is cleared when the TAB1OP T1 register is written. When the interrupt culling counter has been cleared, the measured number of times the interrupt has occurred is discarded. Consequently, the interrupt generation interval is temporarily extended. To avoid this operation, rewrite the TAB1OPT1 register in the intermittent batch rewrite mode (transfer culling mode). For details of rewriting the TAB1OPT1 register, see 11.4.3 Interrupt culling function.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 634 of 1817 Sep 19, 2011 (2) Batch rewrite mode (transfer mode) This mode is set by clearing the TAB1OPT0.TAB1CMS bi t to 0, the TAB1OPT1.TAB1 ID4 to TAB1OPT1.TAB1ID0 bits to 00000, and the TAB1OPT2.TAB1RDE bit to 0. In this mode, the values written to each compare register ar e transferred to the internal buffer register all at once at the transfer timing and compared with the counter value. (a) Rewriting procedure If data is written to the TAB1CCR1 register, the va lues set to the TAB1CCR0 to TAB1CCR3, TAB1OPT1, TAA4CCR0, and TAA4CCR1 registers are transferred all at onc e to the internal buffer register at the next transfer timing. Therefore, write to the TAB1CCR1 register last. Writing to the register is prohibited after the TAB1CCR1 register has been written and before the tr ansfer timing is generated (until the crest (match between the 16-bit counter value and TAB1CCR0 regist er value) or the valley (match between the 16-bit counter value and 0001H)). The operation procedure is as follows. <1> Rewriting the TAB1CCR0, TAB1CCR2, TAB1CCR3, TAB1OPT1, TAA4CCR0, and TAA4CCR1 registers Do not rewrite registers that do not have to be rewritten. <2> Rewriting the TAB1CCR1 register Rewrite the same value to the register even when it is not necessary to rewrite the TAB1CCR1 register. <3> Holding the next rewriting pending until the transfer timing is generated Rewrite the register next time after the IN TTAB1OV or INTTAB1CC0 interrupt has occurred. <4> Return to <1>.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 635 of 1817 Sep 19, 2011 Figure 11-26. Basic Operation in Batch Mode INTTAB1OV signal INTTAB1CC0 signal CCR2 buffer register CCR3 buffer register OPT1 buffer register TAB1CCR2 register TAB1CCR3 register TAB1OPT1 register 16-bit counter (TAB1) Transfer timing TAB1CCR0 register TAB1CCR1 register CCR0 buffer register CCR1 buffer register <Q2> <Q3> <Q3> 16-bit counter (TAA4) Transfer timing TAA4CCR0 register TAA4CCR1 register CCR0 buffer register CCR1 buffer register <P2> <P3> <P3> <Q3> <Q3> <Q3> [Operation of TAB1] <Q1> Write the TAB1CCR1 register <Q2> The target timing is the first transfer timing after a write to the TAB1CCR1 register. <Q3> The values are transferred all at once at the transfer timing. [Operation of TAA4] <P1> Write the TAB1CCR1 register <P2> The target timing is the first transfer timing after a write to the TAB1CCR1 register. <P3> The values are transferred all at once at the transfer timing.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 637 of 1817 Sep 19, 2011 The transfer timing in Figure 11-28 is at the point wher e the crest timing occurs. While the 16-bit counter is counting down, the cycle changes and an asymmetrical tri angular wave is output. Because the cycle changes, rewrite the duty factor (voltage data value). Figure 11-28. Example of Rewriting TAB1CCR0 Register (During Counting Up) (a) M > N 16-bit counter Transfer timing CCR0 buffer register TAB1CCR0 register TAB1CCR1 register CCR1 buffer register TOAB1T1 pin output INTTAB1CC0 signal INTTAB1OV signal kk k k i kk N + 1N + 1 N N M M 0000H 0000H M i i k k (b) M < N 16-bit counter Transfer timing CCR0 buffer register TAB1CCR0 register TAB1CCR1 register CCR1 buffer register TOAB1T1 pin output INTTAB1CC0 signal INTTAB1OV signal kki N + 1N + 1 N N M M 0000H 0000H M i i k k Remarks 1. If transfer (match between the value of the 16- bit counter and the value of the CCR0 buffer register) occurs in the 6-phase PWM output mode, the value of t he TAB1CCR0 register plus 1 is loaded to the 16-bit counter. In this way, the expected wave can be output even if the cycle value is changed at the transfer timing of the cres t (match between the 16-bit counter value and the TAB1CCR0 register value) timing. 2. M: Value of CCR0 buffer register before rewriting N: Value of CCR0 buffer register after rewriting

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 638 of 1817 Sep 19, 2011 Figure 11-29. Example of Rewriting TAB1CCR0 Register (During Counting Down) 16-bit counter Transfer timing TAB1CCR0 register TAB1CCR1 register CCR1 buffer register CCR0 buffer register TOAB1T1 pin output INTTAB1CC0 signal INTTAB1OV signal k kk k ii N N M M + 1 N + 1 0000H 0000H M i i k k Because the next transfer timing is at the point of the valley (match between the 16-bit counter value and 0001H), the cycle value changes from the next cycle and output of a symmetrical triangular wave is maintained. Because the cycle changes, rewrite the duty value (voltage data value) as required.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 639 of 1817 Sep 19, 2011 (c) Rewriting TAB1CCRm register Figure 11-30. Example of Rewriting TAB1CCRm Register Transfer timing TAB1CCRm register 16-bit counter CCRm buffer register TOAB1Tm register INTTAB1CCm signal k k k i i rr r r i 0000H Rewriting during period <1> (rewriting during counting up) Because the TAB1CCRm register value is transferred at the transfer timing of the crest (match between the 16-bit counter value and TAB1CCRm register value), an asymmetrical triangular wave is output. Rewriting during period <2> (rewriting during counting down) Because the TAB1CCRm register value is transferred at the transfer timing of the valley (match between the 16-bit counter value and 0001H), a symmetrical triangular wave is output. Remark m = 1 to 3 (d) Transferring TAB1OPT1 register value Do not set the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits to other than 00000. When using the interrupt culling function, rewrite the TAB1OPT1 register in the intermittent batch rewrite mode (transfer culling mode). For details of rewriting the TAB1OPT1 register, see 11.4.3 Interrupt culling function.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 640 of 1817 Sep 19, 2011 (3) Intermittent batch rewrite mode (transfer culling mode) This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0 and setting the TAB1OPT2.TAB1RDE bit to 1. In this mode, the values written to each compare register are transferred to the internal buffer register all at once after the culled transfer timing and compared with the counter value. The transfer timing is the timing at which an interrupt is generated (INTTAB1CC0, INTTAB1OV) by interrupt culling. For details of the interrupt culling function, see 11.4.3 Interrupt culling function. (a) Rewriting procedure If data is written to the TAB1CCR1 register, the data of the TAB1CCR0 to TAB1CCR3, TAB1OPT1, TAA4CCR0, and TAA4CCR1 registers are transferred all at once to the in ternal buffer register at the next transfer timing. Therefore, write to the TAB1CCR1 register last. Writ ing to the register is prohibited after the TAB1CCR1 register has been written until the transfer timing is ge nerated (until the INTTAB1OV or INTTAB1CC0 interrupt occurs). The operation procedure is as follows. <1> Rewrite the TAB1CCR0, TAB1CCR2, TAB1CCR3, TAB1OPT1, TAA4CCR0, and TAA4CCR1 registers. Do not rewrite registers that do not have to be rewritten. <2> Rewrite the TAB1CCR1 register. Rewrite the same value to the register even when it is not necessary to rewrite the TAB1CCR1 register. <3> Hold the next rewriting pending until the transfer timing is generated. Perform the next rewrite after the INTTAB1 OV or INTTAB1CC0 interrupt has occurred. <4> Return to <1>.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 641 of 1817 Sep 19, 2011 Figure 11-31. Basic Operation in Intermittent Batch Rewrite Mode INTTAB1OV signal INTTAB1CC0 signal CCR2 buffer register CCR3 buffer register OPT1 buffer register TAB1CCR2 register TAB1CCR3 register TAB1OPT1 register <Q4> <Q4> 16-bit counter (TAB1) Transfer timing TAB1CCR0 register TAB1CCR1 register CCR0 buffer register CCR1 buffer register <Q3> <Q3> 16-bit counter (TAA4) Transfer timing TAA4CCR0 register TAA4CCR1 register CCR0 buffer register CCR1 buffer register <P3> <P3> <Q3> <Q3> <Q3> [TAB1 operation] <Q1> Write the TAB1CCR1 register. <Q2> Rewrite the register at t he transfer timing that is generated a fter the TAB1CCR1 register has been rewritten. <Q3> The registers are transferred all at once at the transfer timing. <Q4> The transfer timing is also culled as the interrupts are culled. [TAA4 operation] <P1> Write the TAB1CCR1 register. <P2> Rewrite the register at t he transfer timing that is generated a fter the TAB1CCR1 register has been rewritten. <P3> The registers are transferred all at once at the transfer timing. <P4> The transfer timing is also culled as the interrupts are culled. Remark This is an example of the operation when the TAB1OPT1.TAB1ICE bit = 1, TAB1OPT1.TAB1IOE bit = 1, and TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 642 of 1817 Sep 19, 2011 (b) Rewriting TAB1CCR0 register When rewriting the TAB1CCR0 register in the intermi ttent batch mode, the output waveform differs depending on where the occurrence of the crest or valley interrup t is specified by the interrupt culling setting. The following figure illustrates the change of the output waveform when interrupts are culled. Figure 11-32. Rewriting TAB1CCR0 Register (When Crest Interrupt Is Set) 16-bit counter Transfer timing TAB1CCR0 register TAB1CCR1 register CCR0 buffer register CCR1 buffer register INTTAB1CC0 signal TOAB1T1 pin output INTTAB1OV signal i L i M M 0000H 0000H M N N k k k k kk N + 1i i i The transfer timing is generated when the crest interr upt occurs, the cycle of counting up and counting down changes, and an asymmetrical triangular wave is output. Remarks 1. This is an example of the operation when the TAB1OPT1.TAB1ICE bit = 1, TAB1OPT1.TAB1IOE bit = 0, and TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001. 2. : Culled interrupt

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 643 of 1817 Sep 19, 2011 Figure 11-33. Rewriting TAB1CCR0 Register (When Valley Interrupt Is Set) i L i i M 0000H 0000H M N N k k kk M + 1M + 1 N + 1i i i 16-bit counter Transfer timing TAB1CCR0 register TAB1CCR1 register CCR0 buffer register CCR1 buffer register INTTAB1CC0 signal TOAB1T1 pin output INTTAB1OV signal The transfer timing is generated when the valley interr upt occurs, the cycle of counting up becomes same as cycle of counting down, and a symmetrical triangular wave is output. Remarks 1. This is an example of the operation when the TAB1OPT1.TAB1ICE bit = 0, TAB1OPT1.TAB1IOE bit = 1, and TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001. 2. : Culled interrupt

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 644 of 1817 Sep 19, 2011 (c) Rewriting TAB1CCR1 to TAB1CCR3 registers

• Transfer at crest when crest interrupt is set Because the register is transferred at the transfer ti ming of the crest interrupt, an asymmetrical triangular wave is output. Figure 11-34. Rewriting TAB1CCR1 Register (TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 0, TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00001) 16-bit counter Transfer timing TAB1CCR1 register CCR1 buffer register TOAB1T1 pin output i i i r ik Transfer at crest interrupt k k i INTTAB1CC0 signal INTTAB1OV signal Remark : Culled interrupt

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 645 of 1817 Sep 19, 2011

• Transfer at valley when valley interrupt is set Because the register is transferred at the transfer timing of the valley interrupt, a symmetrical triangular wave is output. Figure 11-35. Rewriting TAB1CCR1 Register (TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00001) 16-bit counter Transfer timing TAB1CCR1 register CCR1 buffer register TOAB1T1 pin output i i r ik Transfer at valley interrupt Transfer at valley interrupt r k kk i INTTAB1CC0 signal INTTAB1OV signal Remark : Culled interrupt (d) Rewriting TAB1OPT1 register Because a new interrupt culling value is transferred when the value of the interrupt culling counter matches the value of the 16-bit counter, the next interrupt and those that follow occur at the set interval. For details of rewriting the TAB1OPT1 register, see 11.4.3 Interrupt culling function.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 646 of 1817 Sep 19, 2011 (4) Rewriting TAB1OPT0.TAB1CMS bit The TAB1CMS bit can select the anytim e rewrite mode and batch rewrite mode. This bit can be rewritten during timer operation (when TAB1CTL0.TAB1CE bit = 1). However, the operation and caution illustrated in Figure 11-36 are necessary. If the TAB1CCR1 register is written when the TAB1CMS bit is cleared to 0, a transfer request signal (internal signal) is set. When the transfer request signal is set, the register is transferred at the next transfer timing, and the transfer request signal is cleared. This transfer request signal is also cleared when the TAB1CMS bit is set to 1. Figure 11-36. Rewriting TAB1CMS Bit 16-bit counter Transfer request signal Transfer timing <1> <2> <3> TAB1CCR1 register 0000HCCR1 buffer register Write signal of TAB1CCR1 Clear Clear TAB1CMS bit ir rs sk i <1> If the TAB1CCR1 register is rewritten when the TAB1CMS bit is 0, the transfer request signal is set. If the TAB1CMS bit is set to 1 in this st atus, the transfer request signal is cleared. <2> The register is not transferred because the TAB1CM S bit is set to 1 and the transfer request signal is cleared. <3> The transfer request signal is not set even if the TAB1CCR1 register is written when the TAB1CMS bit is 1. <4> The transfer request signal is not set even if the TAB1CCR1 register is written when the TAB1CMS bit is 1, so even if the TAB1CMS bit is cleared to 0, transfer does not occur at the subsequent transfer timing. <5> The transfer request signal is set if the TAB1CCR1 register is written when the TAB1CMS bit is 0. Transfer is performed at the subsequent transfer timing and the transfer request signal is cleared. <6> Once transfer has been performed, the transfer re quest signal is cleared. Therefore, transfer is not performed at the next transfer timing.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 647 of 1817 Sep 19, 2011

11.4.5 TAA4 tuning operation for A/D co nversion start trigger signal output

This section explains the tuning operation of TAA4 and TAB1 in the 6-phase PWM output mode. In the 6-phase PWM output mode, the tu ning operation is performed with TAB1 serving as the master and TAA4 as a slave. The conversion start trigger signal of the A/D converter can be set as the A/D conversion start trigger source by the INTTAA4CC0 and INTTAA4CC1 signals of TAA4 and the INTTAB1OV and INTTAB1CC0 signals of TAB1. (1) Tuning operation starting procedure The TAA4 and TAB1 registers should be set using the following procedure to perform the tuning operation. (a) Setting of TAA4 register (stop the operations of TAB1 and TAA4 (by clearing the TAB1CTL0.TAB1CE bit and TAA4CTL0.TAA4CE bit to 0)).

• Set the TAA4CTL1 register to 85H (set the tuning operation slave mode and free-running timer mode).
• Clear the TAA4OPT0 register to 00H (select the compare register).
• Set an appropriate value to the TAA4CCR0 and TAA4C CR1 registers (set the default value for comparison for starting the operation). (b) Setting of TAB1 register
• Set the TAB1CTL1 register to 07H (master mode and 6-phase PWM output mode).
• Set an appropriate value to the TAB1IOC0 register (set the output mode of TOAB1T1 to TOAB1T3). However, clear the TAB1OL0 bit to 0 and set the TAB1OE 0 bit to 1 (enable positive phase output). Unless this setting is made, the crest interrupt (INTTAB1CC0 ) and valley interrupt (INTTAB1OV) do not occur. Consequently, the conversion start trigger signal of the A/D converter is not correctly generated.
• Set the TAB1IOC1 and TAB1IOC2 registers to 00H (the TIAB10 to TIAB13, EVTB1, and TRGB1 pins of TAB1 are not used).
• Clear the TAB1OPT0 register to 00H (select the compare register).
• Set an appropriate value to the TAB1CCR0 to TAB1CCR3 registers (set the default value for comparison for starting the operation).
• Set the TAB1CTL0 register to 0xH (clear the TAB1CE bit to 0 and set the operating clock of TAB1).
• The operating clock of TAB1 se t by the TAB1CTL0 register is al so supplied to TAA4, and the count operation is performed at the same timing. The operating clock of TAA4 set by the TAA4CTL0 register is ignored. (c) Setting of TAB1OP (TAB1 option) register
• Set an appropriate value to the TAB1OPT1 and TAB1OPT2 registers.
• Set an appropriate value to the TAB1IOC3 register (set TOAB1B1 to TOAB1B3 in the output mode).
• Set an appropriate value to the TAB1DTC register (set the default value for comparison for starting the operation). (d) Setting of alternate function
• Set the port to alternate function mode using the port control mode setting.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 648 of 1817 Sep 19, 2011 (e) Set the TAA4CE bit to 1 and set the TAB1CE bit to 1 immediately after that to start the 6-phase PWM output operation Rewriting the TAB1CTL0, TAB1CTL1, TAB1IOC1, TAB1IOC2, TAA4CTL0, and TAA4CTL1 registers is prohibited during operation. The operation and the PWM output wavefo rm are not guaranteed if any of these registers is rewritten during operation. However, rewriting the TAB1CTL0.TAB1CE bit to clear it is permitted. Manipulating (reading/writing) the other TAB1, TAA4, and TAB1 option registers is prohibited until the TAA4CTL0.TAA4CE bit is set to 1 and then the TAB1CE bit is set to 1. (2) Tuning operation clearing procedure To clear the tuning operation and exit the 6-phase PWM output mode, set the TAA4 and TAB1 registers using the following procedure. <1> Clear the TAB1CTL0.TAB1CE bit to 0 and stop the timer operation. <2> Clear the TAA4CTL0.TAA4CE bit to 0 so that TAA4 can be separated. <3> Stop the timer output by using the TAB1IOC0 register. <4> Clear the TAA4CTL1.TAA4SYE bit to 0 to clear the tuning operation. Caution Manipulating (reading/writing) the other TAB1, TAA4, and TAB1 option registers is prohibited until the TAB1CE bit is set to 1 and then the TAA4CE bit is set to 1. (3) When not tuning TAA4 When the match interrupt signal of TAA4 is not necessary as the conversion trigger s ource that starts the A/D converter, TAA4 can be used independently as a separate timer without being tuned. In this case, the match interrupt signal of TAA4 cannot be used as a trigger source to start A/D conversi on in the 6-phase PWM output mode. Therefore, fix the TAB1OPT2.TAB1AT0 to TAB1OPT2.TAB1AT3 bits to 0. The other control bits can be used in the same manner as when TAA4 is tuned. If TAA4 is not tuned, the compare registers (TAA4CCR0 and TAA4CCR1) of TAA4 are not affected by the setting of the TAB1OPT0.TAB1CMS and TAB1OPT2.TAB1RDE bit. For the initialization procedure when TAA4 is not tuned, see (b) to (e) in 11.4.5 (1) Tuning operation starting procedure. (a) is not necessary because it is a step used to set TAA4 for the tuning operation. (4) Basic operation of TAA4 during tuning operation The 16-bit counter of TAA4 only counts up. The 16-bit counter is cleared by the set cycle value of the TAB1CCR0 register and starts counting from 0000H again. The count value of this counter is the same as the value of the 16- bit counter of TAB1 when it counts up. However, it is not the same when the 16-bit counter of TAA4 counts down.

• When TAB1 counts up (same value) 16-bit counter of TAB1: 0000H → M (counting up) 16-bit counter of TAA4: 0000H → M (counting up)
• When TAB1 counts down (not same value) 16-bit counter of TAB1: M + 1 → 0001H (counting down) 16-bit counter of TAA4: 0000H → M (counting up)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 649 of 1817 Sep 19, 2011 Figure 11-37. TAA4 During Tuning Operation r s r s r s r s 16-bit counter of TAB1 16-bit counter of TAA4 M (carrier data)TAB1CCR0 register TOAB0T1 pin output (U) TOAB1B1 pin output (U) TAB1CCR1 register TAA4CCR0 register TAA4CCR1 register INTTAA4CC0 signal INTTAA4CC1 signal TAB1CCR2 register TAB1CCR3 register i (phase U data) s (A/D conversion start trigger timing 2) r (A/D conversion start trigger timing 3) j (phase V data) k (phase W data) i ii i j j j j kkkk M + 1 M + 1 TOAB1T2 pin output (V) TOAB1B2 pin output (V) TOAB1T3 pin output (W) TABTADT0 signal TOAB1B3 pin output (W) Note Note M M M Note The TABTADT0 signal is masked by the TAB1 OPT2.TAB1ATM2 and TAB1OPT2.TAB1ATM3 bits.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 650 of 1817 Sep 19, 2011

11.4.6 A/D conversion start trigger output function

The V850ES/JH3-E and V850ES/JJ3-E have a function to select four trigger sour ces (INTTAB1OV, INTTAB1CC0, INTTAA4CC0, INTTAA4CC1) to generate the A/D conversion start trigger signal (TABTADT0). The trigger sources are specified by the TAB1OPT2.TAB1AT0 to TAB1OPT2.TAB1AT3 bits.

• TAB1AT0 bit = 1: A/D conversion start trigger signal generated when INTTAB1OV (counter underflow) occurs.
• TAB1AT1 bit = 1: A/D conversion start trigger signal generated when INTTAB1CC0 (cycle match) occurs.
• TAB1AT2 bit = 1: A/D conversion start trigger signal generated when IN TTAA4CC0 (match of TAA4CCR0 register of TAA4 during tuning operation) occurs.
• TAB1AT3 bit = 1: A/D conversion start trigger signal generated when IN TTAA4CC1 (match of TAA4CCR1 register of TAA4 during tuning operation) occurs. The A/D conversion start trigger signals selected by the TAB1AT0 to TAB1AT3 bits are ORed and output. Therefore, two or more trigger sources can be specified at the same time. The INTTAB1OV and INTTAB1CC0 signals selected by the TAB1AT0 and TAB1AT1 bits are culled interrupt signals. Therefore, these signals are output after the interrupts have been culled and, unless interrupt output is enabled (by the TAB1OPT1.TAB1ICE and TAB1OPT1.TAB1IOE bits), the A/D conversion start trigger signal is not output. The trigger sources (INTTAA4CC0 and INTTAA4CC1) from T AA4 have a function to mask the A/D conversion start trigger signal depending on the count-up/count-down status of the 16-bit counter, if so set by the TAB1AT2 and TAB1AT3 bits.
• TAB1ATM2 bit: Corresponds to the TAB1AT2 bit and controls INTTAA4CC0 (match interrupt signal) of TAA4.
• TAB1ATM2 bit = 0: The A/D conversion start tri gger signal is output when the 16-bit counter counts up (TAB1OPT0.TAB1CUF bit = 0), and the A/D conver sion start trigger signal is not output when the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 1).
• TAB1ATM2 bit = 1: The A/D conversion start tri gger signal is output when the 16-bit counter counts up (TAB1OPT0.TAB1CUF bit = 1), and the A/D conver sion start trigger signal is not output when the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 0).
• TAB1ATM3 bit: Corresponds to the TAB1AT3 bit and controls INTTAA4CC1 (match interrupt signal) of TAA4.
• TAB1ATM3 bit = 0: The A/D conversion start tri gger signal is output when the 16-bit counter counts up (TAB1OPT0.TAB1CUF bit = 0), and the A/D conver sion start trigger signal is not output when the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 1).
• TAB1ATM3 bit = 1: The A/D conversion start tri gger signal is output when the 16-bit counter counts up (TAB1OPT0.TAB1CUF bit = 1), and the A/D conver sion start trigger signal is not output when the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 0). The TAB1ATM3, TAB1ATM2, and TAB1AT3 to TAB1AT0 bits can be rewritten while the timer is operating. If the bit that sets the A/D conversion start trigger signal is rewritten while the timer is operating, the new setting is immediately reflected in the output status of the A/D conversion start trigger signal. These control bits do not have a transfer function and can be used only in the anytime rewrite mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 651 of 1817 Sep 19, 2011 Cautions 1. The A/D conversion start trigger signal output that is set by the TAB1AT2 and TAB1AT3 bits can be used only when TAA4 is performing a tuning opera tion as the slave timer of TAB1. If TAB1 and TAA4 are not performing a tuning operation, or if a mode other than the 6-phase PWM output mode is used, the output cannot be guaranteed. 2. The TAB1 signal output is internally used to id entify whether the 16-bit counter is counting up or down. Therefore, enable TOAB10 pin output by clearing the TAB1IOC0.TAB1OL0 bit to 0 and setting the TAB1IOC0.TAB1OE0 bit to 1.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 652 of 1817 Sep 19, 2011 Figure 11-38. Example of A/D Conversion Start Trigger (TABTADT0) Signal Output (TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00000: Without Interrupt Culling) 16-bit counter INTTAB1OV signal INTTAA4CC0 signal INTTAA4CC1 signal TAB1CUF bit TABTADT0 signal TABTADT0 signal TABTADT0 signal TABTADT0 signal TABTADT0 signal TABTADT0 signal TABTADT0 signal TABTADT0 signal TAB1AT3 to TAB1AT0 bits = 0001 (INTTAB1OV signal output) TAB1AT3 to TAB1AT0 bits = 0010 (INTTAB1CC0 signal output) TAB1AT3 to TAB1AT0 bits = 0100, TAB1ATM2 bit = 0 (INTTAA4CC0 signal output during counting up) TAB1AT3 to TAB1AT0 bits = 0100, TAB1ATM2 bit = 1 (INTTAA4CC0 signal output during counting down) TAB1AT3 to TAB1AT0 bits = 1000, TAB1ATM3 bit = 1 (INTTAA4CC1 signal output during counting down) TAB1AT3 to TAB1AT0 bits = 0011 (setting to output A/D conversion start trigger signal when both crest and valley interrupts occur) TAB1AT3 to TAB1AT0 bits = 1100, TAB1ATM3 bit = 1, TAB1ATM2 bit = 0 (INTTAA4CC0 and INTTAA4CC1 signals ORed for output. Setting to output A/D conversion start trigger signal when match interrupt of TAA4 occurs when counter is counting up or down) TAB1AT3 to TAB1AT0 bits = 1000, TAB1ATM3 bit = 0 (INTTAA4CC1 signal output during counting up) INTTAB1CC0 signal

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 11 MOTOR CONTROL FUNCTION R01UH0290EJ0300 Rev.3.00 Page 654 of 1817 Sep 19, 2011 (1) Operation under boundary condition (operation when 16-bit counter matches INTTAA4CC0 signal) Table 11-3. Operation When TAB1CCR0 Register = M, TAB1AT2 Bit = 1, TAB1ATM2 Bit = 0 (Counting Up Period Selected) Value of TAA4CCR0 Register Value of 16-Bit Counter of TAB1 Value of 16-Bit Counter of TAA4 Status of 16-Bit Counter of TAB1 TABTADT0 Signal Output by INTTAA4CC0 Signal 0000H 0000H 0000H − Output 0000H M + 1 0000H − Not output 0001H 0001H 0001H Count-up Output 0001H M 0001H Count-down Not output M M M Count-up Output M 0001H M Count-down Not output Table 11-4. Operation When TAB1CCR0 Register = M, TAB1AT2 Bit = 1, TAB1ATM2 Bit = 1 (Counting Down Period Selected) Value of TAA4CCR0 Register Value of 16-Bit Counter of TAB1 Value of 16-Bit Counter of TAA4 Status of 16-Bit Counter of TAB1 TABTADT0 Signal Output by INTTAA4CC0 Signal 0000H 0000H 0000H − Not output 0000H M + 1 0000H − Output 0001H 0001H 0001H Count-up Not output 0001H M 0001H Count-down Output M M M Count-up Not output M 0001H M Count-down Output Caution The TAA4CCRm register enables the setting of “0 ” to “M” when the TAB1CCR0 register = M. Setting a value of “M + 1” or higher is prohibited. If a value of “M + 1” or higher is set, the 16-bit counter of TAA4 is cleared by “M”. Therefore, the TABTADT0 signal is not output. Remark m = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 655 of 1817 Sep 19, 2011 CHAPTER 12 REAL-TIME COUNTER

12.1 Functions

The real-time counter (RTC) has the following features.

• Counting up to 99 years using year, month, day-of-w eek, day, hour, minute, and second sub-counters provided
• Y ear, month, day-of-week, day, hour, minute, and second counter display using BCD codes Note 1
• Alarm interrupt function
• Constant-period interrupt function (period: 1 month to 0.5 second)
• Interval interrupt function (period: 1.95 ms to 125 ms)
• Pin output function of 1 Hz
• Pin output function of 32.768 kHz
• Pin output function of 512 Hz or 16.384 kHz
• Watch error correction function
• Subclock operation or main clock operation Note 2 selectable Notes 1. A BCD (binary coded decimal) code expresses each digit of a decimal number in 4-bit binary format. 2. Use the baud rate generator dedicated to the real-time counter to divide the main clock frequency to 32.768 kHz for use.

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12.2 Configuration

The real-time counter includes the following hardware. Table 12-1. Configuration of Real-Time Counter Item Configuration Control registers Real-time counter control register 0 (RC1CC0) Real-time counter control register 1 (RC1CC1) Real-time counter control register 2 (RC1CC2) Real-time counter control register 3 (RC1CC3) Sub-count register (RC1SUBC) Second count register (RC1SEC) Minute count register (RC1MIN) Hour count register (RC1HOUR) Day count register (RC1DAY) Day-of-week count register (RC1WEEK) Month count register (RC1MONTH) Y ear count register (RC1YEAR) Watch error correction register (RC1SUBU) Alarm minute register (RC1ALM) Alarm hour register (RC1ALH) Alarm week register (RC1ALW) Prescaler mode register 0 (PRSM0) Prescaler compare register 0 (PRSCM0)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 657 of 1817 Sep 19, 2011 Figure 12-1. Block Diagram of Real-Time Counter Count enable/ disable circuit Sub-counter (16-bit) Second counter (7-bit) Second counter write buffer Minute counter write buffer Hour counter write buffer Day counter write buffer Week counter write buffer Minute counter (7-bit) Hour counter (6-bit) Day counter (3-bit) Day-of week counter (3-bit) INTRTC0 INTRTC1 1 minute 1 hour 1 day 1 month Count clock = 32.768 kHz fXT fXT/26 fXT/2 fXT/26 fXT/27 fXT/28 fXT/29 fXT/210 fXT/211 fXT/212 fBRGNote1 Month counter write buffer Y ear counter write buffer Month counter (5-bit) Y ear counter (8-bit) Minute alarm ICT2 to ICT0 Hour alarm Day-of-week alarm 12-bit counter CKDIV RINTE INTRTC2 RTCDIVNote2 CLOE2 RTCCLNote2 CLOE0 RTC1HZNote2 CLOE1 Selector Selector Selector Selector Note For detail of f BRG, refer to 12.3 (17) Prescaler mode register 0 (PRSM0) and 12.3 (18) Prescaler compare register 0 (PRSCM0). Remark f BRG: Real-time counter count clock frequency f XT: Subclock frequency INTRTC0: Real-time counter fixed-cycle interrupt signal INTRTC1: Real-time counter alarm match interrupt signal INTRTC2: Real-time counter interval interrupt signal

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12.2.1 Pin configuration

The RTC outputs included in the real-time counter are alternatively used as shown in Table 12-2. The port function must be set when using each pin (see Table 4-18 Settings When Pins Are Used for Alternate Functions). Table 12-2. Pin Configuration Pin Number V850ES/JH3-E V850ES/JJ3-E Port RTC Output Other Alternate Function 40 40 P22 RTC1HZ TIAB01/TOAB01/INTP02 39 39 P21 RTCDIV TIAB00/TOAB00/RTCCL 39 39 P21 RTCCL TIAB00/TOAB00/RTCDIV

12.2.2 Interrupt functions

The RTC includes the following three types of interrupt signals. (1) INTRTC0 A fixed-cycle interrupt signal is generated every 0.5 second, second, minute, hour, day, or month. (2) INTRTC1 Alarm interrupt signal (3) INTRTC2 An interval interrupt signal of a cycle of fXT/2 , fXT/2 , fXT/2 , fXT/2 , fXT/2 , fXT/2 , or fXT/2 is generated.

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12.3 Registers

The real-time counter is controlled by the following 18 registers. (1) Real-time counter control register 0 (RC1CC0) The RC1CC0 register selects the real-time counter input clock. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. RC1PWR Stops real-time counter operation. Enables real-time counter operation. RC1PWR Real-time counter operation control RC1CC0 RC1CKS 0 0 0 0 0 0 654321 Selects fXT as operation clock. Selects fBRG as operation clock. RC1CKS Operation clock selection After reset: 00H R/W Address: FFFFFADDH Cautions 1. Follow the description in 12.4.8 Initializing real-time counter when stopping (RC1PWR = 1 → 0) the real-time counter while it is operating. 2. The RC1CKS bit can be rewritten only when t he real-time counter is stopped (RC1PWR bit = 0). Furthermore, rewriting the RC1CKS bit at the same time as setting the RC1PWR bit from 0 to 1 is prohibited. (2) Real-time counter control register 1 (RC1CC1) The RC1CC1 register is an 8-bit regi ster that starts or stops the real -time counter, controls the RTCCL and RTC1HZ pins, selects the 12-hour or 24-hour system, and sets the fixed-cycle interrupt function. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 660 of 1817 Sep 19, 2011 RTCE Stops counter operation. Enables counter operation. RTCE Control of operation of each counter RC1CC1 0 CLOE1 CLOE0 AMPM CT2 CT1 CT0 654321 Disables RTC1HZ pin output (1 Hz) Enables RTC1HZ pin output (1 Hz) CLOE1 RTC1HZ pin output control Disables RTCCL pin output (32.768 kHz) Enables RTCCL pin output (32.768 kHz) CLOE0 RTCCL pin output control 24-hour system AMPM 12-hour system/24-hour system selection After reset: 00H R/W Address: FFFFFADEH Does not use fixed-cycle interrupts Once in 0.5 second (synchronous with second count-up) Once in 1 second (simultaneous with second count-up) Once in 1 minute (every minute at 00 seconds) Once in 1 hour (every hour at 00 minutes 00 seconds) Once in 1 day (every day at 00 hours 00 minutes 00 seconds) Once in 1 month (one day every month at 00 hours 00 minutes 00 seconds a.m.) CT2 Fixed-cycle interrupt (INTRTC0) selection CT1 CT0 Cautions 1. Writing 0 to the RTCE bi t while the RTCE bit is 1 is prohibited. Clear the RTCE bit by clearing the RC1PWR bit according to 12.4.8 Initializing real-time counter. 2. The RTC1HZ output operates as follows when the CLOE1 bit setting is changed.

• When changed from 0 to 1: The RTC1HZ output outputs a 1 Hz pulse after two clocks or less (2 × 32.768 kHz).
• When changed from 1 to 0: The RTC1HZ out put is stopped (fixed to low level) after two clocks or less (2 × 32.768 kHz). operation for setting or changing the AMPM bit. Furthermore, re-set the RC1HOUR register when the AMPM bit is rewritten. 4. See 12.4.4 Changing INTRTC0 interrupt setti ng during real-time counter operation when rewriting the CT2 to CT0 bits while the real-time counter operates (RC1PWR bit = 1).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 661 of 1817 Sep 19, 2011 (3) Real-time counter control register 2 (RC1CC2) The RC1CC2 register is an 8-bit register that controls the alarm interrupt function and waiting of counters. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. WALE Does not generate interrupt upon alarm match. Generates interrupt upon alarm match. WALE Alarm interrupt (INTRTC1) operation control RC1CC2 0000 0 RWST RWAIT 654321 Counter operating Counting up of second to year counters stopped (Reading and writing of counter values enabled) RWST Real-time counter wait state This is a status flag indicating whether the RWAIT bit setting is valid. Read or write counter values after confirming that the RWST bit is 1. Sets counter operation. Stops count operation of second to year counters. (Counter value read/write mode) RWAIT Real-time counter wait control This bit controls the operation of the counters. Be sure to write 1 to this bit when reading or writing counter values. If the RC1SUBC register overflows while the RWAIT bit is 1, the overflow information is retained internally and the RC1SEC register is counted up after two clocks or less (2 × 32.768 kHz) after 0 is written to the RWAIT bit. However, if the second counter value is rewritten while the RWAIT bit is 1, the retained overflow information is discarded. After reset: 00H R/W Address: FFFFFADFH Cautions 1 . See 12.4.5 Changing INTRTC1 interrupt setti ng during real-time counter operation when rewriting the WALE bit while the real-time counter operates (RC1PWR bit = 1). 2. Confirm that the RWST bit is set to 1 when reading or writing each counter value. 3. The RWST bit does not become 0 while each counter is being written, even if the RWAIT bit is set to 0. It becomes 0 when writing to each counter is completed.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 662 of 1817 Sep 19, 2011 (4) Real-time counter control register 3 (RC1CC3) The RC1CC3 register is an 8-bit register that controls the interval interrupt function and RTCDIV pin. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. RINTE Does not generate interval interrupt. Generates interval interrupt. RINTE Interval interrupt (INTRTC2) control RC1CC3 CLOE2 CKDIV 00 ICT2 ICT1 ICT0 654321 Disables RTCDIV pin output. Enables RTCDIV pin output. CLOE2 RTCDIV pin output control Outputs 512 Hz (1.95 ms) from RTCDIV pin. Outputs 16.384 kHz (0.061 ms) from RTCDIV pin. CKDIV0 RTCDIV pin output frequency selection After reset: 00H R/W Address: FFFFFAE0H 26/fXT (1.953125 ms) 27/fXT (3.90625 ms) 28/fXT (7.8125 ms) 29/fXT (15.625 ms) 210/fXT (31.25 ms) 211/fXT (62.5 ms) 212/fXT (125 ms) ICT2 Interval interrupt (INTRTC2) selection ICT1 ICT0 Cautions 1 . See 12.4.7 Changing INTRTC2 interrupt setti ng during real-time counter operation when rewriting the RINTE bit during real-time counter operation (RC1PWR bit = 1). 2. The RTCDIV output operates as follows when the CLOE2 bit setting is changed.

• When changed from 0 to 1: A pulse set by t he CKDIV bit is output after two clocks or less (2 × 32.768kHz).
• When changed from 1 to 0: Output of t he RTCDIV output is stopped after two clocks or less (fixed to low level, 2 × 32.768kHz)). 3. See 12.4.7 Changing INTRTC2 interrupt setti ng during real-time counter operation when rewriting the ICT2 to ICT0 bits while the real-time counter operates (RC1PWR bit = 1).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 663 of 1817 Sep 19, 2011 (5) Sub-count register (RC1SUBC) The RC1SUBC register is a 16-bit register that counts the reference time of 1 second of the real-time counter. It takes a value of 0000H to 7FFFH and counts one second with a clock of 32.768 kHz. This register is read-only, in 16-bit units. Reset sets this register to 0000H. Cautions 1 When a correction is made by using the RC1SUBU register, the value may become 8000H or more. 2. This register is also cleared by writing to the second count register. 3. The value read from this register is not gu aranteed if it is read during operation, because a changing value is read. RC1SUBC 12 1 08 6 42 After reset: 0000H R Address: FFFFFAD0H 14 013 11 9 7 5315 1 (6) Second count register (RC1SEC) The RC1SEC register is an 8-bit register that takes a valu e of 0 to 59 (decimal) and indicates the count value of seconds. It counts up when the sub-counter overflows. When data is written to this register , it is written to a buffer and then to the counter up to 2 clocks (2 × 32.768 kHz) later. Set a decimal value of 00 to 59 to this register in BCD code. If a value outside this range is set, the register value returns to the normal value after one period. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Setting the RC1SEC register to va lues other than 00 to 59 is prohibited. Remark See 12.4.1 Initial settings , 12.4.2 Rewriting each counter dur ing real-time counter operation , and

12.4.3 Reading each counter duri ng real-time counter operation when reading or writing the

RC1SEC register. 0RC1SEC After reset: 00H R/W Address: FFFFFAD2H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 664 of 1817 Sep 19, 2011 (7) Minute count register (RC1MIN) The RC1MIN register is an 8-bit register that takes a value of 0 to 59 (decim al) and indicates the count value of minutes. It counts up when the second counter overflows. When data is written to this register , it is written to a buffer and then to the counter up to 2 clocks (2 × 32.768 kHz) later. Set a decimal value of 00 to 59 to this register in BCD code. This register can be read or written 8-bit units. Reset sets this register to 00H. Caution Setting a value other than 00 to 59 to the RC1MIN register is prohibited. Remark See 12.4.1 Initial settings , 12.4.2 Rewriting each counter dur ing real-time counter operation , and RC1MIN register. 0RC1MIN After reset: 00H R/W Address: FFFFFAD3H (8) Hour count register (RC1HOUR) The RC1HOUR register is an 8-bit register that takes a value of 0 to 23 or 1 to 12 (decimal) and indicates the count value of hours. It counts up when the minute counter overflows. When data is written to this register , it is written to a buffer and then to the counter up to 2 clocks (2 × 32.768 kHz) later. Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. This register can be read or written 8-bit units. Reset sets this register to 12H. However, the value of this register is 00H if the AMPM bit is set to 1 after reset. system is selected). 2. Setting a value other than 01 to 12, 21 to 32 (AMPM bit= 0), or 00 to 23 (AMPM bit = 1) to the RC1HOUR register is prohibited. Remark See 12.4.1 Initial settings , 12.4.2 Rewriting each counter dur ing real-time counter operation , and RC1HOUR register. 00RC1HOUR After reset: 12H R/W Address: FFFFFAD4H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 665 of 1817 Sep 19, 2011 Table 12-3 shows the relationship among the AMPM bit setting value, RC1HOUR register value, and time. Table 12-3. Time Digit Display 12-Hour Display (AMPM Bit = 0) 24-Hour Display (AMPM Bit = 1) Time RC1HOUR Register Value Time RC1HOUR Register Value 0:00 a.m. 12 H 0:00 00H 1:00 a.m. 01 H 1:00 01 H 2:00 a.m. 02 H 2:00 02 H 3:00 a.m. 03 H 3:00 03 H 4:00 a.m. 04 H 4:00 04 H 5:00 a.m. 05 H 5:00 05 H 6:00 a.m. 06 H 6:00 06 H 7:00 a.m. 07 H 7:00 07 H 8:00 a.m. 08 H 8:00 08 H 9:00 a.m. 09 H 9:00 09 H 10:00 a.m. 10 H 10:00 10 H 11:00 a.m. 11 H 11:00 11 H 0:00 p.m. 32 H 12:00 12 H 1:00 p.m. 21 H 13:00 13 H 2:00 p.m. 22 H 14:00 14 H 3 :00 p.m. 23 H 15:00 15 H 4:00 p.m. 24 H 16:00 16 H 5:00 p.m. 25 H 17:00 17 H 6:00 p.m. 26 H 18:00 18 H 7:00 p.m. 27 H 19:00 19 H 8:00 p.m. 28 H 20:00 20 H 9:00 p.m. 29 H 21:00 21 H 10:00 p.m. 30 H 22:00 22 H 11:00 p.m. 31 H 23:00 23 H The RC1HOUR register value is displayed in 12 hour-format if the AMPM bit is 0 and in 24-hour format when the AMPM bit is 1. indicating noon or afternoon (p.m.).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 666 of 1817 Sep 19, 2011 (9) Day count register (RC1DAY) The RC1DAY register is an 8-bit register that takes a valu e of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows. This counter counts as follows.

• 01 to 31 (January, March, May, July, August, October, December)
• 01 to 30 (April, June, September, November)
• 01 to 29 (February in leap year)
• 01 to 28 (February in normal year) When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later. Set a decimal value of 00 to 31 to this register in BCD code. This register can be read or written in 8-bit units. Reset sets this register to 01H. Caution Setting a value other than 01 to 31 to the RC1DAY register is prohibited. Setting a value outside the above-mentioned count range, such as “February 30” is also prohibited. Remark See 12.4.1 Initial settings , 12.4.2 Rewriting each counter dur ing real-time counter operation , and

RC1DAY register. 00RC1DAY After reset: 01H R/W Address: FFFFFAD6H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 667 of 1817 Sep 19, 2011 (11) Day-of-week count register (RC1WEEK) The RC1WEEK register is an 8-bit regist er that takes a value of 0 to 6 ( decimal) and indicates the day-of-week count value. It counts up in synchronization with the day counter. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 × 32.768 kHz) later. Set a decimal value of 00 to 06 to this register in BCD code. This register can be read or written in 8-bit units. Reset sets this register to 00H. 00000RC1WEEK After reset: 00H R/W Address: FFFFFAD5H Cautions 1. Setting a value other than 00 to 06 to the RC1WEEK register is prohibited. 2. Values corresponding to the month count register and day count register are not automatically stored to the day-of-week register. Be sure to set as follows after reset. Day of Week RC1WEEK Sunday 00H Monday 01H Tuesday 02H Wednesday 03H Thursday 04H Friday 05H Saturday 06H Remark See 12.4.1 Initial settings, 12.4.2 Rewriting each counter during real-time counter operation, and RC1WEEK register.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 668 of 1817 Sep 19, 2011 (11) Month count register (RC1MONTH) The RC1MONTH register is an 8-bit regist er that takes a value of 1 to 12 ( decimal) and indicates the count value of months. It counts up when the day counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 × 32.768 kHz) later. Set a decimal value of 01 to 12 to this register in BCD code. This register can be read or written in 8-bit units. Reset sets this register to 01H. Caution Setting a value other than 01 to 12 to the RC1MONTH register is prohibited. Remark See 12.4.1 Initial settings, 12.4.2 Rewriting each counter during real-time counter operation, and RC1MONTH register. 000RC1MONTH After reset: 01H R/W Address: FFFFFAD7H (12) Year count re gister (RC1YEAR) The RC1YEAR register is an 8-bit register that takes a va lue of 0 to 99 (decimal) and indicates the count value of years. It counts up when the month counter overflows. Values 00, 04, 08, …, 92, and 96 indicate a leap year. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 × 32.768 kHz) later. Set a decimal value of 00 to 99 to this register in BCD code. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Setting a value other than 00 to 99 to the RC1YEAR register is prohibited. Remark See 12.4.1 Initial settings, 12.4.2 Rewriting each counter during real-time counter operation, and RC1YEAR register. RC1YEAR After reset: 00H R/W Address: FFFFFAD8H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 669 of 1817 Sep 19, 2011 (13) Watch error correction register (RC1SUBU) The RC1SUBU register is an 8-bit re gister that can be used to correct the watch with high accuracy when the watch is early or late, by changing the value (referenc e value: 7FFFH) overflowing from the sub-count register (RSUBC) to the second counter register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Remarks 1. The RC1SUBU register can be rewritten only when the real-time counter is set to its initial values. Be sure to see 12.4.1 Initial settings. 2. See 12.4.9 Watch error correction example of real-time counter for details of watch error correction. DEV Corrects watch errors when RC1SEC (second counter) is at 00, 20, or 40 seconds (every 20 seconds). Corrects watch errors when RC1SEC (second counter) is at 00 seconds (every 60 seconds). DEV Setting of watch error correction timing RC1SUBU F6 F5 F4 F3 F2 F1 F0 654321 Increments the RC1SUBC count value by the value set using the F5 to F0 bits (positive correction). Expression for calculating increment value: (Setting value of F5 to F0 bits − 1) × 2 Decrements the RC1SUBC count value by the value set using the F5 to F0 bits (negative correction). Expression for calculating decrement value: (Inverted value of setting value of F5 to F0 bits + 1) × 2 Setting of watch error correction value If the F6 to F0 bit values are {1/0, 0, 0, 0, 0, 0, 1/0}, watch error correction is not performed. After reset: 00H R/W Address: FFFFFAD9H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 670 of 1817 Sep 19, 2011 (14) Alarm minute setting register (RC1ALM) The RC1ALM register is an 8-bit register that is used to set minutes of alarm. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set, the alarm is not detected. 0RC1ALM After reset: 00H R/W Address: FFFFFADAH (15) Alarm hour setting register (RC1ALH) The RC1ALH register is an 8-bit register that is used to set hours of alarm. This register can be read or written in 8-bit units. Reset sets this register to 12H. Cautions 1. Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. If a value outside the range is set, the alarm is not detected. system) is selected. 00RC1ALH After reset: 12H R/W Address: FFFFFADBH

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 671 of 1817 Sep 19, 2011 (16) Alarm day-of-week setting register (RC1ALW) The RC1ALW register is an 8-bit register that is used to set the day-of-week of the alarm. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution See 12.4.5 Changing INTRTC1 interrupt se tting during clock operation when rewriting the RC1ALW register while the real-time counter operates (RC1PWR bit = 1).

0 RC1ALW6 RC1ALW5 RC1ALW4 RC1ALW3 RC1ALW2 RC1ALW1 RC1ALW0

Saturday Friday Thursday Wednesday Tuesday Monday Sunday RC1ALW After reset: 00H R/W Address: FFFFFADCH Does not generate alarm interrupt if RC1WEEK = 06H (Saturday). Generates an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 06H (Saturday). RC1ALW6 Alarm interrupt day-of-week bit 6 Does not generate alarm interrupt if RC1WEEK = 05H (Friday). Generates an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 05H (Friday). RC1ALW5 Alarm interrupt day-of-week bit 5 Does not generate alarm interrupt if RC1WEEK = 04H (Thursday). Generates an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 04H (Thursday). RC1ALW4 Alarm interrupt day-of-week bit 4 Does not generate alarm interrupt if RC1WEEK = 03H (Wednesday). Generates an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 03H (Wednesday). RC1ALW3 Alarm interrupt day-of-week bit 3 Does not generate alarm interrupt if RC1WEEK = 02H (Tuesday). Generates an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 02H (Tuesday). RC1ALW2 Alarm interrupt day-of-week bit 2 Does not generate alarm interrupt if RC1WEEK = 01H (Monday). Generates an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 01H ( Monday). RC1ALW1 Alarm interrupt day-of-week bit 1 Does not generate alarm interrupt if RC1WEEK = 00H (Sunday). Generates an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 00H (Sunday). RC1ALW0 Alarm interrupt day-of-week bit 0

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 672 of 1817 Sep 19, 2011 (a) Alarm interrupt setting examples (RC1ALM, RC1ALH, and RC1ALW setting examples) Tables 12-4 and 12-5 show setting examples if Sunday is RC1WEEK = 00, Monday is RC1WEEK = 01, Tuesday is RC1WEEK = 02, ···, and Saturday is RC1WEEK = 06. Table 12-4. Alarm Setting Example if AMPM = 0 (RC1HOUR Register 12-Hour Display) Register Alarm Setting Time RC1ALW RC1ALH RC1ALM Sunday, 7:00 a.m. 01H 07H 00H Sunday/Monday, 00:15 p.m. 03H 32H 15H Monday/Tuesday/Friday, 5:30 p.m. 26H 25H 30H Everyday, 10:45 p.m. 7FH 30H 45H Table 12-5. Alarm Setting Example if AMPM = 1 (RC1HOUR Register 24-Hour Display) Register Alarm Setting Time RC1ALW RC1ALH RC1ALM Sunday, 7:00 01H 07H 00H Sunday/Monday, 12:15 03H 12H 15H Monday/Tuesday/Friday, 17:30 26H 17H 30H Everyday, 22:45 7FH 22H 45H (17) Prescaler mode register 0 (PRSM0) The PRSM0 register is an 8-bit register that controls the generation of the real time counter count clock (fBRG). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. 0PRSM0 0 0 BGCE0 0 0 BGCS01 BGCS00 Disabled Enabled BGCE0 Main clock operation enable fX fX/2 fX/4 fX/8

5 MHz

1.6 μs

4 MHz

1 μs 2 μs BGCS01 BGCS00 Selection of real time counter source clock(f BGCS) After reset : 00H R/W Address : FFFFF8B0H < > Cautions 1. Do not change the values of the BG CS00 and BGCS01 bits during real time counteroperation. 2. Set the PRSM0 register befo re setting the BGCE0 bit to 1. 3. Set the PRSM0 and PRSCM0 registers accordi ng to the main clock frequency that is used so as to obtain an f BRG frequency of 32.768 kHz.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 673 of 1817 Sep 19, 2011 (18) Prescaler compare register 0 (PRSCM0) The PRSCM0 register is an 8-bit compare register. This register can be read or written in 8-bit units. Reset sets this register to 00H. PRSCM07PRSCM0 PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00 After reset: 00H R/W Address: FFFFF8B1H Cautions 1. Do not rewrite the PRSCM0 re gister during real time counter operation. 2. Set the PRSCM0 register before setting the PRSM0.BGCE0 bit to 1. 3. Set the PRSM0 and PRSCM0 registers accordi ng to the main clock frequency that is used so as to obtain an fBRG frequency of 32.768 kHz. The calculation for fBRG is shown below. fBRG = fBGCS/2N Remark f BGCS: Watch timer source clock set by the PRSM0 register N: Set value of the PRSCM0 register = 1 to 256 However, N = 256 when the PRSCM0 register is set to 00H.

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12.4 Operation

12.4.1 Initial settings

The initial settings are set when operating the watch function and performing a fixed-cycle interrupt operation. Figure 12-2. Initial Setting Procedure Setting AMPM and CT2 to CT0 RC1CC0.RC1PWR bit = 0 Start INTRTC Intrrupt generated? Stops counter operation. Selects 12-hour system or 24-hour system and interrupt (INTRTC0). RC1CC0.RC1PWR bit = 1 Enables real-time counter (RTC) internal clock operation. Sets each count register. Setting RC1SUBU Sets watch error correction. Setting RC1CKS Selects real-time counter (RTC) operation clock. No Yes Clearing interrupt IF flag Clears interrupt request flag (RTC0IF) Clearing interrupt MK flag Clears interrupt mask flag (RTC0MK) RC1CC1.RTCE bit = 1 Starts counter operation. Reading counter Setting RC1SEC (Clearing RC1SUBC) Setting RC1MIN Setting RC1HOUR Setting RC1WEEK Setting RC1DAY Setting RC1MONTH Setting RC1YEAR

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12.4.2 Rewriting each counter du ring real-time counter operation

Set as follows when rewriting each counter (RC1 SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY , RC1MONTH, RC1YEAR) during real-time counter operation (RC1PWR = 1). Figure 12-3. Rewriting Each Counter During Real-time Counter Operation Start RC1CC2.RWAIT bit = 1 Stops RC1SEC to RC1YEAR counters. Counter value write/read mode Setting AMPM Writing RC1SEC Writing RC1MIN Writing RC1HOUR Writing RC1WEEK Writing RC1DAY Writing RC1MONTH Setting RC1YEAR Writes to each count register. Selects watch counter display method. RC1CC2.RWAIT bit = 0 Sets RC1SEC to RC1YEAR counter operation. RC1CC2.RWST bit = 0?No Yes Checks counter wait status. Checks whether previous writing to RC1SEC to RC1YEAR counters is completed. End RC1CC2.RWST bit = 1?NoteNo Yes Note Be sure to confirm that RWST = 0 before setting STOP mode. Caution Complete the series of operations for setting RWAIT to 1 to clearing RWAIT to 0 within 1 second. If RWAIT = 1 is set, the operation of RC1SEC to RC1YEAR is stopped. If a carry occurs from RC1SUBC while RWAIT = 1, one carry can be inte rnally retained. However, if two or more carries occur, the number of carries cannot be retained. Remark RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY , RC1MONTH, and RC1YEAR may berewrite in any sequence. All the registers do not have to be set and only some registers may be read.

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12.4.3 Reading each counter durin g real-time counter operation

Set as follows when reading each counter (RC1SEC, RC1MIN, RC1HOUR, RC1W EEK, RC1DAY , RC1MONTH, RC1YEAR) during real-time counter operation (RC1PWR = 1, RTCE = 1). Figure 12-4. Reading Each Counter During Real-time Counter Operation Start RC1CC2.RWAIT bit = 1 Stops RC1SEC to RC1YEAR counters. Counter value write/read mode RC1CC2.RWAIT bit = 0 Sets RC1SEC to RC1YEAR counter operation. RC1CC2.RWST bit = 0?No Yes Checks counter wait status. Checks whether previous writing to RC1SEC to RC1YEAR is completed. End RC1CC2.RWST bit = 1?NoteNo Yes Reading RC1SEC Reading RC1MIN Reading RC1HOUR Reading RC1WEEK Reading RC1DAY Reading RC1MONTH Setting RC1YEAR Reads each count register. Note Be sure to confirm that RWST = 0 before setting STOP mode. Caution Complete the series of operations for setting RWAIT to 1 to clearing RWAIT to 0 within 1 second. If RWAIT = 1 is set, the operation of RC1SEC to RC1YEAR is stopped. If a carry occurs from RC1SUBC while RWAIT = 1, one carry can be inte rnally retained. However, if two or more carries occur, the number of carries cannot be retained. Remark RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DA Y , RC1MONTH, and RC1YEAR may be read in any sequence. All the registers do not have to be set and only some registers may be read.

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12.4.4 Changing INTRTC0 interrupt setti ng during real-time counter operation

If the setting of the INTRTC0 interrupt (fixed-cycle interr upt) signal is changed while the real-time counter clock operates (PC1PWR = 1, RTCE =1), the INTRCT0 interrupt waveform may include whiskers and unintended signals may be output. Set as follows when changing the setting of the INTRTC0 interrupt signal during real-time counter operation (RC1PWR = 1), in order to mask the whiskers. Figure 12-5. Changing INTRTC0 Interrupt Setting During Real-time Counter Operation Start Setting RTC0MK bit Masks INTRTC0 interrupt signal. Setting RC1CC1.CT2 to RC1CC1.CT0 Changes INTRTC0 interrupt signal setting. End Clearing RTC0IF flag Clears interrupt request flag. Clearing RTC0MK flag Unmasks INTRTC0 interrupt signal. Remark See 25.3.4 Interrupt control register (xxICn) for details of the RTC0IF and RTC0MK bits.

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12.4.5 Changing INTRTC1 interrupt setti ng during real-time counter operation

If the setting of the INTRTC1 interrupt (alarm interrupt) signal is changed while the real-time counter operates (RC1PWR = 1, RTCE = 1), the INTRCT1 interrupt waveform may include whiskers and unintended signals may be output. Set as follows when changing the setting of the INTRTC1 interrupt signal during real-time counter operation (PC1PWR = 1, RTCE = 1), in order to mask the whiskers. Figure 12-6. Changing INTRTC1 Interrupt Setting During Real-time Counter Operation Start Setting RTC1MK bit Masks interrupt signal (INTRTC1). RC1CC2.WALE bit = 0 Disables alarm interrupt. RC1CC2.WALE bit = 1 Enables alarm interrupt. End Clearing RTC1IF flag Clears interrupt pending bit. Setting RC1ALM Setting RC1ALH Setting RC1ALW Sets alarm minute register. Sets alarm hour register Sets alarm day-of-week register Clearing RTC1MK flag Unmasks interrupt signal (INTRTC1). Remark See 25.3.4 Interrupt control register (xxICn) for details of the RTC1IF and RTC1MK bits.

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12.4.6 Initial INTRTC2 interrupt settings

Set as follows to set the INTRTC1 interrupt (interval interrupt). Figure 12-7. INTRTC2 Interrupt Setting Start RC1CC0.RC1PWR bit = 1 Enables counter operation. Setting RC1CC3.ICT2 to RC1CC3.ICT0 bits <1> Selects INTRTC2 (interval) interrupt interval. End RC1CC3.RINTE bit = 1 <2> Enables INTRTC2 (interval) interrupt. Caution Set <1> and <2> simultaneously or set <1> first. Unintended waveform interrupts may occur if <2> is set first.

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12.4.7 Changing INTRTC2 interrupt setti ng during real-time counter operation

If the setting of the INTRTC2 interrupt (interval interrupt) is changed while the real -time counter clock operates (PC1PWR = 1, RTCE = 1), the INTRCT2 interrupt waveform may include whiskers and unintended signals may be output. Set as follows when changing the setting of the INTRTC2 interrupt signal during real-time counter operation (PC1PWR = 1, RTCE = 1), in order to mask the whiskers. Figure 12-8. Changing INTRTC2 Interrupt Setting During Real-time Counter Operation Start Setting RTC2MK bit Masks interrupt signal (INTRTC2). Setting RC1CC3.ICT2 to RC1CC3.ICT0 bits Selects INTRTC2 (interval) interrupt interval. End RC1CC3.RINTE bit = 1 Enables INTRTC2 (interval) interrupt. Clearing RTC2IF flag Clears interrupt pending bit. Clearing RTC2MK flag Unmasks interrupt signal (INTRTC2). Remark See 25.3.4 Interrupt control register (xxICn) for details of the RTC2IF and RTC2MK bits.

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12.4.8 Initializing real-time counter

The procedure for initializing the real-time counter is shown below. Figure 12-9. Initializing Real-Time Counter Start Setting RTCnMK bit Masks interrupt signal (INTRTCn) End RC1CC0.RC1PWR bit = 0 Initializes real-time counter (RTC). RTCDIV interrupt disable processing RTC1HZ interrupt disable processing RTCCL interrupt disable processing RC1CC3.CLOE2 bit = 0 RC1CC1.CLOE1 bit = 0 RC1CC1.CLOE0 bit = 0 Clearing RTCnIF flag Clears interrupt request bit. Clearing RTCnMK flag Unmasks interrupt signal (INTRTCn). Remarks 1. See 25.3.4 Interrupt control register (xxICn) for details of the RTCnIF and RTCnMK bits. 2. n = 0 to 2

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12.4.9 Watch error correction example of real-time counter

The watch error correction function corrects deviation in the oscillation frequency of a resonator connected to the V850ES/Jx3-E. Deviation, here, refers to steady-state deviation, which is deviation in the frequency when the resonator is designed. Next, the timing chart when an error has occurred in the input clock intended to be 32.768 kHz but a 32.7681 kHz resonator has been connected when designing the system, and the RC1SUBC and RC1SEC count operations to correct the error are shown below. Figure 12-10. Watch Error Correction Example RTCCLK (32.768 kHz) RC1SUBC Watch count(32.768 kHz) Watch count (32.7681 kHz/no error correction) Watch count (32.7681 kHz/error correction(DEV bit = 0, F6 bit = 0, F5 to F0 bit = 000010)) RC1SEC 01 7FFFH0000H 7FFFH 0000H 7FFFH0000H7FFFH7FFFH 0000H0000H RTCCLK (32.7681 kHz) RC1SUBC RC1SEC 7FFFH 7FFFH0000H 0000H 0000H 7FFFH 7FFFH 0000H 7FFFH 8000H 8001H 8000H 8001H0000H 0000H RTCCLK (32.7681 kHz) RC1SUBC RC1SEC 20 secondsNote 3 00 20 2 count numbers are added.2 count numbers are added. 20 secondsNote 1 19.99994 secondsNote 2 01 19 7FFFH 0000H0000H 7FFFH 7FFFH 7FFFH 0000H Notes 1. The RC1SEC counter counts 20 seconds every 32,768 cycles (0000H to 7FFFH) of the 32.768 kHz clock. 2. When 32,768 cycles (0000H to 7FFFH) of the 32.7681 kHz clock are input, the time counted by the RC1SEC counter is calculated as follows: 32,768/3,268.1 ≅ 0.999997 seconds If this counting continues 20 times, the time is calculated as follows: (32,768/32,768.1) x 20 ≅ 19.99994 seconds, which causes an error of 0.00006 seconds. 3. To precisely count 20 seconds by using a 32.7681 kHz clock, clear the DEV and F6 bits to 0 and set the F5 to F0 bits to 2H (000010B) in the RC1SUBU register. As a result, two additional cycles are counted every 20 seconds (when the RC1SEC counter count is 00, 20, and 40 seconds), so that the number of cycles counted at these points is not 32,768, but 32,770 (0000H to 8001H), which is exactly 20 seconds.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 683 of 1817 Sep 19, 2011 As shown in Figure 12-10, the watch can be accurately counted by incrementing the RC1SUBC count value, if a positive error faster than 32.768 kHz occurs at the resonator. Similarly, if a ne gative error slower than 32.768 kHz occurs at the resonator, the watch can be accurately counted by decrementing the RC1SUBC count value. The RC1SUBC correction value is determined by using the RC1SUBU.F6 to RC1SUBU.F0 bits. The F6 bit is used to determine whether to increment or de crement RC1SUBC and the F5 to F0 bits to determine the RC1SUBC value. (1) Incrementing the RC1SUBC count value The RC1SUBC count value is incremented by the value set using the F5 to F0 bits, by setting the F6 bit to 0. Expression for calculating the increment value: (F5 to F0 bit value − 1) × 2 [Example of incrementing the RC1SUBC count value: F6 bit = 0] If 15H (010101B) is set to the F5 to F0 bits (15H − 1) × 2 = 40 (increments the RC1SUBC count value by 40) RC1SUBC count value = 32,768 + 40 = 32,808 (2) Decrementing the RC1SUBC count value The RC1SUBC count value is decremented by an inverted value of the value set using the F5 to F0 bits, by setting the F6 bit to 1. Expression for calculating the decrement value: (Inverted value of F5 to F0 bit value + 1) × 2 [Example of decrementing the RC1SUBC count value: F6 bit = 1] If 15H (010101B) is set to the F5 to F0 bits Inverted data of 15H (010101B) = 2AH (101010B) (2AH + 1) × 2 = 86 (decrements the RC1SUBC count value by 86) RC1SUBC count value = 32,768 − 86 = 32,682

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 684 of 1817 Sep 19, 2011 (3) DEV bit The DEV bit determines when the setting by the F6 to F0 bits is enabled. The value set by the F6 to F0 bits is reflected upon the next timing, but not to the RC1SUBC count value every time. Table 12-6. DEV Bit Setting DEV Bit Value Timing of Reflecting Value to RC1SUBC 0 When RC1SEC is 00, 20, or 40 seconds. 1 When RC1SEC is 00 seconds. [Example when 0010101B is set to F6 to F0 bits]

• If the DEV bit is 0 The RC1SUBC count value is 32,808 at 00, 20, or 40 seconds. Otherwise, it is 32,768.
• IF DEV bit is 1 The RC1SUBC count value is 32,808 at 00 seconds. Otherwise, it is 32,768. As described above, the RC1SUBC count value is correct ed every 20 seconds or 60 seconds, instead of every second, in order to match the RC1SUBC count value with the deviation width of the resonator. The range in which the resonator frequency can be actually corrected is shown below.
• If the DEV bit is 0: 32.76180000 kHz to 32.77420000 kHz
• If the DEV bit is 1: 32.76593333 kHz to 32.77006667 kHz The range in which the frequency can be corrected when the DEV bit is 0 is three times wider than when the DEV bit is 1. However, the accuracy of setting the frequency when the DEV bit is 1 is three times that when the DEV bit is 0. Tables 12-7 and 12-8 show the setting values of the DEV, and F6 to F0 bits, and the corresponding frequencies that can be corrected.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 12 REAL-TIME COUNTER R01UH0290EJ0300 Rev.3.00 Page 685 of 1817 Sep 19, 2011 Table 12-7. Range of Frequencies That Can Be Corrected When DEV Bit = 0 F6 F5 to F0 RC1SUBC Correction Value Frequency of Connected Clock (Including Steady-State Deviation) 0 000000 No correction − 0 000001 No correction − 0 000010 Increments RC1SUBC count value by 2 once every 20 seconds 32.76810000 kHz 0 000011 Increments RC1SUBC count value by 4 once every 20 seconds 32.76820000 kHz 0 000100 Increments RC1SUBC count value by 6 once every 20 seconds 32.76830000 kHz . . . 0 111011 Increments RC1SUBC count value by 120 once every 20 seconds 32.77400000 kHz 0 111110 Increments RC1SUBC count value by 122 once every 20 seconds 32.77410000 kHz 0 111111 Increments RC1SUBC count value by 124 once every 20 seconds 32.77420000 kHz (upper limit) 1 000000 No correction − 1 000001 No correction − 1 000010 Decrements RC1SUBC count value by 124 once every 20 seconds 32.76180000 kHz (lower limit) 1 000011 Decrements RC1SUBC count value by 122 once every 20 seconds 32.76190000 kHz 1 000100 Decrements RC1SUBC count value by 120 once every 20 seconds 32.76200000 kHz . . . 1 11011 Decrements RC1SUBC count value by 6 once every 20 seconds 32.76770000 kHz 1 11110 Decrements RC1SUBC count value by 4 once every 20 seconds 32.76780000 kHz 1 11111 Decrements RC1SUBC count value by 2 once every 20 seconds 32.76790000 kHz Table 12-8. Range of Frequencies That Can Be Corrected When DEV Bit = 1 F6 F5 to F0 RC1SUBC Correction Value Frequency of Connected Clock (Including Steady-State Deviation) 0 000000 No correction − 0 000001 No correction − 0 000010 Increments RC1SUBC count value by 2 once every 60 seconds 32.76803333 kHz 0 000011 Increments RC1SUBC count value by 4 once every 60 seconds 32.76806667 kHz 0 000100 Increments RC1SUBC count value by 6 once every 60 seconds 32.76810000 kHz . . . 0 111011 Increments RC1SUBC count value by 120 once every 60 seconds 32.77000000 kHz 0 111110 Increments RC1SUBC count value by 122 once every 60 seconds 32.77003333 kHz 0 111111 Increments RC1SUBC count value by 124 once every 60 seconds 32.77006667 kHz (upper limit) 1 000000 No correction − 1 000001 No correction − 1 000010 Decrements RC1SUBC count value by 124 once every 60 seconds 32.76593333 kHz (lower limit) 1 000011 Decrements RC1SUBC count value by 122 once every 60 seconds 32.76596667 kHz 1 000100 Decrements RC1SUBC count value by 120 once every 60 seconds 32.76600000 kHz . . . . 1 11011 Decrements RC1SUBC count value by 6 once every 60 seconds 32.76790000 kHz 1 11110 Decrements RC1SUBC count value by 4 once every 60 seconds 32.76793333 kHz 1 11111 Decrements RC1SUBC count value by 2 once every 60 seconds 32.76796667 kHz

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13.1 Functions

Watchdog timer 2 has the following functions.

• Default-start watchdog timer Note 1 → Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDT2RES signal) → Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of INTWDT2 signal) Note 2
• Input from main clock, internal oscillation cl ock, and subclock selectable as the source clock Notes 1. Watchdog timer 2 automatically starts in the reset mode following reset release. When watchdog timer 2 is not used, ei ther stop its operation before reset is executed via this function, or clear watchdog timer 2 once and stop it within the next interval time. Also, write to the WDTM2 register for verification purposes once, even if the default settings (reset mode, interval time: fR/2 ) do not need to be changed. 2. For the non-maskable interrupt servicing due to a no n-maskable interrupt request signal (INTWDT2), see 25.2.2 (2) From INTWDT2 signal.

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13.2 Configuration

The following shows the block diagram of watchdog timer 2. Figure 13-1. Block Diagram of Watchdog Timer 2 fXX/210 Clock input controller Output controller WDT2RES (internal reset signal) WDCS22 Internal bus INTWDT2 WDCS21 WDCS20 fXT WDCS23WDCS240 WDM21 WDM20 Selector16-bit counter fXX/219 to fXX/226, fXT/29 to fXT/216, fR/212 to fR/219 Watchdog timer enable register (WDTE) Watchdog timer mode register 2 (WDTM2) 3 3 Clear fR/23 Remark f XX: Main clock frequency f XT: Subclock frequency f R: Internal oscillation clock frequency INTWDT2: Non-maskable interrupt request signal from watchdog timer 2 WDTRES2: Watchdog timer 2 reset signal Watchdog timer 2 includes the following hardware. Table 13-1. Configuration of Watchdog Timer 2 Item Configuration Control registers Watchdog timer mode register 2 (WDTM2) Watchdog timer enable register (WDTE)

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13.3 Registers

(1) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and operation clock of watchdog timer 2. This register can be read or written in 8-bit units. Th is register can be read any number of times, but it can be written only once following reset release. Reset sets this register to 67H. Caution Accessing the WDTM2 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock 0WDTM2 WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 After reset: 67H R/W Address: FFFFF6D0H Stops operation Non-maskable interrupt request mode (generation of INTWDT2 signal) Reset mode (generation of WDT2RES signal) WDM21 WDM20 Selection of operation mode of watchdog timer 2 Cautions 1. For details of the WDCS20 to W DCS24 bits, see Table 13-2 Watchdog Timer 2 Clock Selection. 2. Although watchdog timer 2 can be stopped just by stopping operation of the internal oscillator, clear the WDTM2 register to 00H to securely stop the timer (to avoid selection of the main clock or subclock due to an erroneous write operation). 3. If the WDTM2 register is rewritten twice afte r reset, an overflow signal is forcibly generated and the counter is reset. 4. To intentionally generate an overflow signa l, write data to the WDTM2 register twice, or write a value other than “ACH” to the WDTE register once. However, when the operation of watchdog timer 2 is set to be stopped, an overflow signal is not generated even if data is written to the WDTM2 register twice, or a value other than “ACH” is written to the WDTE register once. 5. To stop the operation of watchdog timer 2, set the RCM.RSTOP bit to 1 (to stop the internal oscillator) and write 00H in the WDTM 2 register. If the RCM.RSTOP bit cannot be set to 1, set the WDCS23 bit to 1 (2 n /fXX is selected and the clock can be stopped in the IDLE1, IDLW2, sub-IDLE, and subclock operation modes).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2 R01UH0290EJ0300 Rev.3.00 Page 689 of 1817 Sep 19, 2011 Table 13-2. Watchdog Timer 2 Clock Selection WDCS24 WDCS23 WDCS22 WDCS21 WDCS 20 Selected Clock 100 kHz (MIN.) 220 kHz (TYP.) 400 kHz (MAX.) 0 0 0 0 0 2 /fR 41.0 ms 18.6 ms 10.2 ms 0 0 0 0 1 2 /fR 81.9 ms 37.2 ms 20.5 ms 0 0 0 1 0 2 /fR 163.8 ms 74.5 ms 41.0 ms 0 0 0 1 1 2 /fR 327.7 ms 148.9 ms 81.9 ms 0 0 1 0 0 2 /fR 655.4 ms 297.9 ms 163.8 ms 0 0 1 0 1 2 /fR 1,310.7 ms 595.8 ms 327.7 ms 0 0 1 1 0 2 /fR 2,621.4 ms 1191.6 ms 655.4 ms 0 0 1 1 1 2 /fR (Default value) 5,242.9 ms 2383.1 ms 1,310.7 ms fXX = 50 MHz f XX = 48 MHz f XX = 32 MHz 0 1 0 0 0 2 /fXX 10.5 ms 10.9 ms 16.4 ms 0 1 0 0 1 2 /fXX 21.0 ms 21.8 ms 32.8 ms 0 1 0 1 0 2 /fXX 41.9 ms 43.7 ms 65.5 ms 0 1 0 1 1 2 /fXX 83.9 ms 87.4 ms 131.1 ms 0 1 1 0 0 2 /fXX 167.8 ms 174.8 ms 262.1 ms 0 1 1 0 1 2 /fXX 335.5 ms 349.5 ms 524.3 ms 0 1 1 1 0 2 /fXX 671.1 ms 699.1 ms 1048.6 ms 0 1 1 1 1 2 /fXX 1342.2 ms 1398.1 ms 2097.2 ms fXT = 32.768 kHz 1 × 0 0 0 2 /fXT 15.625 ms 1 × 0 0 1 2 /fXT 31.25 ms 1 × 0 1 0 2 /fXT 62.5 ms 1 × 0 1 1 2 /fXT 125 ms 1 × 1 0 0 2 /fXT 250 ms 1 × 1 0 1 2 /fXT 500 ms 1 × 1 1 0 2 /fXT 1,000 ms 1 × 1 1 1 2 /fXT 2,000 ms

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2 R01UH0290EJ0300 Rev.3.00 Page 690 of 1817 Sep 19, 2011 (2) Watchdog timer enable register (WDTE) The counter of watchdog timer 2 is cleared and counting restarted by writing “ACH” to the WDTE register. The WDTE register can be read or written in 8-bit units. Reset sets this register to 9AH. WDTE After reset: 9AH R/W Address: FFFFF6D1H Cautions 1. When a value other than “ACH” is writ ten to the WDTE register, an overflow signal is forcibly output. 2. When a 1-bit memory mani pulation instruction is executed for the WDTE register, an overflow signal is forcibly output. 3. To intentionally generate an overflow signa l, write a value other than “ACH” to the WDTE register once, or write data to the WDTM2 register twice. However, when the operation of watchdog timer 2 is set to be stopped, an overflow signal is not generated even if data is written to the WDTM2 register twice, or a value other than “ACH” is written to the WDTE register once. 4. The read value of the WDTE register is “9 AH” (which differs from written value “ACH”).

13.4 Operation

Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following rese t using byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register us ing an 8-bit memory manipulation instruction. After this, the operation of watchdog timer 2 cannot be stopped. The WDTM2.WDCS24 to WDTM2.WDCS20 bits are used to select the watchdog timer 2 loop detection time interval. Writing ACH to the WDTE register clear s the counter of watchdog timer 2 and star ts the count operation again. After the count operation has started, write ACH to WDTE within the loop detection time interval. If the time interval expires without ACH being written to the WDTE register, a reset signal (WDT2RES) or a non- maskable interrupt request signal (INTWDT2) is generated , depending on the set values of the WDTM2.WDM21 and WDTM2.WDM20 bits. When the WDTM2.WDM21 bit is set to 1 (reset mode), if a WD T overflow occurs during oscillation stabilization after a reset or standby is released, no internal reset will occur and the CPU clock will switch to the internal oscillation clock. To not use watchdog timer 2, write 00H to the WDTM2 register. For the non-maskable interrupt servicing while the non-maskable interrupt request mode is set, see 23.2.2 (2) From INTWDT2 signal.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO) R01UH0290EJ0300 Rev.3.00 Page 691 of 1817 Sep 19, 2011 CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO)

14.1 Function

The real-time output function tr ansfers the data preset to the RTBL0 and RTBH0 register s to the output latches via hardware and outputs the data to an external device, at the same time as a timer interrupt occurs. The pins through which the data is output to an external device constitute a port called the real-time output (RTO) port. Because signals without jitter can be output by using RTO, it is suitable for controlling a stepper motor. One 6-bit real-time output port channel is provided in the V850ES/JH3-E and one 8-bit real-time output port channel is provided in the V850ES/JJ3-E. The real-time output port can be set to the port mode or real-time output port mode in 1-bit units.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO) R01UH0290EJ0300 Rev.3.00 Page 692 of 1817 Sep 19, 2011

14.2 Configuration

The block diagram of RTO is shown below. Figure 14-1. Block Diagram of RTO INTTAA0CC0 INTTAA5CC0 INTTAA4CC0 RTPOE0 RTPEG0 BYTE0 EXTR0 RTP04 to RTP07 RTP00 to RTP03 Real-time output buffer register 0H (RTBH0) Real-time output latch 0H Selector Real-time output latch 0L Real-time output port control register 0 (RTPC0) Transfer trigger (H) Transfer trigger (L) Real-time output port mode register 0 (RTPM0) Internal bus Real-time output buffer register 0L (RTBL0) NoteNote RTPM05RTPM07 RTPM06 RTPM04 RTPM03 RTPM02 RTPM01 RTPM00 Note V850ES/JJ3-E only RTO includes the following hardware. Table 14-1. Configuration of RTO Item Configuration Registers Real-time output buffer registers 0L, 0H (RTBL0, RTBH0) Control registers Real-time output port mode register 0 (RTPM0) Real-time output port control register 0 (RTPC0)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO) R01UH0290EJ0300 Rev.3.00 Page 693 of 1817 Sep 19, 2011 (1) Real-time output buffer registers 0L, 0H (RTBL0, RTBH0) The RTBL0 and RTBH0 registers are 4-bit registers that hold output data in advance. These registers are each mapped to independent addresses in the peripheral I/O register area. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. If an operation mode of 4 bits × 1 channel, 2 bits × 1 channel, or 4 bits × 2 channels is specified (RTPC0.BYTE0 bit = 0), data can be set individually to the RTBL0 and RTBH0 registers. The data of both these registers can be read at once by specifying the address of either of these registers. If an operation mode of 6 bits × 1 channel is specified (BYTE0 bit = 1), 8-bit data can be set to both the RTBL0 and RTBH0 registers by writing the data to ei ther of these registers. Moreover, t he data of both these registers can be read at once by specifying the address of either of these registers. Table 14-2 shows the operation when the RTBL0 and RTBH0 registers are manipulated. RTBH07Note RTBL0 RTBH0 RTBH06Note RTBH05 RTBH04 RTBL03 RTBL02 RTBL01 RTBL00 After reset: 00H R/W Address: RTBL0 FFFFF6E0H, RTBH0 FFFFF6E2H Note V850ES/JJ3-E only Caution Accessing the RTBL0 and RTBH0 regi sters is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

• When the CPU operates on the subclo ck and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock Table 14-2. Operation During Manipulation of RTBL0 and RTBH0 Registers Operation Mode Read Write Note V850ES/JH3-E V850ES/JJ3-E Register to Be Manipulated Higher 4 Bits Lower 4 Bits Higher 4 Bits Lower 4 Bits RTBL0 RTBH0 RTBL0 Invalid RTBL0 4 bits × 1 channel, 2 bits × 1 channel 4 bits × 2 channels RTBH0 RTBH0 RTBL0 RTBH0 Invalid RTBL0 RTBH0 RTBL0 RTBH0 RTBL0 6 bits × 1 channel 8 bits × 1 channel RTBH0 RTBH0 RTBL0 RTBH0 RTBL0 Note After setting the real-time output port, set output data to the RTBL0 and RTBH0 registers by the time a real-time output trigger is generated.

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14.3 Registers

RTO is controlled using the following two registers.

• Real-time output port mode register 0 (RTPM0)
• Real-time output port control register 0 (RTPC0) (1) Real-time output port mode register 0 (RTPM0) The RTPM0 register selects the real-time output port mode or port mode in 1-bit units. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. RTPM07Note RTPM0m Real-time output disabled Real-time output enabled Control of real-time output port (m = 0 to 7) RTPM0 RTPM06Note RTPM05 RTPM04 RTPM03 RTPM02 RTPM01 RTPM00 After reset: 00H R/W Address: RTPM0 FFFFF6E4H Note V850ES/JJ3-E only Cautions 1. By enabling the real-time output operation (RTPC0.RTPOE0 bit = 1), the bits enabled for real-time output among the RT P00 to RTP07 signals perform real- time output, and the bits set to port mode output 0. 2. If real-time output is disabled (RTPOE0 bit = 0), the real-time output pins (RTP00 to RTP07) all output 0, regardless of the RTPM0 register setting. 3. In order to use this register for th e real-time output pins (RTP00 to RTP07), set these pins as real-time output port pins using the PMC and PFC registers.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO) R01UH0290EJ0300 Rev.3.00 Page 695 of 1817 Sep 19, 2011 (2) Real-time output port control register 0 (RTPC0) The RTPC0 register is a register that sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Table 14-4. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. RTPOE0 Disables operationNote 1 Enables operation RTPOE0 Control of real-time output operation RTPC0 RTPEG0 BYTE0 EXTR0 0 0 0 0 Falling edgeNote 2 Rising edge Valid edge of INTTP0CC0 signal 4 bits × 1 channel, 2 bits × 1 channel (V850ES/JH3-E) 4 bits × 2 channels (V850ES/JJ3-E) BYTE0 RTPEG0 Specification of channel configuration for real-time output After reset: 00H R/W Address: FFFFF6E5H < > 6 bits × 1 channel (V850ES/JH3-E) 8 bits × 1 channel (V850ES/JJ3-E) Notes 1. When the real-time output operation is disa bled (RTPOE0 bit = 0), all real-time output pins (RTP00 to RTP07) output “0”. 2. The INTTAA0CC0 signal is output for 1 clock of the count clock selected by TAA0. Caution Set the RTPEG0, BYTE0, and EXTR0 bits only when the RTPOE0 bit = 0. Table 14-3. Operation Modes and Output Triggers of Real-Time Output Port (V850ES/JH3-E) BYTE0 EXTR0 Operation Mode RTBH0 (RTP04, RTP05) RTBL0 (RTP00 to RTP03)

0 INTTAA5CC0 INTTAA4CC0 0

4 bits × 1 channel, 2 bits × 1 channel INTTAA4CC0 INTTAA0CC0

0 INTTAA4CC0 1

6 bits × 1 channel INTTAA0CC0 Table 14-4. Operation Modes and Output Triggers of Real-Time Output Port (V850ES/JJ3-E) BYTE0 EXTR0 Operation Mode RTBH0 (RTP04 to RTP07) RTBL0 (RTP00 to RTP03) 4 bits × 2 channel INTTAA4CC0 INTTAA0CC0 8 bits × 1 channel INTTAA0CC0

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14.4 Operation

If the real-time output operatio n is enabled by setting the RTPC0.RTPOE0 bi t to 1, the data of the RTBH0 and RTBL0 registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPC0.EXTR0 and RT PC0.BYTE0 bits). Of the transferred data, only the data of the bits for which real-time output is enabled by the RTPM0 r egister is output from the RTP00 to RTP07 bits . The bits for which real-time output is disabled by the RTPM0 register output 0. If the real-time output operation is disa bled by clearing the RTPOE0 bit to 0, the RTP00 to RTP07 signals output 0 regardless of the setting of the RTPM0 register. Figure 14-2. Example of Operation Timing of RTO0 (When EXTR0 Bit = 0, BYTE0 Bit = 0) ABABABAB D01 D02 D03 D04 D11 D12 D13 D14 D11 D12 D13 D14 D01 D02 D03 D04 INTTAA5CC0 (internal) INTTAA4CC0 (internal) CPU operation RTBH0 RTBL0 RT output latch 0 (H) RT output latch 0 (L) A: Software processing by INTTAA5CC0 interrupt request (RTBH0 write) B: Software processing by INTTAA4CC0 interrupt request (RTBL0 write) Remark For the operation during standby, see CHAPTER 27 STANDBY FUNCTION.

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14.5 Usage

(1) Disable real-time output. Clear the RTPC0.RTPOE0 bit to 0. (2) Perform initialization as follows.

• Set the alternate-function pins of port 4 After setting the PFC4.PFC4m bit and PFCE4.PFCE4m bit to the RTO pin, set the PMC4.PMC4m bit to 1 (m = 0 to 5: V850ES/JH3-E, m = 0 to 7: V850ES/JJ3-E).
• Specify the real-time output port mode or port mode in 1-bit units. Set the RTPM0 register.
• Channel configuration: Select the trigger and valid edge. Set the RTPC0.EXTR0, RTPC0. BYTE0, and RTPC0.RTPEG0 bits.
• Set the initial values to the RTBH0 and RTBL0 registers Note 1 (3) Enable real-time output. Set the RTPOE0 bit = 1. (4) Set the next output value to the RTBH0 and RTBL0 regi sters by the time the selected transfer trigger is generated Note 2 (5) Sequentially set the next real-t ime output value to the RTBH0 and RTBL0 registers via interrupt servicing corresponding to the selected trigger. Notes 1. If the RTBH0 and RTBL0 registers are written when t he RTPOE0 bit = 0, that value is transferred to real-time output latches 0H and 0L. 2. Even if the RTBH0 and RTBL0 registers are written wh en the RTPOE0 bit = 1, data is not transferred to real-time output latches 0H and 0L.

14.6 Cautions

(1) Prevent the following conflicts by software.

• Conflict between real-time output disable/enable switching (RTPOE0 bi t) and the selected real-time output trigger.
• Conflict between writing to the RT BH0 and RTBL0 registers in the re al-time output enabled status and the selected real-time output trigger. (2) Before performing initialization, disable real-time output (RTPOE0 bit = 0). (3) Once real-time output has been disabled (RTPOE0 bit = 0), be sure to initialize the RTBH0 and RTBL0 registers before enabling real-time output again (RTPOE0 bit = 0 → 1).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 698 of 1817 Sep 19, 2011 CHAPTER 15 A/D CONVERTER

15.1 Overview

The A/D converter converts analog input signals into digital values and has a resolution of 10 bits. The A/D converter of the V850ES/Jx3-E has the following number of ANI channels and ANI pins. Part Name V850ES/JH3-E V850ES/JJ3-E Number of ANI channels (m) 10 ch (m = 10) 12 ch (m = 12) ANI pin number (n) ANI0 to ANI9 (n = 0 to 9) ANI0 to ANI11 (n = 0 to 11) In this chapter, “m” indicates the number of ANI channels and “n” indicates the ANI pin (analog input pin) number. The A/D converter has the following features. { 10-bit resolution { Successive approximation method { Operating voltage: AVREF0 = 3.0 to 3.6 V { Analog input voltage: 0 V to AVREF0 { The following functions are provided as operation modes.

• Continuous select mode
• Continuous scan mode
• One-shot select mode
• One-shot scan mode { The following functions are provided as trigger modes.
• Software trigger mode
• External trigger mode (external, 1)
• Timer trigger mode { Power-fail monitor function (conversion result compare function)

15.2 Functions

(1) 10-bit resolution A/D conversion An analog input channel is selected from ANIn, and an A/D conversion operation is repeated at a resolution of 10 bits. Each time A/D conversion has been completed, an interrupt request signal (INTAD) is generated. (2) Power-fail detection function This function is used to detect a drop in the battery volt age. The result of A/D conversion (the value of the ADA0CRnH register) is compared with the value of the ADA0PFT register, and the INTAD signal is generated only when a specified comparison condition is satisfied.

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15.3 Configuration

The block diagram of the A/D converter is shown below. Figure 15-1. Block Diagram of A/D Converter ANI0 ANI1 ANI2 ANI11 Note 1 ADA0M2ADA0M1ADA0M0 ADA0S ADA0PFT Controller Voltage comparator ADA0PFM ADA0CR0 ADA0CR1 ADA0CR09 ADA0CR10Note 3 ADA0CR11Note 3 Internal bus AVREF0 ADA0CE bit AVSS INTAD Edge detectionADTRG Controller Sample & hold circuit ADA0ETS0 bit ADA0ETS1 bit ADA0CE bit ADA0TMD1 bit ADA0TMD0 bit Selector Selector ADA0PFE bit ADA0PFC bit SAR Voltage comparator Compare voltage generation DAC INTTAA2CC0 INTTAA2CC1 TABTADT0Note 2 Notes 1. ANI00 to ANI09 in the V850ES/JH3-E 2. The timer trigger signal from 6-phase PWM output circuit (TABOP) 3. ADA0CR00 to ADA0CR09 in the V850ES/JH3-E The A/D converter includes the following hardware. Table 15-1. Configuration of A/D Converter Item Configuration Analog inputs m channels (ANIn pins) Registers Successive approximation register (SAR) A/D conversion result registers n (ADA0CRn) A/D conversion result registers nH (ADA0CRnH): Only higher 8 bits can be read Control registers A/D converter mode registers 0 to 2 (ADA0M0 to ADA0M2) A/D converter channel specification register 0 (ADA0S) Power fail compare mode register (ADA0PFM) Power fail compare threshold value register (ADA0PFT)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 700 of 1817 Sep 19, 2011 (1) Successive approximation register (SAR) The SAR compares the voltage value of the analog input signal with the output voltage of the compare voltage generation DAC (compare voltage), and holds the comparison result starting from the most significant bit (MSB). When the comparison result has been held down to the leas t significant bit (LSB) (i.e., when A/D conversion is complete), the contents of the SAR are transferred to the ADA0CRn register. (2) A/D conversion result register n (ADA0CRn), A/D conversion result register nH (ADA0CRnH) The ADA0CRn register is a 16-bit regist er that stores the A/D conversion re sult. ADA0ARn consist of 12 registers and the A/D conversion result is stored in the 10 higher bits of the AD0CRn register corresponding to analog input. (The lower 6 bits are fixed to 0.) (3) A/D converter mode register 0 (ADA0M0) This register specifies the operation mode and controls the conversion operation by the A/D converter. (4) A/D converter mode register 1 (ADA0M1) This register sets the conversion time of the analog input signal to be converted. (5) A/D converter mode register 2 (ADA0M2) This register sets the hardware trigger mode. (6) A/D converter channel specification register (ADA0S) This register sets the input port that inputs the analog voltage to be converted. (7) Power-fail compare m ode register (ADA0PFM) This register sets the power-fail monitor mode. (8) Power-fail compare threshol d value register (ADA0PFT) The ADA0PFT register sets the threshold value that is compared with the value of A/D conversion result register nH (ADA0CRnH). The 8-bit data set to the ADA0PFT register is compared with the higher 8 bits of the A/D conversion result register (ADA0CRnH). (9) Controller The controller compares the result of the A/D conversion (the value of the ADA0CRnH register) with the value of the ADA0PFT register when A/D conversion is completed or when the power-fail detection function is used, and generates the INTAD signal only when a specified comparison condition is satisfied. (10) Sample & hold circuit The sample & hold circuit samples each of the analog i nput signals selected by the input circuit and sends the sampled data to the voltage comparator. This circuit also holds the sampled analog input signal voltage during A/D conversion. (11) Voltage comparator The voltage comparator compares a vo ltage value that has been sampled and he ld with the output voltage of the compare voltage generation DAC.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 701 of 1817 Sep 19, 2011 (12) Compare voltage generation DAC This compare voltage generati on DAC is connected between AV REF0 and AV SS and generates a voltage for comparison with the analog input signal. (13) ANIn pins These are analog input pins for the m A/D converte r channels and are used to input analog signals to be converted into digital signals. Pins other than the one selected as the analog input by the ADA0S register can be used as input port pins. Caution Make sure that the voltages input to the ANIn pins do not exceed the rated values. In particular if a voltage of AV REF0 or higher is input to a channel, the conversion value of that channel becomes undefined, and the conversion values of the other channels may also be affected. (14) AV REF0 pin This is the pin used to input the refere nce voltage of the A/D conv erter. Always make the potential at this pin the same as that at the VDD pin even when the A/D converter is not used. The signals input to the ANIn pins are converted to digital signals based on the voltage applied between the AVREF0 and AVSS pins. (15) AV SS pin This is the ground potential pin of the A/D converter. Always make the potential at this pin the same as that at the VSS pin even when the A/D converter is not used.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 702 of 1817 Sep 19, 2011

15.4 Registers

The A/D converter is controlled by the following registers.

• A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2)
• A/D converter channel specification register 0 (ADA0S)
• Power-fail compare mode register (ADA0PFM) The following registers are also used.
• A/D conversion result register n (ADA0CRn)
• A/D conversion result register nH (ADA0CRnH)
• Power-fail compare threshold value register (ADA0PFT) (1) A/D converter mode register 0 (ADA0M0) The ADA0M0 register is an 8-bit register that specifies the operation mode and controls conversion operations. This register can be read or written in 8-bit or 1-bit units. However, the ADA0EF bit is read-only. Reset sets this register to 00H. (1/2) ADA0CE ADA0CE Stops A/D conversion Enables A/D conversion A/D conversion control ADA0M0 0 ADA0MD1 ADA0MD0 ADA0ETS1 ADA0ETS0 ADA0TMD ADA0EF ADA0MD1 ADA0MD0 Continuous select mode Continuous scan mode One-shot select mode One-shot scan mode Specification of A/D converter operation mode After reset: 00H R/W Address: FFFFF200H < > < > ADA0ETS1 ADA0ETS0 No edge detection Falling edge detection Rising edge detection Detection of both rising and falling edges Specification of external trigger (ADTRG pin) input valid edge

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 703 of 1817 Sep 19, 2011 (2/2) ADA0TMD Software trigger mode External trigger mode/timer trigger mode Trigger mode specification ADA0EF A/D conversion stopped A/D conversion in progress A/D converter status display Cautions 1. Accessing the ADA0M0 register is pr ohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock 2. A write operation to bit 0 is ignored. 3. Changing the ADA0M1.ADA0FR2 to ADA0 M1.ADA0FR0 bits is prohibited while A/D conversion is enabled (ADA0CE bit = 1). 4. In the following modes, write data to the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT registers while A/D conversion is stopped (ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1).
• Normal conversion mode
• One-shot select mode/one-shot scan mode in high-speed conversion mode If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers are written in other modes during A/D conversion (ADA0EF bit = 1), the following will be performed according to the mode.
• In software trigger mode A/D conversion is stopped and started again from the beginning.
• In hardware trigger mode A/D conversion is stopped, and th e trigger standby status is set. 5. To select the external trigger mode/timer trigger mode (ADA0TMD bit = 1), set the high- speed conversion mode (ADA0M1.ADA0HS1 bi t = 1). Do not input a trigger during stabilization time that is inserted once af ter the A/D conversion operation is enabled (ADA0CE bit = 1). 6. When not using the A/D converter, stop th e operation by setting the ADA0CE bit to 0 to reduce the power consumption.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 704 of 1817 Sep 19, 2011 (2) A/D converter mode register 1 (ADA0M1) The ADA0M1 register is an 8-bit register that specifies the conversion time. This register can be read or written in 8-bit or 1-bit units. Reset sets this bit to 00H. ADA0HS1ADA0M1 0 00 ADA0FR2ADA0FR3 ADA0FR1 ADA0FR0 After reset: 00H R/W Address: FFFFF201H ADA0HS1 Normal conversion mode High-speed conversion mode Specification of normal conversion mode/high-speed mode (A/D conversion time) Cautions 1. Changing the ADA0M1 register is prohibited while A/D conversion is enabled (ADA0M0.ADA0CE bit = 1). 2. To select the external trigger mode/timer trigger mode (ADA0M0.ADA0TMD bit = 1), set the high-speed conversion mode (ADA0HS1 bi t = 1). Do not input a trigger during the stabilization time that is inserted once af ter the A/D conversion operation is enabled (ADA0CE bit = 1). 3. Be sure to clear bits 6 to 4 to “0”. Remark For A/D conversion time setting examples, see Tables 15-2 and 15-3.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 705 of 1817 Sep 19, 2011 Table 15-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0) A/D Conversion Time ADA0FR3 to ADA0FR0 Bits Stabilization Time + Conversion Time + Wait Time 50MHz 48 MHz 32 MHz 24 MHz 0000 26/f XX + 52/fXX + 54/fXX Setting prohibited Setting prohi bited Setting prohibited 5.50 μs 0001 52/f XX + 104/fXX + 106/fXX 5.24 μs 5.46 μs 8.19 μs Setting prohibited 0010 78/f XX + 156/fXX + 158/fXX 7.84 μs 8.17 μs Setting prohibited Setting prohibited 0011 100/f XX + 208/fXX + 210/fXX Setting prohibited Setting prohibited S etting prohibited Setting prohibited 0100 100/f XX + 260/fXX + 262/fXX Setting prohibited Setting prohibited S etting prohibited Setting prohibited 0101 100/fxx + 312/fxx + 314/f XX Setting prohibited Setting prohibited S etting prohibited Setting prohibited 0110 100/fxx + 364/fxx + 366/f XX Setting prohibited Setting prohibited S etting prohibited Setting prohibited 0111 100/f XX + 416/fXX + 418/fXX Setting prohibited Setting prohibited S etting prohibited Setting prohibited 1000 100/f XX + 468/fXX + 470/fXX Setting prohibited Setting prohibited S etting prohibited Setting prohibited 1001 100/f XX + 520/fXX + 522/fXX Setting prohibited Setting prohibited S etting prohibited Setting prohibited 1010 100/f XX + 572/fXX + 574/fXX Setting prohibited Setting prohibited S etting prohibited Setting prohibited 1011 100/f XX + 624/fXX + 626/fXX Setting prohibited Setting prohibited S etting prohibited Setting prohibited 1100 100/f XX + 676/fXX + 678/fXX Setting prohibited Setting prohibited S etting prohibited Setting prohibited 1101 100/f XX + 728/fXX + 730/fXX Setting prohibited Setting prohibited S etting prohibited Setting prohibited 1110 100/f XX + 780/fXX + 782/fXX Setting prohibited Setting prohibited S etting prohibited Setting prohibited 1111 100/f XX + 832/fXX + 834/fXX Setting prohibited Setting prohibited S etting prohibited Setting prohibited Other than above Setting prohibited Remark Stabilization time: A/D converter setup time (1 μs or longer) Conversion time: Actual A/D conversion time (2.16 to 3.12 μs) Wait time: Wait time inserted before the next conversion f XX: Main clock frequency In the normal conversion mode, the conversion is st arted after the stabilization time elapses after the ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.16 to 3.12 μs). Operation is stopped after the conversion ends and the A/D conversion end interrupt request signal (INTAD) is generated after the wait time elapses. Because the conversion operation is stopped during the wait time, operating current can be reduced. Cautions 1. Set as 2.6 μs ≤ conversion time ≤ 3.12 μs. 2. During A/D conversion, if the ADA0 M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers are written or a trigger is input, reconversion is carried out. However, if the stabilization time end timing conf licts with writing to these registers, or if the stabilization time end timing conflicts with the trigger input, a stabilization time of 64 clocks is reinserted. If a conflict occurs again with the reinserte d stabilization time end timing, the stabilization time is reinserted. Therefore do not set the tr igger input interval and control register write interval to 64 clocks or lower.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 706 of 1817 Sep 19, 2011 Table 15-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1) A/D Conversion Time ADA0FR3 to ADA0FR0 Bits Conversion Time (+ Stabilization Time) 50MHz 48 MHz 32 MHz 24 MHz 0000 52/f XX (+26/fXX) Setting prohibited Setting prohi bited Setting prohibited 2.17 μs 0001 104/f XX (+52/fXX) Setting prohibited 2.17 μs 3.25 μs 4.33 μs 0010 156/f XX (+78/fXX) 3.12 μs 3.25 μs 4.88 μs 6.50 μs 0011 208/f XX (+100/fXX) 4.16 μs 4.33 μs 6.50 μs 8.67 μs 0100 260/f XX (+100/fXX) 5.20 μs 5.42 μs 8.13 μs Setting prohibited 0101 312/f XX (+100/fXX) 6.24 μs 6.50 μs 9.75 μs Setting prohibited 0110 364/f XX (+100/fXX) 7.28 μs 7.58 μs Setting prohibited Setting prohibited 0111 416/f XX (+100/fXX) 8.32 μs 8.67 μs Setting prohibited Setting prohibited 1000 468/f XX (+100/fXX) 9.36 μs 9.75 μs Setting prohibited Setting prohibited 1001 520/f XX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited Setting prohibited 1010 572/f XX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited Setting prohibited 1011 624/f XX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited Setting prohibited 1100 676/f XX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited Setting prohibited 1101 728/f XX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited Setting prohibited 1110 780/f XX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited Setting prohibited 1111 832/f XX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited Setting prohibited Other than above Setting prohibited Remark Stabilization time: A/D converter setup time (1 μs or longer) Conversion time: Actual A/D conversion time (2.17 to 9.36 μs) f XX: Main clock frequency In the high-speed conversion mode, the conversion is started after the stabilization time elapses after the ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.17 to 9.36 μs). The A/D conversion end interrupt request signal (INTAD) is generated immediately after the conversion ends. In continuous conversion mode, the stabilization time is inserted only before the first conversion, and not inserted after the second conversion (the A/D converter remains running). Cautions 1. Set as 2.17 μs ≤ conversion time ≤ 9.36 μs. 2. In the high-speed conver sion mode, rewriting of the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers and trigger input are prohibited during the stabilization time.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 707 of 1817 Sep 19, 2011 (3) A/D converter mode register 2 (ADA0M2) The ADA0M2 register specifies the hardware trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. 0ADA0M2 0 0 0 00 ADA0TMD1 ADA0TMD0 ADA0TMD1 ADA0TMD0 Specification of hardware trigger mode External trigger mode (when ADTRG pin valid edge is detected) Timer trigger mode 0 (when INTTAA2CC0 interrupt request is generated) Timer trigger mode 1 (when INTTAA2CC1 interrupt request is generated) Timer trigger mode 2 (TABTADT0 signal) After reset: 00H R/W Address: FFFFF203H 65 43 2107 Cautions 1. In the following modes, write data to the ADA0M2 register while A/D conversion is stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1).

• Normal conversion mode
• One-shot select mode/one-shot scan mode in high-speed conversion mode 2. Be sure to clear bits 7 to 2 to “0”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 708 of 1817 Sep 19, 2011 (4) Analog input channel specification register 0 (ADA0S) The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. 0ADA0S 0 0 0 ADA0S3 ADA0S2 ADA0S1 ADA0S0 After reset: 00H R/W Address: FFFFF202H ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 Note ANI11Note ANI0 ANI0, ANI1 ANI0 to ANI2 ANI0 to ANI3 ANI0 to ANI4 ANI0 to ANI5 ANI0 to ANI6 ANI0 to ANI7 ANI0 to ANI8 ANI0 to ANI9 ANI0 to ANI10 Note ANI0 to ANI11Note ADA0S3 ADA0S2 ADA0S1 ADA0S0 Select mode Scan mode Note V850ES/JJ3-E only Cautions 1. In the following modes, write data to the ADA0S register while A/D conversion is stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1).

• Normal conversion mode
• One-shot select mode/one-shot scan mode in high-speed conversion mode 2. Be sure to clear bits 7 to 4 to “0”.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 709 of 1817 Sep 19, 2011 (5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) The ADA0CRn and ADA0CRnH registers store the A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, the ADA0CRn register is used for 16-bit access and the ADA0CRnH register for 8-bit access. The 10 bits of th e conversion result are read to the higher 10 bits of the ADA0CRn register, and 0 is read to the lower 6 bits. The higher 8 bits of the conversion result are read to the ADA0CRnH register. Caution Accessing the ADA0CRn and ADA0CRnH regist ers is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.

• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock After reset: Undefined R Address: ADA0CR0 FFFFF210H, ADA0CR1 FFFFF212H, ADA0CR2 FFFFF214H, ADA0CR3 FFFFF216H, ADA0CR4 FFFFF218H, ADA0CR5 FFFFF21AH, ADA0CR6 FFFFF21CH, ADA0CR7 FFFFF21EH, ADA0CR8 FFFFF220H, ADA0CR9 FFFFF222H, ADA0CR10 Note FFFFF224H, ADA0CR11Note FFFFF226H ADA0CRn AD9 AD8 AD7 AD6 A D 0 000000AD1AD2AD3AD4AD5 AD9ADA0CRnH AD8 AD7 AD6 AD5 AD4 AD3 AD2 76 54 321 0 After reset: Undefined R Address: ADA0CR0H FFFFF211H, ADA0CR1H FFFFF213H, ADA0CR2H FFFFF215H, ADA0CR3H FFFFF217H, ADA0CR4H FFFFF219H, ADA0CR5H FFFFF21BH, ADA0CR6H FFFFF21DH, ADA0CR7H FFFFF21FH, ADA0CR8H FFFFF221H, ADA0CR9H FFFFF223H, ADA0CR10H Note FFFFF225H, ADA0CR11HNote FFFFF227H Note V850ES/JJ3-E only Caution A write operation to the ADA0M0 and ADA0S registers may cause the contents of the ADA0CRn register to become undefined. After the conversion, read the conversion result before writing to the ADA0M0 and ADA0S regi sters. Correct conversion results may not be read at a timing other than the above.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 710 of 1817 Sep 19, 2011 The relationship between the analog voltage input to the analog input pins (ANIn) and the A/D conversion result (ADA0CRn register) is as follows. VIN SAR = INT ( AVREF0 × 1,024 + 0.5) ADA0CR Note = SAR × 64 Or, AVREF0 AVREF0 INT( ): Function that returns the integer of the value in ( ) VIN: Analog input voltage AVREF0: AV REF0 pin voltage ADA0CR: Value of ADA0CRn register Note The lower 6 bits of the ADA0CRn register are fixed to 0. The following shows the relationship between the analog input voltage and the A/D conversion results. Figure 15-2. Relationship Between Analog Input Voltage and A/D Conversion Results 1,023 1,022 1,021 Input voltage/AVREF0 2,048 1,024 2,048 1,024 2,048 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 A/D conversion results ADA0CRnSAR FFC0H FF80H FF40H 00C0H 0080H 0040H 0000H

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 711 of 1817 Sep 19, 2011 (6) Power-fail compare mode register (ADA0PFM) The ADA0PFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. ADA0PFE Power-fail compare disabled Power-fail compare enabled ADA0PFE Selection of power-fail compare enable/disable ADA0PFM ADA0PFC 00 000 0 Generates an interrupt request signal (INTAD) when ADA0CRnH ≥ ADA0PFT Generates an interrupt request signal (INTAD) when ADA0CRnH < ADA0PFT ADA0PFC Selection of power-fail compare mode After reset: 00H R/W Address: FFFFF204H < 7 > 65 43 210 Cautions 1. In the select mode, the 8-bit data set to the ADA0PFT regist er is compared with the value of the ADA0CRnH register specified by the ADA0S register. If the result matches the condition specified by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register and the INTAD signal is ge nerated. If it does not match, however, the interrupt signal is not generated. 2. In the scan mode, the 8-bit data set to the ADA0PFT register is compared with the contents of the ADA0CR0H register. If the result matches the c ondition specified by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register and the INTAD signal is generated. If it does not match, however, the INTAD signal is not generated. Regardless of the comparison r esult, the scan operati on is continued and the conversion result is st ored in the ADA0CRn register until the scan operation is completed. However, the INTAD signal is not generated after th e scan operation has been completed. 3. In the following modes, write data to the ADA0PFM register while A/D conversion is stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1).

• Normal conversion mode
• One-shot select mode/one-shot scan mode in high-speed conversion mode

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 712 of 1817 Sep 19, 2011 (7) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets the compare value in the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. ADA0PFT After reset: 00H R/W Address: FFFFF205H 76543210 Caution In the following modes, write data to the ADA0PFT register while A/D conversion is stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1).

• Normal conversion mode
• One-shot select mode/one-shot scan mode in high-speed conversion mode

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15.5 Operation

15.5.1 Basic operation

<1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set, conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or timer trigger mode. <2> When A/D conversion is started, the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> When the sample & hold circuit samples the input channel for a specific time, it ent ers the hold status, and holds the input analog voltage until A/D conversion is complete. <4> Set bit 9 of the successive approximation register (SAR), and set the compare voltage generation DAC to (1/2) AV REF0. <5> The voltage difference between the voltage of the compare voltage genera tion DAC and the analog input voltage is compared by the voltage comparator. If the analog input voltage is higher than (1/2) AV REF0, the MSB of the SAR remains set. If it is lower than (1/2) AVREF0, the MSB is reset. <6> Next, bit 8 of the SAR is automatically set and the next comparison is started. Depending on the value of bit 9, to which a result has been already set, the compare voltage generation DAC is selected as follows.

• Bit 9 = 1: (3/4) AVREF0
• Bit 9 = 0: (1/4) AVREF0 This compare voltage and the analog input voltage ar e compared and, depending on the result, bit 8 is manipulated as follows. Analog input voltage ≥ Compare voltage: Bit 8 = 1 Analog input voltage ≤ Compare voltage: Bit 8 = 0 <7> This comparison is continued to bit 0 of the SAR. <8> When comparison of the 10 bits is complete, the valid di gital result remains in the SAR, and is then transferred to and stored in the ADA0CRn register. After that, an A/D conversion end interrupt request signal (INTAD) is generated. <9> In one-shot select mode, conversion is stopped Note . In one-shot scan mode, conversion is stopped after scanning once Note . In continuous select mode, repeat steps <2> to <8 > until the ADA0M0.ADA0CE bit is cleared to 0. In continuous scan mode, repeat steps <2> to <8> for each channel. Note In the external trigger mode, timer trigger mode 0, or timer trigger mode 1, the trigger standby status is entered. Remark The trigger standby status means the status after the stabilization time has elapsed.

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15.5.2 Conversion op eration timing

Figure 15-3. Conversion Operation Timing (Continuous Conversion) (1) Operation in normal conversion mode (ADA0HS1 bit = 0) ADA0M0.ADA0CE bit Processing state Setup Stabilization time Conversion time Wait time Sampling First conversion Second conversion Setup SamplingWaitA/D conversion INTAD signal 2/fXX (MAX.) 0.5/f XXSampling time (2) Operation in high-speed conversion mode (ADA0HS1 bit = 1) ADA0M0.ADA0CE bit Processing state Setup Conversion time Sampling First conversion Second conversion SamplingA/D conversion A/D conversion INTAD signal 0.5/fXX Stabilization time 2/fXX (MAX.) Sampling time Remark The above timings are applicable when a trigger is generated within the stabilization time. If a trigger is generated after the stabilization time has elapsed, a trigger response time is inserted.

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15.5.3 Trigger mode

The timing of starting the conversion oper ation is specified by setting the trigger mode. The trigger mode includes the software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode. The ADA0M0.ADA0TMD bit is used to set the trigger mode. The hardware trigger modes are set by the ADA0M2.ADA0TMD1 and ADA0M2.ADA0TMD0 bits. (1) Software trigger mode When the ADA0M0.ADA0CE bit is set to 1, the signal of the analog input pin (ANIn pin) specified by the ADA0S register is converted. When conversion is complete, the result is stored in the ADA0CRn register. At the same time, the A/D conversion end interrupt request signal (INTAD) is generated. If the operation mode specified by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits is the continuous select/scan mode, the next conversion is repeated, unless the ADA0CE bit is cleared to 0 after completion of the conversion. Conversion is performed once and ends if the operation mode is the one-shot select/scan mode. When conversion is started, the ADA0M0.ADA0EF bit is set to 1 (indicating that conversion is in progress). If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT regi ster is written during conv ersion, the conversion is aborted and started again from the beginning. However, writing to these registers is prohibited in the normal conversion mode and one-shot select mode/one-shot scan mode in the high-speed conversion mode. (2) External trigger mode In this mode, converting the signal of the analog input pin (ANIn) specified by the ADA0 S register is started when an external trigger is input (to the ADTRG pin). Which edge of the external trigger is to be detected (i.e., the rising edge, falling edge, or both rising and falling edges) can be specified by using the ADA0M0.ADA0ETS1 and ADA0M0.ATA0ETS0 bits. When the ADA0CE bit is set to 1, the A/D converter waits for the trigger, and starts conversion after the external trigger has been input. When conversion is completed, the result of conversion is stored in the ADA0CRn register, regardless of whether the continuous select, continuous scan, one-shot select, or one-shot scan mode is set as the operation mode by the ADA0MD1 and ADA0MD0 bits. At the same time, the INTAD signal is generated, and the A/D converter waits for the trigger again. When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the A/D converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is stopped). If the valid trigger is input during the conversion operati on, the conversion is aborted and started again from the beginning. If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT regi ster is written during the conversion operation, the conversion is aborted, and the A/D converter waits for the tr igger again. However, writing to these registers is prohibited in the one-shot select mode/one-shot scan mode. Caution To select the external trigger mode, set the high-speed conversion mode. Do not input a trigger during the stabilization time that is inserted on ce after the A/D conversion operation is enabled (ADA0M0.ADA0CE bit = 1). Remark The trigger standby status me ans the status after the stabilization time has elapsed.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 716 of 1817 Sep 19, 2011 (3) Timer trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI11) specified by the ADA0S register is started by the compare match interrupt request signal (INTTAA2CC0 or INTTAA2CC1 ) of the capture/compare register connected to the timer. The INTTAA2CC0 or INTTAA2CC1 signal is selected by the ADA0TMD1 and ADA0TMD0 bits, and conversion is started at the rising edge of the specified compare match interrupt request signal. When the ADA0CE bit is set to 1, the A/D converter waits for a trigger, and starts conversion when the compare match interrupt request signal of the timer is input. When conversion is completed, regardless of whether the c ontinuous select, continuous scan, one-shot select, or one-shot scan mode is set as the operation mode by the ADA0MD1 and ADA0MD0 bits, the result of the conversion is stored in the ADA0CRn register. At the same time, t he INTAD signal is generated, and the A/D converter waits for the trigger again. When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the A/D converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is stopped). If the valid trigger is input during the conversion operati on, the conversion is aborted and started again from the beginning. If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT regi ster is written during conv ersion, the conversion is stopped and the A/D converter waits for the trigger again. Ho wever, writing to these registers is prohibited in the one-shot select mode/one-shot scan mode. Caution To select the timer trigger mode, set the hi gh-speed conversion mode. Do not input a trigger during the stabilization time that is inserted on ce after the A/D conversion operation is enabled (ADA0M0.ADA0CE bit = 1). Remark The trigger standby status me ans the status after the stabilization time has elapsed.

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15.5.4 Operation mode

Four operation modes are available as th e modes in which to set the ANIn pins : continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. The operation mode is selected by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits. (1) Continuous select mode In this mode, the voltage of one analog input pin selected by the ADA0S register is continuously converted into a digital value. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin corresponds to an ADA0CRn register on a one-to-one basis. Each time A/D conversion is completed, the A/D conversion end interrupt request signal (INTAD) is generated. After completion of conversion, the next conversion is started, unless the ADA0M0.ADA0CE bit is cleared to 0. Figure 15-4. Timing Example of Continuous Select Mode Operation (ADA0S Register = 01H) ANI1 A/D conversion Data 1 (ANI1) Data 2 (ANI1) Data 3 (ANI1) Data 4 (ANI1) Data 5 (ANI1) Data 6 (ANI1) Data 7 (ANI1) Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 1 (ANI1) Data 2 (ANI1) Data 3 (ANI1) Data 4 (ANI1) Data 6 (ANI1) ADA0CR1 INTAD Conversion start Set ADA0CE bit = 1 Conversion start Set ADA0CE bit = 1 (2) Continuous scan mode In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADA0S register, and their values are continuously converted into digital values. The result of each conversion is stored in the ADA0CRn register corresponding to the analog input pin. When conversion of the analog input pin specified by the ADA0S register is complete, the INTAD signal is generated, and A/D conversion is started again from the ANI0 pin, unless the ADA0CE bit is cleared to 0.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 718 of 1817 Sep 19, 2011 Figure 15-5. Timing Example of Continuous Scan Mode Operation (ADA0S Register = 03H) (a) Timing example A/D conversion Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) Data 5 (ANI0) Data 6 (ANI1) Data 7 (ANI2) Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) Data 5 (ANI0) Data 6 (ANI1) ADA0CRn INTAD Conversion start Set ADA0CE bit = 1 ANI3 ANI0 ANI1 ANI2 Data 1 Data 2 Data 3 Data 4 Data 6 Data 5 Data 7 (b) Block diagram A/D converter ADA0CRn registerAnalog input pin ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI9 ANI10 Note ANI11Note ADA0CR0 ADA0CR1 ADA0CR2 ADA0CR3 ADA0CR4 ADA0CR5 ADA0CR9 ADA0CR10 Note ADA0CR11Note Note V850ES/JJ3-E only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 719 of 1817 Sep 19, 2011 (3) One-shot select mode In this mode, the voltage of one analog input pin specified by the ADA0S register is converted into a digital value only once. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin and an ADA0CRn register correspond on a one-to-one basis. When A/D conversion has been completed once, the INTAD signal is generated. The A/D conversion operation is stopped after it has been completed. Figure 15-6. Timing Example of One-Shot Select Mode Operation (ADA0S Register = 01H) ANI1 A/D conversion Data 1 (ANI1) Data 6 (ANI1) Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 1 (ANI1) Data 6 (ANI1) ADA0CR1 INTAD Conversion start Set ADA0CE bit = 1 Conversion start Set ADA0CE bit = 1 Conversion endConversion end (4) One-shot scan mode In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADA0S register, and their values are converted into digital values . Each conversion result is stored in the ADA0CRn register corresponding to the analog input pin. When conversion of the analog input pin specified by the ADA0S register is complete, the INTAD signal is generated. A/D conversion is stopped after it has been completed (n = 0 to 11).

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 720 of 1817 Sep 19, 2011 Figure 15-7. Timing Example of One-Shot Scan Mode Operation (ADA0S Register = 03H) (a) Timing example A/D conversion Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) ADA0CRn INTAD Conversion start Set ADA0CE bit = 1 Conversion end ANI3 ANI0 ANI1 ANI2 Data 1 Data 2 Data 3 Data 4 (b) Block diagram A/D converter ADA0CRn registerAnalog input pin ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI9 ANI10 Note ANI11Note ADA0CR0 ADA0CR1 ADA0CR2 ADA0CR3 ADA0CR4 ADA0CR5 ADA0CR9 ADA0CR10 Note ADA0CR11Note Note V850ES/JJ3-E only

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15.5.5 Power-fail compare mode

The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT registers.

• When the ADA0PFM.ADA0PFE bit = 0, the INTAD signal is generated each time conversion is completed (normal use of the A/D converter).
• When the ADA0PFE bit = 1 and when the ADA0PFM.ADA0PF C bit = 0, the value of the ADA0CRnH register is compared with the value of the ADA0PFT register when co nversion is completed, and the INTAD signal is generated only if ADA0CRnH ≥ ADA0PFT.
• When the ADA0PFE bit = 1 and when the ADA0PFC bit = 1, the value of the ADA0CRnH register is compared with the value of the ADA0PFT register when conversion is completed, and t he INTAD signal is generated only if ADA0CRnH < ADA0PFT. In the power-fail compare mode, four modes are available as modes in which to set the ANIn pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 722 of 1817 Sep 19, 2011 (1) Continuous select mode In this mode, the result of converti ng the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CRn register, and the INTAD signal is not generated. After completion of the first conversion, the next conversion is started, unless the ADA0M0.ADA0CE bit is cleared to 0. Figure 15-8. Timing Example of Continuous Select Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 01H) ANI1 A/D conversion Data 1 (ANI1) Data 2 (ANI1) Data 3 (ANI1) Data 4 (ANI1) Data 5 (ANI1) Data 6 (ANI1) Data 7 (ANI1) Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 1 (ANI1) Data 2 (ANI1) Data 3 (ANI1) Data 4 (ANI1) Data 6 (ANI1) ADA0CR1 INTAD Conversion start Set ADA0CE bit = 1 ADA0PFT unmatch ADA0PFT unmatch ADA0PFT match ADA0PFT match ADA0PFT match Conversion start Set ADA0CE bit = 1 (2) Continuous scan mode In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0 pin to the pin specified by the ADA0S regi ster are stored, and the set value of the ADA0CR0H register of channel 0 is compared with the value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register, and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CR0 register, and the INTAD signal is not generated. After the result of the first conversion has been stored in the ADA0CR0 register, the results of sequentially converting the voltages on the analog input pins up to the pin specified by the ADA0S register are continuously stored. After completion of conversion, the next conversion is started from the ANI0 pin again, unless the ADA0CE bit is cleared to 0.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 723 of 1817 Sep 19, 2011 Figure 15-9. Timing Example of Continuous Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example A/D conversion Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) Data 5 (ANI0) Data 6 (ANI1) Data 7 (ANI2) Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) Data 5 (ANI0) Data 6 (ANI1) ADA0CRn INTAD Conversion start Set ADA0CE bit = 1 ADA0PFT match ADA0PFT unmatch ANI3 ANI0 ANI1 ANI2 Data 1 Data 2 Data 3 Data 4 Data 6 Data 5 Data 7 (b) Block diagram A/D converter ADA0CRn registerAnalog input pin ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI9 ANI10 Note ANI11Note ADA0CR0 ADA0CR1 ADA0CR2 ADA0CR3 ADA0CR4 ADA0CR5 ADA0CR9 ADA0CR10 Note ADA0CR11Note Note V850ES/JJ3-E only

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 724 of 1817 Sep 19, 2011 (3) One-shot select mode In this mode, the result of converti ng the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CRn register, and the INTAD signal is not generated. Conversion is stopped after it has been completed. Figure 15-10. Timing Example of One-Shot Select Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 01H) ANI1 A/D conversion Data 1 (ANI1) Data 6 (ANI1) Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 1 (ANI1) Data 6 (ANI1) ADA0CR1 INTAD Conversion start Set ADA0CE bit = 1 Conversion start Set ADA0CE bit = 1 ADA0PFT match Conversion end ADA0PFT unmatch Conversion end (4) One-shot scan mode In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0 pin to the pin specified by the ADA0S regi ster are stored, and the set value of the ADA0CR0H register of channel 0 is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CR0 r egister, and the INTAD0 signal is not generated. After the result of the first conversion ha s been stored in the ADA0CR0 register, the results of converting the signals on the analog input pins specified by the ADA0S register are sequentially stored. The conversion is stopped after it has been completed.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 725 of 1817 Sep 19, 2011 Figure 15-11. Timing Example of One-Shot Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example A/D conversion Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) ADA0CRn INTAD Conversion start Set ADA0CE bit = 1 Conversion end ADA0PFT match ANI3 ANI0 ANI1 ANI2 Data 1 Data 2 Data 3 Data 4 (b) Block diagram A/D converter ADA0CRn registerAnalog input pin ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI9 ANI10 Note ANI11Note ADA0CR0 ADA0CR1 ADA0CR2 ADA0CR3 ADA0CR4 ADA0CR5 ADA0CR9 ADA0CR10 Note ADA0CR11Note Note V850ES/JJ3-E only

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15.6 Cautions

(1) When A/D converter is not used When the A/D converter is not used, the power consumpt ion can be reduced by clearing the ADA0M0.ADA0CE bit to 0. (2) Input range of ANIn pins Input the voltage within the specified range to the ANIn pins. If a voltage equal to or higher than AV REF0 or equal to or lower than AV SS (even within the range of the absolute maximum ratings) is input to any of these pins, the conversion value of that channel is undefined, and the conversion value of the other channels may also be affected. (3) Countermeasures against noise To maintain the 10-bit resolution, the ANIn pins must be effectively protected from noise. The effect of noise increases as the output impedance of t he analog input source becomes higher. To lower the noise, connecting an external capacitor as shown in Figure 15-12 is recommended. Figure 15-12. Processing of Analog Input Pin AVREF0 VDD VSS AVSS Clamp with a diode with a low VF (0.3 V or less) if noise equal to or higher than AVREF0 or equal to or lower than AVSS may be generated. ANIn (4) Alternate I/O The analog input pins (ANIn) function alternately as port pi ns. When selecting one of the ANIn pins to execute A/D conversion, do not execute an instru ction to read an input port or write to an output port during conversion as the conversion resolution may drop. Also the conversion resolution may drop at the pins se t as output port pins during A/D conversion if the output current fluctuates due to the effect of the external circuit connected to the port pins. If a digital pulse is applied to a pin adjacent to the pin whose input signal is being converted, the A/D conversion value may not be as expected due to the effect of coupling noise. Therefore, do not apply a pulse to a pin adjacent to the pin undergoing A/D conversion.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 728 of 1817 Sep 19, 2011 (7) AVREF0 pin (a) The AVREF0 pin is used as the power supply pin of the A/D converter and also supplies power to the alternate- function ports. In an application where a backup power supply is used, be sure to supply the same potential as VDD to the AVREF0 pin as shown in Figure 15-15. (b) The AVREF0 pin is also used as the reference voltage pin of the A/D converter. If the source supplying power to the AVREF0 pin has a high impedance or if the power supply has a low current supply capability, the reference voltage may fluctuate due to the cu rrent that flows during conversion (especially, immediately after the conversion operation enable bit ADA0CE has been set to 1). As a result, the conversion accuracy may drop. To avoid this, it is recommended to connect a capacitor across the AV REF0 and AV SS pins to suppress the reference voltage fluctuation as shown in Figure 15-15. (c) If the source supplying power to the AV REF0 pin has a high DC resistance (for example, because of insertion of a diode), the voltage when conversion is enabled may be lower than the voltage when conversion is stopped, because of a voltage drop caused by the A/D conversion current. Figure 15-15. AVREF0 Pin Processing Example AVREF0 Note AVSS Main power supply Note Parasitic inductance (8) Reading ADA0CRn register When the ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written, the contents of the ADA0CRn register may be undefined. Read the conversion result a fter completion of conversion and before writing to the ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT r egister. Also, when an external/timer trigger is acknowledged, the contents of the ADA0CRn register may be undefined. Read the conversion result after completion of conversion and before the next external/timer trigger is acknowledged. The correct conversion result may not be read at a timing different from the above. (9) External trigger mode When using the external trigger mode, the input trigger during A/D conversion will not be acknowledged.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 15 A/D CONVERTER R01UH0290EJ0300 Rev.3.00 Page 729 of 1817 Sep 19, 2011 (10) Standby mode Because the A/D converter stops operating in the STOP mode, the conversion results are invalid, so power consumption can be reduced. Operatio ns are resumed after the STOP mode is released, but the A/D conversion results after the STOP mode is released are invalid. When using the A/D converter after the STOP mode is released, clear the ADA0M0.ADA0CE bit to 0 before se tting the STOP mode or after releasing the STOP mode, then set the ADA0CE bit to 1 after releasing the STOP mode. In the IDLE1, IDLE2, or subclock operation mode, operation continues. To lower the power consumption, therefore, clear the ADA0M0.ADA0CE bit to 0. In the IDLE1 and IDLE2 modes, since the analog input voltage value cannot be retained, the A/D conversion results after the IDLE1 and IDLE2 modes are released are invalid. The results of conversions before the IDLE1 and IDLE2 modes were set are valid. (11) High-speed conversion mode In the high-speed conversion mode, rewriting t he ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers and trigger input during the stabilization time are prohibited. (12) A/D conversion time The A/D conversion time is the total of the stabilization time, conversion time, wait time, and trigger response time (for details of these times, refer to Table 15-2 Conversion Time Sel ection in Normal Conversion Mode (ADA0HS1 Bit = 0) and Table 15-3 Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1)). During A/D conversion in the normal conversion m ode, if the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers are written or a trigger is input, reconv ersion is carried out. However, if the stabilization time end timing conflicts with writing to thes e registers, or if the stabilization ti me end timing conflicts with the trigger input, a stabilization time of 64 clocks is reinserted. If a conflict occurs again with the reinse rted stabilization time end timing, the stabilization time is reinserted. Therefore do not set the trigger input interval and control register write interval to 64 clocks or lower. (13) Variation of A/D conversion results The results of A/D conversion may vary due to a fluctuation in the supply voltage or the effect of noise. To reduce this variation, take countermeasures with the program such as averaging the A/D conversion results. (14) A/D conversion result hysteresis characteristics The successive comparison type A/D converter holds the analog input voltage in the internal sample & hold capacitor and then performs A/D conversion. After A/D conversion has finished, the analog input voltage remains in the internal sample & hold capacitor. As a result, the following phenomena may occur.

• When the same channel is used for A/D conversions, if the voltage is higher or lo wer than the previous A/D conversion, then hysteresis characte ristics may appear in which the conv ersion result is affected by the previous value. Thus, even if the conversion is performed at the same potential, the result may vary.
• When switching the analog input channel , hysteresis characteristics may app ear in which the conversion result is affected by the previous channel value. This is because one A/D converter is used for the A/D conversions. Thus, even if the conversion is performed at the same potential, the result may vary.

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15.7 How to Read A/D Converter Characteristics Table

This section describes the terms related to the A/D converter. (1) Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit). The ratio of 1 LSB to the full scale is expressed as %FSR (full-scale range). %FSR is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be expressed as follows, independently of the resolution. 1%FSR = (Maximum value of convertible analog input voltage – Minimum value of convertible analog input voltage)/100 = (AV REF0 − 0)/100 = AV REF0/100 When the resolution is 10 bits, 1 LSB is as follows:

1 LSB = 1/2

= 1/1,024 = 0.098%FSR The accuracy is determined by the overall error, independently of the resolution. (2) Overall error This is the maximum value of the difference between an actually measured value and a theoretical value. It is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. The overall error in the characteristics table does not include the quantization error. Figure 15-16. Overall Error Ideal line Overall error 0A V REF0 Analog input Digital output

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn) R01UH0290EJ0300 Rev.3.00 Page 734 of 1817 Sep 19, 2011 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn) In the V850ES/JH3-E and V850ES/JJ3-E, asynchronous serial interface B with FIFO (UARTBn) is provided with 2 channels.

16.1 Features

• Transfer rate: Maximum 300 bps to 3.125 Mbps (using a dedicated baud rate generator)
• Full-duplex communications
• Single mode and FIFO mode selectable
• Single mode: 8-bit × 1-stage data register (UBnTX r egister or UBnRX register) is used for each of transmission and reception.
• FIFO mode Transmit FIFO: UBnTX register (8 bits × 16 stages). Receive FIFO: UBnRXAP register (16 bits × 16 stages) The higher 8 bits of the UBnRXAP register stor e information about errors in the received data.
• Two-pin configuration TXDBn: Transmit data output pin RXDBn: Receive data input pin
• Reception error detection function
• Overflow error (FIFO mode only)
• Parity error
• Framing error
• Overrun error (single mode only)
• Interrupt sources: 5 types
• Reception error interrupt request signal (INTUBnTIRE)
• Reception end interrupt request signal (INTUBnTIR)
• Transmission enable interrupt request signal (INTUBnTIT)
• FIFO transmission end interrupt reques t signal (INTUBnTIF) (FIFO mode only)
• Reception timeout interrupt request si gnal (INTUBnTITO) (FIFO mode only)
• The character length of transmit/receive data is specified according to the UBnCTL0 register
• Character length: 7 or 8 bits
• Parity functions: Odd, even, 0, or none
• Transmission stop bits: 1 or 2 bits
• MSB first/LSB first selectable for transfer data
• On-chip dedicated baud rate generator Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn) R01UH0290EJ0300 Rev.3.00 Page 735 of 1817 Sep 19, 2011

16.2 Configuration

The block diagram of the UARTBn is shown below. Figure 16-1. Block Diagram of UARTBn RXDBn Internal bus Receive shift register UARTBn control register 0 (UBnCTL0) UARTBn control register 2 (UBnCTL2) UARTBn status register (UBnSTR) UARTBnFIFO control register 0 (UBnFIC0) UARTBnFIFO control register 1 (UBnFIC1) UARTBnFIFO control register 2 (UBnFIC2) UARTBnFIFO status register 0 (UBnFIS0) UARTBnFIFO status register 1 (UBnFIS1)UBnRX Receive FIFOn Timeout counter Sampling block Receive controller Transmit controller Baud rate generator n Reception unit Transmission unit Baud rate generator n Transmit shift register UBnTX Transmit FIFOn INTUBnTITO TXDBn INTUBnTIF INTUBnTIT INTUBnTIR INTUBnTIRE fXX/2 Remark 1. fxx: Main clock frequency 2. For the configuration of the baud rate generator, see Figure 16-10. 3. n = 0, 1 UARTBn consists of the following hardware units. Table 16-1. Configuration of UARTBn Item Configuration Registers UARTBn control register 0 (UBnCTL0) UARTBn control register 2 (UBnCTL2) UARTBn status register (UBnSTR) UARTBn FIFO control register 0 (UBnFIC0) UARTBn FIFO control register 1 (UBnFIC1) UARTBn FIFO control register 2 (UBnFIC2) UARTBn FIFO status register 0 (UBnFIS0) UARTBn FIFO status register 1 (UBnFIS1) Receive shift register UARTBn receive data register AP (UBnRXAP) UARTBn receive data register (UBnRX) Transmit shift register UARTBn transmit data register (UBnTX)

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn) R01UH0290EJ0300 Rev.3.00 Page 736 of 1817 Sep 19, 2011 (1) UARTBn control register 0 (UBnCTL0) This register controls the transfer operation of UARTBn. (2) UARTBn status register (UBnSTR) This register indicates the transfer status during transmission and the contents of a receptio n error. The status flag of this register, which indicates the transfer status during transmission, i ndicates the data ret ention status of the transmit shift register and the transmit data register (the UBnTX register in the single mode or transmit FIFO in the FIFO mode). Each reception error flag is set to 1 when a reception error occurs, and cleared to 0 when 0 is written to the UBnSTR register. (3) UARTBn control register 2 (UBnCTL2) This register is used to specify the division ratio by which to control the baud rate (serial transfer speed) of UARTBn. (4) UARTBn FIFO control register 0 (UBnFIC0) This register is used to select the operation mode of UARTBn, clear the transmit FIFO/receive FIFO that becomes valid in the FIFO mode, and specify the timing mode in which the transmi ssion enable interrupt request signal (INTUBnTIT)/reception end interrupt request signal (INTUBnTIR) occurs. (5) UARTBn FIFO control register 1 (UBnFIC1) This register is valid in the FIFO m ode. It generates a reception timeout in terrupt request signal (INTUBnTITO) if data is stored in the receive FIFO w hen the next data does not come (start bi t is not detected) even after the reception wait time of the next data has elapsed after the stop bit has been received. (6) UARTBn FIFO control register 2 (UBnFIC2) This register is valid in the FIFO m ode. It is used to set the timing to generate the transmission enable interrupt request signal (INTUBnTIT)/recepti on end interrupt request signal (INT UBnTIR), using t he number of data transmitted or received as a trigger. (7) UARTBn FIFO status register 0 (UBnFIS0) This register is valid in the FIFO mode. The number of bytes of data stored in the receive FIFO can be read from this register. (8) UARTBn FIFO status register 1 (UBnFIS1) This register is valid in the FIFO mode. The number of empty bytes of t he transmit FIFO can be read from this register. (9) Receive shift register This is a shift register that converts the serial data that was input to the RXDBn pin into parallel data. One byte of data is received, and if a stop bit is detected, the received data is transferred to the receive data register. This register cannot be directly manipulated. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn) R01UH0290EJ0300 Rev.3.00 Page 737 of 1817 Sep 19, 2011 (10) UARTBn receive data register AP (UBnRXAP), UARTBn receive data register (UBnRX) The receive data register holds receive data. In the single mode, the 8-bit × 1-stage UBnRX register is used. The 16-bit × 16-stage receive FIFO (UBnRXAP register) is used in the FIFO mode. The receive data is stored in the lower 8 bits of the receive FIFO (UBnRXAP register) and the error information of the received data is stored in the higher 8 bits (bit 8 and bit 9). If a reception error (such as a parity error or a framing error) occurs in the FIFO mode, the error data can be identified by reading the UBnRXAP register in 16- bit (halfword) units (error information is appended as UBnP EF bit = 1 or UBnFEF bit = 1). When the lower 8 bits of the UBnRXAP register are read in 8-bi t (byte) units, the higher 8 bits are di scarded. Therefore, if no error has occurred, only the receive dat a of the UBnRXAP register c an be read successively by being read in 8-bit (byte) units in the same way as the UBnRX register. When 7-bit length data is received with the LSB first, the re ceived data is transferred to bits 6 to 0 of the receive data register from the LSB (bit 0), wit h the MSB (bit 7) always being 0. W hen data is received with the MSB first, the received data is transferred to bits 7 to 1 of the rece ive data register from the MSB (bit 7), with the LSB (bit 0) always being 0. If an overrun error occurs, the receive data at that time is not tran sferred to the receive data register. While reception is enabled, the received data is transferr ed from the receive shift r egister to the receive data register, in synchronization with the shift-in processing of one frame. A reception end interrupt request signa l (INTUBnTIR) is generated by transferri ng the data to the UBnRX register in the single mode, or transferring t he number of receive data set as the trigger by the UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits to receive FIFO in the FIFO m ode. If data is stored in re ceive FIFO when the next data does not come (start bit is not detected) after the next data reception wait time specified by the UBnFIC1.UBnTC4 to UBnFIC1.UBnTC0 bits has elapsed in the FIFO mode, a reception timeout interrupt request signal (INTUBnTITO) is generated. (11) Transmit shift register This is a shift register that converts the parallel data that was transferred from the transmit data register into serial data. When one byte of data is transferred from the transmit data register, the transmit shift register data is output from the TXDBn pin. This register cannot be directly manipulated. Remark n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn) R01UH0290EJ0300 Rev.3.00 Page 738 of 1817 Sep 19, 2011 (12) UARTBn transmit data register (UBnTX) The transmit data register is a buffer for transmit data. The 8-bit × 1-stage UBnTX register is used as this buffer in the single mode. In the FIFO mode, the 8-bit × 16-stage transmit FIFO is used. When 7-bit length data is transmitted with the LSB first, bits 6 to 0 of the transmit data re gister are transmitted as the transmit data from the LSB (bit 0) with the MSB (bit 7) always being 0. When data is transmitted with the MSB first, bits 7 to 1 of the transmit data register are transmi tted as the transmit data from the MSB (bit 7) with the LSB (bit 0) always being 0. In the single mode, transmission is star ted by writing transmit data to the UB nTX register while transmission is enabled (UBnCTL0.UBnTXE bit = 1). When writing the tr ansmit data to the UBnTX register is enabled (when 1- byte data is transferred from the UBnT X register to the transmit shift regi ster), a transmission enable interrupt request signal (INTUBnTIT) is generated. In the FIFO mode, transmission is start ed by writing at least the number of tr ansmit data set as the trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits and 16 bytes or less to transmit FIFO and then enabling transmission (UBnTXE bit = 1). When the number of transmit data set as the trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits have been transferred from transmit FIFO to the transmit shift register (transmit data of the number set as the trigger can be written), a transmiss ion enable interrupt request signal (INTUBnTIT) is generated. In the FIFO mode, a FI FO transmission enable interrupt reques t signal (INTUBnTIF) is generated when there is no more data in transmit FIFO and the trans mit shift register (when FIFO and the register become empty). (13) Timeout counter This counter is used to recognize that data exists (rema ins) in receive FIFO when the number of received data does not reach the number set as the trigger by the UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits, and is valid only in the FIFO mode. If data is stored in receive FIFO when the next data does not come (start bi t is not detected) after the next data reception wait time specified by t he UBnFIC1.UBnTC4 to UBnFIC1.UBnTC0 bits has elapsed after the stop bit has been received, a reception timeout interrupt request signal (INTUBnTITO) is generated. (14) Sampling block This block samples the RXDBn signal at the rising edge of the peripheral clock (f XX). If the same sampling value is detected two times, output of the match detector changes, and the value is sampled as input data. Data of less than one clock width is judged as noise and is not transmitted to the internal circuitry.

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16.3 Switching Between UARTB and Other Serial Interface Modes

In the V850ES/JH3-E and V850ES/JJ3-E, RXDB0 and TXDB0 for UARTB0 are each assigned to two pins, as shown in Table 16-2. When using UARTB0 in the V850ES/JH3-E, use pins 32 and 31 or pins 109 and 108 as a set. Do not use pins 32 and 108 or pins 109 and 31 simultaneously. When using UARTB0 in the V850ES/JJ3-E, use pins 32 and 31 or pins 115 and 114 as a set. Do not use pins 32 and 114 or pins 115 and 31 simultaneously Table 16-2. Pin Assignment in UARTB0 Function Pin Number Function V850ES/JH3-E V850ES/JJ3-E Alternate Function 32 32 P34/SOF4/TIAA20/TOAA20 RXDB0 109 115 PDH4/A20/SOF4 31 31 P33/SIF4/TIAA11/TOAA11 TXDB0 108 114 PDH3/A19/SIF4

16.3.1 Using UARTB0 and CSIF4 at the same time

In the V850ES/JH3-E and V850ES/JJ3-E, UARTB0 and CSIF4 share the same pin in port 3. These function therefore cannot be used at the same time. To switch between UARTB0 and CSIF4, the PMC3, PFC3, and PFCE3 registers or the PMDH, PMCDH, and PMFEDH registers must be set in advance. Figure 16-2 shows an example of port settings when using UARTB0 via port 3 and CSIF4 via port HD. Caution The operations related to tr ansmission and reception of UARTB0 or CSIF4 are not guaranteed if the mode is switched during transmission or reception. Be sure to disable the unit that is not used.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn) R01UH0290EJ0300 Rev.3.00 Page 740 of 1817 Sep 19, 2011 Figure 16-2. Mode Switch Settings of UARTB0 and CSIF4 (1) UARTB0 settings (2) CSIF4 settings PMCDH PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 SCKF4 SOF4 SIF4 PMCDH2 PMCDH1 PMCDH0 PFCDH PFCDH5 PFCDH4 PFCDH3 PFCDH2 PFCDH1 PFCDH0 SCKF4 SOF4 SIF4 PFCEDH PFCEDH4 PFCEDH3 SOF4 SIF4 PFCE3 PFCE37 PFCE36 PFCE35 PFCE34 PFCE33 PFCE32 PFCE31 PFCE30 RXDB0 TXDB0 PFC3 PFC37 PFC36 PFC35 PFC34 PFC33 PFC32 PFC31 PFC30 RXDB0 TXDB0 PMC3 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 RXDB0 TXDB0

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16.3.2 Switching between UARTB1 and CSIF3 mode

In the V850ES/JH3-E and V850ES/JJ3-E, UARTB1 and CSIF3 shar e the same pin, so thes e functions cannot be used at the same time. To switch between UARTB1 and CSIF 3, the PMC9, PFC9, and PFCE9 registers must be set in advance. Caution The operations related to tr ansmission and reception of UARTB1 or CSIF3 are not guaranteed if the mode is switched during transmission or reception. Be sure to disable the unit that is not used. Figure 16-3. Mode Switch Settings of UARTB1 and CSIF3 PMC9 (PMC9H) (PMC9L) (PFC9L) (PFCE9L) After reset: 0000H R/W Address: PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90 PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98 89101112131415 PFC9 (PFC9H) After reset: 0000H R/W Address: PFC915 PFC914 PFC913 PFC912 PFC911 PFC910 PFC99 PFC98 PFC97 PFC96 PFC95 PFC94 PFC93 PFC92 PFC91 PFC90 89101112131415 PFCE915 PFCE914 PFCE913 0 PFCE911 PFCE910 PFCE99 PFCE98 PFCE97 PFCE96 PFCE95 PFCE94 PFCE93 PFCE92 PFCE91 PFCE90 89101112131415 PFCE9 (PFCE9H) After reset: 0000H R/W Address: Port I/O mode SOF3 (CSIF3) RXDB1 (UARTB1) PMC914 Port I/O modePFCE914 PFC914 Port I/O mode SIF3 (CSIF3) TXDB1 (UARTB1) PMC913 Port I/O modePFCE913 PFC913 Port I/O mode SCKF3 (CSIF3) PMC915 Operation modePFCE915 PFC915 PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H PFC9 FFFFF472H, PFC9L FFFFF472H, PFC9H FFFFF473H PFCE9 FFFFF712H, PFCE9L FFFFF712H, PFCE9H FFFFF713H Remark x = don’t care

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16.4 Control Registers

(1) UARTBn control register 0 (UBnCTL0) The UBnCTL0 register controls the transfer operations of UARTBn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 10H. Cautions 1. When using UARTBn, set the external pins related to the UARTBn fu nction in the alternate- function mode, set UARTBn cont rol register 2 (UBnCTL2). Then set the UBnPWR bit to 1 before setting the other bits. 2. Be sure to input a high level to the RXDBn pin when setting the external pins related to the UARTBn function in the alternate -function mode. If a low level is input, it is judged that a falling edge is input after the UBnRXE bit has been set to 1, and reception may be started. Remarks 1. When reception is disabled, the receive shift regi ster does not detect a start bit. No shift-in processing or transfer processing to the receive dat a register is performed, and the contents of the receive data register are retained. When reception is enabled, the receive shift operation starts, in synchronization with the detection of the start bit, and when the reception of one fram e is completed, the contents of the receive shift register are transferred to the receive data register. A reception end interrupt request signal (INTUB nTIR) is also generated, in synchronization with the transfer to the receive data register (in FIFO m ode, transfer triggered by reaching set number of receive data). If data is stored in receive FIFO when the next data does not come (start bit is not detected) after the next data reception wait time specified by the UBnFIC1.UBnTC4 to UBnFIC1.UBnTC0 bits has elapsed in the FIFO mode, a reception timeout interrupt request signal (INTUBnTITO) is generated. 2. n = 0, 1

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn) R01UH0290EJ0300 Rev.3.00 Page 743 of 1817 Sep 19, 2011 (1/2) UBnPWRUBnCTL0 (n = 1, 0) UBnTXE UBnRXE UBnDIR UBnPS1 UBnPS0 UBnCL UBnSL 321 After reset: 10H R/W Address: UB0CTL0 FFFFFB80H, UB1CTL0 FFFFFBA0H Transmission is disabled Transmission is enabled UBnTXE Transmission enable

• On startup, set the UBnPWR bit to 1 and then set the UBnTXE bit to 1. To stop transmission, clear the UBnTXE bit to 0 and then the UBnPWR bit to 0.
• When the transmission unit status is to be initialized, the transmission status may not be able to be initialized unless the UBnTXE bit is set to 1 again after an interval of two cycles of fXX has elapsed since the UBnTXE bit was cleared to 0. Stops supply of clocks to UARTBn Supplies clocks to UARTBn UBnPWR Operation clock control to UARTBn
• When the UBnPWR bit is cleared to 0, the UARTBn can be asynchronously reset.
• When the UBnPWR bit = 0, UARTBn is in a reset state. Therefore, to operate UARTBn, the UBnPWR bit must be set to 1.
• When the UBnPWR bit is changed from 1 to 0, all registers of UARTBn are initialized. When the UBnPWR bit is set to 1 again, the UARTBn registers must be set again.
• The TXDBn pin output is high level when the UBnPWR bit is cleared to 0. Reception is disabled Reception is enabled UBnRXE Reception enable
• On startup, set the UBnPWR bit to 1 and then set the UBnRXE bit to 1. To stop reception, clear the UBnRXE bit to 0 and then the UBnPWR bit to 0.
• When the reception unit status is to be initialized, the reception status may not be able to be initialized unless the UBnRXE bit is set to 1 again after an interval of two cycles of fXX has elapsed since the UBnRXE bit was cleared to 0.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn) R01UH0290EJ0300 Rev.3.00 Page 744 of 1817 Sep 19, 2011 (2/2) MSB transfer first LSB transfer first UBnDIR Specification of transfer direction mode (MSB/LSB)

• Clear the UBnPWR bit or UBnTXE and UBnRXE bits to 0 before rewriting the UBnDIR bit. Do not output a parity bit Output 0 parity Output odd parity Output even parity Receive with no parity Receive as 0 parity Judge as odd parity Judge as even parity UBnPS1 Parity selection during transmission Parity selection during receptionUBnPS0
• Clear the UBnTXE and UBnRXE bits to 0 before overwriting the UBnPS1 and UBnPS0 bits.
• If “0 parity” is selected for reception, no parity judgment is made. Therefore, no error interrupt is generated because the UBnSTR.UBnPE bit is not set to 1. 7 bits 8 bits UBnCL Specification of data character length of 1-frame transmit/receive data Clear the UBnTXE and UBnRXE bits to 0 before overwriting the UBnCL bit. 1 bit 2 bits UBnSL Specification of stop bit length of transmit data
• Clear the UBnTXE bit to 0 before overwriting the UBnSL bit.
• Since reception always operates by using a single stop bit length, the UBnSL bit setting does not affect receive operations. Remark For details of parity, see 16.7.6 Parity types and corresponding operation.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn) R01UH0290EJ0300 Rev.3.00 Page 745 of 1817 Sep 19, 2011 (2) UARTBn status register (UBnSTR) The UBnSTR register indicates the transfer status and reception error contents while UARTBn is transmitting data. The status flag that indicates the tr ansfer status during transmission indicate s the data retention status of the transmit shift register and transmit data register (the UBnTX register in the single mode or transmit FIFO in the FIFO mode). The status flag that indicates a reception error holds its status until it is cleared to 0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution When the UBnCTL0.UBn PWR bit or UBnCTL0.UBnRXE bit is set to 0, or when 0 is written to the UBnSTR register, the UBnSTR.UBnOVF, UBnSTR.UBnPE, UBnSTR.UBnFE, and UBnSTR.UBnOVE bits are cleared to 0. (1/2) UBnTSFUBnSTR (n = 0, 1) 0 0 0 UBnOVF UBnPE UBnFE UBnOVE After reset: 00H R/W Address: UB0STR FFFFFB84H, UB1STR FFFFFBA4H <0>456<7> Overflow did not occur. Overflow occurred (during reception).

• In single mode (UBnFIC0.UBnMOD bit = 0) Data to be transferred to the transmit shift register and UBnTX register does not exist (cleared (0) when UBnCTL0.UBnPWR bit = 0 or UBnCTL0.UBnTXE bit = 0).
• In FIFO mode (UBnFIC0.UBnMOD bit = 1) Data to be transferred to the transmit shift register and transmit FIFO does not exist (cleared (0) when UBnCTL0.UBnPWR bit = 0 or UBnCTL0.UBnTXE bit = 0).
• In single mode (UBnFIC0.UBnMOD bit = 0) Data to be transferred to the transmit shift register or UBnTX register exists (transmission in progress).
• In FIFO mode (UBnFIC0.UBnMOD bit = 1) Data to be transferred to the transmit shift register and transmit FIFO exists (transmission in progress). UBnOVF Overflow flag
• The UBnOVF bit is valid only in the FIFO mode (when UBnFIC0.UBnMOD bit = 1), and invalid in the single mode (when UBnFIC0.UBnMOD bit = 0).
• If an overflow occurs, the received data is not written to receive FIFO but discarded. The value of the UBnTSF bit is reflected after two periods of fXX have elapsed, after the transmit data is written to the UBnTX register. Therefore, exercise care when referencing the UBnTSF bit after transmit data has been written to the UBnTX UBnTSF Transfer status flag

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn) R01UH0290EJ0300 Rev.3.00 Page 746 of 1817 Sep 19, 2011 (2/2) Parity error did not occur. Parity error occurred (during reception). UBnPE Parity error flag

• The UBnPE bit is valid only in the single mode (when UBnFIC0.UBnMOD bit = 0), and invalid in the FIFO mode (when UBnFIC0.UBnMOD bit = 1).
• The operation of the UBnPE bit differs according to the settings of the UBnCTL0.UBnPS1 and UBnCTL0.UBnPS0 bits. Framing error did not occur. Framing error occurred (during reception). UBnFE Framing error flag
• The UBnFE bit is valid only in the single mode (when UBnFIC0.UBnMOD bit = 0), and invalid in the FIFO mode (when UBnFIC0.UBnMOD bit = 1).
• Only the first bit of the stop bits of the receive data is checked, regardless of the stop bit length. Overrun error did not occur. Overrun error occurred (during reception). UBnOVE Overrun error flag
• The UBnOVE bit is valid only in the single mode (when UBnFIC0.UBnMOD bit = 0), and invalid in the FIFO mode (when UBnFIC0.UBnMOD bit = 1).
• When an overrun error occurs, the next receive data value is not written to the UBnRX register and the data is discarded.

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn) R01UH0290EJ0300 Rev.3.00 Page 747 of 1817 Sep 19, 2011 (3) UARTBn control register 2 (UBnCTL2) The UBnCTL2 register is used to specify the division ratio by which to control the baud rate (serial transfer speed) of UARTBn. This register can be read or written in 16-bit units. Reset sets this register to FFFFH. Caution When rewriting the UBnBRS 15 to UBnBRS0 bits of this regi ster, set the UBnCTL0.UBnTXE and UBnCTL0.UBnRXE bits to 0 or clear the UBnCTL0.UBnPWR bit to 0. UBnBRS15UBnCTL2 (n = 0, 1) UBnBRS14 UBnBRS13 UBnBRS12 UBnBRS11UBnBRS10 UBnBRS9 UBnBRS8 11 10 9 After reset: FFFFH R/W Address: UB0CTL2 FFFFFB82H, UB1CTL2 FFFFFBA2H 812131415 UBnBRS7 UBnBRS6 UBnBRS5 UBnBRS4 UBnBRS3 UBnBRS2 UBnBRS1 UBnBRS0 321 04567 Remark For the UBnBRS15 to UBnBRS0 bits, see Table 16-3 Division Value of 16-bit Counter. Table 16-3. Division Value of 16-bit Counter UBn BRS UBn BRS UBn BRS UBn BRS UBn BRS UBn BRS UBn BRS UBn BRS UBn BRS UBn BRS UBn BRS UBn BRS UBn BRS UBn BRS UBn BRS UBn BRS k Output Clock Selected 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x − Setting prohibited 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 f UCLK/k 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 5 f UCLK/k 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 6 f UCLK/k 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 65530 f UCLK/k 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 65531 f UCLK/k 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 65532 f UCLK/k 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 65533 f UCLK/k 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 65534 f UCLK/k 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 65535 f UCLK/k Remarks 1. f UCLK: Peripheral clock (fxx/2) 2. k: Value set by the UBnCTL2.UBnBRS15 to UBnCTL2.UBnBRS0 bits (k = 4, 5, 6, …, 65535) 3. x: Don’t care

V850ES/JH3-E, V850ES/JJ3-E CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn) R01UH0290EJ0300 Rev.3.00 Page 748 of 1817 Sep 19, 2011 (4) UARTBn transmit data register (UBnTX) The UBnTX register is used to set trans mit data. It functions as the 8-bit × 1-stage UBnTX register, in the single mode (UBnFIC0.UBnMOD bit = 0), and as the 8-bit × 16-stage transmit FIFO in the FIFO mode (UBnFIC0.UBnMOD bit = 1). In the single mode, transmission is started by writing transmit data to the UBnTX register when transmission is enabled (UBnCTL0.UBnTXE bit = 1). When data can be wr itten to the UBnTX register (when 1 byte of data is transferred from the UBnTX register to the transmit shift register), a transmission enable interrupt request signal (INTUBnTIT) is generated. In the FIFO mode, transmission is star ted by enabling transmission (UBnTXE bit = 1) after writing at least the number of transmit data set as the trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits and 16 bytes or less to transmit FIFO. When the number of transmit data set as the trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits have been transferred from transmit FIFO to the transmit shift register (transmit data of the number set as the trigger can be written to transmit FIFO), a transmission enable interrupt request signal (INTUBnTIT) is generated. In the FI FO mode, a FIFO transmission enable in terrupt request signal (INTUBnTIF) is generated when there is no more data in transmit FI FO and the transmit shift register (when the FIFO and register become empty). For the generation timing of the interrupt, see 16.5 Interrupt Request Signals. When 7-bit length data is transmitted with the LSB first, bits 6 to 0 of the transmit data re gister are transmitted as the transmit data from the LSB (bit 0) with the MSB (bit 7) always being 0. When data is transmitted with the MSB first, bits 7 to 1 of the transmit data register are transmi tted as the transmit data from the MSB (bit 7) with the LSB (bit 0) always being 0. This register is write-only in 8-bit units. Data is written to the transmit data register. Reset sets this register to FFH. UBnTD7UBnTX (n = 0, 1) UBnTD6 UBnTD5 UBnTD4 UBnTD3 UBnTD2 UBnTD1 UBnTD0 0467 After reset: FFH W Address: UB0TX FFFFFB88H, UB1TX FFFFFBA8H

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